stats.txt revision 11680
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 23776000 # Number of ticks simulated 5final_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 93889 # Simulator instruction rate (inst/s) 8host_op_rate 93856 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 349385939 # Simulator tick rate (ticks/s) 10host_mem_usage 252568 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 6385 # Number of instructions simulated 13sim_ops 6385 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 19system.physmem.bytes_read::total 31040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 485 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 839838493 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1305518170 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 839838493 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 839838493 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 839838493 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1305518170 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 485 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 31040 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 31040 # Total read bytes from the system interface side 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 69 # Per bank write bursts 46system.physmem.perBankRdBursts::1 32 # Per bank write bursts 47system.physmem.perBankRdBursts::2 33 # Per bank write bursts 48system.physmem.perBankRdBursts::3 47 # Per bank write bursts 49system.physmem.perBankRdBursts::4 42 # Per bank write bursts 50system.physmem.perBankRdBursts::5 20 # Per bank write bursts 51system.physmem.perBankRdBursts::6 1 # Per bank write bursts 52system.physmem.perBankRdBursts::7 3 # Per bank write bursts 53system.physmem.perBankRdBursts::8 0 # Per bank write bursts 54system.physmem.perBankRdBursts::9 1 # Per bank write bursts 55system.physmem.perBankRdBursts::10 22 # Per bank write bursts 56system.physmem.perBankRdBursts::11 25 # Per bank write bursts 57system.physmem.perBankRdBursts::12 14 # Per bank write bursts 58system.physmem.perBankRdBursts::13 118 # Per bank write bursts 59system.physmem.perBankRdBursts::14 45 # Per bank write bursts 60system.physmem.perBankRdBursts::15 13 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 23381000 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 485 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 141 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 348.044944 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 230.274346 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 313.082327 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation 204system.physmem.totQLat 8009750 # Total ticks spent queuing 205system.physmem.totMemAccLat 17103500 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2425000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 16514.95 # Average queueing delay per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 35264.95 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1305.52 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 1305.52 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 10.20 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.20 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 395 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 48208.25 # Average gap between requests 225system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 1763580 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 3005040 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 7623180 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 132480 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 14783715 # Total energy per rank (pJ) 237system.physmem_0.averagePower 621.784975 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 16957250 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 344500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 5900500 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 16710500 # Time in different power states 245system.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 2978250 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 7628310 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 68160 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 14960400 # Total energy per rank (pJ) 256system.physmem_1.averagePower 629.216130 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 16769000 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 5875500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 16728000 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 2854 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1681 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 2203 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 713 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 32.364957 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 441 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 462 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 25 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 437 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.fetch_hits 0 # ITB hits 280system.cpu.dtb.fetch_misses 0 # ITB misses 281system.cpu.dtb.fetch_acv 0 # ITB acv 282system.cpu.dtb.fetch_accesses 0 # ITB accesses 283system.cpu.dtb.read_hits 2252 # DTB read hits 284system.cpu.dtb.read_misses 48 # DTB read misses 285system.cpu.dtb.read_acv 0 # DTB read access violations 286system.cpu.dtb.read_accesses 2300 # DTB read accesses 287system.cpu.dtb.write_hits 1038 # DTB write hits 288system.cpu.dtb.write_misses 28 # DTB write misses 289system.cpu.dtb.write_acv 0 # DTB write access violations 290system.cpu.dtb.write_accesses 1066 # DTB write accesses 291system.cpu.dtb.data_hits 3290 # DTB hits 292system.cpu.dtb.data_misses 76 # DTB misses 293system.cpu.dtb.data_acv 0 # DTB access violations 294system.cpu.dtb.data_accesses 3366 # DTB accesses 295system.cpu.itb.fetch_hits 2295 # ITB hits 296system.cpu.itb.fetch_misses 27 # ITB misses 297system.cpu.itb.fetch_acv 0 # ITB acv 298system.cpu.itb.fetch_accesses 2322 # ITB accesses 299system.cpu.itb.read_hits 0 # DTB read hits 300system.cpu.itb.read_misses 0 # DTB read misses 301system.cpu.itb.read_acv 0 # DTB read access violations 302system.cpu.itb.read_accesses 0 # DTB read accesses 303system.cpu.itb.write_hits 0 # DTB write hits 304system.cpu.itb.write_misses 0 # DTB write misses 305system.cpu.itb.write_acv 0 # DTB write access violations 306system.cpu.itb.write_accesses 0 # DTB write accesses 307system.cpu.itb.data_hits 0 # DTB hits 308system.cpu.itb.data_misses 0 # DTB misses 309system.cpu.itb.data_acv 0 # DTB access violations 310system.cpu.itb.data_accesses 0 # DTB accesses 311system.cpu.workload.num_syscalls 17 # Number of system calls 312system.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states 313system.cpu.numCycles 47553 # number of cpu cycles simulated 314system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 315system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 316system.cpu.fetch.icacheStallCycles 8496 # Number of cycles fetch is stalled on an Icache miss 317system.cpu.fetch.Insts 16559 # Number of instructions fetch has processed 318system.cpu.fetch.Branches 2854 # Number of branches that fetch encountered 319system.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken 320system.cpu.fetch.Cycles 5759 # Number of cycles fetch has run and was not squashing or blocked 321system.cpu.fetch.SquashCycles 1046 # Number of cycles fetch has spent squashing 322system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 323system.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps 324system.cpu.fetch.CacheLines 2295 # Number of cache lines fetched 325system.cpu.fetch.IcacheSquashes 335 # Number of outstanding Icache misses that were squashed 326system.cpu.fetch.rateDist::samples 15456 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::mean 1.071364 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::stdev 2.458774 # Number of instructions fetched each cycle (Total) 329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::0 12470 80.68% 80.68% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::1 297 1.92% 82.60% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::2 230 1.49% 84.09% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::3 258 1.67% 85.76% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::4 292 1.89% 87.65% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::5 234 1.51% 89.16% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::6 282 1.82% 90.99% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::7 146 0.94% 91.93% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::8 1247 8.07% 100.00% # Number of instructions fetched each cycle (Total) 339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::total 15456 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.branchRate 0.060017 # Number of branch fetches per cycle 344system.cpu.fetch.rate 0.348222 # Number of inst fetches per cycle 345system.cpu.decode.IdleCycles 8339 # Number of cycles decode is idle 346system.cpu.decode.BlockedCycles 4008 # Number of cycles decode is blocked 347system.cpu.decode.RunCycles 2446 # Number of cycles decode is running 348system.cpu.decode.UnblockCycles 214 # Number of cycles decode is unblocking 349system.cpu.decode.SquashCycles 449 # Number of cycles decode is squashing 350system.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch 351system.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction 352system.cpu.decode.DecodedInsts 15004 # Number of instructions handled by decode 353system.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode 354system.cpu.rename.SquashCycles 449 # Number of cycles rename is squashing 355system.cpu.rename.IdleCycles 8498 # Number of cycles rename is idle 356system.cpu.rename.BlockCycles 1841 # Number of cycles rename is blocking 357system.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst 358system.cpu.rename.RunCycles 2476 # Number of cycles rename is running 359system.cpu.rename.UnblockCycles 1537 # Number of cycles rename is unblocking 360system.cpu.rename.RenamedInsts 14448 # Number of instructions processed by rename 361system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 362system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full 363system.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full 364system.cpu.rename.SQFullEvents 1471 # Number of times rename has blocked due to SQ full 365system.cpu.rename.RenamedOperands 10929 # Number of destination operands rename has renamed 366system.cpu.rename.RenameLookups 17896 # Number of register rename lookups that rename has made 367system.cpu.rename.int_rename_lookups 17887 # Number of integer rename lookups 368system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 369system.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed 370system.cpu.rename.UndoneMaps 6352 # Number of HB maps that are undone due to squashing 371system.cpu.rename.serializingInsts 28 # count of serializing insts renamed 372system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed 373system.cpu.rename.skidInsts 585 # count of insts added to the skid buffer 374system.cpu.memDep0.insertedLoads 2834 # Number of loads inserted to the mem dependence unit. 375system.cpu.memDep0.insertedStores 1292 # Number of stores inserted to the mem dependence unit. 376system.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. 377system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. 378system.cpu.iq.iqInstsAdded 13054 # Number of instructions added to the IQ (excludes non-spec) 379system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ 380system.cpu.iq.iqInstsIssued 10776 # Number of instructions issued 381system.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued 382system.cpu.iq.iqSquashedInstsExamined 6695 # Number of squashed instructions iterated over during squash; mainly for profiling 383system.cpu.iq.iqSquashedOperandsExamined 3669 # Number of squashed operands that are examined and possibly removed from graph 384system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed 385system.cpu.iq.issued_per_cycle::samples 15456 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::mean 0.697205 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::stdev 1.442232 # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::0 11416 73.86% 73.86% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::1 1297 8.39% 82.25% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::2 916 5.93% 88.18% # Number of insts issued each cycle 392system.cpu.iq.issued_per_cycle::3 681 4.41% 92.59% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::4 517 3.34% 95.93% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::5 347 2.25% 98.18% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::6 200 1.29% 99.47% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::7 55 0.36% 99.83% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::8 27 0.17% 100.00% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::total 15456 # Number of insts issued each cycle 402system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::IntAlu 21 14.89% 14.89% # attempts to use FU when none available 404system.cpu.iq.fu_full::IntMult 0 0.00% 14.89% # attempts to use FU when none available 405system.cpu.iq.fu_full::IntDiv 0 0.00% 14.89% # attempts to use FU when none available 406system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.89% # attempts to use FU when none available 407system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.89% # attempts to use FU when none available 408system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.89% # attempts to use FU when none available 409system.cpu.iq.fu_full::FloatMult 0 0.00% 14.89% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.89% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.89% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.89% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.89% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.89% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.89% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.89% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.89% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdMult 0 0.00% 14.89% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.89% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdShift 0 0.00% 14.89% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.89% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.89% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.89% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.89% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.89% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.89% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.89% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.89% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.89% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.89% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.89% # attempts to use FU when none available 432system.cpu.iq.fu_full::MemRead 83 58.87% 73.76% # attempts to use FU when none available 433system.cpu.iq.fu_full::MemWrite 37 26.24% 100.00% # attempts to use FU when none available 434system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 435system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 436system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 437system.cpu.iq.FU_type_0::IntAlu 7185 66.68% 66.69% # Type of FU issued 438system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.70% # Type of FU issued 439system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.70% # Type of FU issued 440system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.72% # Type of FU issued 441system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.72% # Type of FU issued 442system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.72% # Type of FU issued 443system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.72% # Type of FU issued 444system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.72% # Type of FU issued 445system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.72% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.72% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.72% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.72% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.72% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.72% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.72% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.72% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.72% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.72% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.72% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.72% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.72% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.72% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.72% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.72% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.72% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.72% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.72% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.72% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.72% # Type of FU issued 466system.cpu.iq.FU_type_0::MemRead 2475 22.97% 89.69% # Type of FU issued 467system.cpu.iq.FU_type_0::MemWrite 1111 10.31% 100.00% # Type of FU issued 468system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 469system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 470system.cpu.iq.FU_type_0::total 10776 # Type of FU issued 471system.cpu.iq.rate 0.226610 # Inst issue rate 472system.cpu.iq.fu_busy_cnt 141 # FU busy when requested 473system.cpu.iq.fu_busy_rate 0.013085 # FU busy rate (busy events/executed inst) 474system.cpu.iq.int_inst_queue_reads 37145 # Number of integer instruction queue reads 475system.cpu.iq.int_inst_queue_writes 19787 # Number of integer instruction queue writes 476system.cpu.iq.int_inst_queue_wakeup_accesses 9745 # Number of integer instruction queue wakeup accesses 477system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 478system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 479system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 480system.cpu.iq.int_alu_accesses 10904 # Number of integer alu accesses 481system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 482system.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores 483system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 484system.cpu.iew.lsq.thread0.squashedLoads 1649 # Number of loads squashed 485system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed 486system.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations 487system.cpu.iew.lsq.thread0.squashedStores 427 # Number of stores squashed 488system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 489system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 490system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 491system.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked 492system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 493system.cpu.iew.iewSquashCycles 449 # Number of cycles IEW is squashing 494system.cpu.iew.iewBlockCycles 1429 # Number of cycles IEW is blocking 495system.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking 496system.cpu.iew.iewDispatchedInsts 13165 # Number of instructions dispatched to IQ 497system.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch 498system.cpu.iew.iewDispLoadInsts 2834 # Number of dispatched load instructions 499system.cpu.iew.iewDispStoreInsts 1292 # Number of dispatched store instructions 500system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 501system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 502system.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall 503system.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations 504system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly 505system.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly 506system.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute 507system.cpu.iew.iewExecutedInsts 10290 # Number of executed instructions 508system.cpu.iew.iewExecLoadInsts 2300 # Number of load instructions executed 509system.cpu.iew.iewExecSquashedInsts 486 # Number of squashed instructions skipped in execute 510system.cpu.iew.exec_swp 0 # number of swp insts executed 511system.cpu.iew.exec_nop 84 # number of nop insts executed 512system.cpu.iew.exec_refs 3376 # number of memory reference insts executed 513system.cpu.iew.exec_branches 1642 # Number of branches executed 514system.cpu.iew.exec_stores 1076 # Number of stores executed 515system.cpu.iew.exec_rate 0.216390 # Inst execution rate 516system.cpu.iew.wb_sent 9948 # cumulative count of insts sent to commit 517system.cpu.iew.wb_count 9755 # cumulative count of insts written-back 518system.cpu.iew.wb_producers 5155 # num instructions producing a value 519system.cpu.iew.wb_consumers 7025 # num instructions consuming a value 520system.cpu.iew.wb_rate 0.205140 # insts written-back per cycle 521system.cpu.iew.wb_fanout 0.733808 # average fanout of values written-back 522system.cpu.commit.commitSquashedInsts 6712 # The number of squashed insts skipped by commit 523system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 524system.cpu.commit.branchMispredicts 408 # The number of times a branch was mispredicted 525system.cpu.commit.committed_per_cycle::samples 14219 # Number of insts commited each cycle 526system.cpu.commit.committed_per_cycle::mean 0.450243 # Number of insts commited each cycle 527system.cpu.commit.committed_per_cycle::stdev 1.361136 # Number of insts commited each cycle 528system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 529system.cpu.commit.committed_per_cycle::0 11792 82.93% 82.93% # Number of insts commited each cycle 530system.cpu.commit.committed_per_cycle::1 1158 8.14% 91.08% # Number of insts commited each cycle 531system.cpu.commit.committed_per_cycle::2 469 3.30% 94.37% # Number of insts commited each cycle 532system.cpu.commit.committed_per_cycle::3 205 1.44% 95.82% # Number of insts commited each cycle 533system.cpu.commit.committed_per_cycle::4 133 0.94% 96.75% # Number of insts commited each cycle 534system.cpu.commit.committed_per_cycle::5 85 0.60% 97.35% # Number of insts commited each cycle 535system.cpu.commit.committed_per_cycle::6 97 0.68% 98.03% # Number of insts commited each cycle 536system.cpu.commit.committed_per_cycle::7 88 0.62% 98.65% # Number of insts commited each cycle 537system.cpu.commit.committed_per_cycle::8 192 1.35% 100.00% # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::total 14219 # Number of insts commited each cycle 542system.cpu.commit.committedInsts 6402 # Number of instructions committed 543system.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed 544system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 545system.cpu.commit.refs 2050 # Number of memory references committed 546system.cpu.commit.loads 1185 # Number of loads committed 547system.cpu.commit.membars 0 # Number of memory barriers committed 548system.cpu.commit.branches 1056 # Number of branches committed 549system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 550system.cpu.commit.int_insts 6319 # Number of committed integer instructions. 551system.cpu.commit.function_calls 127 # Number of function calls committed. 552system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 553system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction 554system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction 555system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction 556system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction 557system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction 558system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction 559system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction 560system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction 561system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction 562system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction 563system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction 564system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction 567system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction 568system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction 569system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction 570system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction 571system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction 572system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction 573system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction 574system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction 576system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction 577system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction 578system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction 579system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction 580system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 581system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 582system.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction 583system.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction 584system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 585system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 586system.cpu.commit.op_class_0::total 6402 # Class of committed instruction 587system.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached 588system.cpu.rob.rob_reads 26790 # The number of ROB reads 589system.cpu.rob.rob_writes 27482 # The number of ROB writes 590system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself 591system.cpu.idleCycles 32097 # Total number of cycles that the CPU has spent unscheduled due to idling 592system.cpu.committedInsts 6385 # Number of Instructions Simulated 593system.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated 594system.cpu.cpi 7.447612 # CPI: Cycles Per Instruction 595system.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads 596system.cpu.ipc 0.134271 # IPC: Instructions Per Cycle 597system.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads 598system.cpu.int_regfile_reads 12923 # number of integer regfile reads 599system.cpu.int_regfile_writes 7437 # number of integer regfile writes 600system.cpu.fp_regfile_reads 8 # number of floating regfile reads 601system.cpu.fp_regfile_writes 2 # number of floating regfile writes 602system.cpu.misc_regfile_reads 1 # number of misc regfile reads 603system.cpu.misc_regfile_writes 1 # number of misc regfile writes 604system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 605system.cpu.dcache.tags.replacements 0 # number of replacements 606system.cpu.dcache.tags.tagsinuse 110.182603 # Cycle average of tags in use 607system.cpu.dcache.tags.total_refs 2402 # Total number of references to valid blocks. 608system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. 609system.cpu.dcache.tags.avg_refs 13.884393 # Average number of references to valid blocks. 610system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 611system.cpu.dcache.tags.occ_blocks::cpu.data 110.182603 # Average occupied blocks per requestor 612system.cpu.dcache.tags.occ_percent::cpu.data 0.026900 # Average percentage of cache occupancy 613system.cpu.dcache.tags.occ_percent::total 0.026900 # Average percentage of cache occupancy 614system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id 615system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 616system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 617system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id 618system.cpu.dcache.tags.tag_accesses 6051 # Number of tag accesses 619system.cpu.dcache.tags.data_accesses 6051 # Number of data accesses 620system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 621system.cpu.dcache.ReadReq_hits::cpu.data 1894 # number of ReadReq hits 622system.cpu.dcache.ReadReq_hits::total 1894 # number of ReadReq hits 623system.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits 624system.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits 625system.cpu.dcache.demand_hits::cpu.data 2402 # number of demand (read+write) hits 626system.cpu.dcache.demand_hits::total 2402 # number of demand (read+write) hits 627system.cpu.dcache.overall_hits::cpu.data 2402 # number of overall hits 628system.cpu.dcache.overall_hits::total 2402 # number of overall hits 629system.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses 630system.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses 631system.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses 632system.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses 633system.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses 634system.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses 635system.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses 636system.cpu.dcache.overall_misses::total 537 # number of overall misses 637system.cpu.dcache.ReadReq_miss_latency::cpu.data 13953000 # number of ReadReq miss cycles 638system.cpu.dcache.ReadReq_miss_latency::total 13953000 # number of ReadReq miss cycles 639system.cpu.dcache.WriteReq_miss_latency::cpu.data 31158482 # number of WriteReq miss cycles 640system.cpu.dcache.WriteReq_miss_latency::total 31158482 # number of WriteReq miss cycles 641system.cpu.dcache.demand_miss_latency::cpu.data 45111482 # number of demand (read+write) miss cycles 642system.cpu.dcache.demand_miss_latency::total 45111482 # number of demand (read+write) miss cycles 643system.cpu.dcache.overall_miss_latency::cpu.data 45111482 # number of overall miss cycles 644system.cpu.dcache.overall_miss_latency::total 45111482 # number of overall miss cycles 645system.cpu.dcache.ReadReq_accesses::cpu.data 2074 # number of ReadReq accesses(hits+misses) 646system.cpu.dcache.ReadReq_accesses::total 2074 # number of ReadReq accesses(hits+misses) 647system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 648system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 649system.cpu.dcache.demand_accesses::cpu.data 2939 # number of demand (read+write) accesses 650system.cpu.dcache.demand_accesses::total 2939 # number of demand (read+write) accesses 651system.cpu.dcache.overall_accesses::cpu.data 2939 # number of overall (read+write) accesses 652system.cpu.dcache.overall_accesses::total 2939 # number of overall (read+write) accesses 653system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086789 # miss rate for ReadReq accesses 654system.cpu.dcache.ReadReq_miss_rate::total 0.086789 # miss rate for ReadReq accesses 655system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses 656system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses 657system.cpu.dcache.demand_miss_rate::cpu.data 0.182715 # miss rate for demand accesses 658system.cpu.dcache.demand_miss_rate::total 0.182715 # miss rate for demand accesses 659system.cpu.dcache.overall_miss_rate::cpu.data 0.182715 # miss rate for overall accesses 660system.cpu.dcache.overall_miss_rate::total 0.182715 # miss rate for overall accesses 661system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77516.666667 # average ReadReq miss latency 662system.cpu.dcache.ReadReq_avg_miss_latency::total 77516.666667 # average ReadReq miss latency 663system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87278.661064 # average WriteReq miss latency 664system.cpu.dcache.WriteReq_avg_miss_latency::total 87278.661064 # average WriteReq miss latency 665system.cpu.dcache.demand_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency 666system.cpu.dcache.demand_avg_miss_latency::total 84006.484171 # average overall miss latency 667system.cpu.dcache.overall_avg_miss_latency::cpu.data 84006.484171 # average overall miss latency 668system.cpu.dcache.overall_avg_miss_latency::total 84006.484171 # average overall miss latency 669system.cpu.dcache.blocked_cycles::no_mshrs 3098 # number of cycles access was blocked 670system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 671system.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked 672system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 673system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.729730 # average number of cycles each access was blocked 674system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 675system.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits 676system.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits 678system.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits 679system.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits 680system.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits 681system.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits 682system.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits 683system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 684system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 685system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 686system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 687system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 688system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 689system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 690system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses 691system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9401500 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.ReadReq_mshr_miss_latency::total 9401500 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7013500 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::total 7013500 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16415000 # number of demand (read+write) MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::total 16415000 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16415000 # number of overall MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::total 16415000 # number of overall MSHR miss cycles 699system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048698 # mshr miss rate for ReadReq accesses 700system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048698 # mshr miss rate for ReadReq accesses 701system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 702system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 703system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for demand accesses 704system.cpu.dcache.demand_mshr_miss_rate::total 0.058864 # mshr miss rate for demand accesses 705system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058864 # mshr miss rate for overall accesses 706system.cpu.dcache.overall_mshr_miss_rate::total 0.058864 # mshr miss rate for overall accesses 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93084.158416 # average ReadReq mshr miss latency 708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93084.158416 # average ReadReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97409.722222 # average WriteReq mshr miss latency 710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97409.722222 # average WriteReq mshr miss latency 711system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency 712system.cpu.dcache.demand_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency 713system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94884.393064 # average overall mshr miss latency 714system.cpu.dcache.overall_avg_mshr_miss_latency::total 94884.393064 # average overall mshr miss latency 715system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 716system.cpu.icache.tags.replacements 0 # number of replacements 717system.cpu.icache.tags.tagsinuse 160.538154 # Cycle average of tags in use 718system.cpu.icache.tags.total_refs 1837 # Total number of references to valid blocks. 719system.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. 720system.cpu.icache.tags.avg_refs 5.869010 # Average number of references to valid blocks. 721system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 722system.cpu.icache.tags.occ_blocks::cpu.inst 160.538154 # Average occupied blocks per requestor 723system.cpu.icache.tags.occ_percent::cpu.inst 0.078388 # Average percentage of cache occupancy 724system.cpu.icache.tags.occ_percent::total 0.078388 # Average percentage of cache occupancy 725system.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id 726system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 727system.cpu.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id 728system.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id 729system.cpu.icache.tags.tag_accesses 4903 # Number of tag accesses 730system.cpu.icache.tags.data_accesses 4903 # Number of data accesses 731system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 732system.cpu.icache.ReadReq_hits::cpu.inst 1837 # number of ReadReq hits 733system.cpu.icache.ReadReq_hits::total 1837 # number of ReadReq hits 734system.cpu.icache.demand_hits::cpu.inst 1837 # number of demand (read+write) hits 735system.cpu.icache.demand_hits::total 1837 # number of demand (read+write) hits 736system.cpu.icache.overall_hits::cpu.inst 1837 # number of overall hits 737system.cpu.icache.overall_hits::total 1837 # number of overall hits 738system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses 739system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses 740system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses 741system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses 742system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses 743system.cpu.icache.overall_misses::total 458 # number of overall misses 744system.cpu.icache.ReadReq_miss_latency::cpu.inst 35507500 # number of ReadReq miss cycles 745system.cpu.icache.ReadReq_miss_latency::total 35507500 # number of ReadReq miss cycles 746system.cpu.icache.demand_miss_latency::cpu.inst 35507500 # number of demand (read+write) miss cycles 747system.cpu.icache.demand_miss_latency::total 35507500 # number of demand (read+write) miss cycles 748system.cpu.icache.overall_miss_latency::cpu.inst 35507500 # number of overall miss cycles 749system.cpu.icache.overall_miss_latency::total 35507500 # number of overall miss cycles 750system.cpu.icache.ReadReq_accesses::cpu.inst 2295 # number of ReadReq accesses(hits+misses) 751system.cpu.icache.ReadReq_accesses::total 2295 # number of ReadReq accesses(hits+misses) 752system.cpu.icache.demand_accesses::cpu.inst 2295 # number of demand (read+write) accesses 753system.cpu.icache.demand_accesses::total 2295 # number of demand (read+write) accesses 754system.cpu.icache.overall_accesses::cpu.inst 2295 # number of overall (read+write) accesses 755system.cpu.icache.overall_accesses::total 2295 # number of overall (read+write) accesses 756system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199564 # miss rate for ReadReq accesses 757system.cpu.icache.ReadReq_miss_rate::total 0.199564 # miss rate for ReadReq accesses 758system.cpu.icache.demand_miss_rate::cpu.inst 0.199564 # miss rate for demand accesses 759system.cpu.icache.demand_miss_rate::total 0.199564 # miss rate for demand accesses 760system.cpu.icache.overall_miss_rate::cpu.inst 0.199564 # miss rate for overall accesses 761system.cpu.icache.overall_miss_rate::total 0.199564 # miss rate for overall accesses 762system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77527.292576 # average ReadReq miss latency 763system.cpu.icache.ReadReq_avg_miss_latency::total 77527.292576 # average ReadReq miss latency 764system.cpu.icache.demand_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency 765system.cpu.icache.demand_avg_miss_latency::total 77527.292576 # average overall miss latency 766system.cpu.icache.overall_avg_miss_latency::cpu.inst 77527.292576 # average overall miss latency 767system.cpu.icache.overall_avg_miss_latency::total 77527.292576 # average overall miss latency 768system.cpu.icache.blocked_cycles::no_mshrs 67 # number of cycles access was blocked 769system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 770system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 771system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 772system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked 773system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 774system.cpu.icache.ReadReq_mshr_hits::cpu.inst 145 # number of ReadReq MSHR hits 775system.cpu.icache.ReadReq_mshr_hits::total 145 # number of ReadReq MSHR hits 776system.cpu.icache.demand_mshr_hits::cpu.inst 145 # number of demand (read+write) MSHR hits 777system.cpu.icache.demand_mshr_hits::total 145 # number of demand (read+write) MSHR hits 778system.cpu.icache.overall_mshr_hits::cpu.inst 145 # number of overall MSHR hits 779system.cpu.icache.overall_mshr_hits::total 145 # number of overall MSHR hits 780system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 781system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 782system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 783system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 784system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 785system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses 786system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26275500 # number of ReadReq MSHR miss cycles 787system.cpu.icache.ReadReq_mshr_miss_latency::total 26275500 # number of ReadReq MSHR miss cycles 788system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26275500 # number of demand (read+write) MSHR miss cycles 789system.cpu.icache.demand_mshr_miss_latency::total 26275500 # number of demand (read+write) MSHR miss cycles 790system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26275500 # number of overall MSHR miss cycles 791system.cpu.icache.overall_mshr_miss_latency::total 26275500 # number of overall MSHR miss cycles 792system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for ReadReq accesses 793system.cpu.icache.ReadReq_mshr_miss_rate::total 0.136383 # mshr miss rate for ReadReq accesses 794system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for demand accesses 795system.cpu.icache.demand_mshr_miss_rate::total 0.136383 # mshr miss rate for demand accesses 796system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136383 # mshr miss rate for overall accesses 797system.cpu.icache.overall_mshr_miss_rate::total 0.136383 # mshr miss rate for overall accesses 798system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83947.284345 # average ReadReq mshr miss latency 799system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83947.284345 # average ReadReq mshr miss latency 800system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency 801system.cpu.icache.demand_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency 802system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83947.284345 # average overall mshr miss latency 803system.cpu.icache.overall_avg_mshr_miss_latency::total 83947.284345 # average overall mshr miss latency 804system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 805system.cpu.l2cache.tags.replacements 0 # number of replacements 806system.cpu.l2cache.tags.tagsinuse 270.818986 # Cycle average of tags in use 807system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 808system.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. 809system.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. 810system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 811system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.559983 # Average occupied blocks per requestor 812system.cpu.l2cache.tags.occ_blocks::cpu.data 110.259003 # Average occupied blocks per requestor 813system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004900 # Average percentage of cache occupancy 814system.cpu.l2cache.tags.occ_percent::cpu.data 0.003365 # Average percentage of cache occupancy 815system.cpu.l2cache.tags.occ_percent::total 0.008265 # Average percentage of cache occupancy 816system.cpu.l2cache.tags.occ_task_id_blocks::1024 485 # Occupied blocks per task id 817system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id 818system.cpu.l2cache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id 819system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014801 # Percentage of cache occupancy per task id 820system.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses 821system.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses 822system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 823system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 824system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 825system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 826system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 827system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 828system.cpu.l2cache.overall_hits::total 1 # number of overall hits 829system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 830system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 831system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 312 # number of ReadCleanReq misses 832system.cpu.l2cache.ReadCleanReq_misses::total 312 # number of ReadCleanReq misses 833system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 834system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses 835system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses 836system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses 837system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses 838system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses 839system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses 840system.cpu.l2cache.overall_misses::total 485 # number of overall misses 841system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6902500 # number of ReadExReq miss cycles 842system.cpu.l2cache.ReadExReq_miss_latency::total 6902500 # number of ReadExReq miss cycles 843system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25792500 # number of ReadCleanReq miss cycles 844system.cpu.l2cache.ReadCleanReq_miss_latency::total 25792500 # number of ReadCleanReq miss cycles 845system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9241500 # number of ReadSharedReq miss cycles 846system.cpu.l2cache.ReadSharedReq_miss_latency::total 9241500 # number of ReadSharedReq miss cycles 847system.cpu.l2cache.demand_miss_latency::cpu.inst 25792500 # number of demand (read+write) miss cycles 848system.cpu.l2cache.demand_miss_latency::cpu.data 16144000 # number of demand (read+write) miss cycles 849system.cpu.l2cache.demand_miss_latency::total 41936500 # number of demand (read+write) miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.inst 25792500 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::cpu.data 16144000 # number of overall miss cycles 852system.cpu.l2cache.overall_miss_latency::total 41936500 # number of overall miss cycles 853system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 854system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 855system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) 856system.cpu.l2cache.ReadCleanReq_accesses::total 313 # number of ReadCleanReq accesses(hits+misses) 857system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) 858system.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) 859system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses 860system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses 861system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses 862system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses 863system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses 864system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses 865system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 866system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 867system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadCleanReq accesses 868system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996805 # miss rate for ReadCleanReq accesses 869system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 870system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 871system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses 872system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 873system.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses 874system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses 875system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 876system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses 877system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 95868.055556 # average ReadExReq miss latency 878system.cpu.l2cache.ReadExReq_avg_miss_latency::total 95868.055556 # average ReadExReq miss latency 879system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82668.269231 # average ReadCleanReq miss latency 880system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82668.269231 # average ReadCleanReq miss latency 881system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91500 # average ReadSharedReq miss latency 882system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91500 # average ReadSharedReq miss latency 883system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency 884system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency 885system.cpu.l2cache.demand_avg_miss_latency::total 86467.010309 # average overall miss latency 886system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82668.269231 # average overall miss latency 887system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93317.919075 # average overall miss latency 888system.cpu.l2cache.overall_avg_miss_latency::total 86467.010309 # average overall miss latency 889system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 890system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 891system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 894system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 895system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 896system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 897system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses 898system.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses 899system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 900system.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses 901system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 902system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 903system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses 904system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 905system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 906system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses 907system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6182500 # number of ReadExReq MSHR miss cycles 908system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6182500 # number of ReadExReq MSHR miss cycles 909system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22672500 # number of ReadCleanReq MSHR miss cycles 910system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22672500 # number of ReadCleanReq MSHR miss cycles 911system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8231500 # number of ReadSharedReq MSHR miss cycles 912system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8231500 # number of ReadSharedReq MSHR miss cycles 913system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22672500 # number of demand (read+write) MSHR miss cycles 914system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14414000 # number of demand (read+write) MSHR miss cycles 915system.cpu.l2cache.demand_mshr_miss_latency::total 37086500 # number of demand (read+write) MSHR miss cycles 916system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22672500 # number of overall MSHR miss cycles 917system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14414000 # number of overall MSHR miss cycles 918system.cpu.l2cache.overall_mshr_miss_latency::total 37086500 # number of overall MSHR miss cycles 919system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 920system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 921system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses 922system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses 923system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 924system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 925system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 926system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 927system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses 928system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 929system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 930system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses 931system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85868.055556 # average ReadExReq mshr miss latency 932system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85868.055556 # average ReadExReq mshr miss latency 933system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72668.269231 # average ReadCleanReq mshr miss latency 934system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72668.269231 # average ReadCleanReq mshr miss latency 935system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81500 # average ReadSharedReq mshr miss latency 936system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81500 # average ReadSharedReq mshr miss latency 937system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency 938system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency 939system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency 940system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72668.269231 # average overall mshr miss latency 941system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83317.919075 # average overall mshr miss latency 942system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76467.010309 # average overall mshr miss latency 943system.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. 944system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 945system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 946system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 947system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 948system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 949system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 950system.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution 951system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 952system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 953system.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution 954system.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution 955system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) 956system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) 957system.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes) 958system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20032 # Cumulative packet size per connected master and slave (bytes) 959system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) 960system.cpu.toL2Bus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) 961system.cpu.toL2Bus.snoops 0 # Total snoops (count) 962system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 963system.cpu.toL2Bus.snoop_fanout::samples 486 # Request fanout histogram 964system.cpu.toL2Bus.snoop_fanout::mean 0.002058 # Request fanout histogram 965system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram 966system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 967system.cpu.toL2Bus.snoop_fanout::0 485 99.79% 99.79% # Request fanout histogram 968system.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram 969system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 970system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 971system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 972system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 973system.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram 974system.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) 975system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 976system.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) 977system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 978system.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) 979system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 980system.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. 981system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 982system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 983system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 984system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 985system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 986system.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 987system.membus.trans_dist::ReadResp 413 # Transaction distribution 988system.membus.trans_dist::ReadExReq 72 # Transaction distribution 989system.membus.trans_dist::ReadExResp 72 # Transaction distribution 990system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution 991system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes) 992system.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes) 993system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes) 994system.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) 995system.membus.snoops 0 # Total snoops (count) 996system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 997system.membus.snoop_fanout::samples 485 # Request fanout histogram 998system.membus.snoop_fanout::mean 0 # Request fanout histogram 999system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1000system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1001system.membus.snoop_fanout::0 485 100.00% 100.00% # Request fanout histogram 1002system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1003system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1004system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1005system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1006system.membus.snoop_fanout::total 485 # Request fanout histogram 1007system.membus.reqLayer0.occupancy 595000 # Layer occupancy (ticks) 1008system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) 1009system.membus.respLayer1.occupancy 2572250 # Layer occupancy (ticks) 1010system.membus.respLayer1.utilization 10.8 # Layer utilization (%) 1011 1012---------- End Simulation Statistics ---------- 1013