stats.txt revision 10242:cb4e86c17767
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21025000 # Number of ticks simulated 5final_tick 21025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 63804 # Simulator instruction rate (inst/s) 8host_op_rate 63793 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 210460029 # Simulator tick rate (ticks/s) 10host_mem_usage 221600 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host 12sim_insts 6372 # Number of instructions simulated 13sim_ops 6372 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 18system.physmem.bytes_read::total 31168 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 487 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 952770511 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 529655172 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1482425684 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 952770511 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 952770511 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 952770511 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 529655172 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1482425684 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 488 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 31232 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 69 # Per bank write bursts 45system.physmem.perBankRdBursts::1 34 # Per bank write bursts 46system.physmem.perBankRdBursts::2 32 # Per bank write bursts 47system.physmem.perBankRdBursts::3 47 # Per bank write bursts 48system.physmem.perBankRdBursts::4 43 # Per bank write bursts 49system.physmem.perBankRdBursts::5 21 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1 # Per bank write bursts 51system.physmem.perBankRdBursts::7 3 # Per bank write bursts 52system.physmem.perBankRdBursts::8 0 # Per bank write bursts 53system.physmem.perBankRdBursts::9 1 # Per bank write bursts 54system.physmem.perBankRdBursts::10 23 # Per bank write bursts 55system.physmem.perBankRdBursts::11 24 # Per bank write bursts 56system.physmem.perBankRdBursts::12 14 # Per bank write bursts 57system.physmem.perBankRdBursts::13 119 # Per bank write bursts 58system.physmem.perBankRdBursts::14 45 # Per bank write bursts 59system.physmem.perBankRdBursts::15 12 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 20992000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 488 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 351.594937 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 222.888418 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 329.838248 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 22 27.85% 27.85% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 18 22.78% 50.63% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 11 13.92% 64.56% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 8 10.13% 74.68% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 5 6.33% 81.01% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 1.27% 82.28% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 2.53% 84.81% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 2.53% 87.34% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation 203system.physmem.totQLat 4169250 # Total ticks spent queuing 204system.physmem.totMemAccLat 13319250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2440000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 8543.55 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 27293.55 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1485.47 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1485.47 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.61 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.61 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 394 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.74 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 43016.39 # Average gap between requests 224system.physmem.pageHitRate 80.74 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 22000 # Time in different power states 226system.physmem.memoryStateTime::REF 520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 15304250 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 1482425684 # Throughput (bytes/s) 231system.membus.trans_dist::ReadReq 416 # Transaction distribution 232system.membus.trans_dist::ReadResp 415 # Transaction distribution 233system.membus.trans_dist::ReadExReq 72 # Transaction distribution 234system.membus.trans_dist::ReadExResp 72 # Transaction distribution 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 31168 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 241system.membus.reqLayer0.occupancy 617000 # Layer occupancy (ticks) 242system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 243system.membus.respLayer1.occupancy 4554750 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 21.7 # Layer utilization (%) 245system.cpu_clk_domain.clock 500 # Clock period in ticks 246system.cpu.branchPred.lookups 2922 # Number of BP lookups 247system.cpu.branchPred.condPredicted 1714 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 512 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 2236 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 763 # Number of BTB hits 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 252system.cpu.branchPred.BTBHitPct 34.123435 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 417 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 255system.cpu.dtb.fetch_hits 0 # ITB hits 256system.cpu.dtb.fetch_misses 0 # ITB misses 257system.cpu.dtb.fetch_acv 0 # ITB acv 258system.cpu.dtb.fetch_accesses 0 # ITB accesses 259system.cpu.dtb.read_hits 2080 # DTB read hits 260system.cpu.dtb.read_misses 47 # DTB read misses 261system.cpu.dtb.read_acv 0 # DTB read access violations 262system.cpu.dtb.read_accesses 2127 # DTB read accesses 263system.cpu.dtb.write_hits 1064 # DTB write hits 264system.cpu.dtb.write_misses 31 # DTB write misses 265system.cpu.dtb.write_acv 0 # DTB write access violations 266system.cpu.dtb.write_accesses 1095 # DTB write accesses 267system.cpu.dtb.data_hits 3144 # DTB hits 268system.cpu.dtb.data_misses 78 # DTB misses 269system.cpu.dtb.data_acv 0 # DTB access violations 270system.cpu.dtb.data_accesses 3222 # DTB accesses 271system.cpu.itb.fetch_hits 2403 # ITB hits 272system.cpu.itb.fetch_misses 39 # ITB misses 273system.cpu.itb.fetch_acv 0 # ITB acv 274system.cpu.itb.fetch_accesses 2442 # ITB accesses 275system.cpu.itb.read_hits 0 # DTB read hits 276system.cpu.itb.read_misses 0 # DTB read misses 277system.cpu.itb.read_acv 0 # DTB read access violations 278system.cpu.itb.read_accesses 0 # DTB read accesses 279system.cpu.itb.write_hits 0 # DTB write hits 280system.cpu.itb.write_misses 0 # DTB write misses 281system.cpu.itb.write_acv 0 # DTB write access violations 282system.cpu.itb.write_accesses 0 # DTB write accesses 283system.cpu.itb.data_hits 0 # DTB hits 284system.cpu.itb.data_misses 0 # DTB misses 285system.cpu.itb.data_acv 0 # DTB access violations 286system.cpu.itb.data_accesses 0 # DTB accesses 287system.cpu.workload.num_syscalls 17 # Number of system calls 288system.cpu.numCycles 42051 # number of cpu cycles simulated 289system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 290system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 291system.cpu.fetch.icacheStallCycles 8528 # Number of cycles fetch is stalled on an Icache miss 292system.cpu.fetch.Insts 16754 # Number of instructions fetch has processed 293system.cpu.fetch.Branches 2922 # Number of branches that fetch encountered 294system.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken 295system.cpu.fetch.Cycles 2995 # Number of cycles fetch has run and was not squashing or blocked 296system.cpu.fetch.SquashCycles 1927 # Number of cycles fetch has spent squashing 297system.cpu.fetch.BlockedCycles 1100 # Number of cycles fetch has spent blocked 298system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 299system.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps 300system.cpu.fetch.CacheLines 2403 # Number of cache lines fetched 301system.cpu.fetch.IcacheSquashes 389 # Number of outstanding Icache misses that were squashed 302system.cpu.fetch.rateDist::samples 14718 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::mean 1.138334 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::stdev 2.533627 # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::0 11723 79.65% 79.65% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::1 324 2.20% 81.85% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::2 234 1.59% 83.44% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::3 214 1.45% 84.90% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::4 255 1.73% 86.63% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::5 243 1.65% 88.28% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::6 264 1.79% 90.07% # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::7 187 1.27% 91.34% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::8 1274 8.66% 100.00% # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::total 14718 # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.branchRate 0.069487 # Number of branch fetches per cycle 320system.cpu.fetch.rate 0.398421 # Number of inst fetches per cycle 321system.cpu.decode.IdleCycles 9297 # Number of cycles decode is idle 322system.cpu.decode.BlockedCycles 1311 # Number of cycles decode is blocked 323system.cpu.decode.RunCycles 2827 # Number of cycles decode is running 324system.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking 325system.cpu.decode.SquashCycles 1242 # Number of cycles decode is squashing 326system.cpu.decode.BranchResolved 247 # Number of times decode resolved a branch 327system.cpu.decode.BranchMispred 86 # Number of times decode detected a branch misprediction 328system.cpu.decode.DecodedInsts 15491 # Number of instructions handled by decode 329system.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode 330system.cpu.rename.SquashCycles 1242 # Number of cycles rename is squashing 331system.cpu.rename.IdleCycles 9496 # Number of cycles rename is idle 332system.cpu.rename.BlockCycles 220 # Number of cycles rename is blocking 333system.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst 334system.cpu.rename.RunCycles 2672 # Number of cycles rename is running 335system.cpu.rename.UnblockCycles 534 # Number of cycles rename is unblocking 336system.cpu.rename.RenamedInsts 14802 # Number of instructions processed by rename 337system.cpu.rename.ROBFullEvents 11 # Number of times rename has blocked due to ROB full 338system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full 339system.cpu.rename.LQFullEvents 4 # Number of times rename has blocked due to LQ full 340system.cpu.rename.SQFullEvents 481 # Number of times rename has blocked due to SQ full 341system.cpu.rename.RenamedOperands 11114 # Number of destination operands rename has renamed 342system.cpu.rename.RenameLookups 18470 # Number of register rename lookups that rename has made 343system.cpu.rename.int_rename_lookups 18461 # Number of integer rename lookups 344system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 345system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 346system.cpu.rename.UndoneMaps 6544 # Number of HB maps that are undone due to squashing 347system.cpu.rename.serializingInsts 31 # count of serializing insts renamed 348system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed 349system.cpu.rename.skidInsts 484 # count of insts added to the skid buffer 350system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 351system.cpu.memDep0.insertedStores 1358 # Number of stores inserted to the mem dependence unit. 352system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 353system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 354system.cpu.iq.iqInstsAdded 13092 # Number of instructions added to the IQ (excludes non-spec) 355system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ 356system.cpu.iq.iqInstsIssued 10822 # Number of instructions issued 357system.cpu.iq.iqSquashedInstsIssued 61 # Number of squashed instructions issued 358system.cpu.iq.iqSquashedInstsExamined 6316 # Number of squashed instructions iterated over during squash; mainly for profiling 359system.cpu.iq.iqSquashedOperandsExamined 3704 # Number of squashed operands that are examined and possibly removed from graph 360system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 361system.cpu.iq.issued_per_cycle::samples 14718 # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::mean 0.735290 # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::stdev 1.419888 # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::0 10506 71.38% 71.38% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::1 1362 9.25% 80.64% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::2 966 6.56% 87.20% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::3 797 5.42% 92.61% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::4 583 3.96% 96.58% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::5 288 1.96% 98.53% # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::6 161 1.09% 99.63% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::7 41 0.28% 99.90% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::total 14718 # Number of insts issued each cycle 378system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 379system.cpu.iq.fu_full::IntAlu 18 15.38% 15.38% # attempts to use FU when none available 380system.cpu.iq.fu_full::IntMult 0 0.00% 15.38% # attempts to use FU when none available 381system.cpu.iq.fu_full::IntDiv 0 0.00% 15.38% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.38% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.38% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.38% # attempts to use FU when none available 385system.cpu.iq.fu_full::FloatMult 0 0.00% 15.38% # attempts to use FU when none available 386system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.38% # attempts to use FU when none available 387system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.38% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.38% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.38% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.38% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.38% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.38% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.38% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdMult 0 0.00% 15.38% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.38% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdShift 0 0.00% 15.38% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.38% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.38% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.38% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.38% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.38% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.38% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.38% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.38% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.38% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.38% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.38% # attempts to use FU when none available 408system.cpu.iq.fu_full::MemRead 61 52.14% 67.52% # attempts to use FU when none available 409system.cpu.iq.fu_full::MemWrite 38 32.48% 100.00% # attempts to use FU when none available 410system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 411system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 412system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 413system.cpu.iq.FU_type_0::IntAlu 7283 67.30% 67.32% # Type of FU issued 414system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.33% # Type of FU issued 415system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.33% # Type of FU issued 416system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.34% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.34% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.34% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.34% # Type of FU issued 420system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.34% # Type of FU issued 421system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.34% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.34% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.34% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.34% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.34% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.34% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.34% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.34% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.34% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.34% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.34% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.34% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.34% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.34% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.34% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.34% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.34% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.34% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.34% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.34% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.34% # Type of FU issued 442system.cpu.iq.FU_type_0::MemRead 2401 22.19% 89.53% # Type of FU issued 443system.cpu.iq.FU_type_0::MemWrite 1133 10.47% 100.00% # Type of FU issued 444system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 445system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 446system.cpu.iq.FU_type_0::total 10822 # Type of FU issued 447system.cpu.iq.rate 0.257354 # Inst issue rate 448system.cpu.iq.fu_busy_cnt 117 # FU busy when requested 449system.cpu.iq.fu_busy_rate 0.010811 # FU busy rate (busy events/executed inst) 450system.cpu.iq.int_inst_queue_reads 36519 # Number of integer instruction queue reads 451system.cpu.iq.int_inst_queue_writes 19441 # Number of integer instruction queue writes 452system.cpu.iq.int_inst_queue_wakeup_accesses 9646 # Number of integer instruction queue wakeup accesses 453system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 454system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 455system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 456system.cpu.iq.int_alu_accesses 10926 # Number of integer alu accesses 457system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 458system.cpu.iew.lsq.thread0.forwLoads 74 # Number of loads that had data forwarded from stores 459system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 460system.cpu.iew.lsq.thread0.squashedLoads 1607 # Number of loads squashed 461system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 462system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations 463system.cpu.iew.lsq.thread0.squashedStores 493 # Number of stores squashed 464system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 465system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 466system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 467system.cpu.iew.lsq.thread0.cacheBlocked 138 # Number of times an access to memory failed due to the cache being blocked 468system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 469system.cpu.iew.iewSquashCycles 1242 # Number of cycles IEW is squashing 470system.cpu.iew.iewBlockCycles 105 # Number of cycles IEW is blocking 471system.cpu.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking 472system.cpu.iew.iewDispatchedInsts 13210 # Number of instructions dispatched to IQ 473system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch 474system.cpu.iew.iewDispLoadInsts 2790 # Number of dispatched load instructions 475system.cpu.iew.iewDispStoreInsts 1358 # Number of dispatched store instructions 476system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions 477system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 478system.cpu.iew.iewLSQFullEvents 36 # Number of times the LSQ has become full, causing a stall 479system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations 480system.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly 481system.cpu.iew.predictedNotTakenIncorrect 383 # Number of branches that were predicted not taken incorrectly 482system.cpu.iew.branchMispredicts 506 # Number of branch mispredicts detected at execute 483system.cpu.iew.iewExecutedInsts 10117 # Number of executed instructions 484system.cpu.iew.iewExecLoadInsts 2138 # Number of load instructions executed 485system.cpu.iew.iewExecSquashedInsts 705 # Number of squashed instructions skipped in execute 486system.cpu.iew.exec_swp 0 # number of swp insts executed 487system.cpu.iew.exec_nop 89 # number of nop insts executed 488system.cpu.iew.exec_refs 3235 # number of memory reference insts executed 489system.cpu.iew.exec_branches 1594 # Number of branches executed 490system.cpu.iew.exec_stores 1097 # Number of stores executed 491system.cpu.iew.exec_rate 0.240589 # Inst execution rate 492system.cpu.iew.wb_sent 9800 # cumulative count of insts sent to commit 493system.cpu.iew.wb_count 9656 # cumulative count of insts written-back 494system.cpu.iew.wb_producers 5168 # num instructions producing a value 495system.cpu.iew.wb_consumers 7004 # num instructions consuming a value 496system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 497system.cpu.iew.wb_rate 0.229626 # insts written-back per cycle 498system.cpu.iew.wb_fanout 0.737864 # average fanout of values written-back 499system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 500system.cpu.commit.commitSquashedInsts 6822 # The number of squashed insts skipped by commit 501system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 502system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted 503system.cpu.commit.committed_per_cycle::samples 13476 # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::mean 0.474102 # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::stdev 1.366169 # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::0 10977 81.46% 81.46% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::1 1202 8.92% 90.38% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::2 500 3.71% 94.09% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::3 222 1.65% 95.73% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::4 141 1.05% 96.78% # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::5 79 0.59% 97.37% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::6 99 0.73% 98.10% # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::7 80 0.59% 98.69% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::8 176 1.31% 100.00% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::total 13476 # Number of insts commited each cycle 520system.cpu.commit.committedInsts 6389 # Number of instructions committed 521system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 522system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 523system.cpu.commit.refs 2048 # Number of memory references committed 524system.cpu.commit.loads 1183 # Number of loads committed 525system.cpu.commit.membars 0 # Number of memory barriers committed 526system.cpu.commit.branches 1050 # Number of branches committed 527system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 528system.cpu.commit.int_insts 6307 # Number of committed integer instructions. 529system.cpu.commit.function_calls 127 # Number of function calls committed. 530system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 531system.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction 532system.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction 533system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction 534system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction 535system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction 536system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction 537system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction 538system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction 539system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 553system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 554system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 555system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 556system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 557system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 558system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 559system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 560system.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 561system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 562system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 563system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 564system.cpu.commit.op_class_0::total 6389 # Class of committed instruction 565system.cpu.commit.bw_lim_events 176 # number cycles where commit BW limit reached 566system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 567system.cpu.rob.rob_reads 26160 # The number of ROB reads 568system.cpu.rob.rob_writes 27673 # The number of ROB writes 569system.cpu.timesIdled 280 # Number of times that the entire CPU went into an idle state and unscheduled itself 570system.cpu.idleCycles 27333 # Total number of cycles that the CPU has spent unscheduled due to idling 571system.cpu.committedInsts 6372 # Number of Instructions Simulated 572system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 573system.cpu.cpi 6.599341 # CPI: Cycles Per Instruction 574system.cpu.cpi_total 6.599341 # CPI: Total CPI of All Threads 575system.cpu.ipc 0.151530 # IPC: Instructions Per Cycle 576system.cpu.ipc_total 0.151530 # IPC: Total IPC of All Threads 577system.cpu.int_regfile_reads 12844 # number of integer regfile reads 578system.cpu.int_regfile_writes 7306 # number of integer regfile writes 579system.cpu.fp_regfile_reads 8 # number of floating regfile reads 580system.cpu.fp_regfile_writes 2 # number of floating regfile writes 581system.cpu.misc_regfile_reads 1 # number of misc regfile reads 582system.cpu.misc_regfile_writes 1 # number of misc regfile writes 583system.cpu.toL2Bus.throughput 1485469679 # Throughput (bytes/s) 584system.cpu.toL2Bus.trans_dist::ReadReq 417 # Transaction distribution 585system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution 586system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 587system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 588system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes) 589system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) 590system.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes) 591system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) 592system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 593system.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) 594system.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) 595system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 596system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) 597system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 598system.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) 599system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) 600system.cpu.toL2Bus.respLayer1.occupancy 276750 # Layer occupancy (ticks) 601system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 602system.cpu.icache.tags.replacements 0 # number of replacements 603system.cpu.icache.tags.tagsinuse 159.493349 # Cycle average of tags in use 604system.cpu.icache.tags.total_refs 1913 # Total number of references to valid blocks. 605system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. 606system.cpu.icache.tags.avg_refs 6.092357 # Average number of references to valid blocks. 607system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 608system.cpu.icache.tags.occ_blocks::cpu.inst 159.493349 # Average occupied blocks per requestor 609system.cpu.icache.tags.occ_percent::cpu.inst 0.077878 # Average percentage of cache occupancy 610system.cpu.icache.tags.occ_percent::total 0.077878 # Average percentage of cache occupancy 611system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 614system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id 615system.cpu.icache.tags.tag_accesses 5120 # Number of tag accesses 616system.cpu.icache.tags.data_accesses 5120 # Number of data accesses 617system.cpu.icache.ReadReq_hits::cpu.inst 1913 # number of ReadReq hits 618system.cpu.icache.ReadReq_hits::total 1913 # number of ReadReq hits 619system.cpu.icache.demand_hits::cpu.inst 1913 # number of demand (read+write) hits 620system.cpu.icache.demand_hits::total 1913 # number of demand (read+write) hits 621system.cpu.icache.overall_hits::cpu.inst 1913 # number of overall hits 622system.cpu.icache.overall_hits::total 1913 # number of overall hits 623system.cpu.icache.ReadReq_misses::cpu.inst 490 # number of ReadReq misses 624system.cpu.icache.ReadReq_misses::total 490 # number of ReadReq misses 625system.cpu.icache.demand_misses::cpu.inst 490 # number of demand (read+write) misses 626system.cpu.icache.demand_misses::total 490 # number of demand (read+write) misses 627system.cpu.icache.overall_misses::cpu.inst 490 # number of overall misses 628system.cpu.icache.overall_misses::total 490 # number of overall misses 629system.cpu.icache.ReadReq_miss_latency::cpu.inst 31404750 # number of ReadReq miss cycles 630system.cpu.icache.ReadReq_miss_latency::total 31404750 # number of ReadReq miss cycles 631system.cpu.icache.demand_miss_latency::cpu.inst 31404750 # number of demand (read+write) miss cycles 632system.cpu.icache.demand_miss_latency::total 31404750 # number of demand (read+write) miss cycles 633system.cpu.icache.overall_miss_latency::cpu.inst 31404750 # number of overall miss cycles 634system.cpu.icache.overall_miss_latency::total 31404750 # number of overall miss cycles 635system.cpu.icache.ReadReq_accesses::cpu.inst 2403 # number of ReadReq accesses(hits+misses) 636system.cpu.icache.ReadReq_accesses::total 2403 # number of ReadReq accesses(hits+misses) 637system.cpu.icache.demand_accesses::cpu.inst 2403 # number of demand (read+write) accesses 638system.cpu.icache.demand_accesses::total 2403 # number of demand (read+write) accesses 639system.cpu.icache.overall_accesses::cpu.inst 2403 # number of overall (read+write) accesses 640system.cpu.icache.overall_accesses::total 2403 # number of overall (read+write) accesses 641system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.203912 # miss rate for ReadReq accesses 642system.cpu.icache.ReadReq_miss_rate::total 0.203912 # miss rate for ReadReq accesses 643system.cpu.icache.demand_miss_rate::cpu.inst 0.203912 # miss rate for demand accesses 644system.cpu.icache.demand_miss_rate::total 0.203912 # miss rate for demand accesses 645system.cpu.icache.overall_miss_rate::cpu.inst 0.203912 # miss rate for overall accesses 646system.cpu.icache.overall_miss_rate::total 0.203912 # miss rate for overall accesses 647system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64091.326531 # average ReadReq miss latency 648system.cpu.icache.ReadReq_avg_miss_latency::total 64091.326531 # average ReadReq miss latency 649system.cpu.icache.demand_avg_miss_latency::cpu.inst 64091.326531 # average overall miss latency 650system.cpu.icache.demand_avg_miss_latency::total 64091.326531 # average overall miss latency 651system.cpu.icache.overall_avg_miss_latency::cpu.inst 64091.326531 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::total 64091.326531 # average overall miss latency 653system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 654system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 656system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 658system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu.icache.fast_writes 0 # number of fast writes performed 660system.cpu.icache.cache_copies 0 # number of cache copies performed 661system.cpu.icache.ReadReq_mshr_hits::cpu.inst 175 # number of ReadReq MSHR hits 662system.cpu.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits 663system.cpu.icache.demand_mshr_hits::cpu.inst 175 # number of demand (read+write) MSHR hits 664system.cpu.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits 665system.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits 666system.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits 667system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 668system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 669system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 670system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 671system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 672system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses 673system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22044500 # number of ReadReq MSHR miss cycles 674system.cpu.icache.ReadReq_mshr_miss_latency::total 22044500 # number of ReadReq MSHR miss cycles 675system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22044500 # number of demand (read+write) MSHR miss cycles 676system.cpu.icache.demand_mshr_miss_latency::total 22044500 # number of demand (read+write) MSHR miss cycles 677system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22044500 # number of overall MSHR miss cycles 678system.cpu.icache.overall_mshr_miss_latency::total 22044500 # number of overall MSHR miss cycles 679system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for ReadReq accesses 680system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131086 # mshr miss rate for ReadReq accesses 681system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for demand accesses 682system.cpu.icache.demand_mshr_miss_rate::total 0.131086 # mshr miss rate for demand accesses 683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131086 # mshr miss rate for overall accesses 684system.cpu.icache.overall_mshr_miss_rate::total 0.131086 # mshr miss rate for overall accesses 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69982.539683 # average ReadReq mshr miss latency 686system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69982.539683 # average ReadReq mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69982.539683 # average overall mshr miss latency 688system.cpu.icache.demand_avg_mshr_miss_latency::total 69982.539683 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69982.539683 # average overall mshr miss latency 690system.cpu.icache.overall_avg_mshr_miss_latency::total 69982.539683 # average overall mshr miss latency 691system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 692system.cpu.l2cache.tags.replacements 0 # number of replacements 693system.cpu.l2cache.tags.tagsinuse 219.991091 # Cycle average of tags in use 694system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 695system.cpu.l2cache.tags.sampled_refs 415 # Sample count of references to valid blocks. 696system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. 697system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 698system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.576725 # Average occupied blocks per requestor 699system.cpu.l2cache.tags.occ_blocks::cpu.data 60.414366 # Average occupied blocks per requestor 700system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004870 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::cpu.data 0.001844 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_percent::total 0.006714 # Average percentage of cache occupancy 703system.cpu.l2cache.tags.occ_task_id_blocks::1024 415 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id 706system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012665 # Percentage of cache occupancy per task id 707system.cpu.l2cache.tags.tag_accesses 4399 # Number of tag accesses 708system.cpu.l2cache.tags.data_accesses 4399 # Number of data accesses 709system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 710system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 711system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 712system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 713system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 714system.cpu.l2cache.overall_hits::total 1 # number of overall hits 715system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses 716system.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses 717system.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses 718system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 719system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 720system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses 721system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 722system.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses 723system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses 724system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 725system.cpu.l2cache.overall_misses::total 488 # number of overall misses 726system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21718500 # number of ReadReq miss cycles 727system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7799500 # number of ReadReq miss cycles 728system.cpu.l2cache.ReadReq_miss_latency::total 29518000 # number of ReadReq miss cycles 729system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5388750 # number of ReadExReq miss cycles 730system.cpu.l2cache.ReadExReq_miss_latency::total 5388750 # number of ReadExReq miss cycles 731system.cpu.l2cache.demand_miss_latency::cpu.inst 21718500 # number of demand (read+write) miss cycles 732system.cpu.l2cache.demand_miss_latency::cpu.data 13188250 # number of demand (read+write) miss cycles 733system.cpu.l2cache.demand_miss_latency::total 34906750 # number of demand (read+write) miss cycles 734system.cpu.l2cache.overall_miss_latency::cpu.inst 21718500 # number of overall miss cycles 735system.cpu.l2cache.overall_miss_latency::cpu.data 13188250 # number of overall miss cycles 736system.cpu.l2cache.overall_miss_latency::total 34906750 # number of overall miss cycles 737system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) 738system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) 739system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses) 740system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 741system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 742system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses 743system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 744system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses 745system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses 746system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 747system.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses 748system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses 749system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 750system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses 751system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 752system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 753system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses 754system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 755system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses 756system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses 757system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 758system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses 759system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69167.197452 # average ReadReq miss latency 760system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76465.686275 # average ReadReq miss latency 761system.cpu.l2cache.ReadReq_avg_miss_latency::total 70956.730769 # average ReadReq miss latency 762system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74843.750000 # average ReadExReq miss latency 763system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74843.750000 # average ReadExReq miss latency 764system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69167.197452 # average overall miss latency 765system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75794.540230 # average overall miss latency 766system.cpu.l2cache.demand_avg_miss_latency::total 71530.225410 # average overall miss latency 767system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69167.197452 # average overall miss latency 768system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75794.540230 # average overall miss latency 769system.cpu.l2cache.overall_avg_miss_latency::total 71530.225410 # average overall miss latency 770system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 771system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 772system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 773system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 774system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 775system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 776system.cpu.l2cache.fast_writes 0 # number of fast writes performed 777system.cpu.l2cache.cache_copies 0 # number of cache copies performed 778system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 779system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 780system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses 781system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 782system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 783system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 784system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 785system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses 786system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 787system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 788system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses 789system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17765000 # number of ReadReq MSHR miss cycles 790system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6546500 # number of ReadReq MSHR miss cycles 791system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24311500 # number of ReadReq MSHR miss cycles 792system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4505750 # number of ReadExReq MSHR miss cycles 793system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4505750 # number of ReadExReq MSHR miss cycles 794system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17765000 # number of demand (read+write) MSHR miss cycles 795system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11052250 # number of demand (read+write) MSHR miss cycles 796system.cpu.l2cache.demand_mshr_miss_latency::total 28817250 # number of demand (read+write) MSHR miss cycles 797system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17765000 # number of overall MSHR miss cycles 798system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11052250 # number of overall MSHR miss cycles 799system.cpu.l2cache.overall_mshr_miss_latency::total 28817250 # number of overall MSHR miss cycles 800system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses 801system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 802system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses 803system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 804system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 805system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses 806system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 807system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses 808system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses 809system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 810system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses 811system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56576.433121 # average ReadReq mshr miss latency 812system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64181.372549 # average ReadReq mshr miss latency 813system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58441.105769 # average ReadReq mshr miss latency 814system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62579.861111 # average ReadExReq mshr miss latency 815system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62579.861111 # average ReadExReq mshr miss latency 816system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56576.433121 # average overall mshr miss latency 817system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63518.678161 # average overall mshr miss latency 818system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59051.741803 # average overall mshr miss latency 819system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56576.433121 # average overall mshr miss latency 820system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63518.678161 # average overall mshr miss latency 821system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59051.741803 # average overall mshr miss latency 822system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 823system.cpu.dcache.tags.replacements 0 # number of replacements 824system.cpu.dcache.tags.tagsinuse 107.281632 # Cycle average of tags in use 825system.cpu.dcache.tags.total_refs 2231 # Total number of references to valid blocks. 826system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. 827system.cpu.dcache.tags.avg_refs 12.821839 # Average number of references to valid blocks. 828system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 829system.cpu.dcache.tags.occ_blocks::cpu.data 107.281632 # Average occupied blocks per requestor 830system.cpu.dcache.tags.occ_percent::cpu.data 0.026192 # Average percentage of cache occupancy 831system.cpu.dcache.tags.occ_percent::total 0.026192 # Average percentage of cache occupancy 832system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id 833system.cpu.dcache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 834system.cpu.dcache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id 835system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id 836system.cpu.dcache.tags.tag_accesses 5696 # Number of tag accesses 837system.cpu.dcache.tags.data_accesses 5696 # Number of data accesses 838system.cpu.dcache.ReadReq_hits::cpu.data 1725 # number of ReadReq hits 839system.cpu.dcache.ReadReq_hits::total 1725 # number of ReadReq hits 840system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 841system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 842system.cpu.dcache.demand_hits::cpu.data 2231 # number of demand (read+write) hits 843system.cpu.dcache.demand_hits::total 2231 # number of demand (read+write) hits 844system.cpu.dcache.overall_hits::cpu.data 2231 # number of overall hits 845system.cpu.dcache.overall_hits::total 2231 # number of overall hits 846system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses 847system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses 848system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 849system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 850system.cpu.dcache.demand_misses::cpu.data 530 # number of demand (read+write) misses 851system.cpu.dcache.demand_misses::total 530 # number of demand (read+write) misses 852system.cpu.dcache.overall_misses::cpu.data 530 # number of overall misses 853system.cpu.dcache.overall_misses::total 530 # number of overall misses 854system.cpu.dcache.ReadReq_miss_latency::cpu.data 11477000 # number of ReadReq miss cycles 855system.cpu.dcache.ReadReq_miss_latency::total 11477000 # number of ReadReq miss cycles 856system.cpu.dcache.WriteReq_miss_latency::cpu.data 23139722 # number of WriteReq miss cycles 857system.cpu.dcache.WriteReq_miss_latency::total 23139722 # number of WriteReq miss cycles 858system.cpu.dcache.demand_miss_latency::cpu.data 34616722 # number of demand (read+write) miss cycles 859system.cpu.dcache.demand_miss_latency::total 34616722 # number of demand (read+write) miss cycles 860system.cpu.dcache.overall_miss_latency::cpu.data 34616722 # number of overall miss cycles 861system.cpu.dcache.overall_miss_latency::total 34616722 # number of overall miss cycles 862system.cpu.dcache.ReadReq_accesses::cpu.data 1896 # number of ReadReq accesses(hits+misses) 863system.cpu.dcache.ReadReq_accesses::total 1896 # number of ReadReq accesses(hits+misses) 864system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 865system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 866system.cpu.dcache.demand_accesses::cpu.data 2761 # number of demand (read+write) accesses 867system.cpu.dcache.demand_accesses::total 2761 # number of demand (read+write) accesses 868system.cpu.dcache.overall_accesses::cpu.data 2761 # number of overall (read+write) accesses 869system.cpu.dcache.overall_accesses::total 2761 # number of overall (read+write) accesses 870system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090190 # miss rate for ReadReq accesses 871system.cpu.dcache.ReadReq_miss_rate::total 0.090190 # miss rate for ReadReq accesses 872system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 873system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 874system.cpu.dcache.demand_miss_rate::cpu.data 0.191959 # miss rate for demand accesses 875system.cpu.dcache.demand_miss_rate::total 0.191959 # miss rate for demand accesses 876system.cpu.dcache.overall_miss_rate::cpu.data 0.191959 # miss rate for overall accesses 877system.cpu.dcache.overall_miss_rate::total 0.191959 # miss rate for overall accesses 878system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67116.959064 # average ReadReq miss latency 879system.cpu.dcache.ReadReq_avg_miss_latency::total 67116.959064 # average ReadReq miss latency 880system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64456.050139 # average WriteReq miss latency 881system.cpu.dcache.WriteReq_avg_miss_latency::total 64456.050139 # average WriteReq miss latency 882system.cpu.dcache.demand_avg_miss_latency::cpu.data 65314.569811 # average overall miss latency 883system.cpu.dcache.demand_avg_miss_latency::total 65314.569811 # average overall miss latency 884system.cpu.dcache.overall_avg_miss_latency::cpu.data 65314.569811 # average overall miss latency 885system.cpu.dcache.overall_avg_miss_latency::total 65314.569811 # average overall miss latency 886system.cpu.dcache.blocked_cycles::no_mshrs 1676 # number of cycles access was blocked 887system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 888system.cpu.dcache.blocked::no_mshrs 40 # number of cycles access was blocked 889system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 890system.cpu.dcache.avg_blocked_cycles::no_mshrs 41.900000 # average number of cycles each access was blocked 891system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 892system.cpu.dcache.fast_writes 0 # number of fast writes performed 893system.cpu.dcache.cache_copies 0 # number of cache copies performed 894system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 895system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 896system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 897system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits 898system.cpu.dcache.demand_mshr_hits::cpu.data 356 # number of demand (read+write) MSHR hits 899system.cpu.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits 900system.cpu.dcache.overall_mshr_hits::cpu.data 356 # number of overall MSHR hits 901system.cpu.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits 902system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 903system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 904system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 905system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 906system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 907system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 908system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 909system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 910system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7909000 # number of ReadReq MSHR miss cycles 911system.cpu.dcache.ReadReq_mshr_miss_latency::total 7909000 # number of ReadReq MSHR miss cycles 912system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5463750 # number of WriteReq MSHR miss cycles 913system.cpu.dcache.WriteReq_mshr_miss_latency::total 5463750 # number of WriteReq MSHR miss cycles 914system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13372750 # number of demand (read+write) MSHR miss cycles 915system.cpu.dcache.demand_mshr_miss_latency::total 13372750 # number of demand (read+write) MSHR miss cycles 916system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13372750 # number of overall MSHR miss cycles 917system.cpu.dcache.overall_mshr_miss_latency::total 13372750 # number of overall MSHR miss cycles 918system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053797 # mshr miss rate for ReadReq accesses 919system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053797 # mshr miss rate for ReadReq accesses 920system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 921system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 922system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063021 # mshr miss rate for demand accesses 923system.cpu.dcache.demand_mshr_miss_rate::total 0.063021 # mshr miss rate for demand accesses 924system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063021 # mshr miss rate for overall accesses 925system.cpu.dcache.overall_mshr_miss_rate::total 0.063021 # mshr miss rate for overall accesses 926system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77539.215686 # average ReadReq mshr miss latency 927system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77539.215686 # average ReadReq mshr miss latency 928system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75885.416667 # average WriteReq mshr miss latency 929system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75885.416667 # average WriteReq mshr miss latency 930system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76854.885057 # average overall mshr miss latency 931system.cpu.dcache.demand_avg_mshr_miss_latency::total 76854.885057 # average overall mshr miss latency 932system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76854.885057 # average overall mshr miss latency 933system.cpu.dcache.overall_avg_mshr_miss_latency::total 76854.885057 # average overall mshr miss latency 934system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 935 936---------- End Simulation Statistics ---------- 937