stats.txt revision 9988
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 39729Sandreas.hansson@arm.comsim_seconds 0.000021 # Number of seconds simulated 49978Sandreas.hansson@arm.comsim_ticks 21065000 # Number of ticks simulated 59978Sandreas.hansson@arm.comfinal_tick 21065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79988Snilay@cs.wisc.eduhost_inst_rate 36663 # Simulator instruction rate (inst/s) 89988Snilay@cs.wisc.eduhost_op_rate 36659 # Simulator op (including micro ops) rate (op/s) 99988Snilay@cs.wisc.eduhost_tick_rate 121177991 # Simulator tick rate (ticks/s) 109988Snilay@cs.wisc.eduhost_mem_usage 273132 # Number of bytes of host memory used 119988Snilay@cs.wisc.eduhost_seconds 0.17 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6372 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6372 # Number of ops (including micro ops) simulated 149729Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 159322Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 169729Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 31168 # Number of bytes read from this memory 179729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 189729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 199729Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 209322Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 219729Sandreas.hansson@arm.comsystem.physmem.num_reads::total 487 # Number of read requests responded to by this memory 229978Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 950961310 # Total read bandwidth from this memory (bytes/s) 239978Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 528649418 # Total read bandwidth from this memory (bytes/s) 249978Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1479610729 # Total read bandwidth from this memory (bytes/s) 259978Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 950961310 # Instruction read bandwidth from this memory (bytes/s) 269978Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 950961310 # Instruction read bandwidth from this memory (bytes/s) 279978Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 950961310 # Total bandwidth to/from this memory (bytes/s) 289978Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 528649418 # Total bandwidth to/from this memory (bytes/s) 299978Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1479610729 # Total bandwidth to/from this memory (bytes/s) 309978Sandreas.hansson@arm.comsystem.physmem.readReqs 488 # Number of read requests accepted 319978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 329978Sandreas.hansson@arm.comsystem.physmem.readBursts 488 # Number of DRAM read bursts, including those serviced by the write queue 339978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 349978Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 31232 # Total number of bytes read from DRAM 359978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 369978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 31232 # Total read bytes from the system interface side 389978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 399978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 409978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 419978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 429978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 69 # Per bank write bursts 439978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 34 # Per bank write bursts 449978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 32 # Per bank write bursts 459978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 47 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 43 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 21 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 1 # Per bank write bursts 499978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 3 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 0 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 1 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 23 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 24 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 14 # Per bank write bursts 559978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 119 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 45 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 12 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 759978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 769978Sandreas.hansson@arm.comsystem.physmem.totGap 21032000 # Total gap between requests 779978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 789978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 488 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see 929797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see 939978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see 949978Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see 959729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 969322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 979312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 989312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1559978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 85 # Bytes accessed per row activation 1569978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 326.023529 # Bytes accessed per row activation 1579978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 167.928934 # Bytes accessed per row activation 1589978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 483.454089 # Bytes accessed per row activation 1599978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::64 37 43.53% 43.53% # Bytes accessed per row activation 1609978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128 8 9.41% 52.94% # Bytes accessed per row activation 1619978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::192 10 11.76% 64.71% # Bytes accessed per row activation 1629978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256 7 8.24% 72.94% # Bytes accessed per row activation 1639978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::320 3 3.53% 76.47% # Bytes accessed per row activation 1649978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384 2 2.35% 78.82% # Bytes accessed per row activation 1659978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::448 2 2.35% 81.18% # Bytes accessed per row activation 1669978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512 4 4.71% 85.88% # Bytes accessed per row activation 1679978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::576 1 1.18% 87.06% # Bytes accessed per row activation 1689978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640 1 1.18% 88.24% # Bytes accessed per row activation 1699978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::832 2 2.35% 90.59% # Bytes accessed per row activation 1709978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::960 1 1.18% 91.76% # Bytes accessed per row activation 1719978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024 1 1.18% 92.94% # Bytes accessed per row activation 1729978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1472 3 3.53% 96.47% # Bytes accessed per row activation 1739978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1920 1 1.18% 97.65% # Bytes accessed per row activation 1749978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2304 1 1.18% 98.82% # Bytes accessed per row activation 1759978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2432 1 1.18% 100.00% # Bytes accessed per row activation 1769978Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 85 # Bytes accessed per row activation 1779978Sandreas.hansson@arm.comsystem.physmem.totQLat 3258750 # Total ticks spent queuing 1789978Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 13288750 # Total ticks spent from burst creation until serviced by the DRAM 1799978Sandreas.hansson@arm.comsystem.physmem.totBusLat 2440000 # Total ticks spent in databus transfers 1809978Sandreas.hansson@arm.comsystem.physmem.totBankLat 7590000 # Total ticks spent accessing banks 1819978Sandreas.hansson@arm.comsystem.physmem.avgQLat 6677.77 # Average queueing delay per DRAM burst 1829978Sandreas.hansson@arm.comsystem.physmem.avgBankLat 15553.28 # Average bank access latency per DRAM burst 1839978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 1849978Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 27231.05 # Average memory access latency per DRAM burst 1859978Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1482.65 # Average DRAM read bandwidth in MiByte/s 1869978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 1879978Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1482.65 # Average system read bandwidth in MiByte/s 1889978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 1899978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 1909978Sandreas.hansson@arm.comsystem.physmem.busUtil 11.58 # Data bus utilization in percentage 1919978Sandreas.hansson@arm.comsystem.physmem.busUtilRead 11.58 # Data bus utilization in percentage for reads 1929978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 1939978Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.63 # Average read queue length when enqueuing 1949978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 1959978Sandreas.hansson@arm.comsystem.physmem.readRowHits 403 # Number of row buffer hits during reads 1969312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1979978Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 82.58 # Row buffer hit rate for reads 1989312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1999978Sandreas.hansson@arm.comsystem.physmem.avgGap 43098.36 # Average gap between requests 2009978Sandreas.hansson@arm.comsystem.physmem.pageHitRate 82.58 # Row buffer hit rate, read and write combined 2019978Sandreas.hansson@arm.comsystem.physmem.prechargeAllPercent 0.10 # Percentage of time for which DRAM has all the banks in precharge state 2029978Sandreas.hansson@arm.comsystem.membus.throughput 1479610729 # Throughput (bytes/s) 2039729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 415 # Transaction distribution 2049729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 414 # Transaction distribution 2059729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 73 # Transaction distribution 2069729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 73 # Transaction distribution 2079838Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes) 2089838Sandreas.hansson@arm.comsystem.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes) 2099838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) 2109838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) 2119729Sandreas.hansson@arm.comsystem.membus.data_through_bus 31168 # Total data (bytes) 2129729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 2139978Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 619000 # Layer occupancy (ticks) 2149978Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 2159978Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4556000 # Layer occupancy (ticks) 2169978Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 21.6 # Layer utilization (%) 2179988Snilay@cs.wisc.edusystem.cpu.branchPred.lookups 2883 # Number of BP lookups 2189988Snilay@cs.wisc.edusystem.cpu.branchPred.condPredicted 1697 # Number of conditional branches predicted 2199729Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect 2209978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups 2219978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 756 # Number of BTB hits 2229481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2239978Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 34.363636 # BTB Hit Percentage 2249978Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. 2259490Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 2268428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2278428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2288428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2298428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 2309978Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 2076 # DTB read hits 2319729Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 47 # DTB read misses 2328428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 2339978Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 2123 # DTB read accesses 2349729Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 1063 # DTB write hits 2359729Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 31 # DTB write misses 2368428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 2379729Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 1094 # DTB write accesses 2389978Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 3139 # DTB hits 2399729Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 78 # DTB misses 2408428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 2419978Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 3217 # DTB accesses 2429978Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 2382 # ITB hits 2439729Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 39 # ITB misses 2448428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 2459978Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 2421 # ITB accesses 2468428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2478428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2488428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2498428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2508428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2518428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2528428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2538428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2548428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2558428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2568428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2578428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2588428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 2599978Sandreas.hansson@arm.comsystem.cpu.numCycles 42131 # number of cpu cycles simulated 2608428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2618428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2629988Snilay@cs.wisc.edusystem.cpu.fetch.icacheStallCycles 8531 # Number of cycles fetch is stalled on an Icache miss 2639988Snilay@cs.wisc.edusystem.cpu.fetch.Insts 16553 # Number of instructions fetch has processed 2649988Snilay@cs.wisc.edusystem.cpu.fetch.Branches 2883 # Number of branches that fetch encountered 2659978Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 1172 # Number of branches that fetch has predicted taken 2669988Snilay@cs.wisc.edusystem.cpu.fetch.Cycles 2963 # Number of cycles fetch has run and was not squashing or blocked 2679978Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1902 # Number of cycles fetch has spent squashing 2689978Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 1547 # Number of cycles fetch has spent blocked 2699729Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2709797Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps 2719978Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 2382 # Number of cache lines fetched 2729978Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 383 # Number of outstanding Icache misses that were squashed 2739978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 15113 # Number of instructions fetched each cycle (Total) 2749988Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::mean 1.095282 # Number of instructions fetched each cycle (Total) 2759988Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::stdev 2.492986 # Number of instructions fetched each cycle (Total) 2766291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2779988Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::0 12150 80.39% 80.39% # Number of instructions fetched each cycle (Total) 2789988Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::1 318 2.10% 82.50% # Number of instructions fetched each cycle (Total) 2799988Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::2 234 1.55% 84.05% # Number of instructions fetched each cycle (Total) 2809978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 214 1.42% 85.46% # Number of instructions fetched each cycle (Total) 2819988Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::4 255 1.69% 87.15% # Number of instructions fetched each cycle (Total) 2829988Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::5 240 1.59% 88.74% # Number of instructions fetched each cycle (Total) 2839988Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::6 264 1.75% 90.49% # Number of instructions fetched each cycle (Total) 2849988Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::7 183 1.21% 91.70% # Number of instructions fetched each cycle (Total) 2859988Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::8 1255 8.30% 100.00% # Number of instructions fetched each cycle (Total) 2866291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2876291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2886291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2899978Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 15113 # Number of instructions fetched each cycle (Total) 2909988Snilay@cs.wisc.edusystem.cpu.fetch.branchRate 0.068429 # Number of branch fetches per cycle 2919988Snilay@cs.wisc.edusystem.cpu.fetch.rate 0.392894 # Number of inst fetches per cycle 2929978Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 9345 # Number of cycles decode is idle 2939978Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 1711 # Number of cycles decode is blocked 2949978Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2764 # Number of cycles decode is running 2959797Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking 2969978Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1219 # Number of cycles decode is squashing 2979729Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch 2989729Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction 2999978Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 15308 # Number of instructions handled by decode 3009729Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode 3019978Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1219 # Number of cycles rename is squashing 3029978Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9554 # Number of cycles rename is idle 3039978Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 808 # Number of cycles rename is blocking 3049978Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 554 # count of cycles rename stalled for serializing inst 3059978Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2623 # Number of cycles rename is running 3069797Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 355 # Number of cycles rename is unblocking 3079978Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 14604 # Number of instructions processed by rename 3089729Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full 3099348SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full 3109797Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 313 # Number of times rename has blocked due to LSQ full 3119978Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 10951 # Number of destination operands rename has renamed 3129978Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 18225 # Number of register rename lookups that rename has made 3139978Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 18216 # Number of integer rename lookups 3149924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 3159150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 3169978Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6381 # Number of HB maps that are undone due to squashing 3179797Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 29 # count of serializing insts renamed 3189797Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 23 # count of temporary serializing insts renamed 3199797Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 808 # count of insts added to the skid buffer 3209978Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2766 # Number of loads inserted to the mem dependence unit. 3219797Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. 3229490Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. 3238428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 3249978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 12953 # Number of instructions added to the IQ (excludes non-spec) 3259797Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ 3269978Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 10771 # Number of instructions issued 3279797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued 3289978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6180 # Number of squashed instructions iterated over during squash; mainly for profiling 3299978Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3598 # Number of squashed operands that are examined and possibly removed from graph 3309797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 3319978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 15113 # Number of insts issued each cycle 3329978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.712698 # Number of insts issued each cycle 3339978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.354769 # Number of insts issued each cycle 3348428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3359978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10572 69.95% 69.95% # Number of insts issued each cycle 3369978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1678 11.10% 81.06% # Number of insts issued each cycle 3379978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 1174 7.77% 88.82% # Number of insts issued each cycle 3389978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 728 4.82% 93.64% # Number of insts issued each cycle 3399978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 498 3.30% 96.94% # Number of insts issued each cycle 3409978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 270 1.79% 98.72% # Number of insts issued each cycle 3419978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 146 0.97% 99.69% # Number of insts issued each cycle 3429797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle 3439729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle 3448428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3458428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3468428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3479978Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 15113 # Number of insts issued each cycle 3488428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3499978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 14 12.50% 12.50% # attempts to use FU when none available 3509978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 12.50% # attempts to use FU when none available 3519978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 12.50% # attempts to use FU when none available 3529978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 12.50% # attempts to use FU when none available 3539978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 12.50% # attempts to use FU when none available 3549978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 12.50% # attempts to use FU when none available 3559978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 12.50% # attempts to use FU when none available 3569978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 12.50% # attempts to use FU when none available 3579978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.50% # attempts to use FU when none available 3589978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 12.50% # attempts to use FU when none available 3599978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.50% # attempts to use FU when none available 3609978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 12.50% # attempts to use FU when none available 3619978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 12.50% # attempts to use FU when none available 3629978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 12.50% # attempts to use FU when none available 3639978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 12.50% # attempts to use FU when none available 3649978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 12.50% # attempts to use FU when none available 3659978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.50% # attempts to use FU when none available 3669978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 12.50% # attempts to use FU when none available 3679978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.50% # attempts to use FU when none available 3689978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.50% # attempts to use FU when none available 3699978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.50% # attempts to use FU when none available 3709978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.50% # attempts to use FU when none available 3719978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.50% # attempts to use FU when none available 3729978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.50% # attempts to use FU when none available 3739978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.50% # attempts to use FU when none available 3749978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.50% # attempts to use FU when none available 3759978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.50% # attempts to use FU when none available 3769978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.50% # attempts to use FU when none available 3779978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.50% # attempts to use FU when none available 3789978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 60 53.57% 66.07% # attempts to use FU when none available 3799978Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 38 33.93% 100.00% # attempts to use FU when none available 3808428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3818428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3828241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 3839978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 7236 67.18% 67.20% # Type of FU issued 3849978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.21% # Type of FU issued 3859978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.21% # Type of FU issued 3869978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.23% # Type of FU issued 3879978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued 3889978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued 3899978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued 3909978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued 3919978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued 3929978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued 3939978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued 3949978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued 3959978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued 3969978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued 3979978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued 3989978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued 3999978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued 4009978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued 4019978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued 4029978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued 4039978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued 4049978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued 4059978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued 4069978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued 4079978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued 4089978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.23% # Type of FU issued 4099978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued 4109978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued 4119978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued 4129978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2397 22.25% 89.48% # Type of FU issued 4139978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1133 10.52% 100.00% # Type of FU issued 4148241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4158241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4169978Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 10771 # Type of FU issued 4179978Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.255655 # Inst issue rate 4189978Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 112 # FU busy when requested 4199978Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.010398 # FU busy rate (busy events/executed inst) 4209978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 36800 # Number of integer instruction queue reads 4219978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 19167 # Number of integer instruction queue writes 4229978Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9598 # Number of integer instruction queue wakeup accesses 4238428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 4248428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 4258428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 4269978Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 10870 # Number of integer alu accesses 4278428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 4289729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores 4298428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4309978Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1583 # Number of loads squashed 4319285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 4329490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations 4339797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed 4348428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4358428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4368428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 4379797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 131 # Number of times an access to memory failed due to the cache being blocked 4388428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4399978Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1219 # Number of cycles IEW is squashing 4409978Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 264 # Number of cycles IEW is blocking 4419797Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking 4429978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 13071 # Number of instructions dispatched to IQ 4439797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch 4449978Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2766 # Number of dispatched load instructions 4459797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions 4469797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions 4479348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 4488428SN/Asystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4499490Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations 4509978Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 122 # Number of branches that were predicted taken incorrectly 4519978Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 381 # Number of branches that were predicted not taken incorrectly 4529978Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute 4539978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 10067 # Number of executed instructions 4549978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed 4559978Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 704 # Number of squashed instructions skipped in execute 4568428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4579729Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 89 # number of nop insts executed 4589978Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3230 # number of memory reference insts executed 4599978Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1588 # Number of branches executed 4609729Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1096 # Number of stores executed 4619978Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.238945 # Inst execution rate 4629978Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 9751 # cumulative count of insts sent to commit 4639978Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 9608 # cumulative count of insts written-back 4649978Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 5048 # num instructions producing a value 4659978Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 6764 # num instructions consuming a value 4668428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4679978Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.228051 # insts written-back per cycle 4689978Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.746304 # average fanout of values written-back 4698428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4709978Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6680 # The number of squashed insts skipped by commit 4718428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 4729729Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted 4739978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13894 # Number of insts commited each cycle 4749978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.459839 # Number of insts commited each cycle 4759978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.263268 # Number of insts commited each cycle 4768428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4779978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 11073 79.70% 79.70% # Number of insts commited each cycle 4789978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1524 10.97% 90.67% # Number of insts commited each cycle 4799978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 530 3.81% 94.48% # Number of insts commited each cycle 4809978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 235 1.69% 96.17% # Number of insts commited each cycle 4819978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 148 1.07% 97.24% # Number of insts commited each cycle 4829978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 110 0.79% 98.03% # Number of insts commited each cycle 4839978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 103 0.74% 98.77% # Number of insts commited each cycle 4849978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 28 0.20% 98.97% # Number of insts commited each cycle 4859978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle 4868428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4878428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4888428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4899978Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13894 # Number of insts commited each cycle 4909150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6389 # Number of instructions committed 4919150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 4928428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4939150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2048 # Number of memory references committed 4949150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1183 # Number of loads committed 4958428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 4969150SAli.Saidi@ARM.comsystem.cpu.commit.branches 1050 # Number of branches committed 4978428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 4989150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 6307 # Number of committed integer instructions. 4998428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 5009978Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached 5018428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 5029978Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 26469 # The number of ROB reads 5039978Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 27366 # The number of ROB writes 5049978Sandreas.hansson@arm.comsystem.cpu.timesIdled 271 # Number of times that the entire CPU went into an idle state and unscheduled itself 5059978Sandreas.hansson@arm.comsystem.cpu.idleCycles 27018 # Total number of cycles that the CPU has spent unscheduled due to idling 5069150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6372 # Number of Instructions Simulated 5079150SAli.Saidi@ARM.comsystem.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 5089150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 6372 # Number of Instructions Simulated 5099978Sandreas.hansson@arm.comsystem.cpu.cpi 6.611896 # CPI: Cycles Per Instruction 5109978Sandreas.hansson@arm.comsystem.cpu.cpi_total 6.611896 # CPI: Total CPI of All Threads 5119978Sandreas.hansson@arm.comsystem.cpu.ipc 0.151243 # IPC: Instructions Per Cycle 5129978Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.151243 # IPC: Total IPC of All Threads 5139978Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 12780 # number of integer regfile reads 5149978Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7264 # number of integer regfile writes 5158428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 5168428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 5178428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 5188428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 5199978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 1482648944 # Throughput (bytes/s) 5209729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution 5219729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution 5229729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 5239729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 5249838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes) 5259838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) 5269838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes) 5279838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) 5289838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 5299838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) 5309729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) 5319729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 5329729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) 5339729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 5349978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 529000 # Layer occupancy (ticks) 5359978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) 5369978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 278500 # Layer occupancy (ticks) 5379978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 5389838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 5399978Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 159.548856 # Cycle average of tags in use 5409978Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1893 # Total number of references to valid blocks. 5419838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. 5429978Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 6.028662 # Average number of references to valid blocks. 5439838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5449978Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 159.548856 # Average occupied blocks per requestor 5459978Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.077905 # Average percentage of cache occupancy 5469978Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.077905 # Average percentage of cache occupancy 5479978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1893 # number of ReadReq hits 5489978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1893 # number of ReadReq hits 5499978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1893 # number of demand (read+write) hits 5509978Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1893 # number of demand (read+write) hits 5519978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1893 # number of overall hits 5529978Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1893 # number of overall hits 5539797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses 5549797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses 5559797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses 5569797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses 5579797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses 5589797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 489 # number of overall misses 5599978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 31381500 # number of ReadReq miss cycles 5609978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 31381500 # number of ReadReq miss cycles 5619978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 31381500 # number of demand (read+write) miss cycles 5629978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 31381500 # number of demand (read+write) miss cycles 5639978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 31381500 # number of overall miss cycles 5649978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 31381500 # number of overall miss cycles 5659978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2382 # number of ReadReq accesses(hits+misses) 5669978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2382 # number of ReadReq accesses(hits+misses) 5679978Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2382 # number of demand (read+write) accesses 5689978Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2382 # number of demand (read+write) accesses 5699978Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2382 # number of overall (read+write) accesses 5709978Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2382 # number of overall (read+write) accesses 5719978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.205290 # miss rate for ReadReq accesses 5729978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.205290 # miss rate for ReadReq accesses 5739978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.205290 # miss rate for demand accesses 5749978Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.205290 # miss rate for demand accesses 5759978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.205290 # miss rate for overall accesses 5769978Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.205290 # miss rate for overall accesses 5779978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64174.846626 # average ReadReq miss latency 5789978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 64174.846626 # average ReadReq miss latency 5799978Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency 5809978Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 64174.846626 # average overall miss latency 5819978Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 64174.846626 # average overall miss latency 5829978Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 64174.846626 # average overall miss latency 5838428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5848428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5858428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 5868428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5878983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5888983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5898428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5908428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5919797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 174 # number of ReadReq MSHR hits 5929797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 174 # number of ReadReq MSHR hits 5939797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 174 # number of demand (read+write) MSHR hits 5949797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 174 # number of demand (read+write) MSHR hits 5959797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 174 # number of overall MSHR hits 5969797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 174 # number of overall MSHR hits 5979729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 5989729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 5999729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 6009729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 6019729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 6029729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses 6039978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22109000 # number of ReadReq MSHR miss cycles 6049978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 22109000 # number of ReadReq MSHR miss cycles 6059978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 22109000 # number of demand (read+write) MSHR miss cycles 6069978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 22109000 # number of demand (read+write) MSHR miss cycles 6079978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 22109000 # number of overall MSHR miss cycles 6089978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 22109000 # number of overall MSHR miss cycles 6099978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for ReadReq accesses 6109978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.132242 # mshr miss rate for ReadReq accesses 6119978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for demand accesses 6129978Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.132242 # mshr miss rate for demand accesses 6139978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132242 # mshr miss rate for overall accesses 6149978Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.132242 # mshr miss rate for overall accesses 6159978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70187.301587 # average ReadReq mshr miss latency 6169978Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70187.301587 # average ReadReq mshr miss latency 6179978Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency 6189978Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency 6199978Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70187.301587 # average overall mshr miss latency 6209978Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 70187.301587 # average overall mshr miss latency 6218428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6229838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 6239978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 219.420292 # Cycle average of tags in use 6249838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 6259838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. 6269838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. 6279838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6289978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 159.632644 # Average occupied blocks per requestor 6299978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 59.787647 # Average occupied blocks per requestor 6309978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004872 # Average percentage of cache occupancy 6319978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001825 # Average percentage of cache occupancy 6329978Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006696 # Average percentage of cache occupancy 6338835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 6348835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 6358835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 6368835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 6378835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 6388835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 6399729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses 6409322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses 6419729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses 6429096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 6439096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 6449729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses 6459322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 6469729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses 6479729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses 6489322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 6499729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 488 # number of overall misses 6509978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21783000 # number of ReadReq miss cycles 6519978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 7718750 # number of ReadReq miss cycles 6529978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 29501750 # number of ReadReq miss cycles 6539978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5390750 # number of ReadExReq miss cycles 6549978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 5390750 # number of ReadExReq miss cycles 6559978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 21783000 # number of demand (read+write) miss cycles 6569978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 13109500 # number of demand (read+write) miss cycles 6579978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 34892500 # number of demand (read+write) miss cycles 6589978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 21783000 # number of overall miss cycles 6599978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 13109500 # number of overall miss cycles 6609978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 34892500 # number of overall miss cycles 6619729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) 6629322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) 6639729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) 6649096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 6659096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 6669729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses 6679322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 6689729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses 6699729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses 6709322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 6719729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses 6729729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses 6738835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 6749729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses 6758835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6769055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6779729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses 6788835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 6799729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses 6809729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses 6818835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 6829729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses 6839978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69372.611465 # average ReadReq miss latency 6849978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76423.267327 # average ReadReq miss latency 6859978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 71088.554217 # average ReadReq miss latency 6869978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73845.890411 # average ReadExReq miss latency 6879978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 73845.890411 # average ReadExReq miss latency 6889978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency 6899978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency 6909978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 71501.024590 # average overall miss latency 6919978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69372.611465 # average overall miss latency 6929978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 75341.954023 # average overall miss latency 6939978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 71501.024590 # average overall miss latency 6948428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6958428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6968428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6978428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6988983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6998983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7008428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 7018428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 7029729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 7039322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 7049729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses 7059096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 7069096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 7079729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 7089322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 7099729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses 7109729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 7119322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 7129729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses 7139978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17830500 # number of ReadReq MSHR miss cycles 7149978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6478250 # number of ReadReq MSHR miss cycles 7159978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 24308750 # number of ReadReq MSHR miss cycles 7169978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4491250 # number of ReadExReq MSHR miss cycles 7179978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4491250 # number of ReadExReq MSHR miss cycles 7189978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17830500 # number of demand (read+write) MSHR miss cycles 7199978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10969500 # number of demand (read+write) MSHR miss cycles 7209978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 28800000 # number of demand (read+write) MSHR miss cycles 7219978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17830500 # number of overall MSHR miss cycles 7229978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10969500 # number of overall MSHR miss cycles 7239978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 28800000 # number of overall MSHR miss cycles 7249729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses 7258835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 7269729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses 7278835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 7289055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 7299729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses 7308835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 7319729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses 7329729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses 7338835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 7349729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses 7359978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56785.031847 # average ReadReq mshr miss latency 7369978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64141.089109 # average ReadReq mshr miss latency 7379978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58575.301205 # average ReadReq mshr miss latency 7389978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61523.972603 # average ReadExReq mshr miss latency 7399978Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61523.972603 # average ReadExReq mshr miss latency 7409978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency 7419978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency 7429978Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency 7439978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56785.031847 # average overall mshr miss latency 7449978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63043.103448 # average overall mshr miss latency 7459978Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 59016.393443 # average overall mshr miss latency 7468428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 7479838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 7489978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 107.351368 # Cycle average of tags in use 7499978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2230 # Total number of references to valid blocks. 7509838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. 7519978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 12.816092 # Average number of references to valid blocks. 7529838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 7539978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 107.351368 # Average occupied blocks per requestor 7549978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.026209 # Average percentage of cache occupancy 7559978Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.026209 # Average percentage of cache occupancy 7569978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1724 # number of ReadReq hits 7579978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1724 # number of ReadReq hits 7589348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 7599348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 7609978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2230 # number of demand (read+write) hits 7619978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2230 # number of demand (read+write) hits 7629978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2230 # number of overall hits 7639978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2230 # number of overall hits 7649729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses 7659729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses 7669348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 7679348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 7689729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 529 # number of demand (read+write) misses 7699729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses 7709729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses 7719729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 529 # number of overall misses 7729978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11435000 # number of ReadReq miss cycles 7739978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11435000 # number of ReadReq miss cycles 7749978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 23196228 # number of WriteReq miss cycles 7759978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 23196228 # number of WriteReq miss cycles 7769978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 34631228 # number of demand (read+write) miss cycles 7779978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 34631228 # number of demand (read+write) miss cycles 7789978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 34631228 # number of overall miss cycles 7799978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 34631228 # number of overall miss cycles 7809978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) 7819978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) 7829348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 7839348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 7849978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses 7859978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses 7869978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses 7879978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses 7889978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089757 # miss rate for ReadReq accesses 7899978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.089757 # miss rate for ReadReq accesses 7909348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 7919348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 7929978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.191736 # miss rate for demand accesses 7939978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.191736 # miss rate for demand accesses 7949978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.191736 # miss rate for overall accesses 7959978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.191736 # miss rate for overall accesses 7969978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67264.705882 # average ReadReq miss latency 7979978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 67264.705882 # average ReadReq miss latency 7989978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64613.448468 # average WriteReq miss latency 7999978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 64613.448468 # average WriteReq miss latency 8009978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency 8019978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 65465.459357 # average overall miss latency 8029978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 65465.459357 # average overall miss latency 8039978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 65465.459357 # average overall miss latency 8049978Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 1486 # number of cycles access was blocked 8059348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8069729Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked 8079348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 8089978Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 45.030303 # average number of cycles each access was blocked 8099348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8109348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8119348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8129729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 8139729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 8149348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits 8159348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits 8169729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits 8179729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits 8189729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits 8199729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits 8209348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 8219348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 8229348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 8239348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 8249348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 8259348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 8269348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 8279348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 8289978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7827250 # number of ReadReq MSHR miss cycles 8299978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 7827250 # number of ReadReq MSHR miss cycles 8309978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5466750 # number of WriteReq MSHR miss cycles 8319978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 5466750 # number of WriteReq MSHR miss cycles 8329978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 13294000 # number of demand (read+write) MSHR miss cycles 8339978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 13294000 # number of demand (read+write) MSHR miss cycles 8349978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 13294000 # number of overall MSHR miss cycles 8359978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 13294000 # number of overall MSHR miss cycles 8369978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses 8379978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses 8389348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 8399348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 8409978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses 8419978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses 8429978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses 8439978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses 8449978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77497.524752 # average ReadReq mshr miss latency 8459978Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77497.524752 # average ReadReq mshr miss latency 8469978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74886.986301 # average WriteReq mshr miss latency 8479978Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74886.986301 # average WriteReq mshr miss latency 8489978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency 8499978Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency 8509978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76402.298851 # average overall mshr miss latency 8519978Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 76402.298851 # average overall mshr miss latency 8529348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8533096SN/A 8543096SN/A---------- End Simulation Statistics ---------- 855