stats.txt revision 9924
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 39729Sandreas.hansson@arm.comsim_seconds 0.000021 # Number of seconds simulated 49797Sandreas.hansson@arm.comsim_ticks 20671000 # Number of ticks simulated 59797Sandreas.hansson@arm.comfinal_tick 20671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79924Ssteve.reinhardt@amd.comhost_inst_rate 10783 # Simulator instruction rate (inst/s) 89924Ssteve.reinhardt@amd.comhost_op_rate 10783 # Simulator op (including micro ops) rate (op/s) 99924Ssteve.reinhardt@amd.comhost_tick_rate 34979840 # Simulator tick rate (ticks/s) 109924Ssteve.reinhardt@amd.comhost_mem_usage 229184 # Number of bytes of host memory used 119924Ssteve.reinhardt@amd.comhost_seconds 0.59 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6372 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6372 # Number of ops (including micro ops) simulated 149729Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 159322Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 169729Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 31168 # Number of bytes read from this memory 179729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 189729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 199729Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 209322Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 219729Sandreas.hansson@arm.comsystem.physmem.num_reads::total 487 # Number of read requests responded to by this memory 229797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 969087127 # Total read bandwidth from this memory (bytes/s) 239797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 538725751 # Total read bandwidth from this memory (bytes/s) 249797Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1507812878 # Total read bandwidth from this memory (bytes/s) 259797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 969087127 # Instruction read bandwidth from this memory (bytes/s) 269797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 969087127 # Instruction read bandwidth from this memory (bytes/s) 279797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 969087127 # Total bandwidth to/from this memory (bytes/s) 289797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 538725751 # Total bandwidth to/from this memory (bytes/s) 299797Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1507812878 # Total bandwidth to/from this memory (bytes/s) 309838Sandreas.hansson@arm.comsystem.physmem.readReqs 488 # Total number of read requests accepted by DRAM controller 319838Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 329838Sandreas.hansson@arm.comsystem.physmem.readBursts 488 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 339838Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 349729Sandreas.hansson@arm.comsystem.physmem.bytesRead 31168 # Total number of bytes read from memory 359312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 369729Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() 379312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 389838Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 399312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 409729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis 419729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis 429729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis 439729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis 449729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis 459729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis 469729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis 479729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis 489729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 499729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis 509729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis 519729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis 529729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis 539729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis 549729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis 559729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis 569312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 579312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 589312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 729312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 739312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 749797Sandreas.hansson@arm.comsystem.physmem.totGap 20638000 # Total gap between requests 759312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 769312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 779312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 789312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 799312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 809312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 819729Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 488 # Categorize read packet sizes 829568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 839568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 849568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 859568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 869568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 879568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 889568Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Categorize write packet sizes 899797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 286 # What read queue length does an incoming req see 909797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see 919729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see 929729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 939729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 949322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 959312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 969312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 979312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 989312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1539729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation 1549729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation 1559729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation 1569729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation 1579729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation 1589729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation 1599729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation 1609729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation 1619729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation 1629729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation 1639729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation 1649729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation 1659729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation 1669729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation 1679729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation 1689729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation 1699729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation 1709729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation 1719729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation 1729797Sandreas.hansson@arm.comsystem.physmem.totQLat 2449250 # Total cycles spent in queuing delays 1739797Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 12424250 # Sum of mem lat for all requests 1749729Sandreas.hansson@arm.comsystem.physmem.totBusLat 2440000 # Total cycles spent in databus access 1759797Sandreas.hansson@arm.comsystem.physmem.totBankLat 7535000 # Total cycles spent in bank access 1769797Sandreas.hansson@arm.comsystem.physmem.avgQLat 5018.95 # Average queueing delay per request 1779797Sandreas.hansson@arm.comsystem.physmem.avgBankLat 15440.57 # Average bank access latency per request 1789490Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per request 1799797Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 25459.53 # Average memory access latency 1809797Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1507.81 # Average achieved read bandwidth in MB/s 1819312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1829797Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 1507.81 # Average consumed read bandwidth in MB/s 1839312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1849490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 1859797Sandreas.hansson@arm.comsystem.physmem.busUtil 11.78 # Data bus utilization in percentage 1869797Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.60 # Average read queue length over time 1879312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1889729Sandreas.hansson@arm.comsystem.physmem.readRowHits 419 # Number of row buffer hits during reads 1899312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1909729Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads 1919312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1929797Sandreas.hansson@arm.comsystem.physmem.avgGap 42290.98 # Average gap between requests 1939797Sandreas.hansson@arm.comsystem.membus.throughput 1507812878 # Throughput (bytes/s) 1949729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 415 # Transaction distribution 1959729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 414 # Transaction distribution 1969729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 73 # Transaction distribution 1979729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 73 # Transaction distribution 1989838Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 975 # Packet count per connected master and slave (bytes) 1999838Sandreas.hansson@arm.comsystem.membus.pkt_count::total 975 # Packet count per connected master and slave (bytes) 2009838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) 2019838Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) 2029729Sandreas.hansson@arm.comsystem.membus.data_through_bus 31168 # Total data (bytes) 2039729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 2049797Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 619500 # Layer occupancy (ticks) 2059797Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 2069797Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4561500 # Layer occupancy (ticks) 2079729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 22.1 # Layer utilization (%) 2089797Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2888 # Number of BP lookups 2099797Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1700 # Number of conditional branches predicted 2109729Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect 2119797Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups 2129797Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 757 # Number of BTB hits 2139481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2149797Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 34.393458 # BTB Hit Percentage 2159797Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 418 # Number of times the RAS was used to get a target. 2169490Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 2178428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2188428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2198428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2208428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 2219797Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 2082 # DTB read hits 2229729Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 47 # DTB read misses 2238428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 2249797Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 2129 # DTB read accesses 2259729Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 1063 # DTB write hits 2269729Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 31 # DTB write misses 2278428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 2289729Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 1094 # DTB write accesses 2299797Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 3145 # DTB hits 2309729Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 78 # DTB misses 2318428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 2329797Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 3223 # DTB accesses 2339797Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 2387 # ITB hits 2349729Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 39 # ITB misses 2358428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 2369797Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 2426 # ITB accesses 2378428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2388428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2398428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2408428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2418428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2428428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2438428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2448428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2458428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2468428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2478428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2488428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2498428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 2509797Sandreas.hansson@arm.comsystem.cpu.numCycles 41343 # number of cpu cycles simulated 2518428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2528428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2539797Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8507 # Number of cycles fetch is stalled on an Icache miss 2549797Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 16592 # Number of instructions fetch has processed 2559797Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2888 # Number of branches that fetch encountered 2569797Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 1175 # Number of branches that fetch has predicted taken 2579797Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 2970 # Number of cycles fetch has run and was not squashing or blocked 2589797Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1903 # Number of cycles fetch has spent squashing 2599797Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 1523 # Number of cycles fetch has spent blocked 2609729Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2619797Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 747 # Number of stall cycles due to pending traps 2629797Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 2387 # Number of cache lines fetched 2639797Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 382 # Number of outstanding Icache misses that were squashed 2649797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 15073 # Number of instructions fetched each cycle (Total) 2659797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.100776 # Number of instructions fetched each cycle (Total) 2669797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.497742 # Number of instructions fetched each cycle (Total) 2676291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2689797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 12103 80.30% 80.30% # Number of instructions fetched each cycle (Total) 2699797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 318 2.11% 82.41% # Number of instructions fetched each cycle (Total) 2709797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 234 1.55% 83.96% # Number of instructions fetched each cycle (Total) 2719797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 215 1.43% 85.38% # Number of instructions fetched each cycle (Total) 2729797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 257 1.71% 87.09% # Number of instructions fetched each cycle (Total) 2739797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 241 1.60% 88.69% # Number of instructions fetched each cycle (Total) 2749797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 264 1.75% 90.44% # Number of instructions fetched each cycle (Total) 2759797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 184 1.22% 91.66% # Number of instructions fetched each cycle (Total) 2769797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1257 8.34% 100.00% # Number of instructions fetched each cycle (Total) 2776291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2786291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2796291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2809797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 15073 # Number of instructions fetched each cycle (Total) 2819797Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.069855 # Number of branch fetches per cycle 2829797Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.401325 # Number of inst fetches per cycle 2839797Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 9323 # Number of cycles decode is idle 2849797Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 1686 # Number of cycles decode is blocked 2859797Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2770 # Number of cycles decode is running 2869797Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking 2879797Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1220 # Number of cycles decode is squashing 2889729Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch 2899729Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction 2909797Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 15336 # Number of instructions handled by decode 2919729Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode 2929797Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1220 # Number of cycles rename is squashing 2939797Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9534 # Number of cycles rename is idle 2949797Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 784 # Number of cycles rename is blocking 2959797Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 553 # count of cycles rename stalled for serializing inst 2969797Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2627 # Number of cycles rename is running 2979797Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 355 # Number of cycles rename is unblocking 2989797Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 14625 # Number of instructions processed by rename 2999729Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full 3009348SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full 3019797Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 313 # Number of times rename has blocked due to LSQ full 3029797Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 10969 # Number of destination operands rename has renamed 3039797Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 18250 # Number of register rename lookups that rename has made 3049924Ssteve.reinhardt@amd.comsystem.cpu.rename.int_rename_lookups 18241 # Number of integer rename lookups 3059924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 3069150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 3079797Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6399 # Number of HB maps that are undone due to squashing 3089797Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 29 # count of serializing insts renamed 3099797Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 23 # count of temporary serializing insts renamed 3109797Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 808 # count of insts added to the skid buffer 3119797Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2769 # Number of loads inserted to the mem dependence unit. 3129797Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1356 # Number of stores inserted to the mem dependence unit. 3139490Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. 3148428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 3159797Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 12962 # Number of instructions added to the IQ (excludes non-spec) 3169797Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ 3179797Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 10787 # Number of instructions issued 3189797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued 3199797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6234 # Number of squashed instructions iterated over during squash; mainly for profiling 3209797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3590 # Number of squashed operands that are examined and possibly removed from graph 3219797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 3229797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 15073 # Number of insts issued each cycle 3239797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.715651 # Number of insts issued each cycle 3249797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.357561 # Number of insts issued each cycle 3258428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3269797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10531 69.87% 69.87% # Number of insts issued each cycle 3279797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1674 11.11% 80.97% # Number of insts issued each cycle 3289797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 1174 7.79% 88.76% # Number of insts issued each cycle 3299797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 731 4.85% 93.61% # Number of insts issued each cycle 3309797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 498 3.30% 96.92% # Number of insts issued each cycle 3319797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 271 1.80% 98.71% # Number of insts issued each cycle 3329797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 147 0.98% 99.69% # Number of insts issued each cycle 3339797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 33 0.22% 99.91% # Number of insts issued each cycle 3349729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle 3358428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3368428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3378428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3389797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 15073 # Number of insts issued each cycle 3398428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3409797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 15 13.27% 13.27% # attempts to use FU when none available 3419797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 13.27% # attempts to use FU when none available 3429797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 13.27% # attempts to use FU when none available 3439797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 13.27% # attempts to use FU when none available 3449797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 13.27% # attempts to use FU when none available 3459797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 13.27% # attempts to use FU when none available 3469797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 13.27% # attempts to use FU when none available 3479797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 13.27% # attempts to use FU when none available 3489797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.27% # attempts to use FU when none available 3499797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 13.27% # attempts to use FU when none available 3509797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.27% # attempts to use FU when none available 3519797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 13.27% # attempts to use FU when none available 3529797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 13.27% # attempts to use FU when none available 3539797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 13.27% # attempts to use FU when none available 3549797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 13.27% # attempts to use FU when none available 3559797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 13.27% # attempts to use FU when none available 3569797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.27% # attempts to use FU when none available 3579797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 13.27% # attempts to use FU when none available 3589797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.27% # attempts to use FU when none available 3599797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.27% # attempts to use FU when none available 3609797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.27% # attempts to use FU when none available 3619797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.27% # attempts to use FU when none available 3629797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.27% # attempts to use FU when none available 3639797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.27% # attempts to use FU when none available 3649797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.27% # attempts to use FU when none available 3659797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.27% # attempts to use FU when none available 3669797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.27% # attempts to use FU when none available 3679797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.27% # attempts to use FU when none available 3689797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.27% # attempts to use FU when none available 3699797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 60 53.10% 66.37% # attempts to use FU when none available 3709797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 38 33.63% 100.00% # attempts to use FU when none available 3718428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3728428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3738241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 3749797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 7249 67.20% 67.22% # Type of FU issued 3759797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.23% # Type of FU issued 3769797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued 3779797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.25% # Type of FU issued 3789797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.25% # Type of FU issued 3799797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.25% # Type of FU issued 3809797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.25% # Type of FU issued 3819797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.25% # Type of FU issued 3829797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.25% # Type of FU issued 3839797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.25% # Type of FU issued 3849797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.25% # Type of FU issued 3859797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.25% # Type of FU issued 3869797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.25% # Type of FU issued 3879797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.25% # Type of FU issued 3889797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.25% # Type of FU issued 3899797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.25% # Type of FU issued 3909797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.25% # Type of FU issued 3919797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.25% # Type of FU issued 3929797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.25% # Type of FU issued 3939797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.25% # Type of FU issued 3949797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.25% # Type of FU issued 3959797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.25% # Type of FU issued 3969797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.25% # Type of FU issued 3979797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.25% # Type of FU issued 3989797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.25% # Type of FU issued 3999797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.25% # Type of FU issued 4009797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.25% # Type of FU issued 4019797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.25% # Type of FU issued 4029797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.25% # Type of FU issued 4039797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2400 22.25% 89.50% # Type of FU issued 4049797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1133 10.50% 100.00% # Type of FU issued 4058241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4068241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4079797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 10787 # Type of FU issued 4089797Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.260915 # Inst issue rate 4099797Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 113 # FU busy when requested 4109797Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.010476 # FU busy rate (busy events/executed inst) 4119797Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 36793 # Number of integer instruction queue reads 4129797Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 19230 # Number of integer instruction queue writes 4139797Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9615 # Number of integer instruction queue wakeup accesses 4148428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 4158428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 4168428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 4179797Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 10887 # Number of integer alu accesses 4188428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 4199729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores 4208428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4219797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1586 # Number of loads squashed 4229285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 4239490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations 4249797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 491 # Number of stores squashed 4258428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4268428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4278428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 4289797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 131 # Number of times an access to memory failed due to the cache being blocked 4298428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4309797Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1220 # Number of cycles IEW is squashing 4319797Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking 4329797Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking 4339797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 13080 # Number of instructions dispatched to IQ 4349797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 175 # Number of squashed instructions skipped by dispatch 4359797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2769 # Number of dispatched load instructions 4369797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1356 # Number of dispatched store instructions 4379797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions 4389348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 4398428SN/Asystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4409490Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations 4419797Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 123 # Number of branches that were predicted taken incorrectly 4429797Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 382 # Number of branches that were predicted not taken incorrectly 4439797Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 505 # Number of branch mispredicts detected at execute 4449797Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 10087 # Number of executed instructions 4459797Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2140 # Number of load instructions executed 4469797Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 700 # Number of squashed instructions skipped in execute 4478428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4489729Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 89 # number of nop insts executed 4499797Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3236 # number of memory reference insts executed 4509797Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1591 # Number of branches executed 4519729Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1096 # Number of stores executed 4529797Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.243983 # Inst execution rate 4539797Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 9767 # cumulative count of insts sent to commit 4549797Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 9625 # cumulative count of insts written-back 4559797Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 5058 # num instructions producing a value 4569797Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 6775 # num instructions consuming a value 4578428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4589797Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.232808 # insts written-back per cycle 4599797Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.746568 # average fanout of values written-back 4608428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4619797Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6689 # The number of squashed insts skipped by commit 4628428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 4639729Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted 4649797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13853 # Number of insts commited each cycle 4659797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.461200 # Number of insts commited each cycle 4669797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.266599 # Number of insts commited each cycle 4678428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4689797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 11035 79.66% 79.66% # Number of insts commited each cycle 4699797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1522 10.99% 90.64% # Number of insts commited each cycle 4709797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 530 3.83% 94.47% # Number of insts commited each cycle 4719797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 235 1.70% 96.17% # Number of insts commited each cycle 4729797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 147 1.06% 97.23% # Number of insts commited each cycle 4739797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 108 0.78% 98.01% # Number of insts commited each cycle 4749797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 103 0.74% 98.75% # Number of insts commited each cycle 4759797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 28 0.20% 98.95% # Number of insts commited each cycle 4769797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 145 1.05% 100.00% # Number of insts commited each cycle 4778428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4788428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4798428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4809797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13853 # Number of insts commited each cycle 4819150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6389 # Number of instructions committed 4829150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 4838428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4849150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2048 # Number of memory references committed 4859150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1183 # Number of loads committed 4868428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 4879150SAli.Saidi@ARM.comsystem.cpu.commit.branches 1050 # Number of branches committed 4888428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 4899150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 6307 # Number of committed integer instructions. 4908428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 4919797Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached 4928428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4939797Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 26435 # The number of ROB reads 4949797Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 27385 # The number of ROB writes 4959797Sandreas.hansson@arm.comsystem.cpu.timesIdled 269 # Number of times that the entire CPU went into an idle state and unscheduled itself 4969797Sandreas.hansson@arm.comsystem.cpu.idleCycles 26270 # Total number of cycles that the CPU has spent unscheduled due to idling 4979150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6372 # Number of Instructions Simulated 4989150SAli.Saidi@ARM.comsystem.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 4999150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 6372 # Number of Instructions Simulated 5009797Sandreas.hansson@arm.comsystem.cpu.cpi 6.488230 # CPI: Cycles Per Instruction 5019797Sandreas.hansson@arm.comsystem.cpu.cpi_total 6.488230 # CPI: Total CPI of All Threads 5029797Sandreas.hansson@arm.comsystem.cpu.ipc 0.154125 # IPC: Instructions Per Cycle 5039797Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.154125 # IPC: Total IPC of All Threads 5049797Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 12801 # number of integer regfile reads 5059797Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7277 # number of integer regfile writes 5068428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 5078428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 5088428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 5098428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 5109797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 1510909003 # Throughput (bytes/s) 5119729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution 5129729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution 5139729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 5149729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 5159838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 629 # Packet count per connected master and slave (bytes) 5169838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) 5179838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 977 # Packet count per connected master and slave (bytes) 5189838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) 5199838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 5209838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) 5219729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) 5229729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 5239729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) 5249729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 5259797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 531250 # Layer occupancy (ticks) 5269797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 5279797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 281250 # Layer occupancy (ticks) 5289797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 5299838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 5309838Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 159.268512 # Cycle average of tags in use 5319838Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1898 # Total number of references to valid blocks. 5329838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. 5339838Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 6.044586 # Average number of references to valid blocks. 5349838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5359838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 159.268512 # Average occupied blocks per requestor 5369838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.077768 # Average percentage of cache occupancy 5379838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.077768 # Average percentage of cache occupancy 5389797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1898 # number of ReadReq hits 5399797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1898 # number of ReadReq hits 5409797Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1898 # number of demand (read+write) hits 5419797Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1898 # number of demand (read+write) hits 5429797Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1898 # number of overall hits 5439797Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1898 # number of overall hits 5449797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 489 # number of ReadReq misses 5459797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 489 # number of ReadReq misses 5469797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 489 # number of demand (read+write) misses 5479797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 489 # number of demand (read+write) misses 5489797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 489 # number of overall misses 5499797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 489 # number of overall misses 5509797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 30301750 # number of ReadReq miss cycles 5519797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 30301750 # number of ReadReq miss cycles 5529797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 30301750 # number of demand (read+write) miss cycles 5539797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 30301750 # number of demand (read+write) miss cycles 5549797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 30301750 # number of overall miss cycles 5559797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 30301750 # number of overall miss cycles 5569797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2387 # number of ReadReq accesses(hits+misses) 5579797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2387 # number of ReadReq accesses(hits+misses) 5589797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2387 # number of demand (read+write) accesses 5599797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2387 # number of demand (read+write) accesses 5609797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2387 # number of overall (read+write) accesses 5619797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2387 # number of overall (read+write) accesses 5629797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204860 # miss rate for ReadReq accesses 5639797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.204860 # miss rate for ReadReq accesses 5649797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.204860 # miss rate for demand accesses 5659797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.204860 # miss rate for demand accesses 5669797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.204860 # miss rate for overall accesses 5679797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.204860 # miss rate for overall accesses 5689797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61966.768916 # average ReadReq miss latency 5699797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 61966.768916 # average ReadReq miss latency 5709797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency 5719797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 61966.768916 # average overall miss latency 5729797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 61966.768916 # average overall miss latency 5739797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 61966.768916 # average overall miss latency 5748428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5758428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5768428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 5778428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5788983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5798983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5808428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5818428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5829797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 174 # number of ReadReq MSHR hits 5839797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 174 # number of ReadReq MSHR hits 5849797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 174 # number of demand (read+write) MSHR hits 5859797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 174 # number of demand (read+write) MSHR hits 5869797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 174 # number of overall MSHR hits 5879797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 174 # number of overall MSHR hits 5889729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 5899729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 5909729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 5919729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 5929729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 5939729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses 5949797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21363250 # number of ReadReq MSHR miss cycles 5959797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 21363250 # number of ReadReq MSHR miss cycles 5969797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 21363250 # number of demand (read+write) MSHR miss cycles 5979797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 21363250 # number of demand (read+write) MSHR miss cycles 5989797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 21363250 # number of overall MSHR miss cycles 5999797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 21363250 # number of overall MSHR miss cycles 6009797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for ReadReq accesses 6019797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.131965 # mshr miss rate for ReadReq accesses 6029797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for demand accesses 6039797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.131965 # mshr miss rate for demand accesses 6049797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131965 # mshr miss rate for overall accesses 6059797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.131965 # mshr miss rate for overall accesses 6069797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67819.841270 # average ReadReq mshr miss latency 6079797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67819.841270 # average ReadReq mshr miss latency 6089797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency 6099797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency 6109797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67819.841270 # average overall mshr miss latency 6119797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 67819.841270 # average overall mshr miss latency 6128428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6139838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 6149838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 218.982908 # Cycle average of tags in use 6159838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 6169838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. 6179838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. 6189838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6199838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 159.353389 # Average occupied blocks per requestor 6209838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 59.629519 # Average occupied blocks per requestor 6219797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004863 # Average percentage of cache occupancy 6229797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001820 # Average percentage of cache occupancy 6239838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006683 # Average percentage of cache occupancy 6248835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 6258835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 6268835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 6278835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 6288835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 6298835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 6309729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses 6319322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses 6329729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses 6339096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 6349096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 6359729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses 6369322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 6379729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses 6389729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses 6399322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 6409729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 488 # number of overall misses 6419797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21037250 # number of ReadReq miss cycles 6429797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 7945250 # number of ReadReq miss cycles 6439797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 28982500 # number of ReadReq miss cycles 6449797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5109500 # number of ReadExReq miss cycles 6459797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 5109500 # number of ReadExReq miss cycles 6469797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 21037250 # number of demand (read+write) miss cycles 6479797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 13054750 # number of demand (read+write) miss cycles 6489797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 34092000 # number of demand (read+write) miss cycles 6499797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 21037250 # number of overall miss cycles 6509797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 13054750 # number of overall miss cycles 6519797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 34092000 # number of overall miss cycles 6529729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) 6539322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) 6549729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) 6559096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 6569096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 6579729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses 6589322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 6599729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses 6609729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses 6619322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 6629729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses 6639729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses 6648835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 6659729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses 6668835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6679055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6689729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses 6698835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 6709729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses 6719729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses 6728835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 6739729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses 6749797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66997.611465 # average ReadReq miss latency 6759797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78665.841584 # average ReadReq miss latency 6769797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 69837.349398 # average ReadReq miss latency 6779797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69993.150685 # average ReadExReq miss latency 6789797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 69993.150685 # average ReadExReq miss latency 6799797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency 6809797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency 6819797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 69860.655738 # average overall miss latency 6829797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66997.611465 # average overall miss latency 6839797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 75027.298851 # average overall miss latency 6849797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 69860.655738 # average overall miss latency 6858428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6868428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6878428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6888428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6898983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6908983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6918428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6928428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6939729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 6949322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 6959729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses 6969096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 6979096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 6989729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 6999322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 7009729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses 7019729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 7029322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 7039729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses 7049797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17080250 # number of ReadReq MSHR miss cycles 7059797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6700750 # number of ReadReq MSHR miss cycles 7069797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 23781000 # number of ReadReq MSHR miss cycles 7079797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4208000 # number of ReadExReq MSHR miss cycles 7089797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4208000 # number of ReadExReq MSHR miss cycles 7099797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17080250 # number of demand (read+write) MSHR miss cycles 7109797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10908750 # number of demand (read+write) MSHR miss cycles 7119797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 27989000 # number of demand (read+write) MSHR miss cycles 7129797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17080250 # number of overall MSHR miss cycles 7139797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10908750 # number of overall MSHR miss cycles 7149797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 27989000 # number of overall MSHR miss cycles 7159729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses 7168835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 7179729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses 7188835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 7199055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 7209729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses 7218835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 7229729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses 7239729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses 7248835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 7259729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses 7269797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54395.700637 # average ReadReq mshr miss latency 7279797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66344.059406 # average ReadReq mshr miss latency 7289797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57303.614458 # average ReadReq mshr miss latency 7299797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57643.835616 # average ReadExReq mshr miss latency 7309797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57643.835616 # average ReadExReq mshr miss latency 7319797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency 7329797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency 7339797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency 7349797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54395.700637 # average overall mshr miss latency 7359797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62693.965517 # average overall mshr miss latency 7369797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 57354.508197 # average overall mshr miss latency 7378428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 7389838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 7399838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 106.762654 # Cycle average of tags in use 7409838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2236 # Total number of references to valid blocks. 7419838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. 7429838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 12.850575 # Average number of references to valid blocks. 7439838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 7449838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 106.762654 # Average occupied blocks per requestor 7459838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.026065 # Average percentage of cache occupancy 7469838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.026065 # Average percentage of cache occupancy 7479797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1730 # number of ReadReq hits 7489797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1730 # number of ReadReq hits 7499348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 7509348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 7519797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits 7529797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits 7539797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits 7549797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2236 # number of overall hits 7559729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses 7569729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses 7579348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 7589348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 7599729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 529 # number of demand (read+write) misses 7609729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses 7619729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses 7629729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 529 # number of overall misses 7639797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11600250 # number of ReadReq miss cycles 7649797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11600250 # number of ReadReq miss cycles 7659797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 21979228 # number of WriteReq miss cycles 7669797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 21979228 # number of WriteReq miss cycles 7679797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 33579478 # number of demand (read+write) miss cycles 7689797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 33579478 # number of demand (read+write) miss cycles 7699797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 33579478 # number of overall miss cycles 7709797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 33579478 # number of overall miss cycles 7719797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1900 # number of ReadReq accesses(hits+misses) 7729797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1900 # number of ReadReq accesses(hits+misses) 7739348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 7749348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 7759797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2765 # number of demand (read+write) accesses 7769797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2765 # number of demand (read+write) accesses 7779797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2765 # number of overall (read+write) accesses 7789797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2765 # number of overall (read+write) accesses 7799797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089474 # miss rate for ReadReq accesses 7809797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.089474 # miss rate for ReadReq accesses 7819348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 7829348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 7839797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.191320 # miss rate for demand accesses 7849797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.191320 # miss rate for demand accesses 7859797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.191320 # miss rate for overall accesses 7869797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.191320 # miss rate for overall accesses 7879797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68236.764706 # average ReadReq miss latency 7889797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 68236.764706 # average ReadReq miss latency 7899797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61223.476323 # average WriteReq miss latency 7909797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 61223.476323 # average WriteReq miss latency 7919797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency 7929797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 63477.274102 # average overall miss latency 7939797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 63477.274102 # average overall miss latency 7949797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 63477.274102 # average overall miss latency 7959797Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 1567 # number of cycles access was blocked 7969348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7979729Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked 7989348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 7999797Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 47.484848 # average number of cycles each access was blocked 8009348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8019348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8029348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8039729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 8049729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 8059348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits 8069348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits 8079729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits 8089729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits 8099729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits 8109729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits 8119348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 8129348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 8139348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 8149348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 8159348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 8169348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 8179348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 8189348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 8199797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8053750 # number of ReadReq MSHR miss cycles 8209797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 8053750 # number of ReadReq MSHR miss cycles 8219797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5185500 # number of WriteReq MSHR miss cycles 8229797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 5185500 # number of WriteReq MSHR miss cycles 8239797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 13239250 # number of demand (read+write) MSHR miss cycles 8249797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 13239250 # number of demand (read+write) MSHR miss cycles 8259797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 13239250 # number of overall MSHR miss cycles 8269797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 13239250 # number of overall MSHR miss cycles 8279797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053158 # mshr miss rate for ReadReq accesses 8289797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053158 # mshr miss rate for ReadReq accesses 8299348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 8309348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 8319797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for demand accesses 8329797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.062929 # mshr miss rate for demand accesses 8339797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062929 # mshr miss rate for overall accesses 8349797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.062929 # mshr miss rate for overall accesses 8359797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79740.099010 # average ReadReq mshr miss latency 8369797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79740.099010 # average ReadReq mshr miss latency 8379797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71034.246575 # average WriteReq mshr miss latency 8389797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71034.246575 # average WriteReq mshr miss latency 8399797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency 8409797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency 8419797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76087.643678 # average overall mshr miss latency 8429797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 76087.643678 # average overall mshr miss latency 8439348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8443096SN/A 8453096SN/A---------- End Simulation Statistics ---------- 846