stats.txt revision 9729
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 39729Sandreas.hansson@arm.comsim_seconds 0.000021 # Number of seconds simulated 49729Sandreas.hansson@arm.comsim_ticks 20632000 # Number of ticks simulated 59729Sandreas.hansson@arm.comfinal_tick 20632000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79729Sandreas.hansson@arm.comhost_inst_rate 1782 # Simulator instruction rate (inst/s) 89729Sandreas.hansson@arm.comhost_op_rate 1782 # Simulator op (including micro ops) rate (op/s) 99729Sandreas.hansson@arm.comhost_tick_rate 5769044 # Simulator tick rate (ticks/s) 109729Sandreas.hansson@arm.comhost_mem_usage 227476 # Number of bytes of host memory used 119729Sandreas.hansson@arm.comhost_seconds 3.58 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6372 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6372 # Number of ops (including micro ops) simulated 149729Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 159322Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 169729Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 31168 # Number of bytes read from this memory 179729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 189729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 199729Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 209322Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 219729Sandreas.hansson@arm.comsystem.physmem.num_reads::total 487 # Number of read requests responded to by this memory 229729Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 970918961 # Total read bandwidth from this memory (bytes/s) 239729Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 539744087 # Total read bandwidth from this memory (bytes/s) 249729Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1510663048 # Total read bandwidth from this memory (bytes/s) 259729Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 970918961 # Instruction read bandwidth from this memory (bytes/s) 269729Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 970918961 # Instruction read bandwidth from this memory (bytes/s) 279729Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 970918961 # Total bandwidth to/from this memory (bytes/s) 289729Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 539744087 # Total bandwidth to/from this memory (bytes/s) 299729Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1510663048 # Total bandwidth to/from this memory (bytes/s) 309729Sandreas.hansson@arm.comsystem.physmem.readReqs 488 # Total number of read requests seen 319312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 329729Sandreas.hansson@arm.comsystem.physmem.cpureqs 488 # Reqs generatd by CPU via cache - shady 339729Sandreas.hansson@arm.comsystem.physmem.bytesRead 31168 # Total number of bytes read from memory 349312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 359729Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() 369312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 379312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 389312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 399729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 69 # Track reads on a per bank basis 409729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 34 # Track reads on a per bank basis 419729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 32 # Track reads on a per bank basis 429729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis 439729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 43 # Track reads on a per bank basis 449729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 21 # Track reads on a per bank basis 459729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis 469729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis 479729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 489729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis 499729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 23 # Track reads on a per bank basis 509729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis 519729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 14 # Track reads on a per bank basis 529729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis 539729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 45 # Track reads on a per bank basis 549729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis 559312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 569312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 579312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 589312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 729312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 739729Sandreas.hansson@arm.comsystem.physmem.totGap 20599000 # Total gap between requests 749312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 759312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 769312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 779312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 789312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 799312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 809729Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 488 # Categorize read packet sizes 819568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 829568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 839568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 849568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 859568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 869568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 879568Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Categorize write packet sizes 889729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see 899729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see 909729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see 919729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 929729Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 939322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 949312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 959312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 969312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 979312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 989312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1529729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 69 # Bytes accessed per row activation 1539729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 293.101449 # Bytes accessed per row activation 1549729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 146.944081 # Bytes accessed per row activation 1559729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 525.630997 # Bytes accessed per row activation 1569729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::64 33 47.83% 47.83% # Bytes accessed per row activation 1579729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128 7 10.14% 57.97% # Bytes accessed per row activation 1589729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::192 9 13.04% 71.01% # Bytes accessed per row activation 1599729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256 5 7.25% 78.26% # Bytes accessed per row activation 1609729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::320 2 2.90% 81.16% # Bytes accessed per row activation 1619729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384 3 4.35% 85.51% # Bytes accessed per row activation 1629729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::448 2 2.90% 88.41% # Bytes accessed per row activation 1639729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512 2 2.90% 91.30% # Bytes accessed per row activation 1649729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::576 1 1.45% 92.75% # Bytes accessed per row activation 1659729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::960 1 1.45% 94.20% # Bytes accessed per row activation 1669729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1664 1 1.45% 95.65% # Bytes accessed per row activation 1679729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1920 1 1.45% 97.10% # Bytes accessed per row activation 1689729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2496 1 1.45% 98.55% # Bytes accessed per row activation 1699729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2880 1 1.45% 100.00% # Bytes accessed per row activation 1709729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 69 # Bytes accessed per row activation 1719729Sandreas.hansson@arm.comsystem.physmem.totQLat 2633750 # Total cycles spent in queuing delays 1729729Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 12636250 # Sum of mem lat for all requests 1739729Sandreas.hansson@arm.comsystem.physmem.totBusLat 2440000 # Total cycles spent in databus access 1749729Sandreas.hansson@arm.comsystem.physmem.totBankLat 7562500 # Total cycles spent in bank access 1759729Sandreas.hansson@arm.comsystem.physmem.avgQLat 5397.03 # Average queueing delay per request 1769729Sandreas.hansson@arm.comsystem.physmem.avgBankLat 15496.93 # Average bank access latency per request 1779490Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per request 1789729Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 25893.95 # Average memory access latency 1799729Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1510.66 # Average achieved read bandwidth in MB/s 1809312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1819729Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 1510.66 # Average consumed read bandwidth in MB/s 1829312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1839490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 1849729Sandreas.hansson@arm.comsystem.physmem.busUtil 11.80 # Data bus utilization in percentage 1859729Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.61 # Average read queue length over time 1869312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1879729Sandreas.hansson@arm.comsystem.physmem.readRowHits 419 # Number of row buffer hits during reads 1889312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1899729Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 85.86 # Row buffer hit rate for reads 1909312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1919729Sandreas.hansson@arm.comsystem.physmem.avgGap 42211.07 # Average gap between requests 1929729Sandreas.hansson@arm.comsystem.membus.throughput 1510663048 # Throughput (bytes/s) 1939729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 415 # Transaction distribution 1949729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 414 # Transaction distribution 1959729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 73 # Transaction distribution 1969729Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 73 # Transaction distribution 1979729Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side 975 # Packet count per connected master and slave (bytes) 1989729Sandreas.hansson@arm.comsystem.membus.pkt_count 975 # Packet count per connected master and slave (bytes) 1999729Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side 31168 # Cumulative packet size per connected master and slave (bytes) 2009729Sandreas.hansson@arm.comsystem.membus.tot_pkt_size 31168 # Cumulative packet size per connected master and slave (bytes) 2019729Sandreas.hansson@arm.comsystem.membus.data_through_bus 31168 # Total data (bytes) 2029729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 2039729Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 600000 # Layer occupancy (ticks) 2049729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 2059729Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4550500 # Layer occupancy (ticks) 2069729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 22.1 # Layer utilization (%) 2079729Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2906 # Number of BP lookups 2089729Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1709 # Number of conditional branches predicted 2099729Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 511 # Number of conditional branches incorrect 2109729Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 2211 # Number of BTB lookups 2119729Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 759 # Number of BTB hits 2129481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2139729Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 34.328358 # BTB Hit Percentage 2149729Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 420 # Number of times the RAS was used to get a target. 2159490Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 2168428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2178428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2188428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2198428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 2209729Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 2097 # DTB read hits 2219729Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 47 # DTB read misses 2228428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 2239729Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 2144 # DTB read accesses 2249729Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 1063 # DTB write hits 2259729Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 31 # DTB write misses 2268428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 2279729Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 1094 # DTB write accesses 2289729Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 3160 # DTB hits 2299729Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 78 # DTB misses 2308428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 2319729Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 3238 # DTB accesses 2329729Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 2393 # ITB hits 2339729Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 39 # ITB misses 2348428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 2359729Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 2432 # ITB accesses 2368428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2378428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2388428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2398428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2408428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2418428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2428428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2438428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2448428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2458428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2468428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2478428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2488428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 2499729Sandreas.hansson@arm.comsystem.cpu.numCycles 41265 # number of cpu cycles simulated 2508428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2518428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2529729Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8511 # Number of cycles fetch is stalled on an Icache miss 2539729Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 16675 # Number of instructions fetch has processed 2549729Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2906 # Number of branches that fetch encountered 2559729Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 1179 # Number of branches that fetch has predicted taken 2569729Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 2982 # Number of cycles fetch has run and was not squashing or blocked 2579729Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1908 # Number of cycles fetch has spent squashing 2589729Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 1525 # Number of cycles fetch has spent blocked 2599729Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2609729Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 759 # Number of stall cycles due to pending traps 2619729Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 2393 # Number of cache lines fetched 2629729Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 379 # Number of outstanding Icache misses that were squashed 2639729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 15107 # Number of instructions fetched each cycle (Total) 2649729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.103793 # Number of instructions fetched each cycle (Total) 2659729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.501598 # Number of instructions fetched each cycle (Total) 2666291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2679729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 12125 80.26% 80.26% # Number of instructions fetched each cycle (Total) 2689729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 320 2.12% 82.38% # Number of instructions fetched each cycle (Total) 2699729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 234 1.55% 83.93% # Number of instructions fetched each cycle (Total) 2709729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 215 1.42% 85.35% # Number of instructions fetched each cycle (Total) 2719729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 256 1.69% 87.05% # Number of instructions fetched each cycle (Total) 2729729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 241 1.60% 88.64% # Number of instructions fetched each cycle (Total) 2739729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 264 1.75% 90.39% # Number of instructions fetched each cycle (Total) 2749729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 187 1.24% 91.63% # Number of instructions fetched each cycle (Total) 2759729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1265 8.37% 100.00% # Number of instructions fetched each cycle (Total) 2766291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2776291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2786291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2799729Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 15107 # Number of instructions fetched each cycle (Total) 2809729Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.070423 # Number of branch fetches per cycle 2819729Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.404095 # Number of inst fetches per cycle 2829729Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 9355 # Number of cycles decode is idle 2839729Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 1672 # Number of cycles decode is blocked 2849729Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2793 # Number of cycles decode is running 2859729Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking 2869729Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1224 # Number of cycles decode is squashing 2879729Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 242 # Number of times decode resolved a branch 2889729Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction 2899729Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 15419 # Number of instructions handled by decode 2909729Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 223 # Number of squashed instructions handled by decode 2919729Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1224 # Number of cycles rename is squashing 2929729Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9566 # Number of cycles rename is idle 2939729Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 693 # Number of cycles rename is blocking 2949729Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 555 # count of cycles rename stalled for serializing inst 2959729Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2621 # Number of cycles rename is running 2969729Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 448 # Number of cycles rename is unblocking 2979729Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 14692 # Number of instructions processed by rename 2989729Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 10 # Number of times rename has blocked due to ROB full 2999348SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full 3009729Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 388 # Number of times rename has blocked due to LSQ full 3019729Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 11020 # Number of destination operands rename has renamed 3029729Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 18321 # Number of register rename lookups that rename has made 3039729Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 18304 # Number of integer rename lookups 3048428SN/Asystem.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 3059150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 3069729Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6450 # Number of HB maps that are undone due to squashing 3079490Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 30 # count of serializing insts renamed 3089490Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed 3099729Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 976 # count of insts added to the skid buffer 3109729Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2777 # Number of loads inserted to the mem dependence unit. 3119729Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1360 # Number of stores inserted to the mem dependence unit. 3129490Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. 3138428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 3149729Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 12985 # Number of instructions added to the IQ (excludes non-spec) 3159729Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ 3169729Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 10814 # Number of instructions issued 3179729Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued 3189729Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6280 # Number of squashed instructions iterated over during squash; mainly for profiling 3199729Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3603 # Number of squashed operands that are examined and possibly removed from graph 3209729Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed 3219729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 15107 # Number of insts issued each cycle 3229729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.715827 # Number of insts issued each cycle 3239729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.359683 # Number of insts issued each cycle 3248428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3259729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10552 69.85% 69.85% # Number of insts issued each cycle 3269729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1715 11.35% 81.20% # Number of insts issued each cycle 3279729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 1107 7.33% 88.53% # Number of insts issued each cycle 3289729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 773 5.12% 93.65% # Number of insts issued each cycle 3299729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 494 3.27% 96.92% # Number of insts issued each cycle 3309729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 269 1.78% 98.70% # Number of insts issued each cycle 3319729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 148 0.98% 99.68% # Number of insts issued each cycle 3329729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 35 0.23% 99.91% # Number of insts issued each cycle 3339729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 14 0.09% 100.00% # Number of insts issued each cycle 3348428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3358428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3368428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3379729Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 15107 # Number of insts issued each cycle 3388428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3399729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 14 12.61% 12.61% # attempts to use FU when none available 3409729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 12.61% # attempts to use FU when none available 3419729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 12.61% # attempts to use FU when none available 3429729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 12.61% # attempts to use FU when none available 3439729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 12.61% # attempts to use FU when none available 3449729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 12.61% # attempts to use FU when none available 3459729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 12.61% # attempts to use FU when none available 3469729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 12.61% # attempts to use FU when none available 3479729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.61% # attempts to use FU when none available 3489729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 12.61% # attempts to use FU when none available 3499729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.61% # attempts to use FU when none available 3509729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 12.61% # attempts to use FU when none available 3519729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 12.61% # attempts to use FU when none available 3529729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 12.61% # attempts to use FU when none available 3539729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 12.61% # attempts to use FU when none available 3549729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 12.61% # attempts to use FU when none available 3559729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.61% # attempts to use FU when none available 3569729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 12.61% # attempts to use FU when none available 3579729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.61% # attempts to use FU when none available 3589729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.61% # attempts to use FU when none available 3599729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.61% # attempts to use FU when none available 3609729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.61% # attempts to use FU when none available 3619729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.61% # attempts to use FU when none available 3629729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.61% # attempts to use FU when none available 3639729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.61% # attempts to use FU when none available 3649729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.61% # attempts to use FU when none available 3659729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.61% # attempts to use FU when none available 3669729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.61% # attempts to use FU when none available 3679729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.61% # attempts to use FU when none available 3689729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 59 53.15% 65.77% # attempts to use FU when none available 3699729Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 38 34.23% 100.00% # attempts to use FU when none available 3708428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3718428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3728241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 3739729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 7260 67.14% 67.15% # Type of FU issued 3749729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued 3759729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued 3769729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.18% # Type of FU issued 3779729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.18% # Type of FU issued 3789729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.18% # Type of FU issued 3799729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.18% # Type of FU issued 3809729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.18% # Type of FU issued 3819729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.18% # Type of FU issued 3829729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.18% # Type of FU issued 3839729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.18% # Type of FU issued 3849729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.18% # Type of FU issued 3859729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.18% # Type of FU issued 3869729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.18% # Type of FU issued 3879729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.18% # Type of FU issued 3889729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.18% # Type of FU issued 3899729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.18% # Type of FU issued 3909729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.18% # Type of FU issued 3919729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.18% # Type of FU issued 3929729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.18% # Type of FU issued 3939729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.18% # Type of FU issued 3949729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.18% # Type of FU issued 3959729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.18% # Type of FU issued 3969729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.18% # Type of FU issued 3979729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.18% # Type of FU issued 3989729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.18% # Type of FU issued 3999729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.18% # Type of FU issued 4009729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.18% # Type of FU issued 4019729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.18% # Type of FU issued 4029729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2415 22.33% 89.51% # Type of FU issued 4039729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1134 10.49% 100.00% # Type of FU issued 4048241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4058241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 4069729Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 10814 # Type of FU issued 4079729Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.262062 # Inst issue rate 4089729Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 111 # FU busy when requested 4099729Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.010264 # FU busy rate (busy events/executed inst) 4109729Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 36878 # Number of integer instruction queue reads 4119729Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 19300 # Number of integer instruction queue writes 4129729Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9631 # Number of integer instruction queue wakeup accesses 4138428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 4148428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 4158428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 4169729Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 10912 # Number of integer alu accesses 4178428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 4189729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores 4198428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 4209729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1594 # Number of loads squashed 4219285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 4229490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations 4239729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 495 # Number of stores squashed 4248428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4258428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4268428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 4279729Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 136 # Number of times an access to memory failed due to the cache being blocked 4288428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4299729Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1224 # Number of cycles IEW is squashing 4309729Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 218 # Number of cycles IEW is blocking 4319729Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking 4329729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 13104 # Number of instructions dispatched to IQ 4339729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch 4349729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2777 # Number of dispatched load instructions 4359729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1360 # Number of dispatched store instructions 4369729Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions 4379348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 4388428SN/Asystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4399490Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations 4409729Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 124 # Number of branches that were predicted taken incorrectly 4419729Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly 4429729Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 509 # Number of branch mispredicts detected at execute 4439729Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 10116 # Number of executed instructions 4449729Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2155 # Number of load instructions executed 4459729Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 698 # Number of squashed instructions skipped in execute 4468428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4479729Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 89 # number of nop insts executed 4489729Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3251 # number of memory reference insts executed 4499729Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1595 # Number of branches executed 4509729Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1096 # Number of stores executed 4519729Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.245147 # Inst execution rate 4529729Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 9787 # cumulative count of insts sent to commit 4539729Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 9641 # cumulative count of insts written-back 4549729Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 5053 # num instructions producing a value 4559729Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 6805 # num instructions consuming a value 4568428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4579729Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.233636 # insts written-back per cycle 4589729Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.742542 # average fanout of values written-back 4598428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4609729Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6713 # The number of squashed insts skipped by commit 4618428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 4629729Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 430 # The number of times a branch was mispredicted 4639729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13883 # Number of insts commited each cycle 4649729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.460203 # Number of insts commited each cycle 4659729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.266435 # Number of insts commited each cycle 4668428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4679729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 11056 79.64% 79.64% # Number of insts commited each cycle 4689729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1544 11.12% 90.76% # Number of insts commited each cycle 4699729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 511 3.68% 94.44% # Number of insts commited each cycle 4709729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 249 1.79% 96.23% # Number of insts commited each cycle 4719729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 151 1.09% 97.32% # Number of insts commited each cycle 4729729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 81 0.58% 97.90% # Number of insts commited each cycle 4739729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 113 0.81% 98.72% # Number of insts commited each cycle 4749729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 35 0.25% 98.97% # Number of insts commited each cycle 4759729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 143 1.03% 100.00% # Number of insts commited each cycle 4768428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4778428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4788428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4799729Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13883 # Number of insts commited each cycle 4809150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6389 # Number of instructions committed 4819150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 4828428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4839150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2048 # Number of memory references committed 4849150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1183 # Number of loads committed 4858428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 4869150SAli.Saidi@ARM.comsystem.cpu.commit.branches 1050 # Number of branches committed 4878428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 4889150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 6307 # Number of committed integer instructions. 4898428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 4909729Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 143 # number cycles where commit BW limit reached 4918428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4929729Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 26491 # The number of ROB reads 4939729Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 27437 # The number of ROB writes 4949729Sandreas.hansson@arm.comsystem.cpu.timesIdled 274 # Number of times that the entire CPU went into an idle state and unscheduled itself 4959729Sandreas.hansson@arm.comsystem.cpu.idleCycles 26158 # Total number of cycles that the CPU has spent unscheduled due to idling 4969150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6372 # Number of Instructions Simulated 4979150SAli.Saidi@ARM.comsystem.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 4989150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 6372 # Number of Instructions Simulated 4999729Sandreas.hansson@arm.comsystem.cpu.cpi 6.475989 # CPI: Cycles Per Instruction 5009729Sandreas.hansson@arm.comsystem.cpu.cpi_total 6.475989 # CPI: Total CPI of All Threads 5019729Sandreas.hansson@arm.comsystem.cpu.ipc 0.154417 # IPC: Instructions Per Cycle 5029729Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.154417 # IPC: Total IPC of All Threads 5039729Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 12831 # number of integer regfile reads 5049729Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7294 # number of integer regfile writes 5058428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 5068428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 5078428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 5088428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 5099729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 1513765025 # Throughput (bytes/s) 5109729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution 5119729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution 5129729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 5139729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 5149729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 629 # Packet count per connected master and slave (bytes) 5159729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 348 # Packet count per connected master and slave (bytes) 5169729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count 977 # Packet count per connected master and slave (bytes) 5179729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 20096 # Cumulative packet size per connected master and slave (bytes) 5189729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 11136 # Cumulative packet size per connected master and slave (bytes) 5199729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size 31232 # Cumulative packet size per connected master and slave (bytes) 5209729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 31232 # Total data (bytes) 5219729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 5229729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks) 5239729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 5249729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks) 5259729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) 5269729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 261000 # Layer occupancy (ticks) 5279729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 5288428SN/Asystem.cpu.icache.replacements 0 # number of replacements 5299729Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 159.617277 # Cycle average of tags in use 5309729Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 1903 # Total number of references to valid blocks. 5319729Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. 5329729Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 6.060510 # Average number of references to valid blocks. 5338428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5349729Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 159.617277 # Average occupied blocks per requestor 5359729Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.077938 # Average percentage of cache occupancy 5369729Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.077938 # Average percentage of cache occupancy 5379729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1903 # number of ReadReq hits 5389729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1903 # number of ReadReq hits 5399729Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1903 # number of demand (read+write) hits 5409729Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1903 # number of demand (read+write) hits 5419729Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1903 # number of overall hits 5429729Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1903 # number of overall hits 5439729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 490 # number of ReadReq misses 5449729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 490 # number of ReadReq misses 5459729Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 490 # number of demand (read+write) misses 5469729Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 490 # number of demand (read+write) misses 5479729Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 490 # number of overall misses 5489729Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 490 # number of overall misses 5499729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 30064500 # number of ReadReq miss cycles 5509729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 30064500 # number of ReadReq miss cycles 5519729Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 30064500 # number of demand (read+write) miss cycles 5529729Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 30064500 # number of demand (read+write) miss cycles 5539729Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 30064500 # number of overall miss cycles 5549729Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 30064500 # number of overall miss cycles 5559729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2393 # number of ReadReq accesses(hits+misses) 5569729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2393 # number of ReadReq accesses(hits+misses) 5579729Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2393 # number of demand (read+write) accesses 5589729Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2393 # number of demand (read+write) accesses 5599729Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2393 # number of overall (read+write) accesses 5609729Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2393 # number of overall (read+write) accesses 5619729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204764 # miss rate for ReadReq accesses 5629729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.204764 # miss rate for ReadReq accesses 5639729Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.204764 # miss rate for demand accesses 5649729Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.204764 # miss rate for demand accesses 5659729Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.204764 # miss rate for overall accesses 5669729Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.204764 # miss rate for overall accesses 5679729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61356.122449 # average ReadReq miss latency 5689729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 61356.122449 # average ReadReq miss latency 5699729Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency 5709729Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 61356.122449 # average overall miss latency 5719729Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 61356.122449 # average overall miss latency 5729729Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 61356.122449 # average overall miss latency 5738428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5748428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5758428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 5768428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5778983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5788983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5798428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5808428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5819729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 175 # number of ReadReq MSHR hits 5829729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits 5839729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 175 # number of demand (read+write) MSHR hits 5849729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits 5859729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 175 # number of overall MSHR hits 5869729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 175 # number of overall MSHR hits 5879729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 5889729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 5899729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 5909729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 5919729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 5929729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses 5939729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21382000 # number of ReadReq MSHR miss cycles 5949729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 21382000 # number of ReadReq MSHR miss cycles 5959729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 21382000 # number of demand (read+write) MSHR miss cycles 5969729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 21382000 # number of demand (read+write) MSHR miss cycles 5979729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 21382000 # number of overall MSHR miss cycles 5989729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 21382000 # number of overall MSHR miss cycles 5999729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for ReadReq accesses 6009729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.131634 # mshr miss rate for ReadReq accesses 6019729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for demand accesses 6029729Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.131634 # mshr miss rate for demand accesses 6039729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131634 # mshr miss rate for overall accesses 6049729Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.131634 # mshr miss rate for overall accesses 6059729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67879.365079 # average ReadReq mshr miss latency 6069729Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67879.365079 # average ReadReq mshr miss latency 6079729Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67879.365079 # average overall mshr miss latency 6089729Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 67879.365079 # average overall mshr miss latency 6099729Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67879.365079 # average overall mshr miss latency 6109729Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 67879.365079 # average overall mshr miss latency 6118428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 6128428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 6139729Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 219.419406 # Cycle average of tags in use 6148428SN/Asystem.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 6159729Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks. 6169729Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks. 6178428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6189729Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 159.699673 # Average occupied blocks per requestor 6199729Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 59.719733 # Average occupied blocks per requestor 6209729Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004874 # Average percentage of cache occupancy 6219729Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001823 # Average percentage of cache occupancy 6229729Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.006696 # Average percentage of cache occupancy 6238835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 6248835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 6258835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 6268835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 6278835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 6288835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 6299729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses 6309322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses 6319729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses 6329096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 6339096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 6349729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses 6359322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 6369729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses 6379729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses 6389322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 6399729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 488 # number of overall misses 6409729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21056000 # number of ReadReq miss cycles 6419729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 8037000 # number of ReadReq miss cycles 6429729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 29093000 # number of ReadReq miss cycles 6439729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5106500 # number of ReadExReq miss cycles 6449729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 5106500 # number of ReadExReq miss cycles 6459729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 21056000 # number of demand (read+write) miss cycles 6469729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 13143500 # number of demand (read+write) miss cycles 6479729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 34199500 # number of demand (read+write) miss cycles 6489729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 21056000 # number of overall miss cycles 6499729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 13143500 # number of overall miss cycles 6509729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 34199500 # number of overall miss cycles 6519729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) 6529322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) 6539729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) 6549096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 6559096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 6569729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses 6579322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 6589729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses 6599729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses 6609322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 6619729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses 6629729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses 6638835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 6649729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses 6658835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6669055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6679729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses 6688835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 6699729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses 6709729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses 6718835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 6729729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses 6739729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67057.324841 # average ReadReq miss latency 6749729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79574.257426 # average ReadReq miss latency 6759729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 70103.614458 # average ReadReq miss latency 6769729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69952.054795 # average ReadExReq miss latency 6779729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 69952.054795 # average ReadExReq miss latency 6789729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67057.324841 # average overall miss latency 6799729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 75537.356322 # average overall miss latency 6809729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 70080.942623 # average overall miss latency 6819729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67057.324841 # average overall miss latency 6829729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 75537.356322 # average overall miss latency 6839729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 70080.942623 # average overall miss latency 6848428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6858428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6868428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6878428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6888983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6898983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6908428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6918428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6929729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 6939322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 6949729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses 6959096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 6969096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 6979729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 6989322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 6999729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses 7009729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 7019322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 7029729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses 7039729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17174500 # number of ReadReq MSHR miss cycles 7049729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6801500 # number of ReadReq MSHR miss cycles 7059729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 23976000 # number of ReadReq MSHR miss cycles 7069729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4212000 # number of ReadExReq MSHR miss cycles 7079729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4212000 # number of ReadExReq MSHR miss cycles 7089729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17174500 # number of demand (read+write) MSHR miss cycles 7099729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11013500 # number of demand (read+write) MSHR miss cycles 7109729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 28188000 # number of demand (read+write) MSHR miss cycles 7119729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17174500 # number of overall MSHR miss cycles 7129729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11013500 # number of overall MSHR miss cycles 7139729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 28188000 # number of overall MSHR miss cycles 7149729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses 7158835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 7169729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses 7178835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 7189055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 7199729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses 7208835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 7219729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses 7229729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses 7238835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 7249729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses 7259729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54695.859873 # average ReadReq mshr miss latency 7269729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67341.584158 # average ReadReq mshr miss latency 7279729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57773.493976 # average ReadReq mshr miss latency 7289729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57698.630137 # average ReadExReq mshr miss latency 7299729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57698.630137 # average ReadExReq mshr miss latency 7309729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54695.859873 # average overall mshr miss latency 7319729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63295.977011 # average overall mshr miss latency 7329729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 57762.295082 # average overall mshr miss latency 7339729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54695.859873 # average overall mshr miss latency 7349729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63295.977011 # average overall mshr miss latency 7359729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 57762.295082 # average overall mshr miss latency 7368428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 7379348SAli.Saidi@ARM.comsystem.cpu.dcache.replacements 0 # number of replacements 7389729Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 106.967869 # Cycle average of tags in use 7399729Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 2246 # Total number of references to valid blocks. 7409348SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. 7419729Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 12.908046 # Average number of references to valid blocks. 7429348SAli.Saidi@ARM.comsystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 7439729Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 106.967869 # Average occupied blocks per requestor 7449729Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.026115 # Average percentage of cache occupancy 7459729Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::total 0.026115 # Average percentage of cache occupancy 7469729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1740 # number of ReadReq hits 7479729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1740 # number of ReadReq hits 7489348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 7499348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 7509729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2246 # number of demand (read+write) hits 7519729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2246 # number of demand (read+write) hits 7529729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2246 # number of overall hits 7539729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2246 # number of overall hits 7549729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses 7559729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses 7569348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 7579348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 7589729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 529 # number of demand (read+write) misses 7599729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 529 # number of demand (read+write) misses 7609729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 529 # number of overall misses 7619729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 529 # number of overall misses 7629729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11698500 # number of ReadReq miss cycles 7639729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11698500 # number of ReadReq miss cycles 7649729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 21723478 # number of WriteReq miss cycles 7659729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 21723478 # number of WriteReq miss cycles 7669729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 33421978 # number of demand (read+write) miss cycles 7679729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 33421978 # number of demand (read+write) miss cycles 7689729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 33421978 # number of overall miss cycles 7699729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 33421978 # number of overall miss cycles 7709729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1910 # number of ReadReq accesses(hits+misses) 7719729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1910 # number of ReadReq accesses(hits+misses) 7729348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 7739348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 7749729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2775 # number of demand (read+write) accesses 7759729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2775 # number of demand (read+write) accesses 7769729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2775 # number of overall (read+write) accesses 7779729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2775 # number of overall (read+write) accesses 7789729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.089005 # miss rate for ReadReq accesses 7799729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.089005 # miss rate for ReadReq accesses 7809348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 7819348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 7829729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.190631 # miss rate for demand accesses 7839729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.190631 # miss rate for demand accesses 7849729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.190631 # miss rate for overall accesses 7859729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.190631 # miss rate for overall accesses 7869729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68814.705882 # average ReadReq miss latency 7879729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 68814.705882 # average ReadReq miss latency 7889729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60511.080780 # average WriteReq miss latency 7899729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 60511.080780 # average WriteReq miss latency 7909729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency 7919729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 63179.542533 # average overall miss latency 7929729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 63179.542533 # average overall miss latency 7939729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 63179.542533 # average overall miss latency 7949729Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 1568 # number of cycles access was blocked 7959348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7969729Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked 7979348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 7989729Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 47.515152 # average number of cycles each access was blocked 7999348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8009348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 8019348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 8029729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 8039729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 8049348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits 8059348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits 8069729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 355 # number of demand (read+write) MSHR hits 8079729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 355 # number of demand (read+write) MSHR hits 8089729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 355 # number of overall MSHR hits 8099729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 355 # number of overall MSHR hits 8109348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 8119348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 8129348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 8139348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 8149348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 8159348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 8169348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 8179348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 8189729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8145500 # number of ReadReq MSHR miss cycles 8199729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 8145500 # number of ReadReq MSHR miss cycles 8209729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5182500 # number of WriteReq MSHR miss cycles 8219729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 5182500 # number of WriteReq MSHR miss cycles 8229729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 13328000 # number of demand (read+write) MSHR miss cycles 8239729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 13328000 # number of demand (read+write) MSHR miss cycles 8249729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 13328000 # number of overall MSHR miss cycles 8259729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 13328000 # number of overall MSHR miss cycles 8269729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052880 # mshr miss rate for ReadReq accesses 8279729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052880 # mshr miss rate for ReadReq accesses 8289348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 8299348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 8309729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for demand accesses 8319729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.062703 # mshr miss rate for demand accesses 8329729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062703 # mshr miss rate for overall accesses 8339729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.062703 # mshr miss rate for overall accesses 8349729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80648.514851 # average ReadReq mshr miss latency 8359729Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80648.514851 # average ReadReq mshr miss latency 8369729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70993.150685 # average WriteReq mshr miss latency 8379729Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70993.150685 # average WriteReq mshr miss latency 8389729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency 8399729Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency 8409729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76597.701149 # average overall mshr miss latency 8419729Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 76597.701149 # average overall mshr miss latency 8429348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8433096SN/A 8443096SN/A---------- End Simulation Statistics ---------- 845