stats.txt revision 9568
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 39322Sandreas.hansson@arm.comsim_seconds 0.000016 # Number of seconds simulated 49568Sandreas.hansson@arm.comsim_ticks 16039500 # Number of ticks simulated 59568Sandreas.hansson@arm.comfinal_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79568Sandreas.hansson@arm.comhost_inst_rate 1336 # Simulator instruction rate (inst/s) 89568Sandreas.hansson@arm.comhost_op_rate 1336 # Simulator op (including micro ops) rate (op/s) 99568Sandreas.hansson@arm.comhost_tick_rate 3362323 # Simulator tick rate (ticks/s) 109568Sandreas.hansson@arm.comhost_mem_usage 225744 # Number of bytes of host memory used 119568Sandreas.hansson@arm.comhost_seconds 4.77 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6372 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6372 # Number of ops (including micro ops) simulated 149490Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 159322Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 169490Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 31104 # Number of bytes read from this memory 179490Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 189490Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 199490Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory 209322Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 219490Sandreas.hansson@arm.comsystem.physmem.num_reads::total 486 # Number of read requests responded to by this memory 229568Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s) 239568Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s) 249568Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s) 259568Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s) 269568Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s) 279568Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s) 289568Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s) 299568Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s) 309490Sandreas.hansson@arm.comsystem.physmem.readReqs 486 # Total number of read requests seen 319312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 329490Sandreas.hansson@arm.comsystem.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady 339490Sandreas.hansson@arm.comsystem.physmem.bytesRead 31104 # Total number of bytes read from memory 349312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 359490Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() 369312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 379312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 389312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 399490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 50 # Track reads on a per bank basis 409490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 24 # Track reads on a per bank basis 419490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 22 # Track reads on a per bank basis 429312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis 439490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 26 # Track reads on a per bank basis 449490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 50 # Track reads on a per bank basis 459490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 47 # Track reads on a per bank basis 469490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 50 # Track reads on a per bank basis 479490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 31 # Track reads on a per bank basis 489490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 44 # Track reads on a per bank basis 499490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 20 # Track reads on a per bank basis 509490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 6 # Track reads on a per bank basis 519490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 8 # Track reads on a per bank basis 529490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 3 # Track reads on a per bank basis 539490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 30 # Track reads on a per bank basis 549490Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 45 # Track reads on a per bank basis 559312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 569312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 579312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 589312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 729312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 739568Sandreas.hansson@arm.comsystem.physmem.totGap 15803000 # Total gap between requests 749312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 759312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 769312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 779312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 789312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 799312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 809490Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 486 # Categorize read packet sizes 819568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 829568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 839568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 849568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 859568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 869568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 879568Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Categorize write packet sizes 889490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see 899490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see 909490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see 919490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 929490Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 939322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 949312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 959312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 969312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 979312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 989312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1529568Sandreas.hansson@arm.comsystem.physmem.totQLat 2921750 # Total cycles spent in queuing delays 1539568Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests 1549490Sandreas.hansson@arm.comsystem.physmem.totBusLat 2430000 # Total cycles spent in databus access 1559490Sandreas.hansson@arm.comsystem.physmem.totBankLat 8305000 # Total cycles spent in bank access 1569568Sandreas.hansson@arm.comsystem.physmem.avgQLat 6011.83 # Average queueing delay per request 1579490Sandreas.hansson@arm.comsystem.physmem.avgBankLat 17088.48 # Average bank access latency per request 1589490Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per request 1599568Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 28100.31 # Average memory access latency 1609568Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s 1619312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1629568Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s 1639312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1649490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 1659568Sandreas.hansson@arm.comsystem.physmem.busUtil 15.15 # Data bus utilization in percentage 1669490Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.85 # Average read queue length over time 1679312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1689490Sandreas.hansson@arm.comsystem.physmem.readRowHits 396 # Number of row buffer hits during reads 1699312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1709490Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads 1719312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1729568Sandreas.hansson@arm.comsystem.physmem.avgGap 32516.46 # Average gap between requests 1739490Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2896 # Number of BP lookups 1749490Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted 1759490Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect 1769490Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 2200 # Number of BTB lookups 1779490Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 746 # Number of BTB hits 1789481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1799490Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 33.909091 # BTB Hit Percentage 1809490Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 416 # Number of times the RAS was used to get a target. 1819490Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 74 # Number of incorrect RAS predictions. 1828428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 1838428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 1848428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 1858428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 1869490Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 2071 # DTB read hits 1879348SAli.Saidi@ARM.comsystem.cpu.dtb.read_misses 50 # DTB read misses 1888428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 1899490Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 2121 # DTB read accesses 1909490Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 1069 # DTB write hits 1919490Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 30 # DTB write misses 1928428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 1939490Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 1099 # DTB write accesses 1949490Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 3140 # DTB hits 1959490Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 80 # DTB misses 1968428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 1979490Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 3220 # DTB accesses 1989490Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 2349 # ITB hits 1999490Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 38 # ITB misses 2008428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 2019490Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 2387 # ITB accesses 2028428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2038428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2048428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2058428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2068428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2078428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2088428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2098428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2108428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2118428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2128428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2138428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2148428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 2159568Sandreas.hansson@arm.comsystem.cpu.numCycles 32080 # number of cpu cycles simulated 2168428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2178428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2189490Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss 2199490Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 16527 # Number of instructions fetch has processed 2209490Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2896 # Number of branches that fetch encountered 2219490Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken 2229490Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 2951 # Number of cycles fetch has run and was not squashing or blocked 2239490Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1883 # Number of cycles fetch has spent squashing 2249490Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 1142 # Number of cycles fetch has spent blocked 2259490Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2269490Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps 2279490Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 2349 # Number of cache lines fetched 2289490Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed 2299490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 14509 # Number of instructions fetched each cycle (Total) 2309490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.139086 # Number of instructions fetched each cycle (Total) 2319490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.536110 # Number of instructions fetched each cycle (Total) 2326291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2339490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 11558 79.66% 79.66% # Number of instructions fetched each cycle (Total) 2349490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total) 2359490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total) 2369490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total) 2379490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total) 2389490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total) 2399490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total) 2409490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 185 1.28% 91.30% # Number of instructions fetched each cycle (Total) 2419490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total) 2426291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2436291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2446291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2459490Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total) 2469568Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle 2479568Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle 2489490Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle 2499490Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked 2509490Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2753 # Number of cycles decode is running 2519490Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking 2529490Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing 2539490Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch 2549322Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction 2559490Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 15363 # Number of instructions handled by decode 2569348SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode 2579490Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing 2589490Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9517 # Number of cycles rename is idle 2599490Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking 2609490Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst 2619490Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2631 # Number of cycles rename is running 2629490Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking 2639490Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 14679 # Number of instructions processed by rename 2649348SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full 2659490Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full 2669490Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 11023 # Number of destination operands rename has renamed 2679490Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 18314 # Number of register rename lookups that rename has made 2689490Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 18297 # Number of integer rename lookups 2698428SN/Asystem.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 2709150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 2719490Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6453 # Number of HB maps that are undone due to squashing 2729490Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 30 # count of serializing insts renamed 2739490Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed 2749490Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 757 # count of insts added to the skid buffer 2759490Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2761 # Number of loads inserted to the mem dependence unit. 2769490Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. 2779490Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. 2788428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 2799490Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 13018 # Number of instructions added to the IQ (excludes non-spec) 2809490Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ 2819490Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 10806 # Number of instructions issued 2829490Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 50 # Number of squashed instructions issued 2839490Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling 2849490Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph 2859490Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed 2869490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 14509 # Number of insts issued each cycle 2879490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.744779 # Number of insts issued each cycle 2889490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.389331 # Number of insts issued each cycle 2898428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2909490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10032 69.14% 69.14% # Number of insts issued each cycle 2919490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1598 11.01% 80.16% # Number of insts issued each cycle 2929490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 1157 7.97% 88.13% # Number of insts issued each cycle 2939490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 759 5.23% 93.36% # Number of insts issued each cycle 2949490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 472 3.25% 96.62% # Number of insts issued each cycle 2959490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle 2969490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle 2979490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle 2989490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle 2998428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3008428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3018428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3029490Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 14509 # Number of insts issued each cycle 3038428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3049490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available 3059490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available 3069490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 13.56% # attempts to use FU when none available 3079490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 13.56% # attempts to use FU when none available 3089490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available 3099490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 13.56% # attempts to use FU when none available 3109490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 13.56% # attempts to use FU when none available 3119490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 13.56% # attempts to use FU when none available 3129490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.56% # attempts to use FU when none available 3139490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 13.56% # attempts to use FU when none available 3149490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.56% # attempts to use FU when none available 3159490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 13.56% # attempts to use FU when none available 3169490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 13.56% # attempts to use FU when none available 3179490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 13.56% # attempts to use FU when none available 3189490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 13.56% # attempts to use FU when none available 3199490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 13.56% # attempts to use FU when none available 3209490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.56% # attempts to use FU when none available 3219490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 13.56% # attempts to use FU when none available 3229490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.56% # attempts to use FU when none available 3239490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.56% # attempts to use FU when none available 3249490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.56% # attempts to use FU when none available 3259490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.56% # attempts to use FU when none available 3269490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.56% # attempts to use FU when none available 3279490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.56% # attempts to use FU when none available 3289490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.56% # attempts to use FU when none available 3299490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.56% # attempts to use FU when none available 3309490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.56% # attempts to use FU when none available 3319490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.56% # attempts to use FU when none available 3329490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.56% # attempts to use FU when none available 3339490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 63 53.39% 66.95% # attempts to use FU when none available 3349490Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 39 33.05% 100.00% # attempts to use FU when none available 3358428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3368428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3378241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 3389490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 7299 67.55% 67.56% # Type of FU issued 3399490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.57% # Type of FU issued 3409490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.57% # Type of FU issued 3419490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.59% # Type of FU issued 3429490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued 3439490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued 3449490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued 3459490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued 3469490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued 3479490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued 3489490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued 3499490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued 3509490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued 3519490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued 3529490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued 3539490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued 3549490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued 3559490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued 3569490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued 3579490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued 3589490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued 3599490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued 3609490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued 3619490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued 3629490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued 3639490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.59% # Type of FU issued 3649490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued 3659490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued 3669490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued 3679490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2362 21.86% 89.45% # Type of FU issued 3689490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Type of FU issued 3698241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 3708241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 3719490Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 10806 # Type of FU issued 3729568Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.336845 # Inst issue rate 3739490Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 118 # FU busy when requested 3749490Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) 3759490Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads 3769490Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes 3779490Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9700 # Number of integer instruction queue wakeup accesses 3788428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 3798428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 3808428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 3819490Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 10911 # Number of integer alu accesses 3828428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 3839490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 72 # Number of loads that had data forwarded from stores 3848428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 3859490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1578 # Number of loads squashed 3869285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 3879490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations 3889490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed 3898428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 3908428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 3918428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 3929490Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 87 # Number of times an access to memory failed due to the cache being blocked 3938428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 3949490Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1212 # Number of cycles IEW is squashing 3959490Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking 3969490Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking 3979490Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ 3989490Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch 3999490Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions 4009490Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions 4019490Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions 4029348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 4038428SN/Asystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4049490Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations 4059490Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly 4069348SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly 4079490Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute 4089490Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 10154 # Number of executed instructions 4099490Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed 4109348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute 4118428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4129490Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 86 # number of nop insts executed 4139490Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3233 # number of memory reference insts executed 4149490Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1613 # Number of branches executed 4159490Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1101 # Number of stores executed 4169568Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.316521 # Inst execution rate 4179490Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit 4189490Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 9710 # cumulative count of insts written-back 4199490Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 5134 # num instructions producing a value 4209490Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 6919 # num instructions consuming a value 4218428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4229568Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.302681 # insts written-back per cycle 4239490Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back 4248428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4259490Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit 4268428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 4279490Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted 4289490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13297 # Number of insts commited each cycle 4299490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.480484 # Number of insts commited each cycle 4309490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.303494 # Number of insts commited each cycle 4318428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4329490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 10548 79.33% 79.33% # Number of insts commited each cycle 4339490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle 4349490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 514 3.87% 94.07% # Number of insts commited each cycle 4359490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle 4369490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle 4379490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle 4389490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 101 0.76% 98.61% # Number of insts commited each cycle 4399348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle 4409490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 148 1.11% 100.00% # Number of insts commited each cycle 4418428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4428428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4438428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4449490Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13297 # Number of insts commited each cycle 4459150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6389 # Number of instructions committed 4469150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 4478428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4489150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2048 # Number of memory references committed 4499150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1183 # Number of loads committed 4508428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 4519150SAli.Saidi@ARM.comsystem.cpu.commit.branches 1050 # Number of branches committed 4528428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 4539150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 6307 # Number of committed integer instructions. 4548428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 4559490Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached 4568428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4579490Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 25928 # The number of ROB reads 4589490Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 27481 # The number of ROB writes 4599490Sandreas.hansson@arm.comsystem.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself 4609568Sandreas.hansson@arm.comsystem.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling 4619150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6372 # Number of Instructions Simulated 4629150SAli.Saidi@ARM.comsystem.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 4639150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 6372 # Number of Instructions Simulated 4649568Sandreas.hansson@arm.comsystem.cpu.cpi 5.034526 # CPI: Cycles Per Instruction 4659568Sandreas.hansson@arm.comsystem.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads 4669568Sandreas.hansson@arm.comsystem.cpu.ipc 0.198628 # IPC: Instructions Per Cycle 4679568Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.198628 # IPC: Total IPC of All Threads 4689490Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 12888 # number of integer regfile reads 4699490Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7343 # number of integer regfile writes 4708428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 4718428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 4728428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 4738428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 4748428SN/Asystem.cpu.icache.replacements 0 # number of replacements 4759568Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 159.281471 # Cycle average of tags in use 4769490Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 1869 # Total number of references to valid blocks. 4779490Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. 4789490Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. 4798428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4809568Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 159.281471 # Average occupied blocks per requestor 4819568Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.077774 # Average percentage of cache occupancy 4829568Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.077774 # Average percentage of cache occupancy 4839490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits 4849490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits 4859490Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits 4869490Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1869 # number of demand (read+write) hits 4879490Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1869 # number of overall hits 4889490Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1869 # number of overall hits 4899490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses 4909490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses 4919490Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses 4929490Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses 4939490Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses 4949490Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 480 # number of overall misses 4959568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 22197500 # number of ReadReq miss cycles 4969568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 22197500 # number of ReadReq miss cycles 4979568Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 22197500 # number of demand (read+write) miss cycles 4989568Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 22197500 # number of demand (read+write) miss cycles 4999568Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 22197500 # number of overall miss cycles 5009568Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 22197500 # number of overall miss cycles 5019490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) 5029490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) 5039490Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses 5049490Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2349 # number of demand (read+write) accesses 5059490Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2349 # number of overall (read+write) accesses 5069490Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2349 # number of overall (read+write) accesses 5079490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.204342 # miss rate for ReadReq accesses 5089490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.204342 # miss rate for ReadReq accesses 5099490Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.204342 # miss rate for demand accesses 5109490Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses 5119490Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses 5129490Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses 5139568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46244.791667 # average ReadReq miss latency 5149568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 46244.791667 # average ReadReq miss latency 5159568Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency 5169568Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 46244.791667 # average overall miss latency 5179568Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency 5189568Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 46244.791667 # average overall miss latency 5198428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5208428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5218428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 5228428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5238983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5248983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5258428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5268428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5279490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 167 # number of ReadReq MSHR hits 5289490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 167 # number of ReadReq MSHR hits 5299490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 167 # number of demand (read+write) MSHR hits 5309490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 167 # number of demand (read+write) MSHR hits 5319490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 167 # number of overall MSHR hits 5329490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 167 # number of overall MSHR hits 5339490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 5349490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 5359490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 5369490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 5379490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 5389490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses 5399568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16111000 # number of ReadReq MSHR miss cycles 5409568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 16111000 # number of ReadReq MSHR miss cycles 5419568Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 16111000 # number of demand (read+write) MSHR miss cycles 5429568Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 16111000 # number of demand (read+write) MSHR miss cycles 5439568Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 16111000 # number of overall MSHR miss cycles 5449568Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 16111000 # number of overall MSHR miss cycles 5459490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses 5469490Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses 5479490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses 5489490Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses 5499490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses 5509490Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses 5519568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51472.843450 # average ReadReq mshr miss latency 5529568Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51472.843450 # average ReadReq mshr miss latency 5539568Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency 5549568Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency 5559568Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency 5569568Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency 5578428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5588428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5599568Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 219.754912 # Cycle average of tags in use 5608428SN/Asystem.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 5619490Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. 5629490Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. 5638428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5649568Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 159.415983 # Average occupied blocks per requestor 5659568Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 60.338929 # Average occupied blocks per requestor 5669568Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004865 # Average percentage of cache occupancy 5679490Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy 5689568Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.006706 # Average percentage of cache occupancy 5698835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 5708835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 5718835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 5728835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 5738835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 5748835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 5759490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses 5769322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses 5779490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 413 # number of ReadReq misses 5789096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 5799096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 5809490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses 5819322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 5829490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses 5839490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses 5849322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 5859490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 486 # number of overall misses 5869568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15786000 # number of ReadReq miss cycles 5879490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 6080500 # number of ReadReq miss cycles 5889568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 21866500 # number of ReadReq miss cycles 5899490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3687500 # number of ReadExReq miss cycles 5909490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3687500 # number of ReadExReq miss cycles 5919568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 15786000 # number of demand (read+write) miss cycles 5929490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 9768000 # number of demand (read+write) miss cycles 5939568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 25554000 # number of demand (read+write) miss cycles 5949568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 15786000 # number of overall miss cycles 5959490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 9768000 # number of overall miss cycles 5969568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 25554000 # number of overall miss cycles 5979490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) 5989322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) 5999490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) 6009096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 6019096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 6029490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses 6039322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 6049490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses 6059490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses 6069322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 6079490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses 6089490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses 6098835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 6109490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.997585 # miss rate for ReadReq accesses 6118835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6129055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6139490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses 6148835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 6159490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses 6169490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses 6178835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 6189490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses 6199568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50596.153846 # average ReadReq miss latency 6209490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency 6219568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 52945.520581 # average ReadReq miss latency 6229490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency 6239490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency 6249568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency 6259490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency 6269568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 52580.246914 # average overall miss latency 6279568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency 6289490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency 6299568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 52580.246914 # average overall miss latency 6308428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6318428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6328428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6338428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6348983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6358983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6368428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6378428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6389490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses 6399322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 6409490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 413 # number of ReadReq MSHR misses 6419096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 6429096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 6439490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 6449322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 6459490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses 6469490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 6479322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 6489490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses 6499568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916495 # number of ReadReq MSHR miss cycles 6509568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848791 # number of ReadReq MSHR miss cycles 6519568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 16765286 # number of ReadReq MSHR miss cycles 6529568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795781 # number of ReadExReq MSHR miss cycles 6539568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795781 # number of ReadExReq MSHR miss cycles 6549568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916495 # number of demand (read+write) MSHR miss cycles 6559568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644572 # number of demand (read+write) MSHR miss cycles 6569568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 19561067 # number of demand (read+write) MSHR miss cycles 6579568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916495 # number of overall MSHR miss cycles 6589568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644572 # number of overall MSHR miss cycles 6599568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 19561067 # number of overall MSHR miss cycles 6609490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses 6618835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 6629490Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses 6638835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6649055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6659490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 6668835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 6679490Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses 6689490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 6698835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 6709490Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses 6719568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38193.894231 # average ReadReq mshr miss latency 6729568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48007.831683 # average ReadReq mshr miss latency 6739568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40593.912833 # average ReadReq mshr miss latency 6749568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.369863 # average ReadExReq mshr miss latency 6759568Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.369863 # average ReadExReq mshr miss latency 6769568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency 6779568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency 6789568Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency 6799568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency 6809568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency 6819568Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency 6828428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6839348SAli.Saidi@ARM.comsystem.cpu.dcache.replacements 0 # number of replacements 6849568Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 107.750370 # Cycle average of tags in use 6859490Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 2262 # Total number of references to valid blocks. 6869348SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. 6879490Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. 6889348SAli.Saidi@ARM.comsystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6899568Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 107.750370 # Average occupied blocks per requestor 6909568Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.026306 # Average percentage of cache occupancy 6919568Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::total 0.026306 # Average percentage of cache occupancy 6929490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits 6939490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits 6949348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 6959348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 6969490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2262 # number of demand (read+write) hits 6979490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2262 # number of demand (read+write) hits 6989490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2262 # number of overall hits 6999490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2262 # number of overall hits 7009348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses 7019348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses 7029348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 7039348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 7049348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 528 # number of demand (read+write) misses 7059348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses 7069348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses 7079348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 528 # number of overall misses 7089490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 9127000 # number of ReadReq miss cycles 7099490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 9127000 # number of ReadReq miss cycles 7109490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 15893487 # number of WriteReq miss cycles 7119490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 15893487 # number of WriteReq miss cycles 7129490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 25020487 # number of demand (read+write) miss cycles 7139490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 25020487 # number of demand (read+write) miss cycles 7149490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 25020487 # number of overall miss cycles 7159490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 25020487 # number of overall miss cycles 7169490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1925 # number of ReadReq accesses(hits+misses) 7179490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1925 # number of ReadReq accesses(hits+misses) 7189348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 7199348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 7209490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2790 # number of demand (read+write) accesses 7219490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2790 # number of demand (read+write) accesses 7229490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2790 # number of overall (read+write) accesses 7239490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2790 # number of overall (read+write) accesses 7249490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087792 # miss rate for ReadReq accesses 7259490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.087792 # miss rate for ReadReq accesses 7269348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 7279348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 7289490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.189247 # miss rate for demand accesses 7299490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.189247 # miss rate for demand accesses 7309490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.189247 # miss rate for overall accesses 7319490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.189247 # miss rate for overall accesses 7329490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54005.917160 # average ReadReq miss latency 7339490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 54005.917160 # average ReadReq miss latency 7349490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44271.551532 # average WriteReq miss latency 7359490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 44271.551532 # average WriteReq miss latency 7369490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency 7379490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 47387.285985 # average overall miss latency 7389490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency 7399490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 47387.285985 # average overall miss latency 7409490Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 862 # number of cycles access was blocked 7419348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7429490Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked 7439348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 7449490Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 37.478261 # average number of cycles each access was blocked 7459348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7469348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 7479348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 7489348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits 7499348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 7509348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits 7519348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits 7529348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits 7539348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits 7549348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits 7559348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits 7569348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 7579348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 7589348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 7599348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 7609348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 7619348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 7629348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 7639348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 7649490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6189000 # number of ReadReq MSHR miss cycles 7659490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 6189000 # number of ReadReq MSHR miss cycles 7669490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3763500 # number of WriteReq MSHR miss cycles 7679490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3763500 # number of WriteReq MSHR miss cycles 7689490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 9952500 # number of demand (read+write) MSHR miss cycles 7699490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 9952500 # number of demand (read+write) MSHR miss cycles 7709490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 9952500 # number of overall MSHR miss cycles 7719490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 9952500 # number of overall MSHR miss cycles 7729490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052468 # mshr miss rate for ReadReq accesses 7739490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052468 # mshr miss rate for ReadReq accesses 7749348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 7759348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 7769490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for demand accesses 7779490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.062366 # mshr miss rate for demand accesses 7789490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062366 # mshr miss rate for overall accesses 7799490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.062366 # mshr miss rate for overall accesses 7809490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61277.227723 # average ReadReq mshr miss latency 7819490Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61277.227723 # average ReadReq mshr miss latency 7829490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51554.794521 # average WriteReq mshr miss latency 7839490Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51554.794521 # average WriteReq mshr miss latency 7849490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency 7859490Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency 7869490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57198.275862 # average overall mshr miss latency 7879490Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 57198.275862 # average overall mshr miss latency 7889348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 7893096SN/A 7903096SN/A---------- End Simulation Statistics ---------- 791