stats.txt revision 9348
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 39322Sandreas.hansson@arm.comsim_seconds 0.000016 # Number of seconds simulated 49348SAli.Saidi@ARM.comsim_ticks 15802500 # Number of ticks simulated 59348SAli.Saidi@ARM.comfinal_tick 15802500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79348SAli.Saidi@ARM.comhost_inst_rate 38730 # Simulator instruction rate (inst/s) 89348SAli.Saidi@ARM.comhost_op_rate 38726 # Simulator op (including micro ops) rate (op/s) 99348SAli.Saidi@ARM.comhost_tick_rate 96032767 # Simulator tick rate (ticks/s) 109348SAli.Saidi@ARM.comhost_mem_usage 214332 # Number of bytes of host memory used 119348SAli.Saidi@ARM.comhost_seconds 0.16 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6372 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6372 # Number of ops (including micro ops) simulated 149312Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 159322Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 169322Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 31168 # Number of bytes read from this memory 179312Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 189312Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 199312Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 209322Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 219322Sandreas.hansson@arm.comsystem.physmem.num_reads::total 487 # Number of read requests responded to by this memory 229348SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 1267647524 # Total read bandwidth from this memory (bytes/s) 239348SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 704698624 # Total read bandwidth from this memory (bytes/s) 249348SAli.Saidi@ARM.comsystem.physmem.bw_read::total 1972346148 # Total read bandwidth from this memory (bytes/s) 259348SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 1267647524 # Instruction read bandwidth from this memory (bytes/s) 269348SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 1267647524 # Instruction read bandwidth from this memory (bytes/s) 279348SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 1267647524 # Total bandwidth to/from this memory (bytes/s) 289348SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 704698624 # Total bandwidth to/from this memory (bytes/s) 299348SAli.Saidi@ARM.comsystem.physmem.bw_total::total 1972346148 # Total bandwidth to/from this memory (bytes/s) 309322Sandreas.hansson@arm.comsystem.physmem.readReqs 487 # Total number of read requests seen 319312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 329322Sandreas.hansson@arm.comsystem.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady 339322Sandreas.hansson@arm.comsystem.physmem.bytesRead 31168 # Total number of bytes read from memory 349312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 359322Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() 369312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 379312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 389312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 399312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis 409322Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 18 # Track reads on a per bank basis 419312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis 429312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis 439312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis 449348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis 459312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis 469312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis 479322Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis 489322Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis 499348SAli.Saidi@ARM.comsystem.physmem.perBankRdReqs::10 73 # Track reads on a per bank basis 509312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis 519312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis 529312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 2 # Track reads on a per bank basis 539312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 7 # Track reads on a per bank basis 549312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis 559312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 569312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 579312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 589312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 729312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 739348SAli.Saidi@ARM.comsystem.physmem.totGap 15655000 # Total gap between requests 749312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 759312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 769312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 779312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 789312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 799312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 809322Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 487 # Categorize read packet sizes 819312Sandreas.hansson@arm.comsystem.physmem.readPktSize::7 0 # Categorize read packet sizes 829312Sandreas.hansson@arm.comsystem.physmem.readPktSize::8 0 # Categorize read packet sizes 839312Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # categorize write packet sizes 849312Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # categorize write packet sizes 859312Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # categorize write packet sizes 869312Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # categorize write packet sizes 879312Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # categorize write packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # categorize write packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # categorize write packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.writePktSize::7 0 # categorize write packet sizes 919312Sandreas.hansson@arm.comsystem.physmem.writePktSize::8 0 # categorize write packet sizes 929312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::0 0 # categorize neither packet sizes 939312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::1 0 # categorize neither packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::2 0 # categorize neither packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::3 0 # categorize neither packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::4 0 # categorize neither packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::5 0 # categorize neither packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::6 0 # categorize neither packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::7 0 # categorize neither packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.neitherpktsize::8 0 # categorize neither packet sizes 1019322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see 1029348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see 1039322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see 1049348SAli.Saidi@ARM.comsystem.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 1069322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 1679348SAli.Saidi@ARM.comsystem.physmem.totQLat 3073487 # Total cycles spent in queuing delays 1689348SAli.Saidi@ARM.comsystem.physmem.totMemAccLat 12819487 # Sum of mem lat for all requests 1699322Sandreas.hansson@arm.comsystem.physmem.totBusLat 1948000 # Total cycles spent in databus access 1709322Sandreas.hansson@arm.comsystem.physmem.totBankLat 7798000 # Total cycles spent in bank access 1719348SAli.Saidi@ARM.comsystem.physmem.avgQLat 6311.06 # Average queueing delay per request 1729322Sandreas.hansson@arm.comsystem.physmem.avgBankLat 16012.32 # Average bank access latency per request 1739312Sandreas.hansson@arm.comsystem.physmem.avgBusLat 4000.00 # Average bus latency per request 1749348SAli.Saidi@ARM.comsystem.physmem.avgMemAccLat 26323.38 # Average memory access latency 1759348SAli.Saidi@ARM.comsystem.physmem.avgRdBW 1972.35 # Average achieved read bandwidth in MB/s 1769312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1779348SAli.Saidi@ARM.comsystem.physmem.avgConsumedRdBW 1972.35 # Average consumed read bandwidth in MB/s 1789312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1799312Sandreas.hansson@arm.comsystem.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 1809348SAli.Saidi@ARM.comsystem.physmem.busUtil 12.33 # Data bus utilization in percentage 1819348SAli.Saidi@ARM.comsystem.physmem.avgRdQLen 0.81 # Average read queue length over time 1829312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1839348SAli.Saidi@ARM.comsystem.physmem.readRowHits 416 # Number of row buffer hits during reads 1849312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1859348SAli.Saidi@ARM.comsystem.physmem.readRowHitRate 85.42 # Row buffer hit rate for reads 1869312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1879348SAli.Saidi@ARM.comsystem.physmem.avgGap 32145.79 # Average gap between requests 1888428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 1898428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 1908428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 1918428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 1929348SAli.Saidi@ARM.comsystem.cpu.dtb.read_hits 2068 # DTB read hits 1939348SAli.Saidi@ARM.comsystem.cpu.dtb.read_misses 50 # DTB read misses 1948428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 1959348SAli.Saidi@ARM.comsystem.cpu.dtb.read_accesses 2118 # DTB read accesses 1969348SAli.Saidi@ARM.comsystem.cpu.dtb.write_hits 1071 # DTB write hits 1979348SAli.Saidi@ARM.comsystem.cpu.dtb.write_misses 29 # DTB write misses 1988428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 1999348SAli.Saidi@ARM.comsystem.cpu.dtb.write_accesses 1100 # DTB write accesses 2009348SAli.Saidi@ARM.comsystem.cpu.dtb.data_hits 3139 # DTB hits 2019348SAli.Saidi@ARM.comsystem.cpu.dtb.data_misses 79 # DTB misses 2028428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 2039348SAli.Saidi@ARM.comsystem.cpu.dtb.data_accesses 3218 # DTB accesses 2049348SAli.Saidi@ARM.comsystem.cpu.itb.fetch_hits 2370 # ITB hits 2059348SAli.Saidi@ARM.comsystem.cpu.itb.fetch_misses 39 # ITB misses 2068428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 2079348SAli.Saidi@ARM.comsystem.cpu.itb.fetch_accesses 2409 # ITB accesses 2088428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2098428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2108428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2118428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2128428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2138428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2148428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2158428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2168428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2178428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2188428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2198428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2208428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 2219348SAli.Saidi@ARM.comsystem.cpu.numCycles 31606 # number of cpu cycles simulated 2228428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2238428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2249348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 2927 # Number of BP lookups 2259348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 1718 # Number of conditional branches predicted 2269348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 517 # Number of conditional branches incorrect 2279348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBLookups 2238 # Number of BTB lookups 2289348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 757 # Number of BTB hits 2298428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 2309348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 420 # Number of times the RAS was used to get a target. 2319348SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 77 # Number of incorrect RAS predictions. 2329348SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 8266 # Number of cycles fetch is stalled on an Icache miss 2339348SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 16744 # Number of instructions fetch has processed 2349348SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 2927 # Number of branches that fetch encountered 2359348SAli.Saidi@ARM.comsystem.cpu.fetch.predictedBranches 1177 # Number of branches that fetch has predicted taken 2369348SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 2985 # Number of cycles fetch has run and was not squashing or blocked 2379348SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 1897 # Number of cycles fetch has spent squashing 2389348SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 1074 # Number of cycles fetch has spent blocked 2399348SAli.Saidi@ARM.comsystem.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 2409348SAli.Saidi@ARM.comsystem.cpu.fetch.PendingTrapStallCycles 762 # Number of stall cycles due to pending traps 2419348SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 2370 # Number of cache lines fetched 2429348SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 362 # Number of outstanding Icache misses that were squashed 2439348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 14416 # Number of instructions fetched each cycle (Total) 2449348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 1.161487 # Number of instructions fetched each cycle (Total) 2459348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 2.555904 # Number of instructions fetched each cycle (Total) 2466291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 2479348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 11431 79.29% 79.29% # Number of instructions fetched each cycle (Total) 2489348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 317 2.20% 81.49% # Number of instructions fetched each cycle (Total) 2499348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 233 1.62% 83.11% # Number of instructions fetched each cycle (Total) 2509348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 212 1.47% 84.58% # Number of instructions fetched each cycle (Total) 2519348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 264 1.83% 86.41% # Number of instructions fetched each cycle (Total) 2529348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 229 1.59% 88.00% # Number of instructions fetched each cycle (Total) 2539348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 265 1.84% 89.84% # Number of instructions fetched each cycle (Total) 2549348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 186 1.29% 91.13% # Number of instructions fetched each cycle (Total) 2559348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 1279 8.87% 100.00% # Number of instructions fetched each cycle (Total) 2566291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 2576291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 2586291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 2599348SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 14416 # Number of instructions fetched each cycle (Total) 2609348SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.092609 # Number of branch fetches per cycle 2619348SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.529773 # Number of inst fetches per cycle 2629348SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 9179 # Number of cycles decode is idle 2639348SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 1146 # Number of cycles decode is blocked 2649322Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2779 # Number of cycles decode is running 2659348SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 90 # Number of cycles decode is unblocking 2669348SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 1222 # Number of cycles decode is squashing 2679348SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 249 # Number of times decode resolved a branch 2689322Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction 2699348SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 15526 # Number of instructions handled by decode 2709348SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode 2719348SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 1222 # Number of cycles rename is squashing 2729348SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 9389 # Number of cycles rename is idle 2739348SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 326 # Number of cycles rename is blocking 2749348SAli.Saidi@ARM.comsystem.cpu.rename.serializeStallCycles 477 # count of cycles rename stalled for serializing inst 2759348SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 2653 # Number of cycles rename is running 2769348SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 349 # Number of cycles rename is unblocking 2779348SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 14793 # Number of instructions processed by rename 2789348SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full 2799348SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 317 # Number of times rename has blocked due to LSQ full 2809348SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 11113 # Number of destination operands rename has renamed 2819348SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 18446 # Number of register rename lookups that rename has made 2829348SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 18429 # Number of integer rename lookups 2838428SN/Asystem.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 2849150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 2859348SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 6543 # Number of HB maps that are undone due to squashing 2869348SAli.Saidi@ARM.comsystem.cpu.rename.serializingInsts 32 # count of serializing insts renamed 2879348SAli.Saidi@ARM.comsystem.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed 2889348SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 811 # count of insts added to the skid buffer 2899348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 2756 # Number of loads inserted to the mem dependence unit. 2909348SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 1363 # Number of stores inserted to the mem dependence unit. 2919312Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 2928428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 2939348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) 2949348SAli.Saidi@ARM.comsystem.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ 2959348SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 10819 # Number of instructions issued 2969348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued 2979348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 6341 # Number of squashed instructions iterated over during squash; mainly for profiling 2989348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 3614 # Number of squashed operands that are examined and possibly removed from graph 2999348SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed 3009348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 14416 # Number of insts issued each cycle 3019348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.750486 # Number of insts issued each cycle 3029348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.391653 # Number of insts issued each cycle 3038428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 3049348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 9926 68.85% 68.85% # Number of insts issued each cycle 3059348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 1619 11.23% 80.08% # Number of insts issued each cycle 3069348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 1135 7.87% 87.96% # Number of insts issued each cycle 3079348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 768 5.33% 93.29% # Number of insts issued each cycle 3089348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 481 3.34% 96.62% # Number of insts issued each cycle 3099348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 285 1.98% 98.60% # Number of insts issued each cycle 3109348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 151 1.05% 99.65% # Number of insts issued each cycle 3119348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 37 0.26% 99.90% # Number of insts issued each cycle 3129348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle 3138428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3148428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3158428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 3169348SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 14416 # Number of insts issued each cycle 3178428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 3189348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 14 11.97% 11.97% # attempts to use FU when none available 3199348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 11.97% # attempts to use FU when none available 3209348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 11.97% # attempts to use FU when none available 3219348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 11.97% # attempts to use FU when none available 3229348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 11.97% # attempts to use FU when none available 3239348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 11.97% # attempts to use FU when none available 3249348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 11.97% # attempts to use FU when none available 3259348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 11.97% # attempts to use FU when none available 3269348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.97% # attempts to use FU when none available 3279348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 11.97% # attempts to use FU when none available 3289348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.97% # attempts to use FU when none available 3299348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 11.97% # attempts to use FU when none available 3309348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 11.97% # attempts to use FU when none available 3319348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 11.97% # attempts to use FU when none available 3329348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 11.97% # attempts to use FU when none available 3339348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 11.97% # attempts to use FU when none available 3349348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.97% # attempts to use FU when none available 3359348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 11.97% # attempts to use FU when none available 3369348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.97% # attempts to use FU when none available 3379348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.97% # attempts to use FU when none available 3389348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.97% # attempts to use FU when none available 3399348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.97% # attempts to use FU when none available 3409348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.97% # attempts to use FU when none available 3419348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.97% # attempts to use FU when none available 3429348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.97% # attempts to use FU when none available 3439348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.97% # attempts to use FU when none available 3449348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.97% # attempts to use FU when none available 3459348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.97% # attempts to use FU when none available 3469348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.97% # attempts to use FU when none available 3479348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 64 54.70% 66.67% # attempts to use FU when none available 3489348SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 39 33.33% 100.00% # attempts to use FU when none available 3498428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 3508428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 3518241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 3529348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 7317 67.63% 67.65% # Type of FU issued 3539348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued 3549348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued 3559348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.68% # Type of FU issued 3569348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.68% # Type of FU issued 3579348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.68% # Type of FU issued 3589348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.68% # Type of FU issued 3599348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.68% # Type of FU issued 3609348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.68% # Type of FU issued 3619348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.68% # Type of FU issued 3629348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.68% # Type of FU issued 3639348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.68% # Type of FU issued 3649348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.68% # Type of FU issued 3659348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.68% # Type of FU issued 3669348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.68% # Type of FU issued 3679348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.68% # Type of FU issued 3689348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.68% # Type of FU issued 3699348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.68% # Type of FU issued 3709348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.68% # Type of FU issued 3719348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.68% # Type of FU issued 3729348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.68% # Type of FU issued 3739348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.68% # Type of FU issued 3749348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.68% # Type of FU issued 3759348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.68% # Type of FU issued 3769348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.68% # Type of FU issued 3779348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.68% # Type of FU issued 3789348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.68% # Type of FU issued 3799348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.68% # Type of FU issued 3809348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.68% # Type of FU issued 3819348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 2355 21.77% 89.44% # Type of FU issued 3829348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 1142 10.56% 100.00% # Type of FU issued 3838241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 3848241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 3859348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 10819 # Type of FU issued 3869348SAli.Saidi@ARM.comsystem.cpu.iq.rate 0.342308 # Inst issue rate 3879348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 117 # FU busy when requested 3889348SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.010814 # FU busy rate (busy events/executed inst) 3899348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 36206 # Number of integer instruction queue reads 3909348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 19446 # Number of integer instruction queue writes 3919348SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9723 # Number of integer instruction queue wakeup accesses 3928428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 3938428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 3948428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 3959348SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 10923 # Number of integer alu accesses 3968428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 3979348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores 3988428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 3999348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1573 # Number of loads squashed 4009285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 4019348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations 4029348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 498 # Number of stores squashed 4038428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4048428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4058428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 4069348SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.cacheBlocked 90 # Number of times an access to memory failed due to the cache being blocked 4078428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 4089348SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 1222 # Number of cycles IEW is squashing 4099348SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 52 # Number of cycles IEW is blocking 4109348SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking 4119348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 13186 # Number of instructions dispatched to IQ 4129348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 157 # Number of squashed instructions skipped by dispatch 4139348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 2756 # Number of dispatched load instructions 4149348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 1363 # Number of dispatched store instructions 4159348SAli.Saidi@ARM.comsystem.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions 4169348SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 4178428SN/Asystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 4189348SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations 4199348SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 129 # Number of branches that were predicted taken incorrectly 4209348SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly 4219348SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 522 # Number of branch mispredicts detected at execute 4229348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 10167 # Number of executed instructions 4239348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed 4249348SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute 4258428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4269348SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 87 # number of nop insts executed 4279348SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 3231 # number of memory reference insts executed 4289348SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 1614 # Number of branches executed 4299348SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 1102 # Number of stores executed 4309348SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 0.321679 # Inst execution rate 4319348SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 9882 # cumulative count of insts sent to commit 4329348SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 9733 # cumulative count of insts written-back 4339348SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 5145 # num instructions producing a value 4349348SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 6933 # num instructions consuming a value 4358428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 4369348SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 0.307948 # insts written-back per cycle 4379348SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.742103 # average fanout of values written-back 4388428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 4399348SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 6795 # The number of squashed insts skipped by commit 4408428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 4419348SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 435 # The number of times a branch was mispredicted 4429348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 13194 # Number of insts commited each cycle 4439348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 0.484235 # Number of insts commited each cycle 4449348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 1.303292 # Number of insts commited each cycle 4458428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 4469348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 10420 78.98% 78.98% # Number of insts commited each cycle 4479348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 1475 11.18% 90.15% # Number of insts commited each cycle 4489348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 517 3.92% 94.07% # Number of insts commited each cycle 4499348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 247 1.87% 95.95% # Number of insts commited each cycle 4509348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 154 1.17% 97.11% # Number of insts commited each cycle 4519348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 92 0.70% 97.81% # Number of insts commited each cycle 4529348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 106 0.80% 98.61% # Number of insts commited each cycle 4539348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 37 0.28% 98.89% # Number of insts commited each cycle 4549348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 146 1.11% 100.00% # Number of insts commited each cycle 4558428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 4568428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 4578428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 4589348SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 13194 # Number of insts commited each cycle 4599150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6389 # Number of instructions committed 4609150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 4618428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 4629150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2048 # Number of memory references committed 4639150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1183 # Number of loads committed 4648428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 4659150SAli.Saidi@ARM.comsystem.cpu.commit.branches 1050 # Number of branches committed 4668428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 4679150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 6307 # Number of committed integer instructions. 4688428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 4699348SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 146 # number cycles where commit BW limit reached 4708428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 4719348SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 25881 # The number of ROB reads 4729348SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 27599 # The number of ROB writes 4739348SAli.Saidi@ARM.comsystem.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself 4749348SAli.Saidi@ARM.comsystem.cpu.idleCycles 17190 # Total number of cycles that the CPU has spent unscheduled due to idling 4759150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6372 # Number of Instructions Simulated 4769150SAli.Saidi@ARM.comsystem.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 4779150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 6372 # Number of Instructions Simulated 4789348SAli.Saidi@ARM.comsystem.cpu.cpi 4.960138 # CPI: Cycles Per Instruction 4799348SAli.Saidi@ARM.comsystem.cpu.cpi_total 4.960138 # CPI: Total CPI of All Threads 4809348SAli.Saidi@ARM.comsystem.cpu.ipc 0.201607 # IPC: Instructions Per Cycle 4819348SAli.Saidi@ARM.comsystem.cpu.ipc_total 0.201607 # IPC: Total IPC of All Threads 4829348SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 12907 # number of integer regfile reads 4839348SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 7365 # number of integer regfile writes 4848428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 4858428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 4868428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 4878428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 4888428SN/Asystem.cpu.icache.replacements 0 # number of replacements 4899348SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 160.479269 # Cycle average of tags in use 4909348SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 1894 # Total number of references to valid blocks. 4919312Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. 4929348SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 6.031847 # Average number of references to valid blocks. 4938428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4949348SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 160.479269 # Average occupied blocks per requestor 4959348SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.078359 # Average percentage of cache occupancy 4969348SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.078359 # Average percentage of cache occupancy 4979348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1894 # number of ReadReq hits 4989348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 1894 # number of ReadReq hits 4999348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 1894 # number of demand (read+write) hits 5009348SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 1894 # number of demand (read+write) hits 5019348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 1894 # number of overall hits 5029348SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 1894 # number of overall hits 5039348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 476 # number of ReadReq misses 5049348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 476 # number of ReadReq misses 5059348SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 476 # number of demand (read+write) misses 5069348SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 476 # number of demand (read+write) misses 5079348SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 476 # number of overall misses 5089348SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 476 # number of overall misses 5099348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 21386500 # number of ReadReq miss cycles 5109348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 21386500 # number of ReadReq miss cycles 5119348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 21386500 # number of demand (read+write) miss cycles 5129348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 21386500 # number of demand (read+write) miss cycles 5139348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 21386500 # number of overall miss cycles 5149348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 21386500 # number of overall miss cycles 5159348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2370 # number of ReadReq accesses(hits+misses) 5169348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 2370 # number of ReadReq accesses(hits+misses) 5179348SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 2370 # number of demand (read+write) accesses 5189348SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 2370 # number of demand (read+write) accesses 5199348SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 2370 # number of overall (read+write) accesses 5209348SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 2370 # number of overall (read+write) accesses 5219348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200844 # miss rate for ReadReq accesses 5229348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.200844 # miss rate for ReadReq accesses 5239348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.200844 # miss rate for demand accesses 5249348SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.200844 # miss rate for demand accesses 5259348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.200844 # miss rate for overall accesses 5269348SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.200844 # miss rate for overall accesses 5279348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44929.621849 # average ReadReq miss latency 5289348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 44929.621849 # average ReadReq miss latency 5299348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency 5309348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::total 44929.621849 # average overall miss latency 5319348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 44929.621849 # average overall miss latency 5329348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::total 44929.621849 # average overall miss latency 5338428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5348428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5358428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 5368428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 5378983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5388983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5398428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 5408428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 5419348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 162 # number of ReadReq MSHR hits 5429348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits 5439348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 162 # number of demand (read+write) MSHR hits 5449348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 162 # number of demand (read+write) MSHR hits 5459348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 162 # number of overall MSHR hits 5469348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 162 # number of overall MSHR hits 5479312Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 5489312Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses 5499312Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 5509312Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses 5519312Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 5529312Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses 5539348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15404000 # number of ReadReq MSHR miss cycles 5549348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 15404000 # number of ReadReq MSHR miss cycles 5559348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 15404000 # number of demand (read+write) MSHR miss cycles 5569348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 15404000 # number of demand (read+write) MSHR miss cycles 5579348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 15404000 # number of overall MSHR miss cycles 5589348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 15404000 # number of overall MSHR miss cycles 5599348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for ReadReq accesses 5609348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.132489 # mshr miss rate for ReadReq accesses 5619348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for demand accesses 5629348SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.132489 # mshr miss rate for demand accesses 5639348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.132489 # mshr miss rate for overall accesses 5649348SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.132489 # mshr miss rate for overall accesses 5659348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49057.324841 # average ReadReq mshr miss latency 5669348SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49057.324841 # average ReadReq mshr miss latency 5679348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency 5689348SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency 5699348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49057.324841 # average overall mshr miss latency 5709348SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 49057.324841 # average overall mshr miss latency 5718428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5728428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5739348SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 220.902491 # Cycle average of tags in use 5748428SN/Asystem.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 5759322Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks. 5769322Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks. 5778428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5789348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 160.626019 # Average occupied blocks per requestor 5799348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 60.276472 # Average occupied blocks per requestor 5809348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004902 # Average percentage of cache occupancy 5819348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001839 # Average percentage of cache occupancy 5829348SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.006741 # Average percentage of cache occupancy 5838835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 5848835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 5858835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 5868835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 5878835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 5888835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 5899312Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses 5909322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses 5919322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses 5929096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 5939096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 5949312Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses 5959322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 5969322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses 5979312Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses 5989322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 5999322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 487 # number of overall misses 6009348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15078000 # number of ReadReq miss cycles 6019348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 6210500 # number of ReadReq miss cycles 6029348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 21288500 # number of ReadReq miss cycles 6039348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3737500 # number of ReadExReq miss cycles 6049348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 3737500 # number of ReadExReq miss cycles 6059348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 15078000 # number of demand (read+write) miss cycles 6069348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 9948000 # number of demand (read+write) miss cycles 6079348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 25026000 # number of demand (read+write) miss cycles 6089348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 15078000 # number of overall miss cycles 6099348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 9948000 # number of overall miss cycles 6109348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 25026000 # number of overall miss cycles 6119312Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) 6129322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) 6139322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) 6149096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 6159096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 6169312Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses 6179322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 6189322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 488 # number of demand (read+write) accesses 6199312Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses 6209322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 6219322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses 6229312Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses 6238835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 6249322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses 6258835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 6269055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 6279312Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses 6288835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 6299322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses 6309312Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses 6318835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 6329322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses 6339348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48172.523962 # average ReadReq miss latency 6349348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61490.099010 # average ReadReq miss latency 6359348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 51421.497585 # average ReadReq miss latency 6369348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51198.630137 # average ReadExReq miss latency 6379348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 51198.630137 # average ReadExReq miss latency 6389348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48172.523962 # average overall miss latency 6399348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 57172.413793 # average overall miss latency 6409348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::total 51388.090349 # average overall miss latency 6419348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48172.523962 # average overall miss latency 6429348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 57172.413793 # average overall miss latency 6439348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::total 51388.090349 # average overall miss latency 6448428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6458428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6468428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 6478428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 6488983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6498983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6508428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6518428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6529312Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 6539322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 6549322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses 6559096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 6569096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 6579312Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 6589322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 6599322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses 6609312Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 6619322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 6629322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses 6639348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11136994 # number of ReadReq MSHR miss cycles 6649348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4966088 # number of ReadReq MSHR miss cycles 6659348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 16103082 # number of ReadReq MSHR miss cycles 6669348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2842064 # number of ReadExReq MSHR miss cycles 6679348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2842064 # number of ReadExReq MSHR miss cycles 6689348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11136994 # number of demand (read+write) MSHR miss cycles 6699348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7808152 # number of demand (read+write) MSHR miss cycles 6709348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 18945146 # number of demand (read+write) MSHR miss cycles 6719348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11136994 # number of overall MSHR miss cycles 6729348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7808152 # number of overall MSHR miss cycles 6739348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 18945146 # number of overall MSHR miss cycles 6749312Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses 6758835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 6769322Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses 6778835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6789055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6799312Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses 6808835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 6819322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses 6829312Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses 6838835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 6849322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses 6859348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35581.450479 # average ReadReq mshr miss latency 6869348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49169.188119 # average ReadReq mshr miss latency 6879348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38896.333333 # average ReadReq mshr miss latency 6889348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38932.383562 # average ReadExReq mshr miss latency 6899348SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38932.383562 # average ReadExReq mshr miss latency 6909348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency 6919348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency 6929348SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency 6939348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35581.450479 # average overall mshr miss latency 6949348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44874.436782 # average overall mshr miss latency 6959348SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 38901.737166 # average overall mshr miss latency 6968428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6979348SAli.Saidi@ARM.comsystem.cpu.dcache.replacements 0 # number of replacements 6989348SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 107.834334 # Cycle average of tags in use 6999348SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 2264 # Total number of references to valid blocks. 7009348SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. 7019348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 13.011494 # Average number of references to valid blocks. 7029348SAli.Saidi@ARM.comsystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 7039348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 107.834334 # Average occupied blocks per requestor 7049348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.026327 # Average percentage of cache occupancy 7059348SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.026327 # Average percentage of cache occupancy 7069348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1758 # number of ReadReq hits 7079348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1758 # number of ReadReq hits 7089348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 7099348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 7109348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 2264 # number of demand (read+write) hits 7119348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 2264 # number of demand (read+write) hits 7129348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 2264 # number of overall hits 7139348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 2264 # number of overall hits 7149348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses 7159348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses 7169348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 7179348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 7189348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 528 # number of demand (read+write) misses 7199348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses 7209348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses 7219348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 528 # number of overall misses 7229348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 9065500 # number of ReadReq miss cycles 7239348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 9065500 # number of ReadReq miss cycles 7249348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 15837484 # number of WriteReq miss cycles 7259348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 15837484 # number of WriteReq miss cycles 7269348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 24902984 # number of demand (read+write) miss cycles 7279348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 24902984 # number of demand (read+write) miss cycles 7289348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 24902984 # number of overall miss cycles 7299348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 24902984 # number of overall miss cycles 7309348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1927 # number of ReadReq accesses(hits+misses) 7319348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1927 # number of ReadReq accesses(hits+misses) 7329348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 7339348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 7349348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2792 # number of demand (read+write) accesses 7359348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2792 # number of demand (read+write) accesses 7369348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2792 # number of overall (read+write) accesses 7379348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2792 # number of overall (read+write) accesses 7389348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087701 # miss rate for ReadReq accesses 7399348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.087701 # miss rate for ReadReq accesses 7409348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 7419348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 7429348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.189112 # miss rate for demand accesses 7439348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.189112 # miss rate for demand accesses 7449348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.189112 # miss rate for overall accesses 7459348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.189112 # miss rate for overall accesses 7469348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53642.011834 # average ReadReq miss latency 7479348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 53642.011834 # average ReadReq miss latency 7489348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44115.554318 # average WriteReq miss latency 7499348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 44115.554318 # average WriteReq miss latency 7509348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency 7519348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::total 47164.742424 # average overall miss latency 7529348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 47164.742424 # average overall miss latency 7539348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::total 47164.742424 # average overall miss latency 7549348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_mshrs 801 # number of cycles access was blocked 7559348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7569348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked 7579348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 7589348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 30.807692 # average number of cycles each access was blocked 7599348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7609348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 7619348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 7629348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 68 # number of ReadReq MSHR hits 7639348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 7649348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits 7659348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits 7669348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits 7679348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits 7689348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits 7699348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits 7709348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 7719348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 7729348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 7739348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 7749348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 7759348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 7769348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 7779348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 7789348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6319000 # number of ReadReq MSHR miss cycles 7799348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 6319000 # number of ReadReq MSHR miss cycles 7809348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3813500 # number of WriteReq MSHR miss cycles 7819348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 3813500 # number of WriteReq MSHR miss cycles 7829348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 10132500 # number of demand (read+write) MSHR miss cycles 7839348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 10132500 # number of demand (read+write) MSHR miss cycles 7849348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 10132500 # number of overall MSHR miss cycles 7859348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 10132500 # number of overall MSHR miss cycles 7869348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052413 # mshr miss rate for ReadReq accesses 7879348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052413 # mshr miss rate for ReadReq accesses 7889348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 7899348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 7909348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for demand accesses 7919348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.062321 # mshr miss rate for demand accesses 7929348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062321 # mshr miss rate for overall accesses 7939348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.062321 # mshr miss rate for overall accesses 7949348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62564.356436 # average ReadReq mshr miss latency 7959348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62564.356436 # average ReadReq mshr miss latency 7969348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52239.726027 # average WriteReq mshr miss latency 7979348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52239.726027 # average WriteReq mshr miss latency 7989348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency 7999348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency 8009348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58232.758621 # average overall mshr miss latency 8019348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 58232.758621 # average overall mshr miss latency 8029348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 8033096SN/A 8043096SN/A---------- End Simulation Statistics ---------- 805