stats.txt revision 9285
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 39285Sandreas.hansson@arm.comsim_seconds 0.000012 # Number of seconds simulated 49285Sandreas.hansson@arm.comsim_ticks 12394500 # Number of ticks simulated 59285Sandreas.hansson@arm.comfinal_tick 12394500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79285Sandreas.hansson@arm.comhost_inst_rate 52290 # Simulator instruction rate (inst/s) 89285Sandreas.hansson@arm.comhost_op_rate 52282 # Simulator op (including micro ops) rate (op/s) 99285Sandreas.hansson@arm.comhost_tick_rate 101684511 # Simulator tick rate (ticks/s) 109285Sandreas.hansson@arm.comhost_mem_usage 219660 # Number of bytes of host memory used 119285Sandreas.hansson@arm.comhost_seconds 0.12 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6372 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6372 # Number of ops (including micro ops) simulated 149285Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 159285Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 11328 # Number of bytes read from this memory 169096Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 31296 # Number of bytes read from this memory 179285Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 189285Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 199285Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory 209285Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 177 # Number of read requests responded to by this memory 219096Sandreas.hansson@arm.comsystem.physmem.num_reads::total 489 # Number of read requests responded to by this memory 229285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1611037154 # Total read bandwidth from this memory (bytes/s) 239285Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 913953770 # Total read bandwidth from this memory (bytes/s) 249285Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2524990923 # Total read bandwidth from this memory (bytes/s) 259285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1611037154 # Instruction read bandwidth from this memory (bytes/s) 269285Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1611037154 # Instruction read bandwidth from this memory (bytes/s) 279285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1611037154 # Total bandwidth to/from this memory (bytes/s) 289285Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 913953770 # Total bandwidth to/from this memory (bytes/s) 299285Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2524990923 # Total bandwidth to/from this memory (bytes/s) 308428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 318428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 328428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 338428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 349285Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 1990 # DTB read hits 359285Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 56 # DTB read misses 368428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 379285Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 2046 # DTB read accesses 389285Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 1084 # DTB write hits 399285Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 30 # DTB write misses 408428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 419285Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 1114 # DTB write accesses 429285Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 3074 # DTB hits 439150SAli.Saidi@ARM.comsystem.cpu.dtb.data_misses 86 # DTB misses 448428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 459285Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 3160 # DTB accesses 469285Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 2336 # ITB hits 479285Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 38 # ITB misses 488428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 499285Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 2374 # ITB accesses 508428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 518428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 528428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 538428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 548428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 558428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 568428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 578428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 588428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 598428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 608428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 618428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 628428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 639285Sandreas.hansson@arm.comsystem.cpu.numCycles 24790 # number of cpu cycles simulated 648428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 658428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 669285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.lookups 2873 # Number of BP lookups 679285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condPredicted 1665 # Number of conditional branches predicted 689285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condIncorrect 545 # Number of conditional branches incorrect 699285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBLookups 2164 # Number of BTB lookups 709285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBHits 779 # Number of BTB hits 718428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 729285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target. 739285Sandreas.hansson@arm.comsystem.cpu.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions. 749285Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8141 # Number of cycles fetch is stalled on an Icache miss 759285Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 16442 # Number of instructions fetch has processed 769285Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2873 # Number of branches that fetch encountered 779285Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 1200 # Number of branches that fetch has predicted taken 789285Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 2939 # Number of cycles fetch has run and was not squashing or blocked 799285Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1838 # Number of cycles fetch has spent squashing 809285Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 885 # Number of cycles fetch has spent blocked 819285Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 829285Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 739 # Number of stall cycles due to pending traps 839285Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 2336 # Number of cache lines fetched 849285Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 367 # Number of outstanding Icache misses that were squashed 859285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 13982 # Number of instructions fetched each cycle (Total) 869285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.175940 # Number of instructions fetched each cycle (Total) 879285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.562615 # Number of instructions fetched each cycle (Total) 886291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 899285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 11043 78.98% 78.98% # Number of instructions fetched each cycle (Total) 909285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 296 2.12% 81.10% # Number of instructions fetched each cycle (Total) 919285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 231 1.65% 82.75% # Number of instructions fetched each cycle (Total) 929285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 234 1.67% 84.42% # Number of instructions fetched each cycle (Total) 939285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 276 1.97% 86.40% # Number of instructions fetched each cycle (Total) 949285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 200 1.43% 87.83% # Number of instructions fetched each cycle (Total) 959285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 274 1.96% 89.79% # Number of instructions fetched each cycle (Total) 969285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 190 1.36% 91.15% # Number of instructions fetched each cycle (Total) 979285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1238 8.85% 100.00% # Number of instructions fetched each cycle (Total) 986291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 996291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1006291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1019285Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 13982 # Number of instructions fetched each cycle (Total) 1029285Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.115894 # Number of branch fetches per cycle 1039285Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.663251 # Number of inst fetches per cycle 1049285Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 9096 # Number of cycles decode is idle 1059285Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 904 # Number of cycles decode is blocked 1069285Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2739 # Number of cycles decode is running 1079285Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking 1089285Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1171 # Number of cycles decode is squashing 1099150SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 257 # Number of times decode resolved a branch 1109285Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 89 # Number of times decode detected a branch misprediction 1119285Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 15180 # Number of instructions handled by decode 1129079SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode 1139285Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1171 # Number of cycles rename is squashing 1149285Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9315 # Number of cycles rename is idle 1159285Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 259 # Number of cycles rename is blocking 1169285Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 364 # count of cycles rename stalled for serializing inst 1179285Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2589 # Number of cycles rename is running 1189285Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 284 # Number of cycles rename is unblocking 1199285Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 14415 # Number of instructions processed by rename 1209150SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 8 # Number of times rename has blocked due to IQ full 1219285Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 250 # Number of times rename has blocked due to LSQ full 1229285Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 10802 # Number of destination operands rename has renamed 1239285Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 18056 # Number of register rename lookups that rename has made 1249285Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 18039 # Number of integer rename lookups 1258428SN/Asystem.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 1269150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 1279285Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6232 # Number of HB maps that are undone due to squashing 1289150SAli.Saidi@ARM.comsystem.cpu.rename.serializingInsts 33 # count of serializing insts renamed 1299150SAli.Saidi@ARM.comsystem.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed 1309285Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 728 # count of insts added to the skid buffer 1319285Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2652 # Number of loads inserted to the mem dependence unit. 1329285Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1357 # Number of stores inserted to the mem dependence unit. 1339285Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. 1348428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 1359285Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 12813 # Number of instructions added to the IQ (excludes non-spec) 1369096Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ 1379285Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 10578 # Number of instructions issued 1389285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued 1399285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6130 # Number of squashed instructions iterated over during squash; mainly for profiling 1409285Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph 1419096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed 1429285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 13982 # Number of insts issued each cycle 1439285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.756544 # Number of insts issued each cycle 1449285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.394074 # Number of insts issued each cycle 1458428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1469285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 9591 68.60% 68.60% # Number of insts issued each cycle 1479285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1568 11.21% 79.81% # Number of insts issued each cycle 1489285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 1143 8.17% 87.98% # Number of insts issued each cycle 1499285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 728 5.21% 93.19% # Number of insts issued each cycle 1509285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 479 3.43% 96.62% # Number of insts issued each cycle 1519285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 273 1.95% 98.57% # Number of insts issued each cycle 1529285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 154 1.10% 99.67% # Number of insts issued each cycle 1539285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 33 0.24% 99.91% # Number of insts issued each cycle 1549285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle 1558428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1568428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1578428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1589285Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 13982 # Number of insts issued each cycle 1598428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1609285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 10 8.70% 8.70% # attempts to use FU when none available 1619285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 8.70% # attempts to use FU when none available 1629285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 8.70% # attempts to use FU when none available 1639285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 8.70% # attempts to use FU when none available 1649285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 8.70% # attempts to use FU when none available 1659285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 8.70% # attempts to use FU when none available 1669285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 8.70% # attempts to use FU when none available 1679285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 8.70% # attempts to use FU when none available 1689285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.70% # attempts to use FU when none available 1699285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 8.70% # attempts to use FU when none available 1709285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.70% # attempts to use FU when none available 1719285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 8.70% # attempts to use FU when none available 1729285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 8.70% # attempts to use FU when none available 1739285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 8.70% # attempts to use FU when none available 1749285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 8.70% # attempts to use FU when none available 1759285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 8.70% # attempts to use FU when none available 1769285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.70% # attempts to use FU when none available 1779285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 8.70% # attempts to use FU when none available 1789285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.70% # attempts to use FU when none available 1799285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.70% # attempts to use FU when none available 1809285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.70% # attempts to use FU when none available 1819285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.70% # attempts to use FU when none available 1829285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.70% # attempts to use FU when none available 1839285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.70% # attempts to use FU when none available 1849285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.70% # attempts to use FU when none available 1859285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.70% # attempts to use FU when none available 1869285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.70% # attempts to use FU when none available 1879285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.70% # attempts to use FU when none available 1889285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.70% # attempts to use FU when none available 1899285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 65 56.52% 65.22% # attempts to use FU when none available 1909285Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 40 34.78% 100.00% # attempts to use FU when none available 1918428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1928428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1938241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 1949285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 7162 67.71% 67.73% # Type of FU issued 1959285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.73% # Type of FU issued 1969285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.73% # Type of FU issued 1979285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.75% # Type of FU issued 1989285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.75% # Type of FU issued 1999285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.75% # Type of FU issued 2009285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.75% # Type of FU issued 2019285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.75% # Type of FU issued 2029285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.75% # Type of FU issued 2039285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.75% # Type of FU issued 2049285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.75% # Type of FU issued 2059285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.75% # Type of FU issued 2069285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.75% # Type of FU issued 2079285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.75% # Type of FU issued 2089285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.75% # Type of FU issued 2099285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.75% # Type of FU issued 2109285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.75% # Type of FU issued 2119285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.75% # Type of FU issued 2129285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.75% # Type of FU issued 2139285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.75% # Type of FU issued 2149285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.75% # Type of FU issued 2159285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.75% # Type of FU issued 2169285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.75% # Type of FU issued 2179285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.75% # Type of FU issued 2189285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.75% # Type of FU issued 2199285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.75% # Type of FU issued 2209285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.75% # Type of FU issued 2219285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.75% # Type of FU issued 2229285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.75% # Type of FU issued 2239285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2248 21.25% 89.01% # Type of FU issued 2249285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1163 10.99% 100.00% # Type of FU issued 2258241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2268241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2279285Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 10578 # Type of FU issued 2289285Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.426704 # Inst issue rate 2299285Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 115 # FU busy when requested 2309285Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.010872 # FU busy rate (busy events/executed inst) 2319285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 35279 # Number of integer instruction queue reads 2329285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 18978 # Number of integer instruction queue writes 2339285Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9581 # Number of integer instruction queue wakeup accesses 2348428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 2358428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 2368428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 2379285Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 10680 # Number of integer alu accesses 2388428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 2399285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores 2408428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2419285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1469 # Number of loads squashed 2429285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 2439285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations 2449285Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 492 # Number of stores squashed 2458428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2468428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2478428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 2488428SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2498428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2509285Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1171 # Number of cycles IEW is squashing 2519150SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 28 # Number of cycles IEW is blocking 2529150SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking 2539285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 12931 # Number of instructions dispatched to IQ 2549285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 181 # Number of squashed instructions skipped by dispatch 2559285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2652 # Number of dispatched load instructions 2569285Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions 2579096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions 2589150SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 2598428SN/Asystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2609285Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations 2619285Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 151 # Number of branches that were predicted taken incorrectly 2629285Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 403 # Number of branches that were predicted not taken incorrectly 2639285Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 554 # Number of branch mispredicts detected at execute 2649285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 9992 # Number of executed instructions 2659285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2057 # Number of load instructions executed 2669285Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 586 # Number of squashed instructions skipped in execute 2678428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2689096Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 88 # number of nop insts executed 2699285Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3174 # number of memory reference insts executed 2709285Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1621 # Number of branches executed 2719285Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1117 # Number of stores executed 2729285Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.403066 # Inst execution rate 2739285Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 9749 # cumulative count of insts sent to commit 2749285Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 9591 # cumulative count of insts written-back 2759285Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 5054 # num instructions producing a value 2769285Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 6863 # num instructions consuming a value 2778428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2789285Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.386890 # insts written-back per cycle 2799285Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.736413 # average fanout of values written-back 2808428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2819285Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6541 # The number of squashed insts skipped by commit 2828428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 2839285Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 462 # The number of times a branch was mispredicted 2849285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 12811 # Number of insts commited each cycle 2859285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.498712 # Number of insts commited each cycle 2869285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.314684 # Number of insts commited each cycle 2878428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2889285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 10031 78.30% 78.30% # Number of insts commited each cycle 2899285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1473 11.50% 89.80% # Number of insts commited each cycle 2909285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 525 4.10% 93.90% # Number of insts commited each cycle 2919285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 241 1.88% 95.78% # Number of insts commited each cycle 2929285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 164 1.28% 97.06% # Number of insts commited each cycle 2939285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 92 0.72% 97.78% # Number of insts commited each cycle 2949285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 108 0.84% 98.62% # Number of insts commited each cycle 2959285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 37 0.29% 98.91% # Number of insts commited each cycle 2969285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 140 1.09% 100.00% # Number of insts commited each cycle 2978428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2988428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2998428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 3009285Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 12811 # Number of insts commited each cycle 3019150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6389 # Number of instructions committed 3029150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 3038428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 3049150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2048 # Number of memory references committed 3059150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1183 # Number of loads committed 3068428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 3079150SAli.Saidi@ARM.comsystem.cpu.commit.branches 1050 # Number of branches committed 3088428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 3099150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 6307 # Number of committed integer instructions. 3108428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 3119285Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 140 # number cycles where commit BW limit reached 3128428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 3139285Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 25250 # The number of ROB reads 3149285Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 27045 # The number of ROB writes 3159285Sandreas.hansson@arm.comsystem.cpu.timesIdled 255 # Number of times that the entire CPU went into an idle state and unscheduled itself 3169285Sandreas.hansson@arm.comsystem.cpu.idleCycles 10808 # Total number of cycles that the CPU has spent unscheduled due to idling 3179150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6372 # Number of Instructions Simulated 3189150SAli.Saidi@ARM.comsystem.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 3199150SAli.Saidi@ARM.comsystem.cpu.committedInsts_total 6372 # Number of Instructions Simulated 3209285Sandreas.hansson@arm.comsystem.cpu.cpi 3.890458 # CPI: Cycles Per Instruction 3219285Sandreas.hansson@arm.comsystem.cpu.cpi_total 3.890458 # CPI: Total CPI of All Threads 3229285Sandreas.hansson@arm.comsystem.cpu.ipc 0.257039 # IPC: Instructions Per Cycle 3239285Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.257039 # IPC: Total IPC of All Threads 3249285Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 12699 # number of integer regfile reads 3259285Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7211 # number of integer regfile writes 3268428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 3278428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 3288428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 3298428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 3308428SN/Asystem.cpu.icache.replacements 0 # number of replacements 3319285Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 158.537993 # Cycle average of tags in use 3329285Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 1881 # Total number of references to valid blocks. 3339285Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. 3349285Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 6.009585 # Average number of references to valid blocks. 3358428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3369285Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 158.537993 # Average occupied blocks per requestor 3379285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.077411 # Average percentage of cache occupancy 3389285Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.077411 # Average percentage of cache occupancy 3399285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1881 # number of ReadReq hits 3409285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1881 # number of ReadReq hits 3419285Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1881 # number of demand (read+write) hits 3429285Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1881 # number of demand (read+write) hits 3439285Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1881 # number of overall hits 3449285Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1881 # number of overall hits 3459285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 455 # number of ReadReq misses 3469285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses 3479285Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 455 # number of demand (read+write) misses 3489285Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses 3499285Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 455 # number of overall misses 3509285Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 455 # number of overall misses 3519285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 15830500 # number of ReadReq miss cycles 3529285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 15830500 # number of ReadReq miss cycles 3539285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 15830500 # number of demand (read+write) miss cycles 3549285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 15830500 # number of demand (read+write) miss cycles 3559285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 15830500 # number of overall miss cycles 3569285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 15830500 # number of overall miss cycles 3579285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2336 # number of ReadReq accesses(hits+misses) 3589285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2336 # number of ReadReq accesses(hits+misses) 3599285Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2336 # number of demand (read+write) accesses 3609285Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2336 # number of demand (read+write) accesses 3619285Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2336 # number of overall (read+write) accesses 3629285Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2336 # number of overall (read+write) accesses 3639285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194777 # miss rate for ReadReq accesses 3649285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.194777 # miss rate for ReadReq accesses 3659285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.194777 # miss rate for demand accesses 3669285Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.194777 # miss rate for demand accesses 3679285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.194777 # miss rate for overall accesses 3689285Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.194777 # miss rate for overall accesses 3699285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34792.307692 # average ReadReq miss latency 3709285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 34792.307692 # average ReadReq miss latency 3719285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency 3729285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 34792.307692 # average overall miss latency 3739285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 34792.307692 # average overall miss latency 3749285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 34792.307692 # average overall miss latency 3758428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3768428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3778428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3788428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3798983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3808983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3818428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3828428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3839285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 142 # number of ReadReq MSHR hits 3849285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 142 # number of ReadReq MSHR hits 3859285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 142 # number of demand (read+write) MSHR hits 3869285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits 3879285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 142 # number of overall MSHR hits 3889285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 142 # number of overall MSHR hits 3899285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 3909285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 3919285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 3929285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 3939285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 3949285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses 3959285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11526000 # number of ReadReq MSHR miss cycles 3969285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 11526000 # number of ReadReq MSHR miss cycles 3979285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 11526000 # number of demand (read+write) MSHR miss cycles 3989285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 11526000 # number of demand (read+write) MSHR miss cycles 3999285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 11526000 # number of overall MSHR miss cycles 4009285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 11526000 # number of overall MSHR miss cycles 4019285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for ReadReq accesses 4029285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.133990 # mshr miss rate for ReadReq accesses 4039285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for demand accesses 4049285Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.133990 # mshr miss rate for demand accesses 4059285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133990 # mshr miss rate for overall accesses 4069285Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.133990 # mshr miss rate for overall accesses 4079285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36824.281150 # average ReadReq mshr miss latency 4089285Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36824.281150 # average ReadReq mshr miss latency 4099285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36824.281150 # average overall mshr miss latency 4109285Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 36824.281150 # average overall mshr miss latency 4119285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36824.281150 # average overall mshr miss latency 4129285Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 36824.281150 # average overall mshr miss latency 4138428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4148428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 4159285Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 107.969871 # Cycle average of tags in use 4169285Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 2254 # Total number of references to valid blocks. 4179285Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 177 # Sample count of references to valid blocks. 4189285Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 12.734463 # Average number of references to valid blocks. 4198428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4209285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 107.969871 # Average occupied blocks per requestor 4219285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.026360 # Average percentage of cache occupancy 4229285Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::total 0.026360 # Average percentage of cache occupancy 4239285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1748 # number of ReadReq hits 4249285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1748 # number of ReadReq hits 4259096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 4269096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 4279285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2254 # number of demand (read+write) hits 4289285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2254 # number of demand (read+write) hits 4299285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2254 # number of overall hits 4309285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2254 # number of overall hits 4319285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 168 # number of ReadReq misses 4329285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 168 # number of ReadReq misses 4339096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 4349096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 4359285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 527 # number of demand (read+write) misses 4369285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 527 # number of demand (read+write) misses 4379285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 527 # number of overall misses 4389285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 527 # number of overall misses 4399285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 6365000 # number of ReadReq miss cycles 4409285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 6365000 # number of ReadReq miss cycles 4419285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 12897000 # number of WriteReq miss cycles 4429285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 12897000 # number of WriteReq miss cycles 4439285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 19262000 # number of demand (read+write) miss cycles 4449285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 19262000 # number of demand (read+write) miss cycles 4459285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 19262000 # number of overall miss cycles 4469285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 19262000 # number of overall miss cycles 4479285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1916 # number of ReadReq accesses(hits+misses) 4489285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1916 # number of ReadReq accesses(hits+misses) 4498835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 4508835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 4519285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2781 # number of demand (read+write) accesses 4529285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2781 # number of demand (read+write) accesses 4539285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2781 # number of overall (read+write) accesses 4549285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2781 # number of overall (read+write) accesses 4559285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087683 # miss rate for ReadReq accesses 4569285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.087683 # miss rate for ReadReq accesses 4579096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 4589096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 4599285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.189500 # miss rate for demand accesses 4609285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.189500 # miss rate for demand accesses 4619285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.189500 # miss rate for overall accesses 4629285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.189500 # miss rate for overall accesses 4639285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37886.904762 # average ReadReq miss latency 4649285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 37886.904762 # average ReadReq miss latency 4659285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35924.791086 # average WriteReq miss latency 4669285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 35924.791086 # average WriteReq miss latency 4679285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency 4689285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 36550.284630 # average overall miss latency 4699285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 36550.284630 # average overall miss latency 4709285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 36550.284630 # average overall miss latency 4718428SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4728428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4738428SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4748428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4758983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4768983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4778428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4788428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4799285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits 4809285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits 4819096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits 4829096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits 4839285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits 4849285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits 4859285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits 4869285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits 4879285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses 4889285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses 4899096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 4909096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 4919285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 177 # number of demand (read+write) MSHR misses 4929285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses 4939285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 177 # number of overall MSHR misses 4949285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 177 # number of overall MSHR misses 4959285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4341000 # number of ReadReq MSHR miss cycles 4969285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 4341000 # number of ReadReq MSHR miss cycles 4979285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2884500 # number of WriteReq MSHR miss cycles 4989285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2884500 # number of WriteReq MSHR miss cycles 4999285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 7225500 # number of demand (read+write) MSHR miss cycles 5009285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 7225500 # number of demand (read+write) MSHR miss cycles 5019285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 7225500 # number of overall MSHR miss cycles 5029285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 7225500 # number of overall MSHR miss cycles 5039285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054280 # mshr miss rate for ReadReq accesses 5049285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054280 # mshr miss rate for ReadReq accesses 5059096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 5069096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 5079285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063646 # mshr miss rate for demand accesses 5089285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.063646 # mshr miss rate for demand accesses 5099285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063646 # mshr miss rate for overall accesses 5109285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.063646 # mshr miss rate for overall accesses 5119285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41740.384615 # average ReadReq mshr miss latency 5129285Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41740.384615 # average ReadReq mshr miss latency 5139285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39513.698630 # average WriteReq mshr miss latency 5149285Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39513.698630 # average WriteReq mshr miss latency 5159285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40822.033898 # average overall mshr miss latency 5169285Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 40822.033898 # average overall mshr miss latency 5179285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40822.033898 # average overall mshr miss latency 5189285Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 40822.033898 # average overall mshr miss latency 5198428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5208428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5219285Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 219.433273 # Cycle average of tags in use 5228428SN/Asystem.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 5239150SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. 5249150SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.002404 # Average number of references to valid blocks. 5258428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5269285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 158.518751 # Average occupied blocks per requestor 5279285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 60.914522 # Average occupied blocks per requestor 5289285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004838 # Average percentage of cache occupancy 5299285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001859 # Average percentage of cache occupancy 5309285Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.006697 # Average percentage of cache occupancy 5318835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 5328835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 5338835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 5348835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 5358835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 5368835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 5379285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses 5389285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses 5399079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses 5409096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 5419096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 5429285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses 5439285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 177 # number of demand (read+write) misses 5449096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 489 # number of demand (read+write) misses 5459285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses 5469285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 177 # number of overall misses 5479096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 489 # number of overall misses 5489285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11209500 # number of ReadReq miss cycles 5499285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4227000 # number of ReadReq miss cycles 5509285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 15436500 # number of ReadReq miss cycles 5519285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2808500 # number of ReadExReq miss cycles 5529285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2808500 # number of ReadExReq miss cycles 5539285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 11209500 # number of demand (read+write) miss cycles 5549285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 7035500 # number of demand (read+write) miss cycles 5559285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 18245000 # number of demand (read+write) miss cycles 5569285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 11209500 # number of overall miss cycles 5579285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 7035500 # number of overall miss cycles 5589285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 18245000 # number of overall miss cycles 5599285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) 5609285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) 5619079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses) 5629096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 5639096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 5649285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses 5659285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 177 # number of demand (read+write) accesses 5669096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 490 # number of demand (read+write) accesses 5679285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses 5689285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 177 # number of overall (read+write) accesses 5699096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 490 # number of overall (read+write) accesses 5709285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses 5718835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 5729079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses 5738835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 5749055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 5759285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses 5768835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 5779096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997959 # miss rate for demand accesses 5789285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses 5798835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 5809096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997959 # miss rate for overall accesses 5819285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35927.884615 # average ReadReq miss latency 5829285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40644.230769 # average ReadReq miss latency 5839285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 37106.971154 # average ReadReq miss latency 5849285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38472.602740 # average ReadExReq miss latency 5859285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 38472.602740 # average ReadExReq miss latency 5869285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35927.884615 # average overall miss latency 5879285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 39748.587571 # average overall miss latency 5889285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 37310.838446 # average overall miss latency 5899285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35927.884615 # average overall miss latency 5909285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 39748.587571 # average overall miss latency 5919285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 37310.838446 # average overall miss latency 5928428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5938428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5948428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5958428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5968983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5978983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5988428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5998428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6009285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses 6019285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses 6029079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses 6039096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 6049096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 6059285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 6069285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 177 # number of demand (read+write) MSHR misses 6079096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 489 # number of demand (read+write) MSHR misses 6089285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 6099285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 177 # number of overall MSHR misses 6109096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 489 # number of overall MSHR misses 6119285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10213000 # number of ReadReq MSHR miss cycles 6129285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3905000 # number of ReadReq MSHR miss cycles 6139285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 14118000 # number of ReadReq MSHR miss cycles 6149285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2577000 # number of ReadExReq MSHR miss cycles 6159285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2577000 # number of ReadExReq MSHR miss cycles 6169285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10213000 # number of demand (read+write) MSHR miss cycles 6179285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6482000 # number of demand (read+write) MSHR miss cycles 6189285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 16695000 # number of demand (read+write) MSHR miss cycles 6199285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10213000 # number of overall MSHR miss cycles 6209285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6482000 # number of overall MSHR miss cycles 6219285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 16695000 # number of overall MSHR miss cycles 6229285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses 6238835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 6249079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses 6258835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6269055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6279285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 6288835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 6299096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997959 # mshr miss rate for demand accesses 6309285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 6318835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 6329096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997959 # mshr miss rate for overall accesses 6339285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32733.974359 # average ReadReq mshr miss latency 6349285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37548.076923 # average ReadReq mshr miss latency 6359285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33937.500000 # average ReadReq mshr miss latency 6369285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35301.369863 # average ReadExReq mshr miss latency 6379285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35301.369863 # average ReadExReq mshr miss latency 6389285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency 6399285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency 6409285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency 6419285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32733.974359 # average overall mshr miss latency 6429285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36621.468927 # average overall mshr miss latency 6439285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 34141.104294 # average overall mshr miss latency 6448428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6453096SN/A 6463096SN/A---------- End Simulation Statistics ---------- 647