stats.txt revision 9096
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 39096Sandreas.hansson@arm.comsim_seconds 0.000013 # Number of seconds simulated 49096Sandreas.hansson@arm.comsim_ticks 12811000 # Number of ticks simulated 59096Sandreas.hansson@arm.comfinal_tick 12811000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79096Sandreas.hansson@arm.comhost_inst_rate 61639 # Simulator instruction rate (inst/s) 89096Sandreas.hansson@arm.comhost_op_rate 61622 # Simulator op (including micro ops) rate (op/s) 99096Sandreas.hansson@arm.comhost_tick_rate 123585600 # Simulator tick rate (ticks/s) 109096Sandreas.hansson@arm.comhost_mem_usage 219212 # Number of bytes of host memory used 119096Sandreas.hansson@arm.comhost_seconds 0.10 # Real time elapsed on the host 128428SN/Asim_insts 6386 # Number of instructions simulated 138835SAli.Saidi@ARM.comsim_ops 6386 # Number of ops (including micro ops) simulated 149096Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory 159096Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 11200 # Number of bytes read from this memory 169096Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 31296 # Number of bytes read from this memory 179096Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory 189096Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory 199096Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory 209096Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 175 # Number of read requests responded to by this memory 219096Sandreas.hansson@arm.comsystem.physmem.num_reads::total 489 # Number of read requests responded to by this memory 229096Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 1568651940 # Total read bandwidth from this memory (bytes/s) 239096Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 874248693 # Total read bandwidth from this memory (bytes/s) 249096Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2442900632 # Total read bandwidth from this memory (bytes/s) 259096Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 1568651940 # Instruction read bandwidth from this memory (bytes/s) 269096Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 1568651940 # Instruction read bandwidth from this memory (bytes/s) 279096Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 1568651940 # Total bandwidth to/from this memory (bytes/s) 289096Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 874248693 # Total bandwidth to/from this memory (bytes/s) 299096Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2442900632 # Total bandwidth to/from this memory (bytes/s) 308428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 318428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 328428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 338428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 349096Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 1966 # DTB read hits 359096Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 45 # DTB read misses 368428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 379096Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 2011 # DTB read accesses 389079SAli.Saidi@ARM.comsystem.cpu.dtb.write_hits 1059 # DTB write hits 399096Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 28 # DTB write misses 408428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 419096Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 1087 # DTB write accesses 429096Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 3025 # DTB hits 439096Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 73 # DTB misses 448428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 459096Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 3098 # DTB accesses 469096Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 2254 # ITB hits 479096Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 39 # ITB misses 488428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 499096Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 2293 # ITB accesses 508428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 518428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 528428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 538428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 548428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 558428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 568428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 578428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 588428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 598428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 608428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 618428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 628428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 639096Sandreas.hansson@arm.comsystem.cpu.numCycles 25623 # number of cpu cycles simulated 648428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 658428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 669096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.lookups 2750 # Number of BP lookups 679096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condPredicted 1591 # Number of conditional branches predicted 689096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.condIncorrect 527 # Number of conditional branches incorrect 699096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBLookups 2077 # Number of BTB lookups 709096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.BTBHits 748 # Number of BTB hits 718428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 729096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.usedRAS 402 # Number of times the RAS was used to get a target. 739096Sandreas.hansson@arm.comsystem.cpu.BPredUnit.RASInCorrect 69 # Number of incorrect RAS predictions. 749096Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8523 # Number of cycles fetch is stalled on an Icache miss 759096Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 15693 # Number of instructions fetch has processed 769096Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2750 # Number of branches that fetch encountered 779096Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 1150 # Number of branches that fetch has predicted taken 789096Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 2817 # Number of cycles fetch has run and was not squashing or blocked 799096Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1761 # Number of cycles fetch has spent squashing 809096Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 996 # Number of cycles fetch has spent blocked 819096Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 829096Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 745 # Number of stall cycles due to pending traps 839096Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 2254 # Number of cache lines fetched 849096Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 361 # Number of outstanding Icache misses that were squashed 859096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 14299 # Number of instructions fetched each cycle (Total) 869096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.097489 # Number of instructions fetched each cycle (Total) 879096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.491166 # Number of instructions fetched each cycle (Total) 886291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 899096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 11482 80.30% 80.30% # Number of instructions fetched each cycle (Total) 909096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 287 2.01% 82.31% # Number of instructions fetched each cycle (Total) 919096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 235 1.64% 83.95% # Number of instructions fetched each cycle (Total) 929096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 221 1.55% 85.50% # Number of instructions fetched each cycle (Total) 939096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 257 1.80% 87.29% # Number of instructions fetched each cycle (Total) 949096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 195 1.36% 88.66% # Number of instructions fetched each cycle (Total) 959096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 267 1.87% 90.52% # Number of instructions fetched each cycle (Total) 969096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 172 1.20% 91.73% # Number of instructions fetched each cycle (Total) 979096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1183 8.27% 100.00% # Number of instructions fetched each cycle (Total) 986291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 996291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1006291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1019096Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 14299 # Number of instructions fetched each cycle (Total) 1029096Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.107325 # Number of branch fetches per cycle 1039096Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.612458 # Number of inst fetches per cycle 1049096Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 9448 # Number of cycles decode is idle 1059096Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 1035 # Number of cycles decode is blocked 1069096Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2627 # Number of cycles decode is running 1079096Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking 1089096Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1110 # Number of cycles decode is squashing 1099096Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 255 # Number of times decode resolved a branch 1109079SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction 1119096Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 14531 # Number of instructions handled by decode 1129079SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode 1139096Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1110 # Number of cycles rename is squashing 1149096Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 9647 # Number of cycles rename is idle 1159096Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 356 # Number of cycles rename is blocking 1169096Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 379 # count of cycles rename stalled for serializing inst 1179096Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2494 # Number of cycles rename is running 1189096Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 313 # Number of cycles rename is unblocking 1199096Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 13871 # Number of instructions processed by rename 1209096Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 1219096Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 268 # Number of times rename has blocked due to LSQ full 1229096Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 10378 # Number of destination operands rename has renamed 1239096Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 17349 # Number of register rename lookups that rename has made 1249096Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 17332 # Number of integer rename lookups 1258428SN/Asystem.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 1268428SN/Asystem.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed 1279096Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 5795 # Number of HB maps that are undone due to squashing 1289096Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 32 # count of serializing insts renamed 1299096Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed 1309096Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 762 # count of insts added to the skid buffer 1319096Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2605 # Number of loads inserted to the mem dependence unit. 1329096Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1307 # Number of stores inserted to the mem dependence unit. 1339079SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. 1348428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 1359096Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 12446 # Number of instructions added to the IQ (excludes non-spec) 1369096Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 30 # Number of non-speculative instructions added to the IQ 1379096Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 10341 # Number of instructions issued 1389096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 37 # Number of squashed instructions issued 1399096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 5740 # Number of squashed instructions iterated over during squash; mainly for profiling 1409096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3350 # Number of squashed operands that are examined and possibly removed from graph 1419096Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed 1429096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 14299 # Number of insts issued each cycle 1439096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.723197 # Number of insts issued each cycle 1449096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.354818 # Number of insts issued each cycle 1458428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1469096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 9905 69.27% 69.27% # Number of insts issued each cycle 1479096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1622 11.34% 80.61% # Number of insts issued each cycle 1489096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 1176 8.22% 88.84% # Number of insts issued each cycle 1499096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 704 4.92% 93.76% # Number of insts issued each cycle 1509096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 444 3.11% 96.87% # Number of insts issued each cycle 1519096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 263 1.84% 98.71% # Number of insts issued each cycle 1529096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 141 0.99% 99.69% # Number of insts issued each cycle 1539096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 34 0.24% 99.93% # Number of insts issued each cycle 1549096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 10 0.07% 100.00% # Number of insts issued each cycle 1558428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1568428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1578428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1589096Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 14299 # Number of insts issued each cycle 1598428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1609096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 8 7.27% 7.27% # attempts to use FU when none available 1619096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 7.27% # attempts to use FU when none available 1629096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 7.27% # attempts to use FU when none available 1639096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 7.27% # attempts to use FU when none available 1649096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 7.27% # attempts to use FU when none available 1659096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 7.27% # attempts to use FU when none available 1669096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 7.27% # attempts to use FU when none available 1679096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 7.27% # attempts to use FU when none available 1689096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.27% # attempts to use FU when none available 1699096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 7.27% # attempts to use FU when none available 1709096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.27% # attempts to use FU when none available 1719096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 7.27% # attempts to use FU when none available 1729096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 7.27% # attempts to use FU when none available 1739096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 7.27% # attempts to use FU when none available 1749096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 7.27% # attempts to use FU when none available 1759096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 7.27% # attempts to use FU when none available 1769096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.27% # attempts to use FU when none available 1779096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 7.27% # attempts to use FU when none available 1789096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.27% # attempts to use FU when none available 1799096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.27% # attempts to use FU when none available 1809096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.27% # attempts to use FU when none available 1819096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.27% # attempts to use FU when none available 1829096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.27% # attempts to use FU when none available 1839096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.27% # attempts to use FU when none available 1849096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.27% # attempts to use FU when none available 1859096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.27% # attempts to use FU when none available 1869096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.27% # attempts to use FU when none available 1879096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.27% # attempts to use FU when none available 1889096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.27% # attempts to use FU when none available 1899096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 65 59.09% 66.36% # attempts to use FU when none available 1909096Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 37 33.64% 100.00% # attempts to use FU when none available 1918428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1928428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1938241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 1949096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 7000 67.69% 67.71% # Type of FU issued 1959096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.72% # Type of FU issued 1969096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.72% # Type of FU issued 1979096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.74% # Type of FU issued 1989096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.74% # Type of FU issued 1999096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.74% # Type of FU issued 2009096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.74% # Type of FU issued 2019096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.74% # Type of FU issued 2029096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.74% # Type of FU issued 2039096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.74% # Type of FU issued 2049096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.74% # Type of FU issued 2059096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.74% # Type of FU issued 2069096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.74% # Type of FU issued 2079096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.74% # Type of FU issued 2089096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.74% # Type of FU issued 2099096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.74% # Type of FU issued 2109096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.74% # Type of FU issued 2119096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.74% # Type of FU issued 2129096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.74% # Type of FU issued 2139096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.74% # Type of FU issued 2149096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.74% # Type of FU issued 2159096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.74% # Type of FU issued 2169096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.74% # Type of FU issued 2179096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.74% # Type of FU issued 2189096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.74% # Type of FU issued 2199096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.74% # Type of FU issued 2209096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.74% # Type of FU issued 2219096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.74% # Type of FU issued 2229096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.74% # Type of FU issued 2239096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2210 21.37% 89.11% # Type of FU issued 2249096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1126 10.89% 100.00% # Type of FU issued 2258241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2268241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2279096Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 10341 # Type of FU issued 2289096Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.403583 # Inst issue rate 2299096Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 110 # FU busy when requested 2309096Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.010637 # FU busy rate (busy events/executed inst) 2319096Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 35107 # Number of integer instruction queue reads 2329096Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 18223 # Number of integer instruction queue writes 2339096Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9409 # Number of integer instruction queue wakeup accesses 2348428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 2358428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 2368428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 2379096Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 10438 # Number of integer alu accesses 2388428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 2399096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores 2408428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2419096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1420 # Number of loads squashed 2429096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 2438844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 2449096Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 442 # Number of stores squashed 2458428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2468428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2478428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 2488428SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2498428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2509096Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1110 # Number of cycles IEW is squashing 2519096Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 39 # Number of cycles IEW is blocking 2528844SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking 2539096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 12564 # Number of instructions dispatched to IQ 2549096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 188 # Number of squashed instructions skipped by dispatch 2559096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2605 # Number of dispatched load instructions 2569096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1307 # Number of dispatched store instructions 2579096Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions 2588844SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 2598428SN/Asystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2608844SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 2619096Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 139 # Number of branches that were predicted taken incorrectly 2629096Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 385 # Number of branches that were predicted not taken incorrectly 2639096Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 524 # Number of branch mispredicts detected at execute 2649096Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 9796 # Number of executed instructions 2659096Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2022 # Number of load instructions executed 2669096Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 545 # Number of squashed instructions skipped in execute 2678428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2689096Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 88 # number of nop insts executed 2699096Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3112 # number of memory reference insts executed 2709079SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 1595 # Number of branches executed 2719096Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1090 # Number of stores executed 2729096Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.382313 # Inst execution rate 2739096Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 9558 # cumulative count of insts sent to commit 2749096Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 9419 # cumulative count of insts written-back 2759096Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 4945 # num instructions producing a value 2769096Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 6634 # num instructions consuming a value 2778428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2789096Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.367599 # insts written-back per cycle 2799096Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.745402 # average fanout of values written-back 2808428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2818428SN/Asystem.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions 2828835SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedOps 6403 # The number of committed instructions 2839096Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6160 # The number of squashed insts skipped by commit 2848428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 2859096Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 444 # The number of times a branch was mispredicted 2869096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13189 # Number of insts commited each cycle 2879096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.485480 # Number of insts commited each cycle 2889096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.291478 # Number of insts commited each cycle 2898428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2909096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 10357 78.53% 78.53% # Number of insts commited each cycle 2919096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1540 11.68% 90.20% # Number of insts commited each cycle 2929096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 523 3.97% 94.17% # Number of insts commited each cycle 2939096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 223 1.69% 95.86% # Number of insts commited each cycle 2949096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 163 1.24% 97.10% # Number of insts commited each cycle 2959096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 109 0.83% 97.92% # Number of insts commited each cycle 2969096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 106 0.80% 98.73% # Number of insts commited each cycle 2979096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 29 0.22% 98.95% # Number of insts commited each cycle 2989096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 139 1.05% 100.00% # Number of insts commited each cycle 2998428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 3008428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 3018428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 3029096Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13189 # Number of insts commited each cycle 3038835SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6403 # Number of instructions committed 3048835SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed 3058428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 3068428SN/Asystem.cpu.commit.refs 2050 # Number of memory references committed 3078428SN/Asystem.cpu.commit.loads 1185 # Number of loads committed 3088428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 3098428SN/Asystem.cpu.commit.branches 1051 # Number of branches committed 3108428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 3118428SN/Asystem.cpu.commit.int_insts 6321 # Number of committed integer instructions. 3128428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 3139096Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 139 # number cycles where commit BW limit reached 3148428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 3159096Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 25262 # The number of ROB reads 3169096Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 26244 # The number of ROB writes 3179096Sandreas.hansson@arm.comsystem.cpu.timesIdled 278 # Number of times that the entire CPU went into an idle state and unscheduled itself 3189096Sandreas.hansson@arm.comsystem.cpu.idleCycles 11324 # Total number of cycles that the CPU has spent unscheduled due to idling 3198428SN/Asystem.cpu.committedInsts 6386 # Number of Instructions Simulated 3208835SAli.Saidi@ARM.comsystem.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated 3218428SN/Asystem.cpu.committedInsts_total 6386 # Number of Instructions Simulated 3229096Sandreas.hansson@arm.comsystem.cpu.cpi 4.012371 # CPI: Cycles Per Instruction 3239096Sandreas.hansson@arm.comsystem.cpu.cpi_total 4.012371 # CPI: Total CPI of All Threads 3249096Sandreas.hansson@arm.comsystem.cpu.ipc 0.249229 # IPC: Instructions Per Cycle 3259096Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.249229 # IPC: Total IPC of All Threads 3269096Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 12434 # number of integer regfile reads 3279096Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7077 # number of integer regfile writes 3288428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 3298428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 3308428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 3318428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 3328428SN/Asystem.cpu.icache.replacements 0 # number of replacements 3339096Sandreas.hansson@arm.comsystem.cpu.icache.tagsinuse 159.968477 # Cycle average of tags in use 3349096Sandreas.hansson@arm.comsystem.cpu.icache.total_refs 1800 # Total number of references to valid blocks. 3359096Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. 3369096Sandreas.hansson@arm.comsystem.cpu.icache.avg_refs 5.714286 # Average number of references to valid blocks. 3378428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3389096Sandreas.hansson@arm.comsystem.cpu.icache.occ_blocks::cpu.inst 159.968477 # Average occupied blocks per requestor 3399096Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::cpu.inst 0.078110 # Average percentage of cache occupancy 3409096Sandreas.hansson@arm.comsystem.cpu.icache.occ_percent::total 0.078110 # Average percentage of cache occupancy 3419096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits 3429096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits 3439096Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits 3449096Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits 3459096Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits 3469096Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1800 # number of overall hits 3479096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses 3489096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses 3499096Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 454 # number of demand (read+write) misses 3509096Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 454 # number of demand (read+write) misses 3519096Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 454 # number of overall misses 3529096Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 454 # number of overall misses 3539096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 16294000 # number of ReadReq miss cycles 3549096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 16294000 # number of ReadReq miss cycles 3559096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 16294000 # number of demand (read+write) miss cycles 3569096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 16294000 # number of demand (read+write) miss cycles 3579096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 16294000 # number of overall miss cycles 3589096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 16294000 # number of overall miss cycles 3599096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2254 # number of ReadReq accesses(hits+misses) 3609096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2254 # number of ReadReq accesses(hits+misses) 3619096Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2254 # number of demand (read+write) accesses 3629096Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2254 # number of demand (read+write) accesses 3639096Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2254 # number of overall (read+write) accesses 3649096Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2254 # number of overall (read+write) accesses 3659096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.201420 # miss rate for ReadReq accesses 3669096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.201420 # miss rate for ReadReq accesses 3679096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.201420 # miss rate for demand accesses 3689096Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.201420 # miss rate for demand accesses 3699096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.201420 # miss rate for overall accesses 3709096Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.201420 # miss rate for overall accesses 3719096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35889.867841 # average ReadReq miss latency 3729096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 35889.867841 # average ReadReq miss latency 3739096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 35889.867841 # average overall miss latency 3749096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 35889.867841 # average overall miss latency 3759096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 35889.867841 # average overall miss latency 3769096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 35889.867841 # average overall miss latency 3778428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3788428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3798428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3808428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3818983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3828983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3838428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3848428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3859096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 139 # number of ReadReq MSHR hits 3869096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 139 # number of ReadReq MSHR hits 3879096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 139 # number of demand (read+write) MSHR hits 3889096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 139 # number of demand (read+write) MSHR hits 3899096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 139 # number of overall MSHR hits 3909096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 139 # number of overall MSHR hits 3919096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 3929096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 3939096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 3949096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 3959096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 3969096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses 3979096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11617000 # number of ReadReq MSHR miss cycles 3989096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 11617000 # number of ReadReq MSHR miss cycles 3999096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 11617000 # number of demand (read+write) MSHR miss cycles 4009096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 11617000 # number of demand (read+write) MSHR miss cycles 4019096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 11617000 # number of overall MSHR miss cycles 4029096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 11617000 # number of overall MSHR miss cycles 4039096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for ReadReq accesses 4049096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.139752 # mshr miss rate for ReadReq accesses 4059096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for demand accesses 4069096Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.139752 # mshr miss rate for demand accesses 4079096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.139752 # mshr miss rate for overall accesses 4089096Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.139752 # mshr miss rate for overall accesses 4099096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36879.365079 # average ReadReq mshr miss latency 4109096Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36879.365079 # average ReadReq mshr miss latency 4119096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36879.365079 # average overall mshr miss latency 4129096Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 36879.365079 # average overall mshr miss latency 4139096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36879.365079 # average overall mshr miss latency 4149096Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 36879.365079 # average overall mshr miss latency 4158428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4168428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 4179096Sandreas.hansson@arm.comsystem.cpu.dcache.tagsinuse 107.786985 # Cycle average of tags in use 4189096Sandreas.hansson@arm.comsystem.cpu.dcache.total_refs 2240 # Total number of references to valid blocks. 4199096Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. 4209096Sandreas.hansson@arm.comsystem.cpu.dcache.avg_refs 12.873563 # Average number of references to valid blocks. 4218428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4229096Sandreas.hansson@arm.comsystem.cpu.dcache.occ_blocks::cpu.data 107.786985 # Average occupied blocks per requestor 4239096Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::cpu.data 0.026315 # Average percentage of cache occupancy 4249096Sandreas.hansson@arm.comsystem.cpu.dcache.occ_percent::total 0.026315 # Average percentage of cache occupancy 4259096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1734 # number of ReadReq hits 4269096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1734 # number of ReadReq hits 4279096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 4289096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 4299096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2240 # number of demand (read+write) hits 4309096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2240 # number of demand (read+write) hits 4319096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2240 # number of overall hits 4329096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2240 # number of overall hits 4339096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 161 # number of ReadReq misses 4349096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 161 # number of ReadReq misses 4359096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 4369096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 4379096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 520 # number of demand (read+write) misses 4389096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 520 # number of demand (read+write) misses 4399096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 520 # number of overall misses 4409096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 520 # number of overall misses 4419096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 6422000 # number of ReadReq miss cycles 4429096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 6422000 # number of ReadReq miss cycles 4439096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 15048500 # number of WriteReq miss cycles 4449096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 15048500 # number of WriteReq miss cycles 4459096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 21470500 # number of demand (read+write) miss cycles 4469096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 21470500 # number of demand (read+write) miss cycles 4479096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 21470500 # number of overall miss cycles 4489096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 21470500 # number of overall miss cycles 4499096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1895 # number of ReadReq accesses(hits+misses) 4509096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1895 # number of ReadReq accesses(hits+misses) 4518835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 4528835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 4539096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2760 # number of demand (read+write) accesses 4549096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2760 # number of demand (read+write) accesses 4559096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2760 # number of overall (read+write) accesses 4569096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2760 # number of overall (read+write) accesses 4579096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084960 # miss rate for ReadReq accesses 4589096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.084960 # miss rate for ReadReq accesses 4599096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 4609096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 4619096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.188406 # miss rate for demand accesses 4629096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.188406 # miss rate for demand accesses 4639096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.188406 # miss rate for overall accesses 4649096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.188406 # miss rate for overall accesses 4659096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39888.198758 # average ReadReq miss latency 4669096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 39888.198758 # average ReadReq miss latency 4679096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41917.827298 # average WriteReq miss latency 4689096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 41917.827298 # average WriteReq miss latency 4699096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 41289.423077 # average overall miss latency 4709096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 41289.423077 # average overall miss latency 4719096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 41289.423077 # average overall miss latency 4729096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 41289.423077 # average overall miss latency 4738428SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4748428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4758428SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4768428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4778983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4788983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4798428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4808428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4819096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits 4829096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits 4839096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits 4849096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits 4859096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 345 # number of demand (read+write) MSHR hits 4869096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits 4879096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 345 # number of overall MSHR hits 4889096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits 4899096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 4909096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 4919096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 4929096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 4939096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 175 # number of demand (read+write) MSHR misses 4949096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses 4959096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 175 # number of overall MSHR misses 4969096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 175 # number of overall MSHR misses 4979096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4236500 # number of ReadReq MSHR miss cycles 4989096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 4236500 # number of ReadReq MSHR miss cycles 4999096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2874500 # number of WriteReq MSHR miss cycles 5009096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2874500 # number of WriteReq MSHR miss cycles 5019096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 7111000 # number of demand (read+write) MSHR miss cycles 5029096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 7111000 # number of demand (read+write) MSHR miss cycles 5039096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 7111000 # number of overall MSHR miss cycles 5049096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 7111000 # number of overall MSHR miss cycles 5059096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053826 # mshr miss rate for ReadReq accesses 5069096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053826 # mshr miss rate for ReadReq accesses 5079096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 5089096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 5099096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063406 # mshr miss rate for demand accesses 5109096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.063406 # mshr miss rate for demand accesses 5119096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063406 # mshr miss rate for overall accesses 5129096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.063406 # mshr miss rate for overall accesses 5139096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 41534.313725 # average ReadReq mshr miss latency 5149096Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 41534.313725 # average ReadReq mshr miss latency 5159096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39376.712329 # average WriteReq mshr miss latency 5169096Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39376.712329 # average WriteReq mshr miss latency 5179096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40634.285714 # average overall mshr miss latency 5189096Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 40634.285714 # average overall mshr miss latency 5199096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40634.285714 # average overall mshr miss latency 5209096Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 40634.285714 # average overall mshr miss latency 5218428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5228428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5239096Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 220.452556 # Cycle average of tags in use 5248428SN/Asystem.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 5259096Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 415 # Sample count of references to valid blocks. 5269096Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 0.002410 # Average number of references to valid blocks. 5278428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5289096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 159.940532 # Average occupied blocks per requestor 5299096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 60.512024 # Average occupied blocks per requestor 5309096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004881 # Average percentage of cache occupancy 5319096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001847 # Average percentage of cache occupancy 5329096Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.006728 # Average percentage of cache occupancy 5338835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 5348835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 5358835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 5368835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 5378835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 5388835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 5399096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses 5409096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses 5419079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses 5429096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 5439096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 5449096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses 5459096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 175 # number of demand (read+write) misses 5469096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 489 # number of demand (read+write) misses 5479096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses 5489096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 175 # number of overall misses 5499096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 489 # number of overall misses 5509096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11286500 # number of ReadReq miss cycles 5519096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 4103500 # number of ReadReq miss cycles 5529096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 15390000 # number of ReadReq miss cycles 5539096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2793500 # number of ReadExReq miss cycles 5549096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2793500 # number of ReadExReq miss cycles 5559096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 11286500 # number of demand (read+write) miss cycles 5569096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 6897000 # number of demand (read+write) miss cycles 5579096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 18183500 # number of demand (read+write) miss cycles 5589096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 11286500 # number of overall miss cycles 5599096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 6897000 # number of overall miss cycles 5609096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 18183500 # number of overall miss cycles 5619096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) 5629096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) 5639079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses) 5649096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 5659096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 5669096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses 5679096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 175 # number of demand (read+write) accesses 5689096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 490 # number of demand (read+write) accesses 5699096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses 5709096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 175 # number of overall (read+write) accesses 5719096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 490 # number of overall (read+write) accesses 5729096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses 5738835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 5749079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses 5758835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 5769055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 5779096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses 5788835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 5799096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997959 # miss rate for demand accesses 5809096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses 5818835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 5829096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997959 # miss rate for overall accesses 5839096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35944.267516 # average ReadReq miss latency 5849096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 40230.392157 # average ReadReq miss latency 5859096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 36995.192308 # average ReadReq miss latency 5869096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38267.123288 # average ReadExReq miss latency 5879096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 38267.123288 # average ReadExReq miss latency 5889096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35944.267516 # average overall miss latency 5899096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 39411.428571 # average overall miss latency 5909096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 37185.071575 # average overall miss latency 5919096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35944.267516 # average overall miss latency 5929096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 39411.428571 # average overall miss latency 5939096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 37185.071575 # average overall miss latency 5948428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5958428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5968428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5978428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5988983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5998983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6008428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6018428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6029096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 6039096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 6049079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses 6059096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 6069096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 6079096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 6089096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 175 # number of demand (read+write) MSHR misses 6099096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 489 # number of demand (read+write) MSHR misses 6109096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 6119096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 175 # number of overall MSHR misses 6129096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 489 # number of overall MSHR misses 6139096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10285500 # number of ReadReq MSHR miss cycles 6149096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3793000 # number of ReadReq MSHR miss cycles 6159096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 14078500 # number of ReadReq MSHR miss cycles 6169096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2567500 # number of ReadExReq MSHR miss cycles 6179096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2567500 # number of ReadExReq MSHR miss cycles 6189096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10285500 # number of demand (read+write) MSHR miss cycles 6199096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6360500 # number of demand (read+write) MSHR miss cycles 6209096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 16646000 # number of demand (read+write) MSHR miss cycles 6219096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10285500 # number of overall MSHR miss cycles 6229096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6360500 # number of overall MSHR miss cycles 6239096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 16646000 # number of overall MSHR miss cycles 6249096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses 6258835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 6269079SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses 6278835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6289055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6299096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses 6308835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 6319096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997959 # mshr miss rate for demand accesses 6329096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses 6338835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 6349096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997959 # mshr miss rate for overall accesses 6359096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32756.369427 # average ReadReq mshr miss latency 6369096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 37186.274510 # average ReadReq mshr miss latency 6379096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33842.548077 # average ReadReq mshr miss latency 6389096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35171.232877 # average ReadExReq mshr miss latency 6399096Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35171.232877 # average ReadExReq mshr miss latency 6409096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32756.369427 # average overall mshr miss latency 6419096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36345.714286 # average overall mshr miss latency 6429096Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 34040.899796 # average overall mshr miss latency 6439096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32756.369427 # average overall mshr miss latency 6449096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36345.714286 # average overall mshr miss latency 6459096Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 34040.899796 # average overall mshr miss latency 6468428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6473096SN/A 6483096SN/A---------- End Simulation Statistics ---------- 649