stats.txt revision 9055
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 35520SN/Asim_seconds 0.000012 # Number of seconds simulated 48844SAli.Saidi@ARM.comsim_ticks 12450500 # Number of ticks simulated 58844SAli.Saidi@ARM.comfinal_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79055Ssaidi@eecs.umich.eduhost_inst_rate 73568 # Simulator instruction rate (inst/s) 89055Ssaidi@eecs.umich.eduhost_op_rate 73552 # Simulator op (including micro ops) rate (op/s) 99055Ssaidi@eecs.umich.eduhost_tick_rate 143373020 # Simulator tick rate (ticks/s) 109055Ssaidi@eecs.umich.eduhost_mem_usage 215332 # Number of bytes of host memory used 119055Ssaidi@eecs.umich.eduhost_seconds 0.09 # Real time elapsed on the host 128428SN/Asim_insts 6386 # Number of instructions simulated 138835SAli.Saidi@ARM.comsim_ops 6386 # Number of ops (including micro ops) simulated 149055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory 159055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory 169055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 31360 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory 209055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory 219055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 490 # Number of read requests responded to by this memory 229055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu.inst 1614071724 # Total read bandwidth from this memory (bytes/s) 239055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu.data 904702622 # Total read bandwidth from this memory (bytes/s) 249055Ssaidi@eecs.umich.edusystem.physmem.bw_read::total 2518774346 # Total read bandwidth from this memory (bytes/s) 259055Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu.inst 1614071724 # Instruction read bandwidth from this memory (bytes/s) 269055Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::total 1614071724 # Instruction read bandwidth from this memory (bytes/s) 279055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.inst 1614071724 # Total bandwidth to/from this memory (bytes/s) 289055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu.data 904702622 # Total bandwidth to/from this memory (bytes/s) 299055Ssaidi@eecs.umich.edusystem.physmem.bw_total::total 2518774346 # Total bandwidth to/from this memory (bytes/s) 308428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 318428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 328428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 338428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 348844SAli.Saidi@ARM.comsystem.cpu.dtb.read_hits 1943 # DTB read hits 358844SAli.Saidi@ARM.comsystem.cpu.dtb.read_misses 53 # DTB read misses 368428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 378844SAli.Saidi@ARM.comsystem.cpu.dtb.read_accesses 1996 # DTB read accesses 388844SAli.Saidi@ARM.comsystem.cpu.dtb.write_hits 1071 # DTB write hits 398844SAli.Saidi@ARM.comsystem.cpu.dtb.write_misses 32 # DTB write misses 408428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 418844SAli.Saidi@ARM.comsystem.cpu.dtb.write_accesses 1103 # DTB write accesses 428844SAli.Saidi@ARM.comsystem.cpu.dtb.data_hits 3014 # DTB hits 438844SAli.Saidi@ARM.comsystem.cpu.dtb.data_misses 85 # DTB misses 448428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 458844SAli.Saidi@ARM.comsystem.cpu.dtb.data_accesses 3099 # DTB accesses 468844SAli.Saidi@ARM.comsystem.cpu.itb.fetch_hits 2367 # ITB hits 478844SAli.Saidi@ARM.comsystem.cpu.itb.fetch_misses 26 # ITB misses 488428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 498844SAli.Saidi@ARM.comsystem.cpu.itb.fetch_accesses 2393 # ITB accesses 508428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 518428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 528428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 538428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 548428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 558428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 568428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 578428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 588428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 598428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 608428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 618428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 628428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 638844SAli.Saidi@ARM.comsystem.cpu.numCycles 24902 # number of cpu cycles simulated 648428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 658428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 668844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.lookups 2873 # Number of BP lookups 678844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condPredicted 1642 # Number of conditional branches predicted 688844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.condIncorrect 561 # Number of conditional branches incorrect 698844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBLookups 2186 # Number of BTB lookups 708844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.BTBHits 748 # Number of BTB hits 718428SN/Asystem.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 728844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.usedRAS 430 # Number of times the RAS was used to get a target. 738844SAli.Saidi@ARM.comsystem.cpu.BPredUnit.RASInCorrect 100 # Number of incorrect RAS predictions. 748844SAli.Saidi@ARM.comsystem.cpu.fetch.icacheStallCycles 7799 # Number of cycles fetch is stalled on an Icache miss 758844SAli.Saidi@ARM.comsystem.cpu.fetch.Insts 16643 # Number of instructions fetch has processed 768844SAli.Saidi@ARM.comsystem.cpu.fetch.Branches 2873 # Number of branches that fetch encountered 778844SAli.Saidi@ARM.comsystem.cpu.fetch.predictedBranches 1178 # Number of branches that fetch has predicted taken 788844SAli.Saidi@ARM.comsystem.cpu.fetch.Cycles 2979 # Number of cycles fetch has run and was not squashing or blocked 798844SAli.Saidi@ARM.comsystem.cpu.fetch.SquashCycles 1864 # Number of cycles fetch has spent squashing 808844SAli.Saidi@ARM.comsystem.cpu.fetch.BlockedCycles 854 # Number of cycles fetch has spent blocked 818844SAli.Saidi@ARM.comsystem.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 828844SAli.Saidi@ARM.comsystem.cpu.fetch.PendingTrapStallCycles 590 # Number of stall cycles due to pending traps 838844SAli.Saidi@ARM.comsystem.cpu.fetch.CacheLines 2367 # Number of cache lines fetched 848844SAli.Saidi@ARM.comsystem.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed 858844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::samples 13505 # Number of instructions fetched each cycle (Total) 868844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::mean 1.232358 # Number of instructions fetched each cycle (Total) 878844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::stdev 2.611762 # Number of instructions fetched each cycle (Total) 886291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 898844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::0 10526 77.94% 77.94% # Number of instructions fetched each cycle (Total) 908844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::1 289 2.14% 80.08% # Number of instructions fetched each cycle (Total) 918844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::2 251 1.86% 81.94% # Number of instructions fetched each cycle (Total) 928844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::3 257 1.90% 83.84% # Number of instructions fetched each cycle (Total) 938844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::4 272 2.01% 85.86% # Number of instructions fetched each cycle (Total) 948844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::5 206 1.53% 87.38% # Number of instructions fetched each cycle (Total) 958844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::6 248 1.84% 89.22% # Number of instructions fetched each cycle (Total) 968844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::7 173 1.28% 90.50% # Number of instructions fetched each cycle (Total) 978844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::8 1283 9.50% 100.00% # Number of instructions fetched each cycle (Total) 986291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 996291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1006291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 1018844SAli.Saidi@ARM.comsystem.cpu.fetch.rateDist::total 13505 # Number of instructions fetched each cycle (Total) 1028844SAli.Saidi@ARM.comsystem.cpu.fetch.branchRate 0.115372 # Number of branch fetches per cycle 1038844SAli.Saidi@ARM.comsystem.cpu.fetch.rate 0.668340 # Number of inst fetches per cycle 1048844SAli.Saidi@ARM.comsystem.cpu.decode.IdleCycles 8546 # Number of cycles decode is idle 1058844SAli.Saidi@ARM.comsystem.cpu.decode.BlockedCycles 938 # Number of cycles decode is blocked 1068844SAli.Saidi@ARM.comsystem.cpu.decode.RunCycles 2784 # Number of cycles decode is running 1078844SAli.Saidi@ARM.comsystem.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking 1088844SAli.Saidi@ARM.comsystem.cpu.decode.SquashCycles 1175 # Number of cycles decode is squashing 1098844SAli.Saidi@ARM.comsystem.cpu.decode.BranchResolved 292 # Number of times decode resolved a branch 1108844SAli.Saidi@ARM.comsystem.cpu.decode.BranchMispred 96 # Number of times decode detected a branch misprediction 1118844SAli.Saidi@ARM.comsystem.cpu.decode.DecodedInsts 15310 # Number of instructions handled by decode 1128844SAli.Saidi@ARM.comsystem.cpu.decode.SquashedInsts 265 # Number of squashed instructions handled by decode 1138844SAli.Saidi@ARM.comsystem.cpu.rename.SquashCycles 1175 # Number of cycles rename is squashing 1148844SAli.Saidi@ARM.comsystem.cpu.rename.IdleCycles 8782 # Number of cycles rename is idle 1158844SAli.Saidi@ARM.comsystem.cpu.rename.BlockCycles 334 # Number of cycles rename is blocking 1168844SAli.Saidi@ARM.comsystem.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst 1178844SAli.Saidi@ARM.comsystem.cpu.rename.RunCycles 2587 # Number of cycles rename is running 1188844SAli.Saidi@ARM.comsystem.cpu.rename.UnblockCycles 270 # Number of cycles rename is unblocking 1198844SAli.Saidi@ARM.comsystem.cpu.rename.RenamedInsts 14488 # Number of instructions processed by rename 1208844SAli.Saidi@ARM.comsystem.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 1218844SAli.Saidi@ARM.comsystem.cpu.rename.LSQFullEvents 212 # Number of times rename has blocked due to LSQ full 1228844SAli.Saidi@ARM.comsystem.cpu.rename.RenamedOperands 10864 # Number of destination operands rename has renamed 1238844SAli.Saidi@ARM.comsystem.cpu.rename.RenameLookups 18125 # Number of register rename lookups that rename has made 1248844SAli.Saidi@ARM.comsystem.cpu.rename.int_rename_lookups 18108 # Number of integer rename lookups 1258428SN/Asystem.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 1268428SN/Asystem.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed 1278844SAli.Saidi@ARM.comsystem.cpu.rename.UndoneMaps 6281 # Number of HB maps that are undone due to squashing 1288428SN/Asystem.cpu.rename.serializingInsts 28 # count of serializing insts renamed 1298428SN/Asystem.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed 1308844SAli.Saidi@ARM.comsystem.cpu.rename.skidInsts 777 # count of insts added to the skid buffer 1318844SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedLoads 2616 # Number of loads inserted to the mem dependence unit. 1328844SAli.Saidi@ARM.comsystem.cpu.memDep0.insertedStores 1352 # Number of stores inserted to the mem dependence unit. 1338844SAli.Saidi@ARM.comsystem.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. 1348428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 1358844SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsAdded 12765 # Number of instructions added to the IQ (excludes non-spec) 1368844SAli.Saidi@ARM.comsystem.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ 1378844SAli.Saidi@ARM.comsystem.cpu.iq.iqInstsIssued 10522 # Number of instructions issued 1388844SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued 1398844SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedInstsExamined 6026 # Number of squashed instructions iterated over during squash; mainly for profiling 1408844SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedOperandsExamined 3602 # Number of squashed operands that are examined and possibly removed from graph 1418844SAli.Saidi@ARM.comsystem.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed 1428844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::samples 13505 # Number of insts issued each cycle 1438844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::mean 0.779119 # Number of insts issued each cycle 1448844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::stdev 1.404443 # Number of insts issued each cycle 1458428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1468844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::0 9165 67.86% 67.86% # Number of insts issued each cycle 1478844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::1 1484 10.99% 78.85% # Number of insts issued each cycle 1488844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::2 1164 8.62% 87.47% # Number of insts issued each cycle 1498844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::3 762 5.64% 93.11% # Number of insts issued each cycle 1508844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::4 469 3.47% 96.59% # Number of insts issued each cycle 1518844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::5 274 2.03% 98.62% # Number of insts issued each cycle 1528844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::6 142 1.05% 99.67% # Number of insts issued each cycle 1538844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::7 34 0.25% 99.92% # Number of insts issued each cycle 1548844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle 1558428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1568428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1578428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 1588844SAli.Saidi@ARM.comsystem.cpu.iq.issued_per_cycle::total 13505 # Number of insts issued each cycle 1598428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1608844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntAlu 10 8.93% 8.93% # attempts to use FU when none available 1618844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available 1628844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available 1638844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available 1648844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available 1658844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available 1668844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available 1678844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available 1688844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available 1698844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available 1708844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available 1718844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available 1728844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available 1738844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available 1748844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available 1758844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available 1768844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available 1778844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available 1788844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available 1798844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available 1808844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available 1818844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available 1828844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available 1838844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available 1848844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available 1858844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available 1868844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available 1878844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available 1888844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available 1898844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemRead 65 58.04% 66.96% # attempts to use FU when none available 1908844SAli.Saidi@ARM.comsystem.cpu.iq.fu_full::MemWrite 37 33.04% 100.00% # attempts to use FU when none available 1918428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 1928428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 1938241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 1948844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntAlu 7148 67.93% 67.95% # Type of FU issued 1958844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.96% # Type of FU issued 1968844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.96% # Type of FU issued 1978844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.98% # Type of FU issued 1988844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.98% # Type of FU issued 1998844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.98% # Type of FU issued 2008844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.98% # Type of FU issued 2018844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.98% # Type of FU issued 2028844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.98% # Type of FU issued 2038844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.98% # Type of FU issued 2048844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.98% # Type of FU issued 2058844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.98% # Type of FU issued 2068844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.98% # Type of FU issued 2078844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.98% # Type of FU issued 2088844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.98% # Type of FU issued 2098844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.98% # Type of FU issued 2108844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.98% # Type of FU issued 2118844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.98% # Type of FU issued 2128844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.98% # Type of FU issued 2138844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.98% # Type of FU issued 2148844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.98% # Type of FU issued 2158844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.98% # Type of FU issued 2168844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.98% # Type of FU issued 2178844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.98% # Type of FU issued 2188844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.98% # Type of FU issued 2198844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.98% # Type of FU issued 2208844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.98% # Type of FU issued 2218844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.98% # Type of FU issued 2228844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.98% # Type of FU issued 2238844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemRead 2225 21.15% 89.13% # Type of FU issued 2248844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::MemWrite 1144 10.87% 100.00% # Type of FU issued 2258241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2268241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2278844SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::total 10522 # Type of FU issued 2288844SAli.Saidi@ARM.comsystem.cpu.iq.rate 0.422536 # Inst issue rate 2298844SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_cnt 112 # FU busy when requested 2308844SAli.Saidi@ARM.comsystem.cpu.iq.fu_busy_rate 0.010644 # FU busy rate (busy events/executed inst) 2318844SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_reads 34684 # Number of integer instruction queue reads 2328844SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_writes 18825 # Number of integer instruction queue writes 2338844SAli.Saidi@ARM.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9477 # Number of integer instruction queue wakeup accesses 2348428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 2358428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 2368428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 2378844SAli.Saidi@ARM.comsystem.cpu.iq.int_alu_accesses 10621 # Number of integer alu accesses 2388428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 2398844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores 2408428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2418844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedLoads 1431 # Number of loads squashed 2428464SN/Asystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 2438844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 2448844SAli.Saidi@ARM.comsystem.cpu.iew.lsq.thread0.squashedStores 487 # Number of stores squashed 2458428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2468428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2478428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 2488428SN/Asystem.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 2498428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2508844SAli.Saidi@ARM.comsystem.cpu.iew.iewSquashCycles 1175 # Number of cycles IEW is squashing 2518844SAli.Saidi@ARM.comsystem.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking 2528844SAli.Saidi@ARM.comsystem.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking 2538844SAli.Saidi@ARM.comsystem.cpu.iew.iewDispatchedInsts 12870 # Number of instructions dispatched to IQ 2548844SAli.Saidi@ARM.comsystem.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch 2558844SAli.Saidi@ARM.comsystem.cpu.iew.iewDispLoadInsts 2616 # Number of dispatched load instructions 2568844SAli.Saidi@ARM.comsystem.cpu.iew.iewDispStoreInsts 1352 # Number of dispatched store instructions 2578844SAli.Saidi@ARM.comsystem.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 2588844SAli.Saidi@ARM.comsystem.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 2598428SN/Asystem.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 2608844SAli.Saidi@ARM.comsystem.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 2618844SAli.Saidi@ARM.comsystem.cpu.iew.predictedTakenIncorrect 166 # Number of branches that were predicted taken incorrectly 2628844SAli.Saidi@ARM.comsystem.cpu.iew.predictedNotTakenIncorrect 401 # Number of branches that were predicted not taken incorrectly 2638844SAli.Saidi@ARM.comsystem.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute 2648844SAli.Saidi@ARM.comsystem.cpu.iew.iewExecutedInsts 9878 # Number of executed instructions 2658844SAli.Saidi@ARM.comsystem.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed 2668844SAli.Saidi@ARM.comsystem.cpu.iew.iewExecSquashedInsts 644 # Number of squashed instructions skipped in execute 2678428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 2688844SAli.Saidi@ARM.comsystem.cpu.iew.exec_nop 79 # number of nop insts executed 2698844SAli.Saidi@ARM.comsystem.cpu.iew.exec_refs 3117 # number of memory reference insts executed 2708844SAli.Saidi@ARM.comsystem.cpu.iew.exec_branches 1605 # Number of branches executed 2718844SAli.Saidi@ARM.comsystem.cpu.iew.exec_stores 1108 # Number of stores executed 2728844SAli.Saidi@ARM.comsystem.cpu.iew.exec_rate 0.396675 # Inst execution rate 2738844SAli.Saidi@ARM.comsystem.cpu.iew.wb_sent 9634 # cumulative count of insts sent to commit 2748844SAli.Saidi@ARM.comsystem.cpu.iew.wb_count 9487 # cumulative count of insts written-back 2758844SAli.Saidi@ARM.comsystem.cpu.iew.wb_producers 4957 # num instructions producing a value 2768844SAli.Saidi@ARM.comsystem.cpu.iew.wb_consumers 6732 # num instructions consuming a value 2778428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2788844SAli.Saidi@ARM.comsystem.cpu.iew.wb_rate 0.380973 # insts written-back per cycle 2798844SAli.Saidi@ARM.comsystem.cpu.iew.wb_fanout 0.736334 # average fanout of values written-back 2808428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2818428SN/Asystem.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions 2828835SAli.Saidi@ARM.comsystem.cpu.commit.commitCommittedOps 6403 # The number of committed instructions 2838844SAli.Saidi@ARM.comsystem.cpu.commit.commitSquashedInsts 6436 # The number of squashed insts skipped by commit 2848428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 2858844SAli.Saidi@ARM.comsystem.cpu.commit.branchMispredicts 475 # The number of times a branch was mispredicted 2868844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::samples 12330 # Number of insts commited each cycle 2878844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::mean 0.519303 # Number of insts commited each cycle 2888844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::stdev 1.354208 # Number of insts commited each cycle 2898428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2908844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::0 9591 77.79% 77.79% # Number of insts commited each cycle 2918844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::1 1448 11.74% 89.53% # Number of insts commited each cycle 2928844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::2 489 3.97% 93.50% # Number of insts commited each cycle 2938844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::3 259 2.10% 95.60% # Number of insts commited each cycle 2948844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::4 152 1.23% 96.83% # Number of insts commited each cycle 2958844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::5 96 0.78% 97.61% # Number of insts commited each cycle 2968844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::6 104 0.84% 98.45% # Number of insts commited each cycle 2978844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::7 40 0.32% 98.78% # Number of insts commited each cycle 2988844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::8 151 1.22% 100.00% # Number of insts commited each cycle 2998428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 3008428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 3018428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 3028844SAli.Saidi@ARM.comsystem.cpu.commit.committed_per_cycle::total 12330 # Number of insts commited each cycle 3038835SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6403 # Number of instructions committed 3048835SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed 3058428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 3068428SN/Asystem.cpu.commit.refs 2050 # Number of memory references committed 3078428SN/Asystem.cpu.commit.loads 1185 # Number of loads committed 3088428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 3098428SN/Asystem.cpu.commit.branches 1051 # Number of branches committed 3108428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 3118428SN/Asystem.cpu.commit.int_insts 6321 # Number of committed integer instructions. 3128428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 3138844SAli.Saidi@ARM.comsystem.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached 3148428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 3158844SAli.Saidi@ARM.comsystem.cpu.rob.rob_reads 24667 # The number of ROB reads 3168844SAli.Saidi@ARM.comsystem.cpu.rob.rob_writes 26868 # The number of ROB writes 3178844SAli.Saidi@ARM.comsystem.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself 3188844SAli.Saidi@ARM.comsystem.cpu.idleCycles 11397 # Total number of cycles that the CPU has spent unscheduled due to idling 3198428SN/Asystem.cpu.committedInsts 6386 # Number of Instructions Simulated 3208835SAli.Saidi@ARM.comsystem.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated 3218428SN/Asystem.cpu.committedInsts_total 6386 # Number of Instructions Simulated 3228844SAli.Saidi@ARM.comsystem.cpu.cpi 3.899468 # CPI: Cycles Per Instruction 3238844SAli.Saidi@ARM.comsystem.cpu.cpi_total 3.899468 # CPI: Total CPI of All Threads 3248844SAli.Saidi@ARM.comsystem.cpu.ipc 0.256445 # IPC: Instructions Per Cycle 3258844SAli.Saidi@ARM.comsystem.cpu.ipc_total 0.256445 # IPC: Total IPC of All Threads 3268844SAli.Saidi@ARM.comsystem.cpu.int_regfile_reads 12526 # number of integer regfile reads 3278844SAli.Saidi@ARM.comsystem.cpu.int_regfile_writes 7116 # number of integer regfile writes 3288428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 3298428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 3308428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 3318428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 3328428SN/Asystem.cpu.icache.replacements 0 # number of replacements 3338844SAli.Saidi@ARM.comsystem.cpu.icache.tagsinuse 162.256588 # Cycle average of tags in use 3348844SAli.Saidi@ARM.comsystem.cpu.icache.total_refs 1909 # Total number of references to valid blocks. 3358844SAli.Saidi@ARM.comsystem.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. 3368844SAli.Saidi@ARM.comsystem.cpu.icache.avg_refs 6.060317 # Average number of references to valid blocks. 3378428SN/Asystem.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3388844SAli.Saidi@ARM.comsystem.cpu.icache.occ_blocks::cpu.inst 162.256588 # Average occupied blocks per requestor 3398844SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.079227 # Average percentage of cache occupancy 3408844SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.079227 # Average percentage of cache occupancy 3418844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits 3428844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits 3438844SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits 3448844SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits 3458844SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits 3468844SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 1909 # number of overall hits 3478844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses 3488844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses 3498844SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses 3508844SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses 3518844SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses 3528844SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 458 # number of overall misses 3538844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 16026500 # number of ReadReq miss cycles 3548844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_latency::total 16026500 # number of ReadReq miss cycles 3558844SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::cpu.inst 16026500 # number of demand (read+write) miss cycles 3568844SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_latency::total 16026500 # number of demand (read+write) miss cycles 3578844SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::cpu.inst 16026500 # number of overall miss cycles 3588844SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles 3598844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses) 3608844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses) 3618844SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses 3628844SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses 3638844SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses 3648844SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses 3658844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses 3669055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::total 0.193494 # miss rate for ReadReq accesses 3678844SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses 3689055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total 0.193494 # miss rate for demand accesses 3698844SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses 3709055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::total 0.193494 # miss rate for overall accesses 3718844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency 3729055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_miss_latency::total 34992.358079 # average ReadReq miss latency 3738844SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency 3749055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_miss_latency::total 34992.358079 # average overall miss latency 3758844SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency 3769055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_miss_latency::total 34992.358079 # average overall miss latency 3778428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3788428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3798428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3808428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3818983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3828983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3838428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3848428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3858844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits 3868844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits 3878844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits 3888844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits 3898844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits 3908844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits 3918844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses 3928844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses 3938844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses 3948844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses 3958844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses 3968844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses 3978844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles 3988844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles 3998844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles 4008844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles 4018844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles 4028844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles 4038844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses 4049055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.133080 # mshr miss rate for ReadReq accesses 4058844SAli.Saidi@ARM.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses 4069055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.133080 # mshr miss rate for demand accesses 4078844SAli.Saidi@ARM.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses 4089055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.133080 # mshr miss rate for overall accesses 4098844SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency 4109055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35344.444444 # average ReadReq mshr miss latency 4118844SAli.Saidi@ARM.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency 4129055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency 4138844SAli.Saidi@ARM.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency 4149055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency 4158428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 4168428SN/Asystem.cpu.dcache.replacements 0 # number of replacements 4178844SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use 4188844SAli.Saidi@ARM.comsystem.cpu.dcache.total_refs 2244 # Total number of references to valid blocks. 4198844SAli.Saidi@ARM.comsystem.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks. 4208844SAli.Saidi@ARM.comsystem.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks. 4218428SN/Asystem.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4228844SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor 4238844SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy 4248844SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy 4258844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1735 # number of ReadReq hits 4268844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 1735 # number of ReadReq hits 4278835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits 4288835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits 4298844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 2244 # number of demand (read+write) hits 4308844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 2244 # number of demand (read+write) hits 4318844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 2244 # number of overall hits 4328844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 2244 # number of overall hits 4338844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 144 # number of ReadReq misses 4348844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 144 # number of ReadReq misses 4358835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses 4368835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses 4378844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses 4388844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses 4398844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses 4408844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 500 # number of overall misses 4418844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 5240000 # number of ReadReq miss cycles 4428844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_latency::total 5240000 # number of ReadReq miss cycles 4438844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 12485500 # number of WriteReq miss cycles 4448844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_latency::total 12485500 # number of WriteReq miss cycles 4458844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::cpu.data 17725500 # number of demand (read+write) miss cycles 4468844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_latency::total 17725500 # number of demand (read+write) miss cycles 4478844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::cpu.data 17725500 # number of overall miss cycles 4488844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_latency::total 17725500 # number of overall miss cycles 4498844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1879 # number of ReadReq accesses(hits+misses) 4508844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses) 4518835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 4528835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 4538844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses 4548844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses 4558844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses 4568844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses 4578844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses 4589055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.076637 # miss rate for ReadReq accesses 4598835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses 4609055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses 4618844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses 4629055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_miss_rate::total 0.182216 # miss rate for demand accesses 4638844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses 4649055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_miss_rate::total 0.182216 # miss rate for overall accesses 4658844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency 4669055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 36388.888889 # average ReadReq miss latency 4678844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency 4689055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 35071.629213 # average WriteReq miss latency 4698844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency 4709055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_avg_miss_latency::total 35451 # average overall miss latency 4718844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency 4729055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_miss_latency::total 35451 # average overall miss latency 4738428SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4748428SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4758428SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4768428SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4778983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4788983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4798428SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4808428SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4818844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits 4828844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits 4838844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits 4848844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits 4858844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits 4868844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits 4878844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 324 # number of overall MSHR hits 4888844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_hits::total 324 # number of overall MSHR hits 4898844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses 4908844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses 4918844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 4928844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 4938844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses 4948844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses 4958844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses 4968844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses 4978844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3722000 # number of ReadReq MSHR miss cycles 4988844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles 4998844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles 5008844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles 5018844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles 5028844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles 5038844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles 5048844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles 5058844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses 5069055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055349 # mshr miss rate for ReadReq accesses 5078844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 5089055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 5098844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses 5109055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.064140 # mshr miss rate for demand accesses 5118844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses 5129055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.064140 # mshr miss rate for overall accesses 5138844SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency 5149055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35788.461538 # average ReadReq mshr miss latency 5158844SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency 5169055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35770.833333 # average WriteReq mshr miss latency 5178844SAli.Saidi@ARM.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency 5189055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency 5198844SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency 5209055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency 5218428SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 5228428SN/Asystem.cpu.l2cache.replacements 0 # number of replacements 5238844SAli.Saidi@ARM.comsystem.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use 5248428SN/Asystem.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 5258844SAli.Saidi@ARM.comsystem.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks. 5268844SAli.Saidi@ARM.comsystem.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks. 5278428SN/Asystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 5288844SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor 5298844SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_blocks::cpu.data 62.558495 # Average occupied blocks per requestor 5308844SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.004951 # Average percentage of cache occupancy 5318844SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::cpu.data 0.001909 # Average percentage of cache occupancy 5328844SAli.Saidi@ARM.comsystem.cpu.l2cache.occ_percent::total 0.006860 # Average percentage of cache occupancy 5338835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 5348835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 5358835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 5368835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 5378835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 5388835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 5398844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses 5408844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses 5418844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 418 # number of ReadReq misses 5428844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 5438844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 5448844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses 5458844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses 5468844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 490 # number of demand (read+write) misses 5478844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses 5488844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses 5498844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 490 # number of overall misses 5508844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10779500 # number of ReadReq miss cycles 5518844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 3600000 # number of ReadReq miss cycles 5528844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_latency::total 14379500 # number of ReadReq miss cycles 5538844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2488500 # number of ReadExReq miss cycles 5548844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2488500 # number of ReadExReq miss cycles 5558844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 10779500 # number of demand (read+write) miss cycles 5568844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 6088500 # number of demand (read+write) miss cycles 5578844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_latency::total 16868000 # number of demand (read+write) miss cycles 5588844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 10779500 # number of overall miss cycles 5598844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 6088500 # number of overall miss cycles 5608844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_latency::total 16868000 # number of overall miss cycles 5618844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) 5628844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) 5638844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 419 # number of ReadReq accesses(hits+misses) 5648844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 5658844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 5668844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses 5678844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses 5688844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses 5698844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses 5708844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses 5718844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses 5728844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses 5738835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 5749055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.997613 # miss rate for ReadReq accesses 5758835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 5769055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 5778844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses 5788835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 5799055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses 5808844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses 5818835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 5829055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses 5838844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency 5848844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency 5859055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_miss_latency::total 34400.717703 # average ReadReq miss latency 5868844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency 5879055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 34562.500000 # average ReadExReq miss latency 5888844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency 5898844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency 5909055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_miss_latency::total 34424.489796 # average overall miss latency 5918844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency 5928844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency 5939055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_miss_latency::total 34424.489796 # average overall miss latency 5948428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5958428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5968428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5978428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5988983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5998983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6008428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 6018428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 6028844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 6038844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses 6048844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses 6058844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 6068844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 6078844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 6088844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses 6098844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses 6108844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 6118844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses 6128844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_misses::total 490 # number of overall MSHR misses 6138844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9770500 # number of ReadReq MSHR miss cycles 6148844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3273500 # number of ReadReq MSHR miss cycles 6158844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 13044000 # number of ReadReq MSHR miss cycles 6168844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264000 # number of ReadExReq MSHR miss cycles 6178844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264000 # number of ReadExReq MSHR miss cycles 6188844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles 6198844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles 6208844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles 6218844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles 6228844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles 6238844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles 6248844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses 6258835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 6269055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997613 # mshr miss rate for ReadReq accesses 6278835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 6289055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 6298844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses 6308835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 6319055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses 6328844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses 6338835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 6349055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses 6358844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency 6368844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency 6379055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31205.741627 # average ReadReq mshr miss latency 6388844SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency 6399055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31444.444444 # average ReadExReq mshr miss latency 6408844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency 6418844SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency 6429055Ssaidi@eecs.umich.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency 6438844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency 6448844SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency 6459055Ssaidi@eecs.umich.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency 6468428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 6473096SN/A 6483096SN/A---------- End Simulation Statistics ---------- 649