stats.txt revision 8721
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 12004500 # Number of ticks simulated 5final_tick 12004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 38695 # Simulator instruction rate (inst/s) 8host_tick_rate 72731813 # Simulator tick rate (ticks/s) 9host_mem_usage 208040 # Number of bytes of host memory used 10host_seconds 0.17 # Real time elapsed on the host 11sim_insts 6386 # Number of instructions simulated 12system.physmem.bytes_read 31040 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 19904 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 0 # Number of bytes written to this memory 15system.physmem.num_reads 485 # Number of read requests responded to by this memory 16system.physmem.num_writes 0 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 2585697030 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 1658044900 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_total 2585697030 # Total bandwidth to/from this memory (bytes/s) 21system.cpu.dtb.fetch_hits 0 # ITB hits 22system.cpu.dtb.fetch_misses 0 # ITB misses 23system.cpu.dtb.fetch_acv 0 # ITB acv 24system.cpu.dtb.fetch_accesses 0 # ITB accesses 25system.cpu.dtb.read_hits 1860 # DTB read hits 26system.cpu.dtb.read_misses 44 # DTB read misses 27system.cpu.dtb.read_acv 0 # DTB read access violations 28system.cpu.dtb.read_accesses 1904 # DTB read accesses 29system.cpu.dtb.write_hits 1041 # DTB write hits 30system.cpu.dtb.write_misses 28 # DTB write misses 31system.cpu.dtb.write_acv 0 # DTB write access violations 32system.cpu.dtb.write_accesses 1069 # DTB write accesses 33system.cpu.dtb.data_hits 2901 # DTB hits 34system.cpu.dtb.data_misses 72 # DTB misses 35system.cpu.dtb.data_acv 0 # DTB access violations 36system.cpu.dtb.data_accesses 2973 # DTB accesses 37system.cpu.itb.fetch_hits 2039 # ITB hits 38system.cpu.itb.fetch_misses 29 # ITB misses 39system.cpu.itb.fetch_acv 0 # ITB acv 40system.cpu.itb.fetch_accesses 2068 # ITB accesses 41system.cpu.itb.read_hits 0 # DTB read hits 42system.cpu.itb.read_misses 0 # DTB read misses 43system.cpu.itb.read_acv 0 # DTB read access violations 44system.cpu.itb.read_accesses 0 # DTB read accesses 45system.cpu.itb.write_hits 0 # DTB write hits 46system.cpu.itb.write_misses 0 # DTB write misses 47system.cpu.itb.write_acv 0 # DTB write access violations 48system.cpu.itb.write_accesses 0 # DTB write accesses 49system.cpu.itb.data_hits 0 # DTB hits 50system.cpu.itb.data_misses 0 # DTB misses 51system.cpu.itb.data_acv 0 # DTB access violations 52system.cpu.itb.data_accesses 0 # DTB accesses 53system.cpu.workload.num_syscalls 17 # Number of system calls 54system.cpu.numCycles 24010 # number of cpu cycles simulated 55system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 56system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 57system.cpu.BPredUnit.lookups 2507 # Number of BP lookups 58system.cpu.BPredUnit.condPredicted 1457 # Number of conditional branches predicted 59system.cpu.BPredUnit.condIncorrect 459 # Number of conditional branches incorrect 60system.cpu.BPredUnit.BTBLookups 1937 # Number of BTB lookups 61system.cpu.BPredUnit.BTBHits 718 # Number of BTB hits 62system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 63system.cpu.BPredUnit.usedRAS 373 # Number of times the RAS was used to get a target. 64system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. 65system.cpu.fetch.icacheStallCycles 7150 # Number of cycles fetch is stalled on an Icache miss 66system.cpu.fetch.Insts 14456 # Number of instructions fetch has processed 67system.cpu.fetch.Branches 2507 # Number of branches that fetch encountered 68system.cpu.fetch.predictedBranches 1091 # Number of branches that fetch has predicted taken 69system.cpu.fetch.Cycles 2619 # Number of cycles fetch has run and was not squashing or blocked 70system.cpu.fetch.SquashCycles 1556 # Number of cycles fetch has spent squashing 71system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked 72system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 73system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps 74system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched 75system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed 76system.cpu.fetch.rateDist::samples 12592 # Number of instructions fetched each cycle (Total) 77system.cpu.fetch.rateDist::mean 1.148030 # Number of instructions fetched each cycle (Total) 78system.cpu.fetch.rateDist::stdev 2.530696 # Number of instructions fetched each cycle (Total) 79system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 80system.cpu.fetch.rateDist::0 9973 79.20% 79.20% # Number of instructions fetched each cycle (Total) 81system.cpu.fetch.rateDist::1 274 2.18% 81.38% # Number of instructions fetched each cycle (Total) 82system.cpu.fetch.rateDist::2 224 1.78% 83.16% # Number of instructions fetched each cycle (Total) 83system.cpu.fetch.rateDist::3 222 1.76% 84.92% # Number of instructions fetched each cycle (Total) 84system.cpu.fetch.rateDist::4 234 1.86% 86.78% # Number of instructions fetched each cycle (Total) 85system.cpu.fetch.rateDist::5 178 1.41% 88.19% # Number of instructions fetched each cycle (Total) 86system.cpu.fetch.rateDist::6 257 2.04% 90.23% # Number of instructions fetched each cycle (Total) 87system.cpu.fetch.rateDist::7 140 1.11% 91.34% # Number of instructions fetched each cycle (Total) 88system.cpu.fetch.rateDist::8 1090 8.66% 100.00% # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 91system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 92system.cpu.fetch.rateDist::total 12592 # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.branchRate 0.104415 # Number of branch fetches per cycle 94system.cpu.fetch.rate 0.602082 # Number of inst fetches per cycle 95system.cpu.decode.IdleCycles 7970 # Number of cycles decode is idle 96system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked 97system.cpu.decode.RunCycles 2449 # Number of cycles decode is running 98system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 99system.cpu.decode.SquashCycles 978 # Number of cycles decode is squashing 100system.cpu.decode.BranchResolved 214 # Number of times decode resolved a branch 101system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction 102system.cpu.decode.DecodedInsts 13378 # Number of instructions handled by decode 103system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode 104system.cpu.rename.SquashCycles 978 # Number of cycles rename is squashing 105system.cpu.rename.IdleCycles 8160 # Number of cycles rename is idle 106system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking 107system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst 108system.cpu.rename.RunCycles 2318 # Number of cycles rename is running 109system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking 110system.cpu.rename.RenamedInsts 12829 # Number of instructions processed by rename 111system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full 112system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full 113system.cpu.rename.RenamedOperands 9573 # Number of destination operands rename has renamed 114system.cpu.rename.RenameLookups 16037 # Number of register rename lookups that rename has made 115system.cpu.rename.int_rename_lookups 16020 # Number of integer rename lookups 116system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 117system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed 118system.cpu.rename.UndoneMaps 4990 # Number of HB maps that are undone due to squashing 119system.cpu.rename.serializingInsts 28 # count of serializing insts renamed 120system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed 121system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer 122system.cpu.memDep0.insertedLoads 2391 # Number of loads inserted to the mem dependence unit. 123system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit. 124system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. 125system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 126system.cpu.iq.iqInstsAdded 11558 # Number of instructions added to the IQ (excludes non-spec) 127system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ 128system.cpu.iq.iqInstsIssued 9757 # Number of instructions issued 129system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued 130system.cpu.iq.iqSquashedInstsExamined 4883 # Number of squashed instructions iterated over during squash; mainly for profiling 131system.cpu.iq.iqSquashedOperandsExamined 2853 # Number of squashed operands that are examined and possibly removed from graph 132system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed 133system.cpu.iq.issued_per_cycle::samples 12592 # Number of insts issued each cycle 134system.cpu.iq.issued_per_cycle::mean 0.774857 # Number of insts issued each cycle 135system.cpu.iq.issued_per_cycle::stdev 1.395692 # Number of insts issued each cycle 136system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 137system.cpu.iq.issued_per_cycle::0 8510 67.58% 67.58% # Number of insts issued each cycle 138system.cpu.iq.issued_per_cycle::1 1462 11.61% 79.19% # Number of insts issued each cycle 139system.cpu.iq.issued_per_cycle::2 1072 8.51% 87.71% # Number of insts issued each cycle 140system.cpu.iq.issued_per_cycle::3 685 5.44% 93.15% # Number of insts issued each cycle 141system.cpu.iq.issued_per_cycle::4 440 3.49% 96.64% # Number of insts issued each cycle 142system.cpu.iq.issued_per_cycle::5 254 2.02% 98.66% # Number of insts issued each cycle 143system.cpu.iq.issued_per_cycle::6 128 1.02% 99.67% # Number of insts issued each cycle 144system.cpu.iq.issued_per_cycle::7 30 0.24% 99.91% # Number of insts issued each cycle 145system.cpu.iq.issued_per_cycle::8 11 0.09% 100.00% # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 148system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::total 12592 # Number of insts issued each cycle 150system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 151system.cpu.iq.fu_full::IntAlu 13 12.26% 12.26% # attempts to use FU when none available 152system.cpu.iq.fu_full::IntMult 0 0.00% 12.26% # attempts to use FU when none available 153system.cpu.iq.fu_full::IntDiv 0 0.00% 12.26% # attempts to use FU when none available 154system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.26% # attempts to use FU when none available 155system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.26% # attempts to use FU when none available 156system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.26% # attempts to use FU when none available 157system.cpu.iq.fu_full::FloatMult 0 0.00% 12.26% # attempts to use FU when none available 158system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.26% # attempts to use FU when none available 159system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.26% # attempts to use FU when none available 160system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.26% # attempts to use FU when none available 161system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.26% # attempts to use FU when none available 162system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.26% # attempts to use FU when none available 163system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.26% # attempts to use FU when none available 164system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.26% # attempts to use FU when none available 165system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.26% # attempts to use FU when none available 166system.cpu.iq.fu_full::SimdMult 0 0.00% 12.26% # attempts to use FU when none available 167system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.26% # attempts to use FU when none available 168system.cpu.iq.fu_full::SimdShift 0 0.00% 12.26% # attempts to use FU when none available 169system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.26% # attempts to use FU when none available 170system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.26% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.26% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.26% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.26% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.26% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.26% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.26% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.26% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.26% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.26% # attempts to use FU when none available 180system.cpu.iq.fu_full::MemRead 54 50.94% 63.21% # attempts to use FU when none available 181system.cpu.iq.fu_full::MemWrite 39 36.79% 100.00% # attempts to use FU when none available 182system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 183system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 184system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 185system.cpu.iq.FU_type_0::IntAlu 6575 67.39% 67.41% # Type of FU issued 186system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued 187system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued 188system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued 189system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued 190system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued 191system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued 192system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued 193system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued 194system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued 195system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued 196system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued 197system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued 198system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued 199system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued 200system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued 201system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued 202system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued 203system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued 204system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued 214system.cpu.iq.FU_type_0::MemRead 2074 21.26% 88.70% # Type of FU issued 215system.cpu.iq.FU_type_0::MemWrite 1103 11.30% 100.00% # Type of FU issued 216system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 217system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 218system.cpu.iq.FU_type_0::total 9757 # Type of FU issued 219system.cpu.iq.rate 0.406372 # Inst issue rate 220system.cpu.iq.fu_busy_cnt 106 # FU busy when requested 221system.cpu.iq.fu_busy_rate 0.010864 # FU busy rate (busy events/executed inst) 222system.cpu.iq.int_inst_queue_reads 32238 # Number of integer instruction queue reads 223system.cpu.iq.int_inst_queue_writes 16474 # Number of integer instruction queue writes 224system.cpu.iq.int_inst_queue_wakeup_accesses 8982 # Number of integer instruction queue wakeup accesses 225system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 226system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 227system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 228system.cpu.iq.int_alu_accesses 9850 # Number of integer alu accesses 229system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 230system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores 231system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 232system.cpu.iew.lsq.thread0.squashedLoads 1206 # Number of loads squashed 233system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 234system.cpu.iew.lsq.thread0.memOrderViolation 17 # Number of memory ordering violations 235system.cpu.iew.lsq.thread0.squashedStores 406 # Number of stores squashed 236system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 237system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 238system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 239system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 240system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 241system.cpu.iew.iewSquashCycles 978 # Number of cycles IEW is squashing 242system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking 243system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking 244system.cpu.iew.iewDispatchedInsts 11665 # Number of instructions dispatched to IQ 245system.cpu.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch 246system.cpu.iew.iewDispLoadInsts 2391 # Number of dispatched load instructions 247system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions 248system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 249system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall 250system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 251system.cpu.iew.memOrderViolationEvents 17 # Number of memory order violations 252system.cpu.iew.predictedTakenIncorrect 120 # Number of branches that were predicted taken incorrectly 253system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly 254system.cpu.iew.branchMispredicts 447 # Number of branch mispredicts detected at execute 255system.cpu.iew.iewExecutedInsts 9313 # Number of executed instructions 256system.cpu.iew.iewExecLoadInsts 1914 # Number of load instructions executed 257system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute 258system.cpu.iew.exec_swp 0 # number of swp insts executed 259system.cpu.iew.exec_nop 80 # number of nop insts executed 260system.cpu.iew.exec_refs 2985 # number of memory reference insts executed 261system.cpu.iew.exec_branches 1504 # Number of branches executed 262system.cpu.iew.exec_stores 1071 # Number of stores executed 263system.cpu.iew.exec_rate 0.387880 # Inst execution rate 264system.cpu.iew.wb_sent 9119 # cumulative count of insts sent to commit 265system.cpu.iew.wb_count 8992 # cumulative count of insts written-back 266system.cpu.iew.wb_producers 4719 # num instructions producing a value 267system.cpu.iew.wb_consumers 6404 # num instructions consuming a value 268system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 269system.cpu.iew.wb_rate 0.374511 # insts written-back per cycle 270system.cpu.iew.wb_fanout 0.736883 # average fanout of values written-back 271system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 272system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions 273system.cpu.commit.commitSquashedInsts 5259 # The number of squashed insts skipped by commit 274system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 275system.cpu.commit.branchMispredicts 381 # The number of times a branch was mispredicted 276system.cpu.commit.committed_per_cycle::samples 11614 # Number of insts commited each cycle 277system.cpu.commit.committed_per_cycle::mean 0.551317 # Number of insts commited each cycle 278system.cpu.commit.committed_per_cycle::stdev 1.413084 # Number of insts commited each cycle 279system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 280system.cpu.commit.committed_per_cycle::0 8938 76.96% 76.96% # Number of insts commited each cycle 281system.cpu.commit.committed_per_cycle::1 1410 12.14% 89.10% # Number of insts commited each cycle 282system.cpu.commit.committed_per_cycle::2 462 3.98% 93.08% # Number of insts commited each cycle 283system.cpu.commit.committed_per_cycle::3 240 2.07% 95.14% # Number of insts commited each cycle 284system.cpu.commit.committed_per_cycle::4 159 1.37% 96.51% # Number of insts commited each cycle 285system.cpu.commit.committed_per_cycle::5 87 0.75% 97.26% # Number of insts commited each cycle 286system.cpu.commit.committed_per_cycle::6 110 0.95% 98.21% # Number of insts commited each cycle 287system.cpu.commit.committed_per_cycle::7 46 0.40% 98.61% # Number of insts commited each cycle 288system.cpu.commit.committed_per_cycle::8 162 1.39% 100.00% # Number of insts commited each cycle 289system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 290system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 291system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 292system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle 293system.cpu.commit.count 6403 # Number of instructions committed 294system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 295system.cpu.commit.refs 2050 # Number of memory references committed 296system.cpu.commit.loads 1185 # Number of loads committed 297system.cpu.commit.membars 0 # Number of memory barriers committed 298system.cpu.commit.branches 1051 # Number of branches committed 299system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 300system.cpu.commit.int_insts 6321 # Number of committed integer instructions. 301system.cpu.commit.function_calls 127 # Number of function calls committed. 302system.cpu.commit.bw_lim_events 162 # number cycles where commit BW limit reached 303system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 304system.cpu.rob.rob_reads 22763 # The number of ROB reads 305system.cpu.rob.rob_writes 24313 # The number of ROB writes 306system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself 307system.cpu.idleCycles 11418 # Total number of cycles that the CPU has spent unscheduled due to idling 308system.cpu.committedInsts 6386 # Number of Instructions Simulated 309system.cpu.committedInsts_total 6386 # Number of Instructions Simulated 310system.cpu.cpi 3.759787 # CPI: Cycles Per Instruction 311system.cpu.cpi_total 3.759787 # CPI: Total CPI of All Threads 312system.cpu.ipc 0.265973 # IPC: Instructions Per Cycle 313system.cpu.ipc_total 0.265973 # IPC: Total IPC of All Threads 314system.cpu.int_regfile_reads 11830 # number of integer regfile reads 315system.cpu.int_regfile_writes 6732 # number of integer regfile writes 316system.cpu.fp_regfile_reads 8 # number of floating regfile reads 317system.cpu.fp_regfile_writes 2 # number of floating regfile writes 318system.cpu.misc_regfile_reads 1 # number of misc regfile reads 319system.cpu.misc_regfile_writes 1 # number of misc regfile writes 320system.cpu.icache.replacements 0 # number of replacements 321system.cpu.icache.tagsinuse 160.112304 # Cycle average of tags in use 322system.cpu.icache.total_refs 1606 # Total number of references to valid blocks. 323system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks. 324system.cpu.icache.avg_refs 5.147436 # Average number of references to valid blocks. 325system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 326system.cpu.icache.occ_blocks::0 160.112304 # Average occupied blocks per context 327system.cpu.icache.occ_percent::0 0.078180 # Average percentage of cache occupancy 328system.cpu.icache.ReadReq_hits 1606 # number of ReadReq hits 329system.cpu.icache.demand_hits 1606 # number of demand (read+write) hits 330system.cpu.icache.overall_hits 1606 # number of overall hits 331system.cpu.icache.ReadReq_misses 433 # number of ReadReq misses 332system.cpu.icache.demand_misses 433 # number of demand (read+write) misses 333system.cpu.icache.overall_misses 433 # number of overall misses 334system.cpu.icache.ReadReq_miss_latency 15431000 # number of ReadReq miss cycles 335system.cpu.icache.demand_miss_latency 15431000 # number of demand (read+write) miss cycles 336system.cpu.icache.overall_miss_latency 15431000 # number of overall miss cycles 337system.cpu.icache.ReadReq_accesses 2039 # number of ReadReq accesses(hits+misses) 338system.cpu.icache.demand_accesses 2039 # number of demand (read+write) accesses 339system.cpu.icache.overall_accesses 2039 # number of overall (read+write) accesses 340system.cpu.icache.ReadReq_miss_rate 0.212359 # miss rate for ReadReq accesses 341system.cpu.icache.demand_miss_rate 0.212359 # miss rate for demand accesses 342system.cpu.icache.overall_miss_rate 0.212359 # miss rate for overall accesses 343system.cpu.icache.ReadReq_avg_miss_latency 35637.413395 # average ReadReq miss latency 344system.cpu.icache.demand_avg_miss_latency 35637.413395 # average overall miss latency 345system.cpu.icache.overall_avg_miss_latency 35637.413395 # average overall miss latency 346system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 347system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 348system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 351system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 352system.cpu.icache.fast_writes 0 # number of fast writes performed 353system.cpu.icache.cache_copies 0 # number of cache copies performed 354system.cpu.icache.writebacks 0 # number of writebacks 355system.cpu.icache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits 356system.cpu.icache.demand_mshr_hits 121 # number of demand (read+write) MSHR hits 357system.cpu.icache.overall_mshr_hits 121 # number of overall MSHR hits 358system.cpu.icache.ReadReq_mshr_misses 312 # number of ReadReq MSHR misses 359system.cpu.icache.demand_mshr_misses 312 # number of demand (read+write) MSHR misses 360system.cpu.icache.overall_mshr_misses 312 # number of overall MSHR misses 361system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 362system.cpu.icache.ReadReq_mshr_miss_latency 11021000 # number of ReadReq MSHR miss cycles 363system.cpu.icache.demand_mshr_miss_latency 11021000 # number of demand (read+write) MSHR miss cycles 364system.cpu.icache.overall_mshr_miss_latency 11021000 # number of overall MSHR miss cycles 365system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 366system.cpu.icache.ReadReq_mshr_miss_rate 0.153016 # mshr miss rate for ReadReq accesses 367system.cpu.icache.demand_mshr_miss_rate 0.153016 # mshr miss rate for demand accesses 368system.cpu.icache.overall_mshr_miss_rate 0.153016 # mshr miss rate for overall accesses 369system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.717949 # average ReadReq mshr miss latency 370system.cpu.icache.demand_avg_mshr_miss_latency 35323.717949 # average overall mshr miss latency 371system.cpu.icache.overall_avg_mshr_miss_latency 35323.717949 # average overall mshr miss latency 372system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 373system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 374system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 375system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 376system.cpu.dcache.replacements 0 # number of replacements 377system.cpu.dcache.tagsinuse 109.290272 # Cycle average of tags in use 378system.cpu.dcache.total_refs 2154 # Total number of references to valid blocks. 379system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. 380system.cpu.dcache.avg_refs 12.379310 # Average number of references to valid blocks. 381system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 382system.cpu.dcache.occ_blocks::0 109.290272 # Average occupied blocks per context 383system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy 384system.cpu.dcache.ReadReq_hits 1645 # number of ReadReq hits 385system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits 386system.cpu.dcache.demand_hits 2154 # number of demand (read+write) hits 387system.cpu.dcache.overall_hits 2154 # number of overall hits 388system.cpu.dcache.ReadReq_misses 154 # number of ReadReq misses 389system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses 390system.cpu.dcache.demand_misses 510 # number of demand (read+write) misses 391system.cpu.dcache.overall_misses 510 # number of overall misses 392system.cpu.dcache.ReadReq_miss_latency 5497500 # number of ReadReq miss cycles 393system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles 394system.cpu.dcache.demand_miss_latency 17965000 # number of demand (read+write) miss cycles 395system.cpu.dcache.overall_miss_latency 17965000 # number of overall miss cycles 396system.cpu.dcache.ReadReq_accesses 1799 # number of ReadReq accesses(hits+misses) 397system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) 398system.cpu.dcache.demand_accesses 2664 # number of demand (read+write) accesses 399system.cpu.dcache.overall_accesses 2664 # number of overall (read+write) accesses 400system.cpu.dcache.ReadReq_miss_rate 0.085603 # miss rate for ReadReq accesses 401system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses 402system.cpu.dcache.demand_miss_rate 0.191441 # miss rate for demand accesses 403system.cpu.dcache.overall_miss_rate 0.191441 # miss rate for overall accesses 404system.cpu.dcache.ReadReq_avg_miss_latency 35698.051948 # average ReadReq miss latency 405system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency 406system.cpu.dcache.demand_avg_miss_latency 35225.490196 # average overall miss latency 407system.cpu.dcache.overall_avg_miss_latency 35225.490196 # average overall miss latency 408system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 409system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 410system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 411system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 412system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 413system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 414system.cpu.dcache.fast_writes 0 # number of fast writes performed 415system.cpu.dcache.cache_copies 0 # number of cache copies performed 416system.cpu.dcache.writebacks 0 # number of writebacks 417system.cpu.dcache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits 418system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits 419system.cpu.dcache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits 420system.cpu.dcache.overall_mshr_hits 336 # number of overall MSHR hits 421system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses 422system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses 423system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses 424system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses 425system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 426system.cpu.dcache.ReadReq_mshr_miss_latency 3654500 # number of ReadReq MSHR miss cycles 427system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 # number of WriteReq MSHR miss cycles 428system.cpu.dcache.demand_mshr_miss_latency 6266000 # number of demand (read+write) MSHR miss cycles 429system.cpu.dcache.overall_mshr_miss_latency 6266000 # number of overall MSHR miss cycles 430system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 431system.cpu.dcache.ReadReq_mshr_miss_rate 0.056142 # mshr miss rate for ReadReq accesses 432system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses 433system.cpu.dcache.demand_mshr_miss_rate 0.065315 # mshr miss rate for demand accesses 434system.cpu.dcache.overall_mshr_miss_rate 0.065315 # mshr miss rate for overall accesses 435system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36183.168317 # average ReadReq mshr miss latency 436system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency 437system.cpu.dcache.demand_avg_mshr_miss_latency 36011.494253 # average overall mshr miss latency 438system.cpu.dcache.overall_avg_mshr_miss_latency 36011.494253 # average overall mshr miss latency 439system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 440system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 441system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 442system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 443system.cpu.l2cache.replacements 0 # number of replacements 444system.cpu.l2cache.tagsinuse 221.643066 # Cycle average of tags in use 445system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. 446system.cpu.l2cache.sampled_refs 412 # Sample count of references to valid blocks. 447system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. 448system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 449system.cpu.l2cache.occ_blocks::0 221.643066 # Average occupied blocks per context 450system.cpu.l2cache.occ_percent::0 0.006764 # Average percentage of cache occupancy 451system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits 452system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits 453system.cpu.l2cache.overall_hits 1 # number of overall hits 454system.cpu.l2cache.ReadReq_misses 412 # number of ReadReq misses 455system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses 456system.cpu.l2cache.demand_misses 485 # number of demand (read+write) misses 457system.cpu.l2cache.overall_misses 485 # number of overall misses 458system.cpu.l2cache.ReadReq_miss_latency 14163000 # number of ReadReq miss cycles 459system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles 460system.cpu.l2cache.demand_miss_latency 16676500 # number of demand (read+write) miss cycles 461system.cpu.l2cache.overall_miss_latency 16676500 # number of overall miss cycles 462system.cpu.l2cache.ReadReq_accesses 413 # number of ReadReq accesses(hits+misses) 463system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) 464system.cpu.l2cache.demand_accesses 486 # number of demand (read+write) accesses 465system.cpu.l2cache.overall_accesses 486 # number of overall (read+write) accesses 466system.cpu.l2cache.ReadReq_miss_rate 0.997579 # miss rate for ReadReq accesses 467system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses 468system.cpu.l2cache.demand_miss_rate 0.997942 # miss rate for demand accesses 469system.cpu.l2cache.overall_miss_rate 0.997942 # miss rate for overall accesses 470system.cpu.l2cache.ReadReq_avg_miss_latency 34376.213592 # average ReadReq miss latency 471system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency 472system.cpu.l2cache.demand_avg_miss_latency 34384.536082 # average overall miss latency 473system.cpu.l2cache.overall_avg_miss_latency 34384.536082 # average overall miss latency 474system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 475system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 476system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 477system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 478system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 479system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 480system.cpu.l2cache.fast_writes 0 # number of fast writes performed 481system.cpu.l2cache.cache_copies 0 # number of cache copies performed 482system.cpu.l2cache.writebacks 0 # number of writebacks 483system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 484system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits 485system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses 486system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses 487system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses 488system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses 489system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 490system.cpu.l2cache.ReadReq_mshr_miss_latency 12850000 # number of ReadReq MSHR miss cycles 491system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles 492system.cpu.l2cache.demand_mshr_miss_latency 15136000 # number of demand (read+write) MSHR miss cycles 493system.cpu.l2cache.overall_mshr_miss_latency 15136000 # number of overall MSHR miss cycles 494system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 495system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997579 # mshr miss rate for ReadReq accesses 496system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses 497system.cpu.l2cache.demand_mshr_miss_rate 0.997942 # mshr miss rate for demand accesses 498system.cpu.l2cache.overall_mshr_miss_rate 0.997942 # mshr miss rate for overall accesses 499system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.320388 # average ReadReq mshr miss latency 500system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency 501system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency 502system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency 503system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 504system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated 505system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 506system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 507 508---------- End Simulation Statistics ---------- 509