stats.txt revision 11606
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 310726Sandreas.hansson@arm.comsim_seconds 0.000022 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 22248000 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 22248000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 114507 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 114481 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 398824007 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 254412 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 0.06 # Real time elapsed on the host 1211390Ssteve.reinhardt@amd.comsim_insts 6385 # Number of instructions simulated 1311390Ssteve.reinhardt@amd.comsim_ops 6385 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 1711440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory 1811390Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 1911440SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 31040 # Number of bytes read from this memory 2011440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory 2111440SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory 2211440SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory 2311390Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory 2411440SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 485 # Number of read requests responded to by this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.inst 897518878 # Total read bandwidth from this memory (bytes/s) 2611606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.data 497662711 # Total read bandwidth from this memory (bytes/s) 2711606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 1395181589 # Total read bandwidth from this memory (bytes/s) 2811606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu.inst 897518878 # Instruction read bandwidth from this memory (bytes/s) 2911606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 897518878 # Instruction read bandwidth from this memory (bytes/s) 3011606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.inst 897518878 # Total bandwidth to/from this memory (bytes/s) 3111606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.data 497662711 # Total bandwidth to/from this memory (bytes/s) 3211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 1395181589 # Total bandwidth to/from this memory (bytes/s) 3311440SCurtis.Dunham@arm.comsystem.physmem.readReqs 485 # Number of read requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511440SCurtis.Dunham@arm.comsystem.physmem.readBursts 485 # Number of DRAM read bursts, including those serviced by the write queue 369978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711440SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 31040 # Total number of bytes read from DRAM 389978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 399978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011440SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 31040 # Total read bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 429978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 439978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 449978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 69 # Per bank write bursts 4611103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::1 32 # Per bank write bursts 4711440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 33 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 47 # Per bank write bursts 4911390Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::4 42 # Per bank write bursts 5010352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 20 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 1 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 3 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 0 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 1 # Per bank write bursts 5510726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 22 # Per bank write bursts 5610352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 25 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 14 # Per bank write bursts 5811103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::13 118 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 45 # Per bank write bursts 6011390Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::15 13 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 779978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 789978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911606Sandreas.sandberg@arm.comsystem.physmem.totGap 22109000 # Total gap between requests 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611440SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 485 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411390Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see 9511606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see 9611606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see 9711440SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 9811103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 999322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011390Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::samples 76 # Bytes accessed per row activation 19111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::mean 352.842105 # Bytes accessed per row activation 19211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::gmean 230.159600 # Bytes accessed per row activation 19311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::stdev 321.021248 # Bytes accessed per row activation 19411390Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::0-127 18 23.68% 23.68% # Bytes accessed per row activation 19511440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 19 25.00% 48.68% # Bytes accessed per row activation 19611606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::256-383 9 11.84% 60.53% # Bytes accessed per row activation 19711606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::384-511 11 14.47% 75.00% # Bytes accessed per row activation 19811606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::512-639 6 7.89% 82.89% # Bytes accessed per row activation 19911606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::640-767 1 1.32% 84.21% # Bytes accessed per row activation 20011440SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 2 2.63% 86.84% # Bytes accessed per row activation 20111390Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::1024-1151 10 13.16% 100.00% # Bytes accessed per row activation 20211390Ssteve.reinhardt@amd.comsystem.physmem.bytesPerActivate::total 76 # Bytes accessed per row activation 20311606Sandreas.sandberg@arm.comsystem.physmem.totQLat 4498250 # Total ticks spent queuing 20411606Sandreas.sandberg@arm.comsystem.physmem.totMemAccLat 13592000 # Total ticks spent from burst creation until serviced by the DRAM 20511440SCurtis.Dunham@arm.comsystem.physmem.totBusLat 2425000 # Total ticks spent in databus transfers 20611606Sandreas.sandberg@arm.comsystem.physmem.avgQLat 9274.74 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20811606Sandreas.sandberg@arm.comsystem.physmem.avgMemAccLat 28024.74 # Average memory access latency per DRAM burst 20911606Sandreas.sandberg@arm.comsystem.physmem.avgRdBW 1395.18 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21111606Sandreas.sandberg@arm.comsystem.physmem.avgRdBWSys 1395.18 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21411606Sandreas.sandberg@arm.comsystem.physmem.busUtil 10.90 # Data bus utilization in percentage 21511606Sandreas.sandberg@arm.comsystem.physmem.busUtilRead 10.90 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21711606Sandreas.sandberg@arm.comsystem.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21911440SCurtis.Dunham@arm.comsystem.physmem.readRowHits 394 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22111440SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 81.24 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22311606Sandreas.sandberg@arm.comsystem.physmem.avgGap 45585.57 # Average gap between requests 22411440SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 81.24 # Row buffer hit rate, read and write combined 22511103Snilay@cs.wisc.edusystem.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) 22611103Snilay@cs.wisc.edusystem.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) 22711606Sandreas.sandberg@arm.comsystem.physmem_0.readEnergy 1645800 # Energy for read commands per rank (pJ) 22810628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 23010726Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) 23110628Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) 23211606Sandreas.sandberg@arm.comsystem.physmem_0.totalEnergy 13790805 # Total energy per rank (pJ) 23311606Sandreas.sandberg@arm.comsystem.physmem_0.averagePower 871.044055 # Core power per rank (mW) 23411606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states 23510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 23610628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23710726Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states 23810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23911390Ssteve.reinhardt@amd.comsystem.physmem_1.actEnergy 294840 # Energy for activate commands per rank (pJ) 24011390Ssteve.reinhardt@amd.comsystem.physmem_1.preEnergy 160875 # Energy for precharge commands per rank (pJ) 24111606Sandreas.sandberg@arm.comsystem.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) 24210628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24310628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24411606Sandreas.sandberg@arm.comsystem.physmem_1.actBackEnergy 10074465 # Energy for active background per rank (pJ) 24511606Sandreas.sandberg@arm.comsystem.physmem_1.preBackEnergy 662250 # Energy for precharge background per rank (pJ) 24611606Sandreas.sandberg@arm.comsystem.physmem_1.totalEnergy 13465350 # Total energy per rank (pJ) 24711606Sandreas.sandberg@arm.comsystem.physmem_1.averagePower 850.487920 # Core power per rank (mW) 24811606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::IDLE 1034500 # Time in different power states 24910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 25010628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25111606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::ACT 14291750 # Time in different power states 25210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25311606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 25411606Sandreas.sandberg@arm.comsystem.cpu.branchPred.lookups 2853 # Number of BP lookups 25511606Sandreas.sandberg@arm.comsystem.cpu.branchPred.condPredicted 1680 # Number of conditional branches predicted 25611440SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 481 # Number of conditional branches incorrect 25711606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBLookups 2201 # Number of BTB lookups 25811440SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 713 # Number of BTB hits 2599481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26011606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHitPct 32.394366 # BTB Hit Percentage 26111440SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. 26211440SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 41 # Number of incorrect RAS predictions. 26311440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups. 26411440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 25 # Number of indirect target hits. 26511440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 436 # Number of indirect misses. 26611440SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. 26710628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2688428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2698428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2708428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2718428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 27211440SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 2261 # DTB read hits 27311440SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 48 # DTB read misses 2748428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 27511440SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 2309 # DTB read accesses 27611440SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 1039 # DTB write hits 27711103Snilay@cs.wisc.edusystem.cpu.dtb.write_misses 28 # DTB write misses 2788428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 27911440SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 1067 # DTB write accesses 28011440SCurtis.Dunham@arm.comsystem.cpu.dtb.data_hits 3300 # DTB hits 28111440SCurtis.Dunham@arm.comsystem.cpu.dtb.data_misses 76 # DTB misses 2828428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 28311440SCurtis.Dunham@arm.comsystem.cpu.dtb.data_accesses 3376 # DTB accesses 28411606Sandreas.sandberg@arm.comsystem.cpu.itb.fetch_hits 2294 # ITB hits 28511440SCurtis.Dunham@arm.comsystem.cpu.itb.fetch_misses 27 # ITB misses 2868428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 28711606Sandreas.sandberg@arm.comsystem.cpu.itb.fetch_accesses 2321 # ITB accesses 2888428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2898428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2908428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2918428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2928428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2938428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2948428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2958428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2968428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2978428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2988428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2998428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 3008428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 30111606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 22248000 # Cumulative time (in ticks) in various power states 30211606Sandreas.sandberg@arm.comsystem.cpu.numCycles 44497 # number of cpu cycles simulated 3038428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3048428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 30511606Sandreas.sandberg@arm.comsystem.cpu.fetch.icacheStallCycles 8475 # Number of cycles fetch is stalled on an Icache miss 30611606Sandreas.sandberg@arm.comsystem.cpu.fetch.Insts 16557 # Number of instructions fetch has processed 30711606Sandreas.sandberg@arm.comsystem.cpu.fetch.Branches 2853 # Number of branches that fetch encountered 30811440SCurtis.Dunham@arm.comsystem.cpu.fetch.predictedBranches 1180 # Number of branches that fetch has predicted taken 30911606Sandreas.sandberg@arm.comsystem.cpu.fetch.Cycles 5121 # Number of cycles fetch has run and was not squashing or blocked 31011440SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 1044 # Number of cycles fetch has spent squashing 31111440SCurtis.Dunham@arm.comsystem.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 31211606Sandreas.sandberg@arm.comsystem.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps 31311606Sandreas.sandberg@arm.comsystem.cpu.fetch.CacheLines 2294 # Number of cache lines fetched 31411440SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheSquashes 333 # Number of outstanding Icache misses that were squashed 31511606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::samples 14796 # Number of instructions fetched each cycle (Total) 31611606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::mean 1.119019 # Number of instructions fetched each cycle (Total) 31711606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::stdev 2.502117 # Number of instructions fetched each cycle (Total) 3186291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 31911606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::0 11808 79.81% 79.81% # Number of instructions fetched each cycle (Total) 32011606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::1 299 2.02% 81.83% # Number of instructions fetched each cycle (Total) 32111606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::2 232 1.57% 83.39% # Number of instructions fetched each cycle (Total) 32211606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::3 257 1.74% 85.13% # Number of instructions fetched each cycle (Total) 32311606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::4 292 1.97% 87.10% # Number of instructions fetched each cycle (Total) 32411606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::5 233 1.57% 88.68% # Number of instructions fetched each cycle (Total) 32511606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::6 283 1.91% 90.59% # Number of instructions fetched each cycle (Total) 32611606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::7 144 0.97% 91.57% # Number of instructions fetched each cycle (Total) 32711606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::8 1248 8.43% 100.00% # Number of instructions fetched each cycle (Total) 3286291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3296291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3306291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 33111606Sandreas.sandberg@arm.comsystem.cpu.fetch.rateDist::total 14796 # Number of instructions fetched each cycle (Total) 33211606Sandreas.sandberg@arm.comsystem.cpu.fetch.branchRate 0.064117 # Number of branch fetches per cycle 33311606Sandreas.sandberg@arm.comsystem.cpu.fetch.rate 0.372093 # Number of inst fetches per cycle 33411606Sandreas.sandberg@arm.comsystem.cpu.decode.IdleCycles 8328 # Number of cycles decode is idle 33511606Sandreas.sandberg@arm.comsystem.cpu.decode.BlockedCycles 3356 # Number of cycles decode is blocked 33611606Sandreas.sandberg@arm.comsystem.cpu.decode.RunCycles 2449 # Number of cycles decode is running 33711440SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 215 # Number of cycles decode is unblocking 33811440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 448 # Number of cycles decode is squashing 33911440SCurtis.Dunham@arm.comsystem.cpu.decode.BranchResolved 226 # Number of times decode resolved a branch 34011440SCurtis.Dunham@arm.comsystem.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction 34111606Sandreas.sandberg@arm.comsystem.cpu.decode.DecodedInsts 15018 # Number of instructions handled by decode 34211440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode 34311440SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 448 # Number of cycles rename is squashing 34411606Sandreas.sandberg@arm.comsystem.cpu.rename.IdleCycles 8488 # Number of cycles rename is idle 34511606Sandreas.sandberg@arm.comsystem.cpu.rename.BlockCycles 1745 # Number of cycles rename is blocking 34611606Sandreas.sandberg@arm.comsystem.cpu.rename.serializeStallCycles 620 # count of cycles rename stalled for serializing inst 34711606Sandreas.sandberg@arm.comsystem.cpu.rename.RunCycles 2480 # Number of cycles rename is running 34811606Sandreas.sandberg@arm.comsystem.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking 34911606Sandreas.sandberg@arm.comsystem.cpu.rename.RenamedInsts 14460 # Number of instructions processed by rename 35011440SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 35111440SCurtis.Dunham@arm.comsystem.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full 35211440SCurtis.Dunham@arm.comsystem.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full 35311606Sandreas.sandberg@arm.comsystem.cpu.rename.SQFullEvents 949 # Number of times rename has blocked due to SQ full 35411606Sandreas.sandberg@arm.comsystem.cpu.rename.RenamedOperands 10938 # Number of destination operands rename has renamed 35511606Sandreas.sandberg@arm.comsystem.cpu.rename.RenameLookups 17913 # Number of register rename lookups that rename has made 35611606Sandreas.sandberg@arm.comsystem.cpu.rename.int_rename_lookups 17904 # Number of integer rename lookups 3579924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 35811390Ssteve.reinhardt@amd.comsystem.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed 35911606Sandreas.sandberg@arm.comsystem.cpu.rename.UndoneMaps 6361 # Number of HB maps that are undone due to squashing 36011440SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 28 # count of serializing insts renamed 36111440SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed 36211440SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 585 # count of insts added to the skid buffer 36311440SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedLoads 2839 # Number of loads inserted to the mem dependence unit. 36411440SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 1293 # Number of stores inserted to the mem dependence unit. 36511440SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingLoads 18 # Number of conflicting loads. 36611440SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. 36711606Sandreas.sandberg@arm.comsystem.cpu.iq.iqInstsAdded 13069 # Number of instructions added to the IQ (excludes non-spec) 36811440SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ 36911606Sandreas.sandberg@arm.comsystem.cpu.iq.iqInstsIssued 10787 # Number of instructions issued 37011440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued 37111606Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6710 # Number of squashed instructions iterated over during squash; mainly for profiling 37211606Sandreas.sandberg@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3679 # Number of squashed operands that are examined and possibly removed from graph 37311440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed 37411606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::samples 14796 # Number of insts issued each cycle 37511606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.729048 # Number of insts issued each cycle 37611606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.467428 # Number of insts issued each cycle 3778428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 37811606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::0 10757 72.70% 72.70% # Number of insts issued each cycle 37911606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::1 1291 8.73% 81.43% # Number of insts issued each cycle 38011606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::2 918 6.20% 87.63% # Number of insts issued each cycle 38111606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::3 680 4.60% 92.23% # Number of insts issued each cycle 38211606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::4 521 3.52% 95.75% # Number of insts issued each cycle 38311606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::5 349 2.36% 98.11% # Number of insts issued each cycle 38411606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::6 197 1.33% 99.44% # Number of insts issued each cycle 38511440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 55 0.37% 99.81% # Number of insts issued each cycle 38611440SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::8 28 0.19% 100.00% # Number of insts issued each cycle 3878428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3888428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3898428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 39011606Sandreas.sandberg@arm.comsystem.cpu.iq.issued_per_cycle::total 14796 # Number of insts issued each cycle 3918428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 39211606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::IntAlu 21 15.00% 15.00% # attempts to use FU when none available 39311606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 15.00% # attempts to use FU when none available 39411606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 15.00% # attempts to use FU when none available 39511606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 15.00% # attempts to use FU when none available 39611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 15.00% # attempts to use FU when none available 39711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 15.00% # attempts to use FU when none available 39811606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 15.00% # attempts to use FU when none available 39911606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 15.00% # attempts to use FU when none available 40011606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.00% # attempts to use FU when none available 40111606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 15.00% # attempts to use FU when none available 40211606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.00% # attempts to use FU when none available 40311606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 15.00% # attempts to use FU when none available 40411606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 15.00% # attempts to use FU when none available 40511606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 15.00% # attempts to use FU when none available 40611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 15.00% # attempts to use FU when none available 40711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 15.00% # attempts to use FU when none available 40811606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.00% # attempts to use FU when none available 40911606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 15.00% # attempts to use FU when none available 41011606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.00% # attempts to use FU when none available 41111606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.00% # attempts to use FU when none available 41211606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.00% # attempts to use FU when none available 41311606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.00% # attempts to use FU when none available 41411606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.00% # attempts to use FU when none available 41511606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.00% # attempts to use FU when none available 41611606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.00% # attempts to use FU when none available 41711606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.00% # attempts to use FU when none available 41811606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.00% # attempts to use FU when none available 41911606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.00% # attempts to use FU when none available 42011606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.00% # attempts to use FU when none available 42111606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::MemRead 82 58.57% 73.57% # attempts to use FU when none available 42211606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_full::MemWrite 37 26.43% 100.00% # attempts to use FU when none available 4238428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4248428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4258241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 42611606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::IntAlu 7188 66.64% 66.65% # Type of FU issued 42711606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 66.66% # Type of FU issued 42811606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.66% # Type of FU issued 42911606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.68% # Type of FU issued 43011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued 43111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued 43211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued 43311606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued 43411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued 43511606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued 43611606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued 43711606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued 43811606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued 43911606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued 44011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued 44111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued 44211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued 44311606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued 44411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued 44511606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued 44611606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued 44711606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued 44811606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued 44911606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued 45011606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued 45111606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued 45211606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued 45311606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued 45411606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued 45511606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::MemRead 2482 23.01% 89.69% # Type of FU issued 45611606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1112 10.31% 100.00% # Type of FU issued 4578241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4588241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 45911606Sandreas.sandberg@arm.comsystem.cpu.iq.FU_type_0::total 10787 # Type of FU issued 46011606Sandreas.sandberg@arm.comsystem.cpu.iq.rate 0.242421 # Inst issue rate 46111606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_busy_cnt 140 # FU busy when requested 46211606Sandreas.sandberg@arm.comsystem.cpu.iq.fu_busy_rate 0.012979 # FU busy rate (busy events/executed inst) 46311606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_reads 36506 # Number of integer instruction queue reads 46411606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_writes 19817 # Number of integer instruction queue writes 46511606Sandreas.sandberg@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9751 # Number of integer instruction queue wakeup accesses 4668428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 4678428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 4688428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 46911606Sandreas.sandberg@arm.comsystem.cpu.iq.int_alu_accesses 10914 # Number of integer alu accesses 4708428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 47111440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores 4728428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 47311440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1654 # Number of loads squashed 47411440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed 47511440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations 47611440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 428 # Number of stores squashed 4778428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4788428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4798428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 48011440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 89 # Number of times an access to memory failed due to the cache being blocked 4818428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 48211440SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 448 # Number of cycles IEW is squashing 48311606Sandreas.sandberg@arm.comsystem.cpu.iew.iewBlockCycles 1381 # Number of cycles IEW is blocking 48411606Sandreas.sandberg@arm.comsystem.cpu.iew.iewUnblockCycles 302 # Number of cycles IEW is unblocking 48511606Sandreas.sandberg@arm.comsystem.cpu.iew.iewDispatchedInsts 13180 # Number of instructions dispatched to IQ 48611440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch 48711440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispLoadInsts 2839 # Number of dispatched load instructions 48811440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 1293 # Number of dispatched store instructions 48911440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 49011440SCurtis.Dunham@arm.comsystem.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 49111606Sandreas.sandberg@arm.comsystem.cpu.iew.iewLSQFullEvents 295 # Number of times the LSQ has become full, causing a stall 49211440SCurtis.Dunham@arm.comsystem.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations 49311440SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly 49411440SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 390 # Number of branches that were predicted not taken incorrectly 49511440SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 497 # Number of branch mispredicts detected at execute 49611606Sandreas.sandberg@arm.comsystem.cpu.iew.iewExecutedInsts 10303 # Number of executed instructions 49711440SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecLoadInsts 2309 # Number of load instructions executed 49811606Sandreas.sandberg@arm.comsystem.cpu.iew.iewExecSquashedInsts 484 # Number of squashed instructions skipped in execute 4998428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 50011440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_nop 84 # number of nop insts executed 50111440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_refs 3386 # number of memory reference insts executed 50211606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_branches 1643 # Number of branches executed 50311440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 1077 # Number of stores executed 50411606Sandreas.sandberg@arm.comsystem.cpu.iew.exec_rate 0.231544 # Inst execution rate 50511606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit 50611606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_count 9761 # cumulative count of insts written-back 50711606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_producers 5150 # num instructions producing a value 50811606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_consumers 7013 # num instructions consuming a value 50911606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_rate 0.219363 # insts written-back per cycle 51011606Sandreas.sandberg@arm.comsystem.cpu.iew.wb_fanout 0.734350 # average fanout of values written-back 51111606Sandreas.sandberg@arm.comsystem.cpu.commit.commitSquashedInsts 6727 # The number of squashed insts skipped by commit 5128428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 51311440SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 407 # The number of times a branch was mispredicted 51411606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::samples 13560 # Number of insts commited each cycle 51511606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.472124 # Number of insts commited each cycle 51611606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.390428 # Number of insts commited each cycle 5178428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 51811606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::0 11134 82.11% 82.11% # Number of insts commited each cycle 51911606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::1 1157 8.53% 90.64% # Number of insts commited each cycle 52011440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::2 469 3.46% 94.10% # Number of insts commited each cycle 52111440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::3 205 1.51% 95.61% # Number of insts commited each cycle 52211606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::4 133 0.98% 96.59% # Number of insts commited each cycle 52311606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::5 85 0.63% 97.22% # Number of insts commited each cycle 52411440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::6 96 0.71% 97.93% # Number of insts commited each cycle 52511440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::7 89 0.66% 98.58% # Number of insts commited each cycle 52611440SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 192 1.42% 100.00% # Number of insts commited each cycle 5278428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5288428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5298428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 53011606Sandreas.sandberg@arm.comsystem.cpu.commit.committed_per_cycle::total 13560 # Number of insts commited each cycle 53111390Ssteve.reinhardt@amd.comsystem.cpu.commit.committedInsts 6402 # Number of instructions committed 53211390Ssteve.reinhardt@amd.comsystem.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed 5338428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 53411390Ssteve.reinhardt@amd.comsystem.cpu.commit.refs 2050 # Number of memory references committed 53511390Ssteve.reinhardt@amd.comsystem.cpu.commit.loads 1185 # Number of loads committed 5368428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 53711390Ssteve.reinhardt@amd.comsystem.cpu.commit.branches 1056 # Number of branches committed 5388428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 53911390Ssteve.reinhardt@amd.comsystem.cpu.commit.int_insts 6319 # Number of committed integer instructions. 5408428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 54110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 54211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction 54311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction 54411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction 54511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction 54611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction 54711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction 54811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction 54911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction 55011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction 55111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction 55211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction 55311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction 55411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction 55511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction 55611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction 55711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction 55811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction 55911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction 56011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction 56111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction 56211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction 56311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction 56411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction 56511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction 56611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction 56711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction 56811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction 56911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 57011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 57111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::MemRead 1185 18.51% 86.49% # Class of committed instruction 57211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::MemWrite 865 13.51% 100.00% # Class of committed instruction 57310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 57410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 57511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::total 6402 # Class of committed instruction 57611440SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 192 # number cycles where commit BW limit reached 57711606Sandreas.sandberg@arm.comsystem.cpu.rob.rob_reads 26146 # The number of ROB reads 57811606Sandreas.sandberg@arm.comsystem.cpu.rob.rob_writes 27511 # The number of ROB writes 57911606Sandreas.sandberg@arm.comsystem.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself 58011606Sandreas.sandberg@arm.comsystem.cpu.idleCycles 29701 # Total number of cycles that the CPU has spent unscheduled due to idling 58111390Ssteve.reinhardt@amd.comsystem.cpu.committedInsts 6385 # Number of Instructions Simulated 58211390Ssteve.reinhardt@amd.comsystem.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated 58311606Sandreas.sandberg@arm.comsystem.cpu.cpi 6.968990 # CPI: Cycles Per Instruction 58411606Sandreas.sandberg@arm.comsystem.cpu.cpi_total 6.968990 # CPI: Total CPI of All Threads 58511606Sandreas.sandberg@arm.comsystem.cpu.ipc 0.143493 # IPC: Instructions Per Cycle 58611606Sandreas.sandberg@arm.comsystem.cpu.ipc_total 0.143493 # IPC: Total IPC of All Threads 58711606Sandreas.sandberg@arm.comsystem.cpu.int_regfile_reads 12938 # number of integer regfile reads 58811606Sandreas.sandberg@arm.comsystem.cpu.int_regfile_writes 7444 # number of integer regfile writes 5898428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 5908428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 5918428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 5928428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 59311606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 59410628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 59511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tagsinuse 109.756228 # Cycle average of tags in use 59611606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.total_refs 2407 # Total number of references to valid blocks. 59711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. 59811606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.avg_refs 13.913295 # Average number of references to valid blocks. 59910628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 60011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 109.756228 # Average occupied blocks per requestor 60111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.026796 # Average percentage of cache occupancy 60211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.026796 # Average percentage of cache occupancy 60311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id 60411390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 60511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id 60611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id 60711440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses 60811440SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 6061 # Number of data accesses 60911606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 61011440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1899 # number of ReadReq hits 61111440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 1899 # number of ReadReq hits 61211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits 61311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits 61411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2407 # number of demand (read+write) hits 61511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::total 2407 # number of demand (read+write) hits 61611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2407 # number of overall hits 61711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::total 2407 # number of overall hits 61811440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses 61911440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses 62011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses 62111606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses 62211606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses 62311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses 62411606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses 62511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_misses::total 537 # number of overall misses 62611606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 12910000 # number of ReadReq miss cycles 62711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 12910000 # number of ReadReq miss cycles 62811606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 24562475 # number of WriteReq miss cycles 62911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 24562475 # number of WriteReq miss cycles 63011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 37472475 # number of demand (read+write) miss cycles 63111606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::total 37472475 # number of demand (read+write) miss cycles 63211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 37472475 # number of overall miss cycles 63311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::total 37472475 # number of overall miss cycles 63411440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 2079 # number of ReadReq accesses(hits+misses) 63511440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 2079 # number of ReadReq accesses(hits+misses) 63610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 63710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 63811440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses 63911440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses 64011440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses 64111440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses 64211440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086580 # miss rate for ReadReq accesses 64311440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.086580 # miss rate for ReadReq accesses 64411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses 64511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses 64611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.182405 # miss rate for demand accesses 64711606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.182405 # miss rate for demand accesses 64811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.182405 # miss rate for overall accesses 64911606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.182405 # miss rate for overall accesses 65011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71722.222222 # average ReadReq miss latency 65111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 71722.222222 # average ReadReq miss latency 65211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68802.450980 # average WriteReq miss latency 65311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 68802.450980 # average WriteReq miss latency 65411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency 65511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 69781.145251 # average overall miss latency 65611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 69781.145251 # average overall miss latency 65711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 69781.145251 # average overall miss latency 65811606Sandreas.sandberg@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 2459 # number of cycles access was blocked 65910628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 66011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.blocked::no_mshrs 43 # number of cycles access was blocked 66110628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 66211606Sandreas.sandberg@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 57.186047 # average number of cycles each access was blocked 66310628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 66411440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits 66511440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits 66611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits 66711606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits 66811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits 66911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits 67011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits 67111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits 67211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 67311390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 67410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 67510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 67611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 67711390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 67811390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 67911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses 68011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8568000 # number of ReadReq MSHR miss cycles 68111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 8568000 # number of ReadReq MSHR miss cycles 68211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6031500 # number of WriteReq MSHR miss cycles 68311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 6031500 # number of WriteReq MSHR miss cycles 68411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 14599500 # number of demand (read+write) MSHR miss cycles 68511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 14599500 # number of demand (read+write) MSHR miss cycles 68611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 14599500 # number of overall MSHR miss cycles 68711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 14599500 # number of overall MSHR miss cycles 68811440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048581 # mshr miss rate for ReadReq accesses 68911440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048581 # mshr miss rate for ReadReq accesses 69010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 69110628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 69211440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for demand accesses 69311440SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.058764 # mshr miss rate for demand accesses 69411440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.058764 # mshr miss rate for overall accesses 69511440SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.058764 # mshr miss rate for overall accesses 69611606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84831.683168 # average ReadReq mshr miss latency 69711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84831.683168 # average ReadReq mshr miss latency 69811606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 83770.833333 # average WriteReq mshr miss latency 69911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 83770.833333 # average WriteReq mshr miss latency 70011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency 70111606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency 70211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84390.173410 # average overall mshr miss latency 70311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 84390.173410 # average overall mshr miss latency 70411606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 7059838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 70611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tagsinuse 159.084059 # Cycle average of tags in use 70711606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.total_refs 1838 # Total number of references to valid blocks. 70811440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 313 # Sample count of references to valid blocks. 70911606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.avg_refs 5.872204 # Average number of references to valid blocks. 7109838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 71111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 159.084059 # Average occupied blocks per requestor 71211606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.077678 # Average percentage of cache occupancy 71311606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::total 0.077678 # Average percentage of cache occupancy 71411440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 313 # Occupied blocks per task id 71511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id 71611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id 71711440SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.152832 # Percentage of cache occupancy per task id 71811606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tag_accesses 4901 # Number of tag accesses 71911606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.data_accesses 4901 # Number of data accesses 72011606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 72111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1838 # number of ReadReq hits 72211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::total 1838 # number of ReadReq hits 72311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1838 # number of demand (read+write) hits 72411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::total 1838 # number of demand (read+write) hits 72511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1838 # number of overall hits 72611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::total 1838 # number of overall hits 72711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 456 # number of ReadReq misses 72811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::total 456 # number of ReadReq misses 72911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::cpu.inst 456 # number of demand (read+write) misses 73011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::total 456 # number of demand (read+write) misses 73111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::cpu.inst 456 # number of overall misses 73211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::total 456 # number of overall misses 73311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 32999500 # number of ReadReq miss cycles 73411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 32999500 # number of ReadReq miss cycles 73511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 32999500 # number of demand (read+write) miss cycles 73611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::total 32999500 # number of demand (read+write) miss cycles 73711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 32999500 # number of overall miss cycles 73811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::total 32999500 # number of overall miss cycles 73911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2294 # number of ReadReq accesses(hits+misses) 74011606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::total 2294 # number of ReadReq accesses(hits+misses) 74111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2294 # number of demand (read+write) accesses 74211606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::total 2294 # number of demand (read+write) accesses 74311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2294 # number of overall (read+write) accesses 74411606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::total 2294 # number of overall (read+write) accesses 74511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.198779 # miss rate for ReadReq accesses 74611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.198779 # miss rate for ReadReq accesses 74711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.198779 # miss rate for demand accesses 74811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_rate::total 0.198779 # miss rate for demand accesses 74911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.198779 # miss rate for overall accesses 75011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_rate::total 0.198779 # miss rate for overall accesses 75111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72367.324561 # average ReadReq miss latency 75211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 72367.324561 # average ReadReq miss latency 75311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency 75411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 72367.324561 # average overall miss latency 75511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 72367.324561 # average overall miss latency 75611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 72367.324561 # average overall miss latency 75711606Sandreas.sandberg@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked 7588428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 75911440SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 7608428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 76111606Sandreas.sandberg@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 56 # average number of cycles each access was blocked 7628983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 76311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits 76411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits 76511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits 76611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits 76711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits 76811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits 76911440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 77011440SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses 77111440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 77211440SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses 77311440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 77411440SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses 77511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24573000 # number of ReadReq MSHR miss cycles 77611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 24573000 # number of ReadReq MSHR miss cycles 77711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 24573000 # number of demand (read+write) MSHR miss cycles 77811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 24573000 # number of demand (read+write) MSHR miss cycles 77911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 24573000 # number of overall MSHR miss cycles 78011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 24573000 # number of overall MSHR miss cycles 78111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for ReadReq accesses 78211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.136443 # mshr miss rate for ReadReq accesses 78311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for demand accesses 78411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.136443 # mshr miss rate for demand accesses 78511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.136443 # mshr miss rate for overall accesses 78611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.136443 # mshr miss rate for overall accesses 78711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78507.987220 # average ReadReq mshr miss latency 78811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78507.987220 # average ReadReq mshr miss latency 78911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency 79011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency 79111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78507.987220 # average overall mshr miss latency 79211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 78507.987220 # average overall mshr miss latency 79311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 7949838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 79511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tagsinuse 268.962928 # Cycle average of tags in use 7969838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 79711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 485 # Sample count of references to valid blocks. 79811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 0.002062 # Average number of references to valid blocks. 7999838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 80011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 159.125052 # Average occupied blocks per requestor 80111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 109.837876 # Average occupied blocks per requestor 80211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004856 # Average percentage of cache occupancy 80311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.003352 # Average percentage of cache occupancy 80411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.008208 # Average percentage of cache occupancy 80511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 485 # Occupied blocks per task id 80611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id 80711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id 80811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.014801 # Percentage of cache occupancy per task id 80911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 4373 # Number of tag accesses 81011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 4373 # Number of data accesses 81111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 81210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 81310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 8148835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 8158835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 8168835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 8178835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 81810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 81910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 82011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 312 # number of ReadCleanReq misses 82111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 312 # number of ReadCleanReq misses 82211390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 82311390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses 82411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses 82511390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses 82611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses 82711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses 82811390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses 82911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 485 # number of overall misses 83011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5920500 # number of ReadExReq miss cycles 83111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 5920500 # number of ReadExReq miss cycles 83211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 24090000 # number of ReadCleanReq miss cycles 83311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 24090000 # number of ReadCleanReq miss cycles 83411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8408000 # number of ReadSharedReq miss cycles 83511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 8408000 # number of ReadSharedReq miss cycles 83611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 24090000 # number of demand (read+write) miss cycles 83711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 14328500 # number of demand (read+write) miss cycles 83811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::total 38418500 # number of demand (read+write) miss cycles 83911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 24090000 # number of overall miss cycles 84011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 14328500 # number of overall miss cycles 84111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::total 38418500 # number of overall miss cycles 84210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 84310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 84411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 313 # number of ReadCleanReq accesses(hits+misses) 84511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 313 # number of ReadCleanReq accesses(hits+misses) 84611390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) 84711390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) 84811440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses 84911390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses 85011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses 85111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses 85211390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses 85311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses 8548835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8559055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 85611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadCleanReq accesses 85711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996805 # miss rate for ReadCleanReq accesses 85810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 85910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 86011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses 8618835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 86211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997942 # miss rate for demand accesses 86311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses 8648835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 86511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses 86611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82229.166667 # average ReadExReq miss latency 86711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 82229.166667 # average ReadExReq miss latency 86811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77211.538462 # average ReadCleanReq miss latency 86911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77211.538462 # average ReadCleanReq miss latency 87011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83247.524752 # average ReadSharedReq miss latency 87111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83247.524752 # average ReadSharedReq miss latency 87211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency 87311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency 87411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 79213.402062 # average overall miss latency 87511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77211.538462 # average overall miss latency 87611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 82823.699422 # average overall miss latency 87711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 79213.402062 # average overall miss latency 8788428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8798428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8808428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8818428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8828983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8838983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 88410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 88510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 88611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 312 # number of ReadCleanReq MSHR misses 88711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 312 # number of ReadCleanReq MSHR misses 88811390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 88911390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses 89011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 89111390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 89211440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses 89311440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 89411390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 89511440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses 89611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5200500 # number of ReadExReq MSHR miss cycles 89711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5200500 # number of ReadExReq MSHR miss cycles 89811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20970000 # number of ReadCleanReq MSHR miss cycles 89911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20970000 # number of ReadCleanReq MSHR miss cycles 90011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7398000 # number of ReadSharedReq MSHR miss cycles 90111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7398000 # number of ReadSharedReq MSHR miss cycles 90211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20970000 # number of demand (read+write) MSHR miss cycles 90311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12598500 # number of demand (read+write) MSHR miss cycles 90411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 33568500 # number of demand (read+write) MSHR miss cycles 90511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20970000 # number of overall MSHR miss cycles 90611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12598500 # number of overall MSHR miss cycles 90711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 33568500 # number of overall MSHR miss cycles 9088835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 9099055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 91011440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadCleanReq accesses 91111440SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996805 # mshr miss rate for ReadCleanReq accesses 91210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 91310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 91411440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses 9158835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 91611440SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 # mshr miss rate for demand accesses 91711440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses 9188835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 91911440SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses 92011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72229.166667 # average ReadExReq mshr miss latency 92111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72229.166667 # average ReadExReq mshr miss latency 92211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67211.538462 # average ReadCleanReq mshr miss latency 92311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67211.538462 # average ReadCleanReq mshr miss latency 92411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73247.524752 # average ReadSharedReq mshr miss latency 92511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73247.524752 # average ReadSharedReq mshr miss latency 92611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency 92711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency 92811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency 92911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67211.538462 # average overall mshr miss latency 93011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72823.699422 # average overall mshr miss latency 93111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 69213.402062 # average overall mshr miss latency 93211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 486 # Total number of requests made to the snoop filter. 93311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 93411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 93511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 93611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 93711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 93811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 93911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 414 # Transaction distribution 94010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 94110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 94211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 313 # Transaction distribution 94311390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution 94411440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 626 # Packet count per connected master and slave (bytes) 94511390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) 94611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 972 # Packet count per connected master and slave (bytes) 94711440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20032 # Cumulative packet size per connected master and slave (bytes) 94811390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) 94911440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) 95010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 95111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 95211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 486 # Request fanout histogram 95311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.002058 # Request fanout histogram 95411440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram 95510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 95611440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 485 99.79% 99.79% # Request fanout histogram 95711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram 95810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 95910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 96011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 96110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 96211440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 486 # Request fanout histogram 96311440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 243000 # Layer occupancy (ticks) 96410726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 96511440SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 469500 # Layer occupancy (ticks) 96610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 96711390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) 96810892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 96911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. 97011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 97111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 97211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 97311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 97411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 97511606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 22248000 # Cumulative time (in ticks) in various power states 97611440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 413 # Transaction distribution 97710628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 72 # Transaction distribution 97810628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 72 # Transaction distribution 97911440SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 413 # Transaction distribution 98011440SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 970 # Packet count per connected master and slave (bytes) 98111440SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 970 # Packet count per connected master and slave (bytes) 98211440SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31040 # Cumulative packet size per connected master and slave (bytes) 98311440SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) 98410628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 98511570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 98611440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 485 # Request fanout histogram 98710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 98810628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 98910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 99011440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 485 100.00% 100.00% # Request fanout histogram 99110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 99210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 99310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 99410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 99511440SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 485 # Request fanout histogram 99611606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.occupancy 591500 # Layer occupancy (ticks) 99710726Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.7 # Layer utilization (%) 99811606Sandreas.sandberg@arm.comsystem.membus.respLayer1.occupancy 2578750 # Layer occupancy (ticks) 99911606Sandreas.sandberg@arm.comsystem.membus.respLayer1.utilization 11.6 # Layer utilization (%) 10003096SN/A 10013096SN/A---------- End Simulation Statistics ---------- 1002