stats.txt revision 11138
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 310726Sandreas.hansson@arm.comsim_seconds 0.000022 # Number of seconds simulated 411103Snilay@cs.wisc.edusim_ticks 21900500 # Number of ticks simulated 511103Snilay@cs.wisc.edufinal_tick 21900500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711138Sandreas.hansson@arm.comhost_inst_rate 94413 # Simulator instruction rate (inst/s) 811138Sandreas.hansson@arm.comhost_op_rate 94393 # Simulator op (including micro ops) rate (op/s) 911138Sandreas.hansson@arm.comhost_tick_rate 324370159 # Simulator tick rate (ticks/s) 1011138Sandreas.hansson@arm.comhost_mem_usage 297000 # Number of bytes of host memory used 1111138Sandreas.hansson@arm.comhost_seconds 0.07 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6372 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6372 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 19840 # Number of bytes read from this memory 1711103Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.data 10944 # Number of bytes read from this memory 1811103Snilay@cs.wisc.edusystem.physmem.bytes_read::total 30784 # Number of bytes read from this memory 1911103Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 19840 # Number of instructions bytes read from this memory 2011103Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 19840 # Number of instructions bytes read from this memory 2111103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 310 # Number of read requests responded to by this memory 2211103Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.data 171 # Number of read requests responded to by this memory 2311103Snilay@cs.wisc.edusystem.physmem.num_reads::total 481 # Number of read requests responded to by this memory 2411103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 905915390 # Total read bandwidth from this memory (bytes/s) 2511103Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.data 499714618 # Total read bandwidth from this memory (bytes/s) 2611103Snilay@cs.wisc.edusystem.physmem.bw_read::total 1405630008 # Total read bandwidth from this memory (bytes/s) 2711103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 905915390 # Instruction read bandwidth from this memory (bytes/s) 2811103Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 905915390 # Instruction read bandwidth from this memory (bytes/s) 2911103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 905915390 # Total bandwidth to/from this memory (bytes/s) 3011103Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.data 499714618 # Total bandwidth to/from this memory (bytes/s) 3111103Snilay@cs.wisc.edusystem.physmem.bw_total::total 1405630008 # Total bandwidth to/from this memory (bytes/s) 3211103Snilay@cs.wisc.edusystem.physmem.readReqs 481 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3411103Snilay@cs.wisc.edusystem.physmem.readBursts 481 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3611103Snilay@cs.wisc.edusystem.physmem.bytesReadDRAM 30784 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3911103Snilay@cs.wisc.edusystem.physmem.bytesReadSys 30784 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4411103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::0 68 # Per bank write bursts 4511103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::1 32 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 32 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 47 # Per bank write bursts 4811103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::4 41 # Per bank write bursts 4910352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 20 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 1 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 3 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 0 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 1 # Per bank write bursts 5410726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 22 # Per bank write bursts 5510352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 25 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 14 # Per bank write bursts 5711103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::13 118 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 45 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 12 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7811103Snilay@cs.wisc.edusystem.physmem.totGap 21763000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8511103Snilay@cs.wisc.edusystem.physmem.readPktSize::6 481 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9311103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see 9411103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see 9511103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see 9610726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 9711103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see 989322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18911103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation 19011103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::mean 337.822785 # Bytes accessed per row activation 19111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::gmean 215.071445 # Bytes accessed per row activation 19211103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::stdev 323.417518 # Bytes accessed per row activation 19311103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::0-127 21 26.58% 26.58% # Bytes accessed per row activation 19411103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::128-255 22 27.85% 54.43% # Bytes accessed per row activation 19511103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::256-383 9 11.39% 65.82% # Bytes accessed per row activation 19611103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::384-511 9 11.39% 77.22% # Bytes accessed per row activation 19711103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::512-639 4 5.06% 82.28% # Bytes accessed per row activation 19811103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::640-767 1 1.27% 83.54% # Bytes accessed per row activation 19911103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::768-895 3 3.80% 87.34% # Bytes accessed per row activation 20011103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::1024-1151 10 12.66% 100.00% # Bytes accessed per row activation 20111103Snilay@cs.wisc.edusystem.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation 20211103Snilay@cs.wisc.edusystem.physmem.totQLat 3965000 # Total ticks spent queuing 20311103Snilay@cs.wisc.edusystem.physmem.totMemAccLat 12983750 # Total ticks spent from burst creation until serviced by the DRAM 20411103Snilay@cs.wisc.edusystem.physmem.totBusLat 2405000 # Total ticks spent in databus transfers 20511103Snilay@cs.wisc.edusystem.physmem.avgQLat 8243.24 # Average queueing delay per DRAM burst 2069978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20711103Snilay@cs.wisc.edusystem.physmem.avgMemAccLat 26993.24 # Average memory access latency per DRAM burst 20811103Snilay@cs.wisc.edusystem.physmem.avgRdBW 1405.63 # Average DRAM read bandwidth in MiByte/s 2099978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21011103Snilay@cs.wisc.edusystem.physmem.avgRdBWSys 1405.63 # Average system read bandwidth in MiByte/s 2119978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21311103Snilay@cs.wisc.edusystem.physmem.busUtil 10.98 # Data bus utilization in percentage 21411103Snilay@cs.wisc.edusystem.physmem.busUtilRead 10.98 # Data bus utilization in percentage for reads 2159978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21611103Snilay@cs.wisc.edusystem.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing 2179978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21811103Snilay@cs.wisc.edusystem.physmem.readRowHits 387 # Number of row buffer hits during reads 2199312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22011103Snilay@cs.wisc.edusystem.physmem.readRowHitRate 80.46 # Row buffer hit rate for reads 2219312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22211103Snilay@cs.wisc.edusystem.physmem.avgGap 45245.32 # Average gap between requests 22311103Snilay@cs.wisc.edusystem.physmem.pageHitRate 80.46 # Row buffer hit rate, read and write combined 22411103Snilay@cs.wisc.edusystem.physmem_0.actEnergy 196560 # Energy for activate commands per rank (pJ) 22511103Snilay@cs.wisc.edusystem.physmem_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) 22611103Snilay@cs.wisc.edusystem.physmem_0.readEnergy 1630200 # Energy for read commands per rank (pJ) 22710628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22810628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 22910726Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) 23010628Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) 23111103Snilay@cs.wisc.edusystem.physmem_0.totalEnergy 13775205 # Total energy per rank (pJ) 23211103Snilay@cs.wisc.edusystem.physmem_0.averagePower 870.058740 # Core power per rank (mW) 23311103Snilay@cs.wisc.edusystem.physmem_0.memoryStateTime::IDLE 209750 # Time in different power states 23410628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 23510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23610726Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states 23710628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23811103Snilay@cs.wisc.edusystem.physmem_1.actEnergy 317520 # Energy for activate commands per rank (pJ) 23911103Snilay@cs.wisc.edusystem.physmem_1.preEnergy 173250 # Energy for precharge commands per rank (pJ) 24011103Snilay@cs.wisc.edusystem.physmem_1.readEnergy 1287000 # Energy for read commands per rank (pJ) 24110628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24210628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24311103Snilay@cs.wisc.edusystem.physmem_1.actBackEnergy 10183905 # Energy for active background per rank (pJ) 24411103Snilay@cs.wisc.edusystem.physmem_1.preBackEnergy 566250 # Energy for precharge background per rank (pJ) 24511103Snilay@cs.wisc.edusystem.physmem_1.totalEnergy 13545045 # Total energy per rank (pJ) 24611103Snilay@cs.wisc.edusystem.physmem_1.averagePower 855.521554 # Core power per rank (mW) 24711103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::IDLE 873500 # Time in different power states 24810628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 24910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25011103Snilay@cs.wisc.edusystem.physmem_1.memoryStateTime::ACT 14452750 # Time in different power states 25110628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25211103Snilay@cs.wisc.edusystem.cpu.branchPred.lookups 2551 # Number of BP lookups 25311103Snilay@cs.wisc.edusystem.cpu.branchPred.condPredicted 1518 # Number of conditional branches predicted 25411103Snilay@cs.wisc.edusystem.cpu.branchPred.condIncorrect 429 # Number of conditional branches incorrect 25511103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBLookups 1991 # Number of BTB lookups 25611103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHits 726 # Number of BTB hits 2579481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25811103Snilay@cs.wisc.edusystem.cpu.branchPred.BTBHitPct 36.464088 # BTB Hit Percentage 25911103Snilay@cs.wisc.edusystem.cpu.branchPred.usedRAS 383 # Number of times the RAS was used to get a target. 26010892Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions. 26110628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2628428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2638428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2648428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2658428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 26611103Snilay@cs.wisc.edusystem.cpu.dtb.read_hits 2033 # DTB read hits 26711103Snilay@cs.wisc.edusystem.cpu.dtb.read_misses 43 # DTB read misses 2688428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 26911103Snilay@cs.wisc.edusystem.cpu.dtb.read_accesses 2076 # DTB read accesses 27011103Snilay@cs.wisc.edusystem.cpu.dtb.write_hits 1052 # DTB write hits 27111103Snilay@cs.wisc.edusystem.cpu.dtb.write_misses 28 # DTB write misses 2728428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 27311103Snilay@cs.wisc.edusystem.cpu.dtb.write_accesses 1080 # DTB write accesses 27411103Snilay@cs.wisc.edusystem.cpu.dtb.data_hits 3085 # DTB hits 27511103Snilay@cs.wisc.edusystem.cpu.dtb.data_misses 71 # DTB misses 2768428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 27711103Snilay@cs.wisc.edusystem.cpu.dtb.data_accesses 3156 # DTB accesses 27811103Snilay@cs.wisc.edusystem.cpu.itb.fetch_hits 2086 # ITB hits 27911103Snilay@cs.wisc.edusystem.cpu.itb.fetch_misses 32 # ITB misses 2808428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 28111103Snilay@cs.wisc.edusystem.cpu.itb.fetch_accesses 2118 # ITB accesses 2828428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2838428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2848428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2858428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2868428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2878428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2888428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2898428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2908428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2918428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2928428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2938428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2948428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 29511103Snilay@cs.wisc.edusystem.cpu.numCycles 43802 # number of cpu cycles simulated 2968428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2978428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 29811103Snilay@cs.wisc.edusystem.cpu.fetch.icacheStallCycles 8360 # Number of cycles fetch is stalled on an Icache miss 29911103Snilay@cs.wisc.edusystem.cpu.fetch.Insts 14953 # Number of instructions fetch has processed 30011103Snilay@cs.wisc.edusystem.cpu.fetch.Branches 2551 # Number of branches that fetch encountered 30111103Snilay@cs.wisc.edusystem.cpu.fetch.predictedBranches 1109 # Number of branches that fetch has predicted taken 30211103Snilay@cs.wisc.edusystem.cpu.fetch.Cycles 4527 # Number of cycles fetch has run and was not squashing or blocked 30311103Snilay@cs.wisc.edusystem.cpu.fetch.SquashCycles 940 # Number of cycles fetch has spent squashing 30411103Snilay@cs.wisc.edusystem.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 30511103Snilay@cs.wisc.edusystem.cpu.fetch.PendingTrapStallCycles 730 # Number of stall cycles due to pending traps 30611103Snilay@cs.wisc.edusystem.cpu.fetch.CacheLines 2086 # Number of cache lines fetched 30711103Snilay@cs.wisc.edusystem.cpu.fetch.IcacheSquashes 308 # Number of outstanding Icache misses that were squashed 30811103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::samples 14111 # Number of instructions fetched each cycle (Total) 30911103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::mean 1.059670 # Number of instructions fetched each cycle (Total) 31011103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::stdev 2.447373 # Number of instructions fetched each cycle (Total) 3116291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 31211103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::0 11381 80.65% 80.65% # Number of instructions fetched each cycle (Total) 31311103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::1 309 2.19% 82.84% # Number of instructions fetched each cycle (Total) 31411103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::2 232 1.64% 84.49% # Number of instructions fetched each cycle (Total) 31511103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::3 210 1.49% 85.98% # Number of instructions fetched each cycle (Total) 31611103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::4 257 1.82% 87.80% # Number of instructions fetched each cycle (Total) 31711103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::5 204 1.45% 89.24% # Number of instructions fetched each cycle (Total) 31811103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::6 249 1.76% 91.01% # Number of instructions fetched each cycle (Total) 31911103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::7 144 1.02% 92.03% # Number of instructions fetched each cycle (Total) 32011103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::8 1125 7.97% 100.00% # Number of instructions fetched each cycle (Total) 3216291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3226291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3236291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 32411103Snilay@cs.wisc.edusystem.cpu.fetch.rateDist::total 14111 # Number of instructions fetched each cycle (Total) 32511103Snilay@cs.wisc.edusystem.cpu.fetch.branchRate 0.058239 # Number of branch fetches per cycle 32611103Snilay@cs.wisc.edusystem.cpu.fetch.rate 0.341377 # Number of inst fetches per cycle 32711103Snilay@cs.wisc.edusystem.cpu.decode.IdleCycles 8350 # Number of cycles decode is idle 32811103Snilay@cs.wisc.edusystem.cpu.decode.BlockedCycles 2903 # Number of cycles decode is blocked 32911103Snilay@cs.wisc.edusystem.cpu.decode.RunCycles 2283 # Number of cycles decode is running 33011103Snilay@cs.wisc.edusystem.cpu.decode.UnblockCycles 178 # Number of cycles decode is unblocking 33111103Snilay@cs.wisc.edusystem.cpu.decode.SquashCycles 397 # Number of cycles decode is squashing 33211103Snilay@cs.wisc.edusystem.cpu.decode.BranchResolved 199 # Number of times decode resolved a branch 33311103Snilay@cs.wisc.edusystem.cpu.decode.BranchMispred 74 # Number of times decode detected a branch misprediction 33411103Snilay@cs.wisc.edusystem.cpu.decode.DecodedInsts 13658 # Number of instructions handled by decode 33511103Snilay@cs.wisc.edusystem.cpu.decode.SquashedInsts 213 # Number of squashed instructions handled by decode 33611103Snilay@cs.wisc.edusystem.cpu.rename.SquashCycles 397 # Number of cycles rename is squashing 33711103Snilay@cs.wisc.edusystem.cpu.rename.IdleCycles 8499 # Number of cycles rename is idle 33811103Snilay@cs.wisc.edusystem.cpu.rename.BlockCycles 1362 # Number of cycles rename is blocking 33911103Snilay@cs.wisc.edusystem.cpu.rename.serializeStallCycles 551 # count of cycles rename stalled for serializing inst 34011103Snilay@cs.wisc.edusystem.cpu.rename.RunCycles 2297 # Number of cycles rename is running 34111103Snilay@cs.wisc.edusystem.cpu.rename.UnblockCycles 1005 # Number of cycles rename is unblocking 34211103Snilay@cs.wisc.edusystem.cpu.rename.RenamedInsts 13185 # Number of instructions processed by rename 34311103Snilay@cs.wisc.edusystem.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 34411103Snilay@cs.wisc.edusystem.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full 34511103Snilay@cs.wisc.edusystem.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full 34610892Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full 34711103Snilay@cs.wisc.edusystem.cpu.rename.RenamedOperands 9916 # Number of destination operands rename has renamed 34811103Snilay@cs.wisc.edusystem.cpu.rename.RenameLookups 16517 # Number of register rename lookups that rename has made 34911103Snilay@cs.wisc.edusystem.cpu.rename.int_rename_lookups 16508 # Number of integer rename lookups 3509924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 3519150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 35211103Snilay@cs.wisc.edusystem.cpu.rename.UndoneMaps 5346 # Number of HB maps that are undone due to squashing 35311103Snilay@cs.wisc.edusystem.cpu.rename.serializingInsts 30 # count of serializing insts renamed 35410352Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed 35511103Snilay@cs.wisc.edusystem.cpu.rename.skidInsts 571 # count of insts added to the skid buffer 35611103Snilay@cs.wisc.edusystem.cpu.memDep0.insertedLoads 2513 # Number of loads inserted to the mem dependence unit. 35711103Snilay@cs.wisc.edusystem.cpu.memDep0.insertedStores 1264 # Number of stores inserted to the mem dependence unit. 35810726Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. 3598428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 36011103Snilay@cs.wisc.edusystem.cpu.iq.iqInstsAdded 12094 # Number of instructions added to the IQ (excludes non-spec) 36110352Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ 36211103Snilay@cs.wisc.edusystem.cpu.iq.iqInstsIssued 10150 # Number of instructions issued 36311103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsIssued 8 # Number of squashed instructions issued 36411103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedInstsExamined 5749 # Number of squashed instructions iterated over during squash; mainly for profiling 36511103Snilay@cs.wisc.edusystem.cpu.iq.iqSquashedOperandsExamined 3122 # Number of squashed operands that are examined and possibly removed from graph 36610352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed 36711103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::samples 14111 # Number of insts issued each cycle 36811103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::mean 0.719297 # Number of insts issued each cycle 36911103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::stdev 1.444291 # Number of insts issued each cycle 3708428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 37111103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::0 10252 72.65% 72.65% # Number of insts issued each cycle 37211103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::1 1258 8.92% 81.57% # Number of insts issued each cycle 37311103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::2 873 6.19% 87.75% # Number of insts issued each cycle 37411103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::3 669 4.74% 92.50% # Number of insts issued each cycle 37511103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::4 489 3.47% 95.96% # Number of insts issued each cycle 37611103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::5 327 2.32% 98.28% # Number of insts issued each cycle 37711103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::6 176 1.25% 99.53% # Number of insts issued each cycle 37811103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::7 44 0.31% 99.84% # Number of insts issued each cycle 37911103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::8 23 0.16% 100.00% # Number of insts issued each cycle 3808428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3818428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3828428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 38311103Snilay@cs.wisc.edusystem.cpu.iq.issued_per_cycle::total 14111 # Number of insts issued each cycle 3848428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 38511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntAlu 18 13.64% 13.64% # attempts to use FU when none available 38611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntMult 0 0.00% 13.64% # attempts to use FU when none available 38711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::IntDiv 0 0.00% 13.64% # attempts to use FU when none available 38811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatAdd 0 0.00% 13.64% # attempts to use FU when none available 38911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCmp 0 0.00% 13.64% # attempts to use FU when none available 39011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatCvt 0 0.00% 13.64% # attempts to use FU when none available 39111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatMult 0 0.00% 13.64% # attempts to use FU when none available 39211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatDiv 0 0.00% 13.64% # attempts to use FU when none available 39311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.64% # attempts to use FU when none available 39411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAdd 0 0.00% 13.64% # attempts to use FU when none available 39511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.64% # attempts to use FU when none available 39611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdAlu 0 0.00% 13.64% # attempts to use FU when none available 39711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCmp 0 0.00% 13.64% # attempts to use FU when none available 39811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdCvt 0 0.00% 13.64% # attempts to use FU when none available 39911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMisc 0 0.00% 13.64% # attempts to use FU when none available 40011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMult 0 0.00% 13.64% # attempts to use FU when none available 40111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.64% # attempts to use FU when none available 40211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShift 0 0.00% 13.64% # attempts to use FU when none available 40311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.64% # attempts to use FU when none available 40411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.64% # attempts to use FU when none available 40511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.64% # attempts to use FU when none available 40611103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.64% # attempts to use FU when none available 40711103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.64% # attempts to use FU when none available 40811103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.64% # attempts to use FU when none available 40911103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.64% # attempts to use FU when none available 41011103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.64% # attempts to use FU when none available 41111103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.64% # attempts to use FU when none available 41211103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.64% # attempts to use FU when none available 41311103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.64% # attempts to use FU when none available 41411103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemRead 73 55.30% 68.94% # attempts to use FU when none available 41511103Snilay@cs.wisc.edusystem.cpu.iq.fu_full::MemWrite 41 31.06% 100.00% # attempts to use FU when none available 4168428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4178428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4188241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 41911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntAlu 6822 67.21% 67.23% # Type of FU issued 42011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.24% # Type of FU issued 42111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued 42211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.26% # Type of FU issued 42311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.26% # Type of FU issued 42411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.26% # Type of FU issued 42511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.26% # Type of FU issued 42611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.26% # Type of FU issued 42711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.26% # Type of FU issued 42811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.26% # Type of FU issued 42911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.26% # Type of FU issued 43011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.26% # Type of FU issued 43111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.26% # Type of FU issued 43211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.26% # Type of FU issued 43311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.26% # Type of FU issued 43411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.26% # Type of FU issued 43511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.26% # Type of FU issued 43611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.26% # Type of FU issued 43711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.26% # Type of FU issued 43811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.26% # Type of FU issued 43911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.26% # Type of FU issued 44011103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.26% # Type of FU issued 44111103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.26% # Type of FU issued 44211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.26% # Type of FU issued 44311103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.26% # Type of FU issued 44411103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.26% # Type of FU issued 44511103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.26% # Type of FU issued 44611103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.26% # Type of FU issued 44711103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.26% # Type of FU issued 44811103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemRead 2214 21.81% 89.07% # Type of FU issued 44911103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::MemWrite 1109 10.93% 100.00% # Type of FU issued 4508241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4518241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 45211103Snilay@cs.wisc.edusystem.cpu.iq.FU_type_0::total 10150 # Type of FU issued 45311103Snilay@cs.wisc.edusystem.cpu.iq.rate 0.231725 # Inst issue rate 45411103Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_cnt 132 # FU busy when requested 45511103Snilay@cs.wisc.edusystem.cpu.iq.fu_busy_rate 0.013005 # FU busy rate (busy events/executed inst) 45611103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_reads 34530 # Number of integer instruction queue reads 45711103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_writes 17879 # Number of integer instruction queue writes 45811103Snilay@cs.wisc.edusystem.cpu.iq.int_inst_queue_wakeup_accesses 9316 # Number of integer instruction queue wakeup accesses 4598428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 4608428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 4618428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 46211103Snilay@cs.wisc.edusystem.cpu.iq.int_alu_accesses 10269 # Number of integer alu accesses 4638428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 46411103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores 4658428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 46611103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedLoads 1330 # Number of loads squashed 46710352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 46810352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 46911103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.squashedStores 399 # Number of stores squashed 4708428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4718428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4728428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 47311103Snilay@cs.wisc.edusystem.cpu.iew.lsq.thread0.cacheBlocked 71 # Number of times an access to memory failed due to the cache being blocked 4748428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 47511103Snilay@cs.wisc.edusystem.cpu.iew.iewSquashCycles 397 # Number of cycles IEW is squashing 47611103Snilay@cs.wisc.edusystem.cpu.iew.iewBlockCycles 1267 # Number of cycles IEW is blocking 47711103Snilay@cs.wisc.edusystem.cpu.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking 47811103Snilay@cs.wisc.edusystem.cpu.iew.iewDispatchedInsts 12206 # Number of instructions dispatched to IQ 47911103Snilay@cs.wisc.edusystem.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch 48011103Snilay@cs.wisc.edusystem.cpu.iew.iewDispLoadInsts 2513 # Number of dispatched load instructions 48111103Snilay@cs.wisc.edusystem.cpu.iew.iewDispStoreInsts 1264 # Number of dispatched store instructions 48210352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions 48311103Snilay@cs.wisc.edusystem.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall 48410892Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall 48510352Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations 48611103Snilay@cs.wisc.edusystem.cpu.iew.predictedTakenIncorrect 85 # Number of branches that were predicted taken incorrectly 48711103Snilay@cs.wisc.edusystem.cpu.iew.predictedNotTakenIncorrect 341 # Number of branches that were predicted not taken incorrectly 48811103Snilay@cs.wisc.edusystem.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute 48911103Snilay@cs.wisc.edusystem.cpu.iew.iewExecutedInsts 9752 # Number of executed instructions 49011103Snilay@cs.wisc.edusystem.cpu.iew.iewExecLoadInsts 2076 # Number of load instructions executed 49111103Snilay@cs.wisc.edusystem.cpu.iew.iewExecSquashedInsts 398 # Number of squashed instructions skipped in execute 4928428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 49311103Snilay@cs.wisc.edusystem.cpu.iew.exec_nop 84 # number of nop insts executed 49411103Snilay@cs.wisc.edusystem.cpu.iew.exec_refs 3158 # number of memory reference insts executed 49511103Snilay@cs.wisc.edusystem.cpu.iew.exec_branches 1540 # Number of branches executed 49611103Snilay@cs.wisc.edusystem.cpu.iew.exec_stores 1082 # Number of stores executed 49711103Snilay@cs.wisc.edusystem.cpu.iew.exec_rate 0.222638 # Inst execution rate 49811103Snilay@cs.wisc.edusystem.cpu.iew.wb_sent 9474 # cumulative count of insts sent to commit 49911103Snilay@cs.wisc.edusystem.cpu.iew.wb_count 9326 # cumulative count of insts written-back 50011103Snilay@cs.wisc.edusystem.cpu.iew.wb_producers 4992 # num instructions producing a value 50111103Snilay@cs.wisc.edusystem.cpu.iew.wb_consumers 6833 # num instructions consuming a value 5028428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 50311103Snilay@cs.wisc.edusystem.cpu.iew.wb_rate 0.212913 # insts written-back per cycle 50411103Snilay@cs.wisc.edusystem.cpu.iew.wb_fanout 0.730572 # average fanout of values written-back 5058428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 50611103Snilay@cs.wisc.edusystem.cpu.commit.commitSquashedInsts 5821 # The number of squashed insts skipped by commit 5078428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 50811103Snilay@cs.wisc.edusystem.cpu.commit.branchMispredicts 356 # The number of times a branch was mispredicted 50911103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::samples 13063 # Number of insts commited each cycle 51011103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::mean 0.489091 # Number of insts commited each cycle 51111103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::stdev 1.409393 # Number of insts commited each cycle 5128428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 51311103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::0 10626 81.34% 81.34% # Number of insts commited each cycle 51411103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::1 1163 8.90% 90.25% # Number of insts commited each cycle 51511103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::2 487 3.73% 93.98% # Number of insts commited each cycle 51611103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::3 202 1.55% 95.52% # Number of insts commited each cycle 51711103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::4 127 0.97% 96.49% # Number of insts commited each cycle 51811103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::5 82 0.63% 97.12% # Number of insts commited each cycle 51911103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::6 98 0.75% 97.87% # Number of insts commited each cycle 52011103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::7 84 0.64% 98.51% # Number of insts commited each cycle 52111103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::8 194 1.49% 100.00% # Number of insts commited each cycle 5228428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5238428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5248428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 52511103Snilay@cs.wisc.edusystem.cpu.commit.committed_per_cycle::total 13063 # Number of insts commited each cycle 5269150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6389 # Number of instructions committed 5279150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 5288428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5299150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2048 # Number of memory references committed 5309150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1183 # Number of loads committed 5318428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 5329150SAli.Saidi@ARM.comsystem.cpu.commit.branches 1050 # Number of branches committed 5338428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 5349150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 6307 # Number of committed integer instructions. 5358428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 53610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 53710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction 53810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction 53910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction 54010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction 54110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction 54210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction 54310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction 54410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction 54510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 54610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction 54710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 54810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction 54910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction 55010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction 55110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction 55210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction 55310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 55410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction 55510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 55610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 55710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 55810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 55910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 56010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 56110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 56210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 56310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 56410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 56510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 56610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 56710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 56810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 56910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 57010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 6389 # Class of committed instruction 57111103Snilay@cs.wisc.edusystem.cpu.commit.bw_lim_events 194 # number cycles where commit BW limit reached 57211103Snilay@cs.wisc.edusystem.cpu.rob.rob_reads 24728 # The number of ROB reads 57311103Snilay@cs.wisc.edusystem.cpu.rob.rob_writes 25475 # The number of ROB writes 57411103Snilay@cs.wisc.edusystem.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself 57511103Snilay@cs.wisc.edusystem.cpu.idleCycles 29691 # Total number of cycles that the CPU has spent unscheduled due to idling 5769150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6372 # Number of Instructions Simulated 5779150SAli.Saidi@ARM.comsystem.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 57811103Snilay@cs.wisc.edusystem.cpu.cpi 6.874137 # CPI: Cycles Per Instruction 57911103Snilay@cs.wisc.edusystem.cpu.cpi_total 6.874137 # CPI: Total CPI of All Threads 58011103Snilay@cs.wisc.edusystem.cpu.ipc 0.145473 # IPC: Instructions Per Cycle 58111103Snilay@cs.wisc.edusystem.cpu.ipc_total 0.145473 # IPC: Total IPC of All Threads 58211103Snilay@cs.wisc.edusystem.cpu.int_regfile_reads 12362 # number of integer regfile reads 58311103Snilay@cs.wisc.edusystem.cpu.int_regfile_writes 7056 # number of integer regfile writes 5848428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 5858428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 5868428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 5878428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 58810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 58911103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tagsinuse 107.516544 # Cycle average of tags in use 59011103Snilay@cs.wisc.edusystem.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. 59111103Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. 59211103Snilay@cs.wisc.edusystem.cpu.dcache.tags.avg_refs 13.309942 # Average number of references to valid blocks. 59310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 59411103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_blocks::cpu.data 107.516544 # Average occupied blocks per requestor 59511103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_percent::cpu.data 0.026249 # Average percentage of cache occupancy 59611103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_percent::total 0.026249 # Average percentage of cache occupancy 59711103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_blocks::1024 171 # Occupied blocks per task id 59811103Snilay@cs.wisc.edusystem.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id 59910726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id 60011103Snilay@cs.wisc.edusystem.cpu.dcache.tags.occ_task_id_percent::1024 0.041748 # Percentage of cache occupancy per task id 60111103Snilay@cs.wisc.edusystem.cpu.dcache.tags.tag_accesses 5747 # Number of tag accesses 60211103Snilay@cs.wisc.edusystem.cpu.dcache.tags.data_accesses 5747 # Number of data accesses 60311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 1770 # number of ReadReq hits 60411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 1770 # number of ReadReq hits 60511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 60611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 60711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits 60811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits 60911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits 61011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 2276 # number of overall hits 61111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 153 # number of ReadReq misses 61211103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 153 # number of ReadReq misses 61311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 61411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 61511103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses 61611103Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses 61711103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses 61811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 512 # number of overall misses 61911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11315000 # number of ReadReq miss cycles 62011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_latency::total 11315000 # number of ReadReq miss cycles 62111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::cpu.data 23651475 # number of WriteReq miss cycles 62211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_latency::total 23651475 # number of WriteReq miss cycles 62311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::cpu.data 34966475 # number of demand (read+write) miss cycles 62411103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_latency::total 34966475 # number of demand (read+write) miss cycles 62511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::cpu.data 34966475 # number of overall miss cycles 62611103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_latency::total 34966475 # number of overall miss cycles 62711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 1923 # number of ReadReq accesses(hits+misses) 62811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 1923 # number of ReadReq accesses(hits+misses) 62910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 63010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 63111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 2788 # number of demand (read+write) accesses 63211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 2788 # number of demand (read+write) accesses 63311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 2788 # number of overall (read+write) accesses 63411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 2788 # number of overall (read+write) accesses 63511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079563 # miss rate for ReadReq accesses 63611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.079563 # miss rate for ReadReq accesses 63711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 63811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 63911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.183644 # miss rate for demand accesses 64011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.183644 # miss rate for demand accesses 64111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.183644 # miss rate for overall accesses 64211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.183644 # miss rate for overall accesses 64311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73954.248366 # average ReadReq miss latency 64411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_miss_latency::total 73954.248366 # average ReadReq miss latency 64511103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65881.545961 # average WriteReq miss latency 64611103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_miss_latency::total 65881.545961 # average WriteReq miss latency 64711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency 64811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_miss_latency::total 68293.896484 # average overall miss latency 64911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::cpu.data 68293.896484 # average overall miss latency 65011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_miss_latency::total 68293.896484 # average overall miss latency 65111103Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 2328 # number of cycles access was blocked 65210628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 65311103Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked 65410628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 65511103Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs 55.428571 # average number of cycles each access was blocked 65610628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 65710628Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 65810628Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 65911103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 54 # number of ReadReq MSHR hits 66011103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits 66111103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 66211103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits 66311103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::cpu.data 341 # number of demand (read+write) MSHR hits 66411103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_hits::total 341 # number of demand (read+write) MSHR hits 66511103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::cpu.data 341 # number of overall MSHR hits 66611103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits 66711103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses 66811103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses 66910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 67010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 67111103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses 67211103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_misses::total 171 # number of demand (read+write) MSHR misses 67311103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses 67411103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_misses::total 171 # number of overall MSHR misses 67511103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8341000 # number of ReadReq MSHR miss cycles 67611103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_latency::total 8341000 # number of ReadReq MSHR miss cycles 67711103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5669500 # number of WriteReq MSHR miss cycles 67811103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_mshr_miss_latency::total 5669500 # number of WriteReq MSHR miss cycles 67911103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 14010500 # number of demand (read+write) MSHR miss cycles 68011103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_latency::total 14010500 # number of demand (read+write) MSHR miss cycles 68111103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 14010500 # number of overall MSHR miss cycles 68211103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_latency::total 14010500 # number of overall MSHR miss cycles 68311103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051482 # mshr miss rate for ReadReq accesses 68411103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051482 # mshr miss rate for ReadReq accesses 68510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 68610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 68711103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for demand accesses 68811103Snilay@cs.wisc.edusystem.cpu.dcache.demand_mshr_miss_rate::total 0.061334 # mshr miss rate for demand accesses 68911103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061334 # mshr miss rate for overall accesses 69011103Snilay@cs.wisc.edusystem.cpu.dcache.overall_mshr_miss_rate::total 0.061334 # mshr miss rate for overall accesses 69111103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84252.525253 # average ReadReq mshr miss latency 69211103Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84252.525253 # average ReadReq mshr miss latency 69311103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78743.055556 # average WriteReq mshr miss latency 69411103Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78743.055556 # average WriteReq mshr miss latency 69511103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency 69611103Snilay@cs.wisc.edusystem.cpu.dcache.demand_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency 69711103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81932.748538 # average overall mshr miss latency 69811103Snilay@cs.wisc.edusystem.cpu.dcache.overall_avg_mshr_miss_latency::total 81932.748538 # average overall mshr miss latency 69910628Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 7009838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 70111138Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 157.774008 # Cycle average of tags in use 70211103Snilay@cs.wisc.edusystem.cpu.icache.tags.total_refs 1627 # Total number of references to valid blocks. 70311103Snilay@cs.wisc.edusystem.cpu.icache.tags.sampled_refs 311 # Sample count of references to valid blocks. 70411103Snilay@cs.wisc.edusystem.cpu.icache.tags.avg_refs 5.231511 # Average number of references to valid blocks. 7059838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 70611138Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 157.774008 # Average occupied blocks per requestor 70711103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::cpu.inst 0.077038 # Average percentage of cache occupancy 70811103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::total 0.077038 # Average percentage of cache occupancy 70911103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id 71011103Snilay@cs.wisc.edusystem.cpu.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id 71110892Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 71211103Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_task_id_percent::1024 0.151855 # Percentage of cache occupancy per task id 71311103Snilay@cs.wisc.edusystem.cpu.icache.tags.tag_accesses 4483 # Number of tag accesses 71411103Snilay@cs.wisc.edusystem.cpu.icache.tags.data_accesses 4483 # Number of data accesses 71511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::cpu.inst 1627 # number of ReadReq hits 71611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::total 1627 # number of ReadReq hits 71711103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::cpu.inst 1627 # number of demand (read+write) hits 71811103Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::total 1627 # number of demand (read+write) hits 71911103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::cpu.inst 1627 # number of overall hits 72011103Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::total 1627 # number of overall hits 72111103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::cpu.inst 459 # number of ReadReq misses 72211103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::total 459 # number of ReadReq misses 72311103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::cpu.inst 459 # number of demand (read+write) misses 72411103Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::total 459 # number of demand (read+write) misses 72511103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::cpu.inst 459 # number of overall misses 72611103Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::total 459 # number of overall misses 72711138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 32353500 # number of ReadReq miss cycles 72811138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 32353500 # number of ReadReq miss cycles 72911138Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 32353500 # number of demand (read+write) miss cycles 73011138Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 32353500 # number of demand (read+write) miss cycles 73111138Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 32353500 # number of overall miss cycles 73211138Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 32353500 # number of overall miss cycles 73311103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 2086 # number of ReadReq accesses(hits+misses) 73411103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::total 2086 # number of ReadReq accesses(hits+misses) 73511103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::cpu.inst 2086 # number of demand (read+write) accesses 73611103Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::total 2086 # number of demand (read+write) accesses 73711103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::cpu.inst 2086 # number of overall (read+write) accesses 73811103Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::total 2086 # number of overall (read+write) accesses 73911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.220038 # miss rate for ReadReq accesses 74011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.220038 # miss rate for ReadReq accesses 74111103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.220038 # miss rate for demand accesses 74211103Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.220038 # miss rate for demand accesses 74311103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.220038 # miss rate for overall accesses 74411103Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.220038 # miss rate for overall accesses 74511138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70486.928105 # average ReadReq miss latency 74611138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 70486.928105 # average ReadReq miss latency 74711138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency 74811138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 70486.928105 # average overall miss latency 74911138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 70486.928105 # average overall miss latency 75011138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 70486.928105 # average overall miss latency 7518428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7528428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7538428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 7548428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 7558983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7568983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7578428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 7588428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 75911103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 148 # number of ReadReq MSHR hits 76011103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_hits::total 148 # number of ReadReq MSHR hits 76111103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::cpu.inst 148 # number of demand (read+write) MSHR hits 76211103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_hits::total 148 # number of demand (read+write) MSHR hits 76311103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::cpu.inst 148 # number of overall MSHR hits 76411103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_hits::total 148 # number of overall MSHR hits 76511103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses 76611103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_misses::total 311 # number of ReadReq MSHR misses 76711103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses 76811103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_misses::total 311 # number of demand (read+write) MSHR misses 76911103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses 77011103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_misses::total 311 # number of overall MSHR misses 77111138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23860500 # number of ReadReq MSHR miss cycles 77211138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 23860500 # number of ReadReq MSHR miss cycles 77311138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 23860500 # number of demand (read+write) MSHR miss cycles 77411138Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 23860500 # number of demand (read+write) MSHR miss cycles 77511138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 23860500 # number of overall MSHR miss cycles 77611138Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 23860500 # number of overall MSHR miss cycles 77711103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for ReadReq accesses 77811103Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.149089 # mshr miss rate for ReadReq accesses 77911103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for demand accesses 78011103Snilay@cs.wisc.edusystem.cpu.icache.demand_mshr_miss_rate::total 0.149089 # mshr miss rate for demand accesses 78111103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149089 # mshr miss rate for overall accesses 78211103Snilay@cs.wisc.edusystem.cpu.icache.overall_mshr_miss_rate::total 0.149089 # mshr miss rate for overall accesses 78311138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76721.864952 # average ReadReq mshr miss latency 78411138Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76721.864952 # average ReadReq mshr miss latency 78511138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency 78611138Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency 78711138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76721.864952 # average overall mshr miss latency 78811138Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 76721.864952 # average overall mshr miss latency 7898428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7909838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 79111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tagsinuse 218.211579 # Cycle average of tags in use 7929838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 79311103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.sampled_refs 409 # Sample count of references to valid blocks. 79411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.avg_refs 0.002445 # Average number of references to valid blocks. 7959838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 79611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.inst 157.816586 # Average occupied blocks per requestor 79711103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_blocks::cpu.data 60.394993 # Average occupied blocks per requestor 79811103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004816 # Average percentage of cache occupancy 79911103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001843 # Average percentage of cache occupancy 80011103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::total 0.006659 # Average percentage of cache occupancy 80111103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id 80211103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id 80310892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 80411103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.012482 # Percentage of cache occupancy per task id 80511103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.tag_accesses 4337 # Number of tag accesses 80611103Snilay@cs.wisc.edusystem.cpu.l2cache.tags.data_accesses 4337 # Number of data accesses 80710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 80810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 8098835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 8108835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 8118835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 8128835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 81310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 81410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 81511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 310 # number of ReadCleanReq misses 81611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_misses::total 310 # number of ReadCleanReq misses 81711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 99 # number of ReadSharedReq misses 81811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_misses::total 99 # number of ReadSharedReq misses 81911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.inst 310 # number of demand (read+write) misses 82011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.data 171 # number of demand (read+write) misses 82111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses 82211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.inst 310 # number of overall misses 82311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.data 171 # number of overall misses 82411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::total 481 # number of overall misses 82511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5558500 # number of ReadExReq miss cycles 82611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_miss_latency::total 5558500 # number of ReadExReq miss cycles 82711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23380000 # number of ReadCleanReq miss cycles 82811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_latency::total 23380000 # number of ReadCleanReq miss cycles 82911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8185000 # number of ReadSharedReq miss cycles 83011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_miss_latency::total 8185000 # number of ReadSharedReq miss cycles 83111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.inst 23380000 # number of demand (read+write) miss cycles 83211103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::cpu.data 13743500 # number of demand (read+write) miss cycles 83311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_latency::total 37123500 # number of demand (read+write) miss cycles 83411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.inst 23380000 # number of overall miss cycles 83511103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::cpu.data 13743500 # number of overall miss cycles 83611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_latency::total 37123500 # number of overall miss cycles 83710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 83810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 83911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 311 # number of ReadCleanReq accesses(hits+misses) 84011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_accesses::total 311 # number of ReadCleanReq accesses(hits+misses) 84111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) 84211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_accesses::total 99 # number of ReadSharedReq accesses(hits+misses) 84311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.inst 311 # number of demand (read+write) accesses 84411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.data 171 # number of demand (read+write) accesses 84511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::total 482 # number of demand (read+write) accesses 84611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.inst 311 # number of overall (read+write) accesses 84711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.data 171 # number of overall (read+write) accesses 84811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::total 482 # number of overall (read+write) accesses 8498835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8509055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 85111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996785 # miss rate for ReadCleanReq accesses 85211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996785 # miss rate for ReadCleanReq accesses 85310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 85410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 85511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996785 # miss rate for demand accesses 8568835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 85711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::total 0.997925 # miss rate for demand accesses 85811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996785 # miss rate for overall accesses 8598835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 86011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::total 0.997925 # miss rate for overall accesses 86111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77201.388889 # average ReadExReq miss latency 86211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 77201.388889 # average ReadExReq miss latency 86311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75419.354839 # average ReadCleanReq miss latency 86411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75419.354839 # average ReadCleanReq miss latency 86511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82676.767677 # average ReadSharedReq miss latency 86611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82676.767677 # average ReadSharedReq miss latency 86711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency 86811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency 86911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_miss_latency::total 77179.833680 # average overall miss latency 87011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75419.354839 # average overall miss latency 87111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 80371.345029 # average overall miss latency 87211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_miss_latency::total 77179.833680 # average overall miss latency 8738428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8748428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8758428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8768428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8778983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8788983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8798428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8808428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 88110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 88210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 88311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 310 # number of ReadCleanReq MSHR misses 88411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 310 # number of ReadCleanReq MSHR misses 88511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 99 # number of ReadSharedReq MSHR misses 88611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 99 # number of ReadSharedReq MSHR misses 88711103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.inst 310 # number of demand (read+write) MSHR misses 88811103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::cpu.data 171 # number of demand (read+write) MSHR misses 88911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses 89011103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.inst 310 # number of overall MSHR misses 89111103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::cpu.data 171 # number of overall MSHR misses 89211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses 89311103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4838500 # number of ReadExReq MSHR miss cycles 89411103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4838500 # number of ReadExReq MSHR miss cycles 89511103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20280000 # number of ReadCleanReq MSHR miss cycles 89611103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20280000 # number of ReadCleanReq MSHR miss cycles 89711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7195000 # number of ReadSharedReq MSHR miss cycles 89811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7195000 # number of ReadSharedReq MSHR miss cycles 89911103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20280000 # number of demand (read+write) MSHR miss cycles 90011103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12033500 # number of demand (read+write) MSHR miss cycles 90111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_latency::total 32313500 # number of demand (read+write) MSHR miss cycles 90211103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20280000 # number of overall MSHR miss cycles 90311103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12033500 # number of overall MSHR miss cycles 90411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_latency::total 32313500 # number of overall MSHR miss cycles 9058835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 9069055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 90711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for ReadCleanReq accesses 90811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996785 # mshr miss rate for ReadCleanReq accesses 90910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 91010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 91111103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for demand accesses 9128835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 91311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997925 # mshr miss rate for demand accesses 91411103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996785 # mshr miss rate for overall accesses 9158835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 91611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997925 # mshr miss rate for overall accesses 91711103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67201.388889 # average ReadExReq mshr miss latency 91811103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67201.388889 # average ReadExReq mshr miss latency 91911103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65419.354839 # average ReadCleanReq mshr miss latency 92011103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65419.354839 # average ReadCleanReq mshr miss latency 92111103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72676.767677 # average ReadSharedReq mshr miss latency 92211103Snilay@cs.wisc.edusystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72676.767677 # average ReadSharedReq mshr miss latency 92311103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency 92411103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency 92511103Snilay@cs.wisc.edusystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency 92611103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65419.354839 # average overall mshr miss latency 92711103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70371.345029 # average overall mshr miss latency 92811103Snilay@cs.wisc.edusystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 67179.833680 # average overall mshr miss latency 9298428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 93011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 482 # Total number of requests made to the snoop filter. 93111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 93211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 93311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 93411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 93511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 93611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution 93710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 93810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 93911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadCleanReq 311 # Transaction distribution 94011103Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadSharedReq 99 # Transaction distribution 94111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 622 # Packet count per connected master and slave (bytes) 94211103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 342 # Packet count per connected master and slave (bytes) 94311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) 94411103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19904 # Cumulative packet size per connected master and slave (bytes) 94511103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) 94611103Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 94710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 94811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram 94911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.002075 # Request fanout histogram 95011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.045549 # Request fanout histogram 95110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 95211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 481 99.79% 99.79% # Request fanout histogram 95311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram 95410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 95510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 95611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 95710628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 95811103Snilay@cs.wisc.edusystem.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram 95911103Snilay@cs.wisc.edusystem.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) 96010726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 96111103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer0.occupancy 466500 # Layer occupancy (ticks) 96210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 96311103Snilay@cs.wisc.edusystem.cpu.toL2Bus.respLayer1.occupancy 256500 # Layer occupancy (ticks) 96410892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 96511103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadResp 409 # Transaction distribution 96610628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 72 # Transaction distribution 96710628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 72 # Transaction distribution 96811103Snilay@cs.wisc.edusystem.membus.trans_dist::ReadSharedReq 409 # Transaction distribution 96911103Snilay@cs.wisc.edusystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 962 # Packet count per connected master and slave (bytes) 97011103Snilay@cs.wisc.edusystem.membus.pkt_count::total 962 # Packet count per connected master and slave (bytes) 97111103Snilay@cs.wisc.edusystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30784 # Cumulative packet size per connected master and slave (bytes) 97211103Snilay@cs.wisc.edusystem.membus.pkt_size::total 30784 # Cumulative packet size per connected master and slave (bytes) 97310628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 97411103Snilay@cs.wisc.edusystem.membus.snoop_fanout::samples 481 # Request fanout histogram 97510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 97610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 97710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 97811103Snilay@cs.wisc.edusystem.membus.snoop_fanout::0 481 100.00% 100.00% # Request fanout histogram 97910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 98010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 98110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 98210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 98311103Snilay@cs.wisc.edusystem.membus.snoop_fanout::total 481 # Request fanout histogram 98411103Snilay@cs.wisc.edusystem.membus.reqLayer0.occupancy 586000 # Layer occupancy (ticks) 98510726Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.7 # Layer utilization (%) 98611103Snilay@cs.wisc.edusystem.membus.respLayer1.occupancy 2558250 # Layer occupancy (ticks) 98711103Snilay@cs.wisc.edusystem.membus.respLayer1.utilization 11.7 # Layer utilization (%) 9883096SN/A 9893096SN/A---------- End Simulation Statistics ---------- 990