stats.txt revision 10892
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 310726Sandreas.hansson@arm.comsim_seconds 0.000022 # Number of seconds simulated 410892Sandreas.hansson@arm.comsim_ticks 21947000 # Number of ticks simulated 510892Sandreas.hansson@arm.comfinal_tick 21947000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710892Sandreas.hansson@arm.comhost_inst_rate 95577 # Simulator instruction rate (inst/s) 810892Sandreas.hansson@arm.comhost_op_rate 95558 # Simulator op (including micro ops) rate (op/s) 910892Sandreas.hansson@arm.comhost_tick_rate 329070081 # Simulator tick rate (ticks/s) 1010892Sandreas.hansson@arm.comhost_mem_usage 294868 # Number of bytes of host memory used 1110892Sandreas.hansson@arm.comhost_seconds 0.07 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6372 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6372 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169729Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 1710726Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 1810726Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 31104 # Number of bytes read from this memory 199729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 209729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 219729Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 2210726Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory 2310726Sandreas.hansson@arm.comsystem.physmem.num_reads::total 486 # Number of read requests responded to by this memory 2410892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 912744339 # Total read bandwidth from this memory (bytes/s) 2510892Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 504488085 # Total read bandwidth from this memory (bytes/s) 2610892Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1417232424 # Total read bandwidth from this memory (bytes/s) 2710892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 912744339 # Instruction read bandwidth from this memory (bytes/s) 2810892Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 912744339 # Instruction read bandwidth from this memory (bytes/s) 2910892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 912744339 # Total bandwidth to/from this memory (bytes/s) 3010892Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 504488085 # Total bandwidth to/from this memory (bytes/s) 3110892Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1417232424 # Total bandwidth to/from this memory (bytes/s) 3210726Sandreas.hansson@arm.comsystem.physmem.readReqs 486 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3410726Sandreas.hansson@arm.comsystem.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3610726Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 31104 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3910726Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 31104 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 449978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 69 # Per bank write bursts 4510352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 33 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 32 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 47 # Per bank write bursts 4810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 42 # Per bank write bursts 4910352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 20 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 1 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 3 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 0 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 1 # Per bank write bursts 5410726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 22 # Per bank write bursts 5510352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 25 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 14 # Per bank write bursts 5710352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 120 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 45 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 12 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810892Sandreas.hansson@arm.comsystem.physmem.totGap 21815000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8510726Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 486 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see 9410892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see 9510892Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see 9610726Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 9710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 989322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation 19010726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation 19110892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 207.725130 # Bytes accessed per row activation 19210892Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 321.981029 # Bytes accessed per row activation 19310726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation 19410726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation 19510726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation 19610726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 9 11.11% 75.31% # Bytes accessed per row activation 19710726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 6 7.41% 82.72% # Bytes accessed per row activation 19810726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # Bytes accessed per row activation 19910726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation 20010726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation 20110726Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation 20210892Sandreas.hansson@arm.comsystem.physmem.totQLat 4379250 # Total ticks spent queuing 20310892Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 13491750 # Total ticks spent from burst creation until serviced by the DRAM 20410726Sandreas.hansson@arm.comsystem.physmem.totBusLat 2430000 # Total ticks spent in databus transfers 20510892Sandreas.hansson@arm.comsystem.physmem.avgQLat 9010.80 # Average queueing delay per DRAM burst 2069978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20710892Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 27760.80 # Average memory access latency per DRAM burst 20810892Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1417.23 # Average DRAM read bandwidth in MiByte/s 2099978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21010892Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1417.23 # Average system read bandwidth in MiByte/s 2119978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21310892Sandreas.hansson@arm.comsystem.physmem.busUtil 11.07 # Data bus utilization in percentage 21410892Sandreas.hansson@arm.comsystem.physmem.busUtilRead 11.07 # Data bus utilization in percentage for reads 2159978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21610726Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing 2179978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21810352Sandreas.hansson@arm.comsystem.physmem.readRowHits 390 # Number of row buffer hits during reads 2199312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22010726Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads 2219312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22210892Sandreas.hansson@arm.comsystem.physmem.avgGap 44886.83 # Average gap between requests 22310726Sandreas.hansson@arm.comsystem.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined 22410726Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) 22510726Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) 22610726Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ) 22710628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 22810628Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 22910726Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) 23010628Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) 23110726Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ) 23210726Sandreas.hansson@arm.comsystem.physmem_0.averagePower 873.750829 # Core power per rank (mW) 23310892Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states 23410628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 520000 # Time in different power states 23510628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23610726Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states 23710628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 23810726Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ) 23910726Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ) 24010892Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 1271400 # Energy for read commands per rank (pJ) 24110628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24210628Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 24310892Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 10129185 # Energy for active background per rank (pJ) 24410892Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 614250 # Energy for precharge background per rank (pJ) 24510892Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 13534410 # Total energy per rank (pJ) 24610892Sandreas.hansson@arm.comsystem.physmem_1.averagePower 854.849834 # Core power per rank (mW) 24710892Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 953500 # Time in different power states 24810628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 520000 # Time in different power states 24910628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25010892Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 14372750 # Time in different power states 25110628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25210892Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2810 # Number of BP lookups 25310892Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted 25410892Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 478 # Number of conditional branches incorrect 25510892Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 2116 # Number of BTB lookups 25610892Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 679 # Number of BTB hits 2579481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 25810892Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 32.088847 # BTB Hit Percentage 25910892Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 396 # Number of times the RAS was used to get a target. 26010892Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 29 # Number of incorrect RAS predictions. 26110628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2628428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2638428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2648428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2658428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 26610726Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 2105 # DTB read hits 26710892Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 55 # DTB read misses 2688428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 26910892Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 2160 # DTB read accesses 27010726Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 1074 # DTB write hits 27110352Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 30 # DTB write misses 2728428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 27310726Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 1104 # DTB write accesses 27410726Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 3179 # DTB hits 27510892Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 85 # DTB misses 2768428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 27710892Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 3264 # DTB accesses 27810892Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 2194 # ITB hits 27910726Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 34 # ITB misses 2808428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 28110892Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 2228 # ITB accesses 2828428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2838428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2848428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2858428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2868428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2878428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2888428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2898428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2908428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2918428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2928428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2938428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2948428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 29510892Sandreas.hansson@arm.comsystem.cpu.numCycles 43895 # number of cpu cycles simulated 2968428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2978428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 29810892Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8597 # Number of cycles fetch is stalled on an Icache miss 29910892Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 16278 # Number of instructions fetch has processed 30010892Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2810 # Number of branches that fetch encountered 30110892Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 1075 # Number of branches that fetch has predicted taken 30210892Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 4298 # Number of cycles fetch has run and was not squashing or blocked 30310892Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1038 # Number of cycles fetch has spent squashing 3049729Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 30510892Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 740 # Number of stall cycles due to pending traps 30610892Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 2194 # Number of cache lines fetched 30710892Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed 30810892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 14179 # Number of instructions fetched each cycle (Total) 30910892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.148036 # Number of instructions fetched each cycle (Total) 31010892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.557344 # Number of instructions fetched each cycle (Total) 3116291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 31210892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 11320 79.84% 79.84% # Number of instructions fetched each cycle (Total) 31310892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 289 2.04% 81.87% # Number of instructions fetched each cycle (Total) 31410892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 216 1.52% 83.40% # Number of instructions fetched each cycle (Total) 31510726Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total) 31610892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 243 1.71% 86.55% # Number of instructions fetched each cycle (Total) 31710892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 208 1.47% 88.02% # Number of instructions fetched each cycle (Total) 31810892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 242 1.71% 89.72% # Number of instructions fetched each cycle (Total) 31910892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 175 1.23% 90.96% # Number of instructions fetched each cycle (Total) 32010892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1282 9.04% 100.00% # Number of instructions fetched each cycle (Total) 3216291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3226291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3236291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 32410892Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 14179 # Number of instructions fetched each cycle (Total) 32510892Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.064016 # Number of branch fetches per cycle 32610892Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.370840 # Number of inst fetches per cycle 32710892Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 8623 # Number of cycles decode is idle 32810892Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 2500 # Number of cycles decode is blocked 32910892Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2414 # Number of cycles decode is running 33010892Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 200 # Number of cycles decode is unblocking 33110892Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 442 # Number of cycles decode is squashing 33210726Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch 33310892Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 81 # Number of times decode detected a branch misprediction 33410892Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 14886 # Number of instructions handled by decode 33510352Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode 33610892Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 442 # Number of cycles rename is squashing 33710892Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 8796 # Number of cycles rename is idle 33810892Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 1074 # Number of cycles rename is blocking 33910892Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 427 # count of cycles rename stalled for serializing inst 34010892Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2425 # Number of cycles rename is running 34110892Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 1015 # Number of cycles rename is unblocking 34210892Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 14276 # Number of instructions processed by rename 34310726Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full 34410892Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full 34510892Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 33 # Number of times rename has blocked due to LQ full 34610892Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 937 # Number of times rename has blocked due to SQ full 34710892Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 10794 # Number of destination operands rename has renamed 34810892Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 17927 # Number of register rename lookups that rename has made 34910892Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 17918 # Number of integer rename lookups 3509924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 3519150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 35210892Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6224 # Number of HB maps that are undone due to squashing 35310352Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 32 # count of serializing insts renamed 35410352Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed 35510892Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 538 # count of insts added to the skid buffer 35610726Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit. 35710726Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit. 35810726Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. 3598428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 36010892Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 12940 # Number of instructions added to the IQ (excludes non-spec) 36110352Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ 36210892Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 10735 # Number of instructions issued 36310726Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued 36410892Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6595 # Number of squashed instructions iterated over during squash; mainly for profiling 36510892Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3561 # Number of squashed operands that are examined and possibly removed from graph 36610352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed 36710892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 14179 # Number of insts issued each cycle 36810892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.757106 # Number of insts issued each cycle 36910892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.490778 # Number of insts issued each cycle 3708428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 37110892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10173 71.75% 71.75% # Number of insts issued each cycle 37210892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1278 9.01% 80.76% # Number of insts issued each cycle 37310892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 898 6.33% 87.09% # Number of insts issued each cycle 37410892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 679 4.79% 91.88% # Number of insts issued each cycle 37510892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 528 3.72% 95.61% # Number of insts issued each cycle 37610892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 333 2.35% 97.95% # Number of insts issued each cycle 37710892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 209 1.47% 99.43% # Number of insts issued each cycle 37810892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 55 0.39% 99.82% # Number of insts issued each cycle 37910892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle 3808428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3818428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3828428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 38310892Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 14179 # Number of insts issued each cycle 3848428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 38510892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 29 20.14% 20.14% # attempts to use FU when none available 38610892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available 38710892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available 38810892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 20.14% # attempts to use FU when none available 38910892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 20.14% # attempts to use FU when none available 39010892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 20.14% # attempts to use FU when none available 39110892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 20.14% # attempts to use FU when none available 39210892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 20.14% # attempts to use FU when none available 39310892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.14% # attempts to use FU when none available 39410892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 20.14% # attempts to use FU when none available 39510892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.14% # attempts to use FU when none available 39610892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 20.14% # attempts to use FU when none available 39710892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 20.14% # attempts to use FU when none available 39810892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 20.14% # attempts to use FU when none available 39910892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 20.14% # attempts to use FU when none available 40010892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 20.14% # attempts to use FU when none available 40110892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.14% # attempts to use FU when none available 40210892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 20.14% # attempts to use FU when none available 40310892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.14% # attempts to use FU when none available 40410892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.14% # attempts to use FU when none available 40510892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.14% # attempts to use FU when none available 40610892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.14% # attempts to use FU when none available 40710892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.14% # attempts to use FU when none available 40810892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.14% # attempts to use FU when none available 40910892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.14% # attempts to use FU when none available 41010892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.14% # attempts to use FU when none available 41110892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.14% # attempts to use FU when none available 41210892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.14% # attempts to use FU when none available 41310892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.14% # attempts to use FU when none available 41410892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 73 50.69% 70.83% # attempts to use FU when none available 41510892Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 42 29.17% 100.00% # attempts to use FU when none available 4168428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4178428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4188241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 41910892Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 7243 67.47% 67.49% # Type of FU issued 42010726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued 42110726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued 42210726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued 42310726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued 42410726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued 42510726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued 42610726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued 42710726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued 42810726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued 42910726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued 43010726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued 43110726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued 43210726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued 43310726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued 43410726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued 43510726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued 43610726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued 43710726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued 43810726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued 43910726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued 44010726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued 44110726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued 44210726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued 44310726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued 44410726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Type of FU issued 44510726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued 44610726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued 44710726Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued 44810892Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2356 21.95% 89.46% # Type of FU issued 44910892Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1131 10.54% 100.00% # Type of FU issued 4508241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4518241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 45210892Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 10735 # Type of FU issued 45310892Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.244561 # Inst issue rate 45410892Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 144 # FU busy when requested 45510892Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.013414 # FU busy rate (busy events/executed inst) 45610892Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 35792 # Number of integer instruction queue reads 45710892Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 19571 # Number of integer instruction queue writes 45810892Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9784 # Number of integer instruction queue wakeup accesses 4598428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 4608428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 4618428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 46210892Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 10866 # Number of integer alu accesses 4638428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 46410892Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 71 # Number of loads that had data forwarded from stores 4658428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 46610726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed 46710352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 46810352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 46910726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed 4708428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4718428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4728428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 47310726Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked 4748428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 47510892Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 442 # Number of cycles IEW is squashing 47610892Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 1033 # Number of cycles IEW is blocking 47710892Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 23 # Number of cycles IEW is unblocking 47810892Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 13054 # Number of instructions dispatched to IQ 47910726Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch 48010726Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions 48110726Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions 48210352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions 48310892Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall 48410892Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 20 # Number of times the LSQ has become full, causing a stall 48510352Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations 48610726Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly 48710892Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 395 # Number of branches that were predicted not taken incorrectly 48810892Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 476 # Number of branch mispredicts detected at execute 48910892Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 10242 # Number of executed instructions 49010892Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2163 # Number of load instructions executed 49110892Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 493 # Number of squashed instructions skipped in execute 4928428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 49310726Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 86 # number of nop insts executed 49410892Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3269 # number of memory reference insts executed 49510892Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1598 # Number of branches executed 49610726Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1106 # Number of stores executed 49710892Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.233330 # Inst execution rate 49810892Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 9957 # cumulative count of insts sent to commit 49910892Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 9794 # cumulative count of insts written-back 50010892Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 5300 # num instructions producing a value 50110892Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 7297 # num instructions consuming a value 5028428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 50310892Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.223123 # insts written-back per cycle 50410892Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.726326 # average fanout of values written-back 5058428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 50610892Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6664 # The number of squashed insts skipped by commit 5078428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 50810892Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted 50910892Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 12978 # Number of insts commited each cycle 51010892Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.492295 # Number of insts commited each cycle 51110892Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.405132 # Number of insts commited each cycle 5128428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 51310892Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 10520 81.06% 81.06% # Number of insts commited each cycle 51410892Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1167 8.99% 90.05% # Number of insts commited each cycle 51510892Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 504 3.88% 93.94% # Number of insts commited each cycle 51610726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle 51710892Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 136 1.05% 96.59% # Number of insts commited each cycle 51810892Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 76 0.59% 97.18% # Number of insts commited each cycle 51910726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle 52010726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle 52110726Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle 5228428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5238428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5248428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 52510892Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 12978 # Number of insts commited each cycle 5269150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6389 # Number of instructions committed 5279150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 5288428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5299150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2048 # Number of memory references committed 5309150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1183 # Number of loads committed 5318428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 5329150SAli.Saidi@ARM.comsystem.cpu.commit.branches 1050 # Number of branches committed 5338428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 5349150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 6307 # Number of committed integer instructions. 5358428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 53610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 53710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction 53810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction 53910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction 54010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction 54110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction 54210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction 54310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction 54410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction 54510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 54610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction 54710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 54810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction 54910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction 55010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction 55110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction 55210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction 55310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 55410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction 55510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 55610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 55710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 55810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 55910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 56010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 56110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 56210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 56310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 56410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 56510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 56610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 56710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 56810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 56910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 57010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 6389 # Class of committed instruction 57110726Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached 57210892Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 25490 # The number of ROB reads 57310892Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 27321 # The number of ROB writes 57410892Sandreas.hansson@arm.comsystem.cpu.timesIdled 258 # Number of times that the entire CPU went into an idle state and unscheduled itself 57510892Sandreas.hansson@arm.comsystem.cpu.idleCycles 29716 # Total number of cycles that the CPU has spent unscheduled due to idling 5769150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6372 # Number of Instructions Simulated 5779150SAli.Saidi@ARM.comsystem.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 57810892Sandreas.hansson@arm.comsystem.cpu.cpi 6.888732 # CPI: Cycles Per Instruction 57910892Sandreas.hansson@arm.comsystem.cpu.cpi_total 6.888732 # CPI: Total CPI of All Threads 58010892Sandreas.hansson@arm.comsystem.cpu.ipc 0.145165 # IPC: Instructions Per Cycle 58110892Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.145165 # IPC: Total IPC of All Threads 58210892Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 13013 # number of integer regfile reads 58310892Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7460 # number of integer regfile writes 5848428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 5858428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 5868428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 5878428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 58810628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 58910892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 107.548347 # Cycle average of tags in use 59010892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2343 # Total number of references to valid blocks. 59110726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. 59210892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 13.543353 # Average number of references to valid blocks. 59310628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 59410892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 107.548347 # Average occupied blocks per requestor 59510892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.026257 # Average percentage of cache occupancy 59610892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.026257 # Average percentage of cache occupancy 59710726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id 59810726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 59910726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id 60010726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id 60110892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 5891 # Number of tag accesses 60210892Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 5891 # Number of data accesses 60310892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1835 # number of ReadReq hits 60410892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1835 # number of ReadReq hits 60510892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits 60610892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits 60710892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2343 # number of demand (read+write) hits 60810892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2343 # number of demand (read+write) hits 60910892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2343 # number of overall hits 61010892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2343 # number of overall hits 61110892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 159 # number of ReadReq misses 61210892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 159 # number of ReadReq misses 61310892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses 61410892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses 61510892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 516 # number of demand (read+write) misses 61610892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 516 # number of demand (read+write) misses 61710892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 516 # number of overall misses 61810892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 516 # number of overall misses 61910892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11993500 # number of ReadReq miss cycles 62010892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11993500 # number of ReadReq miss cycles 62110892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 24175975 # number of WriteReq miss cycles 62210892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 24175975 # number of WriteReq miss cycles 62310892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 36169475 # number of demand (read+write) miss cycles 62410892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 36169475 # number of demand (read+write) miss cycles 62510892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 36169475 # number of overall miss cycles 62610892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 36169475 # number of overall miss cycles 62710892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1994 # number of ReadReq accesses(hits+misses) 62810892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) 62910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 63010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 63110892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2859 # number of demand (read+write) accesses 63210892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2859 # number of demand (read+write) accesses 63310892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2859 # number of overall (read+write) accesses 63410892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2859 # number of overall (read+write) accesses 63510892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079739 # miss rate for ReadReq accesses 63610892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.079739 # miss rate for ReadReq accesses 63710892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses 63810892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses 63910892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.180483 # miss rate for demand accesses 64010892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.180483 # miss rate for demand accesses 64110892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.180483 # miss rate for overall accesses 64210892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.180483 # miss rate for overall accesses 64310892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75430.817610 # average ReadReq miss latency 64410892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 75430.817610 # average ReadReq miss latency 64510892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67719.817927 # average WriteReq miss latency 64610892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 67719.817927 # average WriteReq miss latency 64710892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency 64810892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 70095.881783 # average overall miss latency 64910892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 70095.881783 # average overall miss latency 65010892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 70095.881783 # average overall miss latency 65110892Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 2284 # number of cycles access was blocked 65210628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 65310892Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 41 # number of cycles access was blocked 65410628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 65510892Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 55.707317 # average number of cycles each access was blocked 65610628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 65710628Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 65810628Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 65910892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits 66010892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits 66110892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits 66210892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits 66310892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 343 # number of demand (read+write) MSHR hits 66410892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 343 # number of demand (read+write) MSHR hits 66510892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 343 # number of overall MSHR hits 66610892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 343 # number of overall MSHR hits 66710726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 66810726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 66910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 67010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 67110726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 67210726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 67310726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 67410726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses 67510892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8588000 # number of ReadReq MSHR miss cycles 67610892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 8588000 # number of ReadReq MSHR miss cycles 67710892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5911000 # number of WriteReq MSHR miss cycles 67810892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 5911000 # number of WriteReq MSHR miss cycles 67910892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 14499000 # number of demand (read+write) MSHR miss cycles 68010892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 14499000 # number of demand (read+write) MSHR miss cycles 68110892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 14499000 # number of overall MSHR miss cycles 68210892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 14499000 # number of overall MSHR miss cycles 68310892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050652 # mshr miss rate for ReadReq accesses 68410892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050652 # mshr miss rate for ReadReq accesses 68510628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 68610628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 68710892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for demand accesses 68810892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.060511 # mshr miss rate for demand accesses 68910892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060511 # mshr miss rate for overall accesses 69010892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.060511 # mshr miss rate for overall accesses 69110892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 85029.702970 # average ReadReq mshr miss latency 69210892Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 85029.702970 # average ReadReq mshr miss latency 69310892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82097.222222 # average WriteReq mshr miss latency 69410892Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82097.222222 # average WriteReq mshr miss latency 69510892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency 69610892Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency 69710892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83809.248555 # average overall mshr miss latency 69810892Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 83809.248555 # average overall mshr miss latency 69910628Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 7009838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 70110892Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 158.228991 # Cycle average of tags in use 70210892Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1714 # Total number of references to valid blocks. 7039838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. 70410892Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 5.458599 # Average number of references to valid blocks. 7059838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 70610892Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 158.228991 # Average occupied blocks per requestor 70710892Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.077260 # Average percentage of cache occupancy 70810892Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.077260 # Average percentage of cache occupancy 70910036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id 71010892Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id 71110892Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id 71210036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id 71310892Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 4702 # Number of tag accesses 71410892Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 4702 # Number of data accesses 71510892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1714 # number of ReadReq hits 71610892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1714 # number of ReadReq hits 71710892Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1714 # number of demand (read+write) hits 71810892Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1714 # number of demand (read+write) hits 71910892Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1714 # number of overall hits 72010892Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1714 # number of overall hits 72110892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 480 # number of ReadReq misses 72210892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 480 # number of ReadReq misses 72310892Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 480 # number of demand (read+write) misses 72410892Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses 72510892Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses 72610892Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 480 # number of overall misses 72710892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 33574500 # number of ReadReq miss cycles 72810892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 33574500 # number of ReadReq miss cycles 72910892Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 33574500 # number of demand (read+write) miss cycles 73010892Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 33574500 # number of demand (read+write) miss cycles 73110892Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 33574500 # number of overall miss cycles 73210892Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 33574500 # number of overall miss cycles 73310892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2194 # number of ReadReq accesses(hits+misses) 73410892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2194 # number of ReadReq accesses(hits+misses) 73510892Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2194 # number of demand (read+write) accesses 73610892Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2194 # number of demand (read+write) accesses 73710892Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2194 # number of overall (read+write) accesses 73810892Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2194 # number of overall (read+write) accesses 73910892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218778 # miss rate for ReadReq accesses 74010892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.218778 # miss rate for ReadReq accesses 74110892Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.218778 # miss rate for demand accesses 74210892Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.218778 # miss rate for demand accesses 74310892Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.218778 # miss rate for overall accesses 74410892Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.218778 # miss rate for overall accesses 74510892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69946.875000 # average ReadReq miss latency 74610892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 69946.875000 # average ReadReq miss latency 74710892Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 69946.875000 # average overall miss latency 74810892Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 69946.875000 # average overall miss latency 74910892Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 69946.875000 # average overall miss latency 75010892Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 69946.875000 # average overall miss latency 7518428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7528428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7538428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 7548428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 7558983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7568983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7578428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 7588428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 75910892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 166 # number of ReadReq MSHR hits 76010892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 166 # number of ReadReq MSHR hits 76110892Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 166 # number of demand (read+write) MSHR hits 76210892Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 166 # number of demand (read+write) MSHR hits 76310892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 166 # number of overall MSHR hits 76410892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 166 # number of overall MSHR hits 76510352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 76610352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses 76710352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 76810352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses 76910352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 77010352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses 77110892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24137500 # number of ReadReq MSHR miss cycles 77210892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 24137500 # number of ReadReq MSHR miss cycles 77310892Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 24137500 # number of demand (read+write) MSHR miss cycles 77410892Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 24137500 # number of demand (read+write) MSHR miss cycles 77510892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 24137500 # number of overall MSHR miss cycles 77610892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 24137500 # number of overall MSHR miss cycles 77710892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143118 # mshr miss rate for ReadReq accesses 77810892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.143118 # mshr miss rate for ReadReq accesses 77910892Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143118 # mshr miss rate for demand accesses 78010892Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.143118 # mshr miss rate for demand accesses 78110892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143118 # mshr miss rate for overall accesses 78210892Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.143118 # mshr miss rate for overall accesses 78310892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76871.019108 # average ReadReq mshr miss latency 78410892Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76871.019108 # average ReadReq mshr miss latency 78510892Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76871.019108 # average overall mshr miss latency 78610892Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 76871.019108 # average overall mshr miss latency 78710892Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76871.019108 # average overall mshr miss latency 78810892Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 76871.019108 # average overall mshr miss latency 7898428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7909838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 79110892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 218.935718 # Cycle average of tags in use 7929838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 79310726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. 79410726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. 7959838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 79610892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 158.272937 # Average occupied blocks per requestor 79710892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 60.662780 # Average occupied blocks per requestor 79810892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004830 # Average percentage of cache occupancy 79910892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001851 # Average percentage of cache occupancy 80010892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006681 # Average percentage of cache occupancy 80110726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id 80210892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 80310892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 80410726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.012634 # Percentage of cache occupancy per task id 80510726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 4382 # Number of tag accesses 80610726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 4382 # Number of data accesses 80710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 80810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 8098835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 8108835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 8118835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 8128835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 81310242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 81410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 81510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 313 # number of ReadCleanReq misses 81610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 313 # number of ReadCleanReq misses 81710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 81810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses 81910352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses 82010726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses 82110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses 82210352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses 82310726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses 82410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 486 # number of overall misses 82510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5800000 # number of ReadExReq miss cycles 82610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 5800000 # number of ReadExReq miss cycles 82710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 23655000 # number of ReadCleanReq miss cycles 82810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 23655000 # number of ReadCleanReq miss cycles 82910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 8428500 # number of ReadSharedReq miss cycles 83010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 8428500 # number of ReadSharedReq miss cycles 83110892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 23655000 # number of demand (read+write) miss cycles 83210892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 14228500 # number of demand (read+write) miss cycles 83310892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 37883500 # number of demand (read+write) miss cycles 83410892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 23655000 # number of overall miss cycles 83510892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 14228500 # number of overall miss cycles 83610892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 37883500 # number of overall miss cycles 83710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 83810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 83910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 314 # number of ReadCleanReq accesses(hits+misses) 84010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 314 # number of ReadCleanReq accesses(hits+misses) 84110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) 84210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) 84310352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses 84410726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses 84510726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses 84610352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses 84710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses 84810726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses 8498835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8509055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 85110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadCleanReq accesses 85210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996815 # miss rate for ReadCleanReq accesses 85310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 85410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 85510352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses 8568835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 85710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses 85810352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses 8598835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 86010726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses 86110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80555.555556 # average ReadExReq miss latency 86210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 80555.555556 # average ReadExReq miss latency 86310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75575.079872 # average ReadCleanReq miss latency 86410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75575.079872 # average ReadCleanReq miss latency 86510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83450.495050 # average ReadSharedReq miss latency 86610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83450.495050 # average ReadSharedReq miss latency 86710892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75575.079872 # average overall miss latency 86810892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 82245.664740 # average overall miss latency 86910892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 77949.588477 # average overall miss latency 87010892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75575.079872 # average overall miss latency 87110892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 82245.664740 # average overall miss latency 87210892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 77949.588477 # average overall miss latency 8738428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 8748428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 8758428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 8768428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 8778983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 8788983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 8798428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 8808428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 88110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 88210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 88310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 313 # number of ReadCleanReq MSHR misses 88410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 313 # number of ReadCleanReq MSHR misses 88510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 88610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses 88710352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 88810726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 88910726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses 89010352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 89110726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 89210726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses 89310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5080000 # number of ReadExReq MSHR miss cycles 89410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5080000 # number of ReadExReq MSHR miss cycles 89510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 20525000 # number of ReadCleanReq MSHR miss cycles 89610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 20525000 # number of ReadCleanReq MSHR miss cycles 89710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7418500 # number of ReadSharedReq MSHR miss cycles 89810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7418500 # number of ReadSharedReq MSHR miss cycles 89910892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20525000 # number of demand (read+write) MSHR miss cycles 90010892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12498500 # number of demand (read+write) MSHR miss cycles 90110892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 33023500 # number of demand (read+write) MSHR miss cycles 90210892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20525000 # number of overall MSHR miss cycles 90310892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12498500 # number of overall MSHR miss cycles 90410892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 33023500 # number of overall MSHR miss cycles 9058835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 9069055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 90710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadCleanReq accesses 90810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996815 # mshr miss rate for ReadCleanReq accesses 90910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 91010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 91110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses 9128835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 91310726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses 91410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses 9158835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 91610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses 91710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70555.555556 # average ReadExReq mshr miss latency 91810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70555.555556 # average ReadExReq mshr miss latency 91910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65575.079872 # average ReadCleanReq mshr miss latency 92010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65575.079872 # average ReadCleanReq mshr miss latency 92110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73450.495050 # average ReadSharedReq mshr miss latency 92210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73450.495050 # average ReadSharedReq mshr miss latency 92310892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency 92410892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency 92510892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency 92610892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65575.079872 # average overall mshr miss latency 92710892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72245.664740 # average overall mshr miss latency 92810892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 67949.588477 # average overall mshr miss latency 9298428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 93010726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution 93110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 93210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 93310892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 314 # Transaction distribution 93410892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution 93510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) 93610726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) 93710726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes) 93810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) 93910726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) 94010726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) 94110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 94210726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 487 # Request fanout histogram 94310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 94410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 94510628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 94610628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 94710726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 487 100.00% 100.00% # Request fanout histogram 94810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 94910628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 95010628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 95110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 95210726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram 95310726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks) 95410726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 95510892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 471000 # Layer occupancy (ticks) 95610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) 95710892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) 95810892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 95910726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 414 # Transaction distribution 96010628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 72 # Transaction distribution 96110628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 72 # Transaction distribution 96210892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 414 # Transaction distribution 96310726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes) 96410726Sandreas.hansson@arm.comsystem.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes) 96510726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes) 96610726Sandreas.hansson@arm.comsystem.membus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) 96710628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 96810726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 486 # Request fanout histogram 96910628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 97010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 97110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 97210726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 486 100.00% 100.00% # Request fanout histogram 97310628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 97410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 97510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 97610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 97710726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 486 # Request fanout histogram 97810892Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 594500 # Layer occupancy (ticks) 97910726Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 2.7 # Layer utilization (%) 98010892Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2585500 # Layer occupancy (ticks) 98110892Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 11.8 # Layer utilization (%) 9823096SN/A 9833096SN/A---------- End Simulation Statistics ---------- 984