stats.txt revision 10409
13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 39729Sandreas.hansson@arm.comsim_seconds 0.000021 # Number of seconds simulated 410352Sandreas.hansson@arm.comsim_ticks 20537500 # Number of ticks simulated 510352Sandreas.hansson@arm.comfinal_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710409Sandreas.hansson@arm.comhost_inst_rate 100086 # Simulator instruction rate (inst/s) 810409Sandreas.hansson@arm.comhost_op_rate 100066 # Simulator op (including micro ops) rate (op/s) 910409Sandreas.hansson@arm.comhost_tick_rate 322455292 # Simulator tick rate (ticks/s) 1010409Sandreas.hansson@arm.comhost_mem_usage 290128 # Number of bytes of host memory used 1110409Sandreas.hansson@arm.comhost_seconds 0.06 # Real time elapsed on the host 129150SAli.Saidi@ARM.comsim_insts 6372 # Number of instructions simulated 139150SAli.Saidi@ARM.comsim_ops 6372 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169729Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory 179322Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory 189729Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 31168 # Number of bytes read from this memory 199729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory 209729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory 219729Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory 229322Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory 239729Sandreas.hansson@arm.comsystem.physmem.num_reads::total 487 # Number of read requests responded to by this memory 2410352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 975386488 # Total read bandwidth from this memory (bytes/s) 2510352Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 542227632 # Total read bandwidth from this memory (bytes/s) 2610352Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1517614121 # Total read bandwidth from this memory (bytes/s) 2710352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 975386488 # Instruction read bandwidth from this memory (bytes/s) 2810352Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 975386488 # Instruction read bandwidth from this memory (bytes/s) 2910352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 975386488 # Total bandwidth to/from this memory (bytes/s) 3010352Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 542227632 # Total bandwidth to/from this memory (bytes/s) 3110352Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1517614121 # Total bandwidth to/from this memory (bytes/s) 3210352Sandreas.hansson@arm.comsystem.physmem.readReqs 487 # Number of read requests accepted 339978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3410352Sandreas.hansson@arm.comsystem.physmem.readBursts 487 # Number of DRAM read bursts, including those serviced by the write queue 359978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3610352Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 31168 # Total number of bytes read from DRAM 379978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 389978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 3910352Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 31168 # Total read bytes from the system interface side 409978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 429978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 439978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 449978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 69 # Per bank write bursts 4510352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 33 # Per bank write bursts 469978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 32 # Per bank write bursts 479978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 47 # Per bank write bursts 4810352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 42 # Per bank write bursts 4910352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 20 # Per bank write bursts 509978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 1 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 3 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 0 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 1 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 23 # Per bank write bursts 5510352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 25 # Per bank write bursts 569978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 14 # Per bank write bursts 5710352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 120 # Per bank write bursts 589978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 45 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 12 # Per bank write bursts 609978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 779978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7810352Sandreas.hansson@arm.comsystem.physmem.totGap 20412000 # Total gap between requests 799978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8510352Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 487 # Read request sizes (log2) 869978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9310352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see 9410352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see 9510242Ssteve.reinhardt@amd.comsystem.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 9610352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 9710352Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 989322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 999312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 18910352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation 19010352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 341.853659 # Bytes accessed per row activation 19110352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 204.819475 # Bytes accessed per row activation 19210352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 342.253502 # Bytes accessed per row activation 19310352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 28 34.15% 34.15% # Bytes accessed per row activation 19410352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 17 20.73% 54.88% # Bytes accessed per row activation 19510352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 9 10.98% 65.85% # Bytes accessed per row activation 19610352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 8 9.76% 75.61% # Bytes accessed per row activation 19710352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 4 4.88% 80.49% # Bytes accessed per row activation 19810352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1 1.22% 81.71% # Bytes accessed per row activation 19910352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 1 1.22% 82.93% # Bytes accessed per row activation 20010352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation 20110352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation 20210352Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation 20310409Sandreas.hansson@arm.comsystem.physmem.totQLat 4742750 # Total ticks spent queuing 20410409Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 13874000 # Total ticks spent from burst creation until serviced by the DRAM 20510352Sandreas.hansson@arm.comsystem.physmem.totBusLat 2435000 # Total ticks spent in databus transfers 20610409Sandreas.hansson@arm.comsystem.physmem.avgQLat 9738.71 # Average queueing delay per DRAM burst 2079978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20810409Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 28488.71 # Average memory access latency per DRAM burst 20910352Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s 2109978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21110352Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s 2129978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21410352Sandreas.hansson@arm.comsystem.physmem.busUtil 11.86 # Data bus utilization in percentage 21510352Sandreas.hansson@arm.comsystem.physmem.busUtilRead 11.86 # Data bus utilization in percentage for reads 2169978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21710352Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing 2189978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 21910352Sandreas.hansson@arm.comsystem.physmem.readRowHits 390 # Number of row buffer hits during reads 2209312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22110352Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads 2229312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22310352Sandreas.hansson@arm.comsystem.physmem.avgGap 41913.76 # Average gap between requests 22410352Sandreas.hansson@arm.comsystem.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined 22510220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::IDLE 22000 # Time in different power states 22610220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::REF 520000 # Time in different power states 22710220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 22810352Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT 15339250 # Time in different power states 22910220Sandreas.hansson@arm.comsystem.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 23010352Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 415 # Transaction distribution 23110242Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadResp 415 # Transaction distribution 23210242Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadExReq 72 # Transaction distribution 23310242Ssteve.reinhardt@amd.comsystem.membus.trans_dist::ReadExResp 72 # Transaction distribution 23410352Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) 23510352Sandreas.hansson@arm.comsystem.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) 23610409Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) 23710409Sandreas.hansson@arm.comsystem.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) 23810409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 23910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 487 # Request fanout histogram 24010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 24110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 24210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 24310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram 24410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 24510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 24610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 24710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 24810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 487 # Request fanout histogram 24910352Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) 25010352Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 25110352Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) 25210352Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 22.2 # Layer utilization (%) 25310036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 25410352Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2806 # Number of BP lookups 25510352Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted 25610352Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect 25710352Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 2112 # Number of BTB lookups 25810352Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 686 # Number of BTB hits 2599481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26010352Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage 26110352Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. 26210352Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. 2638428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2648428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2658428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2668428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 26710352Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 2085 # DTB read hits 26810352Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 55 # DTB read misses 2698428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 27010352Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 2140 # DTB read accesses 27110352Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 1069 # DTB write hits 27210352Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 30 # DTB write misses 2738428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 27410352Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 1099 # DTB write accesses 27510352Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 3154 # DTB hits 27610352Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 85 # DTB misses 2778428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 27810352Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 3239 # DTB accesses 27910352Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 2196 # ITB hits 28010352Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 38 # ITB misses 2818428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 28210352Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 2234 # ITB accesses 2838428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2848428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2858428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 2868428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2878428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2888428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 2898428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 2908428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 2918428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 2928428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 2938428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 2948428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 2958428SN/Asystem.cpu.workload.num_syscalls 17 # Number of system calls 29610352Sandreas.hansson@arm.comsystem.cpu.numCycles 41076 # number of cpu cycles simulated 2978428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2988428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 29910352Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8744 # Number of cycles fetch is stalled on an Icache miss 30010352Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 16221 # Number of instructions fetch has processed 30110352Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2806 # Number of branches that fetch encountered 30210352Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 1081 # Number of branches that fetch has predicted taken 30310352Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 4165 # Number of cycles fetch has run and was not squashing or blocked 30410352Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1040 # Number of cycles fetch has spent squashing 3059729Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 30610352Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 801 # Number of stall cycles due to pending traps 30710352Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 2196 # Number of cache lines fetched 30810352Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed 30910352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 14255 # Number of instructions fetched each cycle (Total) 31010352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.137917 # Number of instructions fetched each cycle (Total) 31110352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.547719 # Number of instructions fetched each cycle (Total) 3126291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 31310352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 11405 80.01% 80.01% # Number of instructions fetched each cycle (Total) 31410352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 289 2.03% 82.03% # Number of instructions fetched each cycle (Total) 31510352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 215 1.51% 83.54% # Number of instructions fetched each cycle (Total) 31610352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 201 1.41% 84.95% # Number of instructions fetched each cycle (Total) 31710352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 243 1.70% 86.66% # Number of instructions fetched each cycle (Total) 31810352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 210 1.47% 88.13% # Number of instructions fetched each cycle (Total) 31910352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 240 1.68% 89.81% # Number of instructions fetched each cycle (Total) 32010352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 179 1.26% 91.07% # Number of instructions fetched each cycle (Total) 32110352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1273 8.93% 100.00% # Number of instructions fetched each cycle (Total) 3226291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3236291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3246291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 32510352Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 14255 # Number of instructions fetched each cycle (Total) 32610352Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.068312 # Number of branch fetches per cycle 32710352Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.394902 # Number of inst fetches per cycle 32810352Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 8821 # Number of cycles decode is idle 32910352Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 2387 # Number of cycles decode is blocked 33010352Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2410 # Number of cycles decode is running 33110352Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 194 # Number of cycles decode is unblocking 33210352Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 443 # Number of cycles decode is squashing 33310352Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 229 # Number of times decode resolved a branch 33410352Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction 33510352Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 14785 # Number of instructions handled by decode 33610352Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode 33710352Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 443 # Number of cycles rename is squashing 33810352Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 8987 # Number of cycles rename is idle 33910352Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 1032 # Number of cycles rename is blocking 34010352Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 429 # count of cycles rename stalled for serializing inst 34110352Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2422 # Number of cycles rename is running 34210352Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 942 # Number of cycles rename is unblocking 34310352Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 14195 # Number of instructions processed by rename 34410352Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full 34510352Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 34610352Sandreas.hansson@arm.comsystem.cpu.rename.LQFullEvents 42 # Number of times rename has blocked due to LQ full 34710352Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 850 # Number of times rename has blocked due to SQ full 34810352Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 10723 # Number of destination operands rename has renamed 34910352Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 17814 # Number of register rename lookups that rename has made 35010352Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 17805 # Number of integer rename lookups 3519924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 3529150SAli.Saidi@ARM.comsystem.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed 35310352Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6153 # Number of HB maps that are undone due to squashing 35410352Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 32 # count of serializing insts renamed 35510352Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed 35610352Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 504 # count of insts added to the skid buffer 35710352Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2660 # Number of loads inserted to the mem dependence unit. 35810352Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1309 # Number of stores inserted to the mem dependence unit. 35910352Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. 3608428SN/Asystem.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 36110352Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 12882 # Number of instructions added to the IQ (excludes non-spec) 36210352Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ 36310352Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 10718 # Number of instructions issued 36410352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued 36510352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6142 # Number of squashed instructions iterated over during squash; mainly for profiling 36610352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3483 # Number of squashed operands that are examined and possibly removed from graph 36710352Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed 36810352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 14255 # Number of insts issued each cycle 36910352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.751877 # Number of insts issued each cycle 37010352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.485144 # Number of insts issued each cycle 3718428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 37210352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 10249 71.90% 71.90% # Number of insts issued each cycle 37310352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1278 8.97% 80.86% # Number of insts issued each cycle 37410352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 900 6.31% 87.18% # Number of insts issued each cycle 37510352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 686 4.81% 91.99% # Number of insts issued each cycle 37610352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 522 3.66% 95.65% # Number of insts issued each cycle 37710352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 330 2.31% 97.97% # Number of insts issued each cycle 37810352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 212 1.49% 99.45% # Number of insts issued each cycle 37910352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 52 0.36% 99.82% # Number of insts issued each cycle 38010352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle 3818428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3828428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 3838428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 38410352Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 14255 # Number of insts issued each cycle 3858428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 38610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 30 20.69% 20.69% # attempts to use FU when none available 38710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 20.69% # attempts to use FU when none available 38810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 20.69% # attempts to use FU when none available 38910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 20.69% # attempts to use FU when none available 39010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 20.69% # attempts to use FU when none available 39110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 20.69% # attempts to use FU when none available 39210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 20.69% # attempts to use FU when none available 39310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 20.69% # attempts to use FU when none available 39410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.69% # attempts to use FU when none available 39510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 20.69% # attempts to use FU when none available 39610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.69% # attempts to use FU when none available 39710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 20.69% # attempts to use FU when none available 39810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 20.69% # attempts to use FU when none available 39910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 20.69% # attempts to use FU when none available 40010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 20.69% # attempts to use FU when none available 40110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 20.69% # attempts to use FU when none available 40210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.69% # attempts to use FU when none available 40310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 20.69% # attempts to use FU when none available 40410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.69% # attempts to use FU when none available 40510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.69% # attempts to use FU when none available 40610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.69% # attempts to use FU when none available 40710352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.69% # attempts to use FU when none available 40810352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.69% # attempts to use FU when none available 40910352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.69% # attempts to use FU when none available 41010352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.69% # attempts to use FU when none available 41110352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.69% # attempts to use FU when none available 41210352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.69% # attempts to use FU when none available 41310352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.69% # attempts to use FU when none available 41410352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.69% # attempts to use FU when none available 41510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 73 50.34% 71.03% # attempts to use FU when none available 41610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 42 28.97% 100.00% # attempts to use FU when none available 4178428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4188428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4198241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 42010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 7258 67.72% 67.74% # Type of FU issued 42110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 67.75% # Type of FU issued 42210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.75% # Type of FU issued 42310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.76% # Type of FU issued 42410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued 42510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued 42610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued 42710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued 42810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued 42910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued 43010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued 43110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued 43210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued 43310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued 43410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued 43510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued 43610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued 43710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued 43810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued 43910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued 44010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued 44110352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued 44210352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued 44310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued 44410352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued 44510352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued 44610352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued 44710352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued 44810352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued 44910352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2331 21.75% 89.51% # Type of FU issued 45010352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1124 10.49% 100.00% # Type of FU issued 4518241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4528241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 45310352Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 10718 # Type of FU issued 45410352Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.260931 # Inst issue rate 45510352Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 145 # FU busy when requested 45610352Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.013529 # FU busy rate (busy events/executed inst) 45710352Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 35836 # Number of integer instruction queue reads 45810352Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 19060 # Number of integer instruction queue writes 45910352Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9783 # Number of integer instruction queue wakeup accesses 4608428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 4618428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 4628428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 46310352Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 10850 # Number of integer alu accesses 4648428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 46510352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores 4668428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 46710352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1477 # Number of loads squashed 46810352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 46910352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 47010352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 444 # Number of stores squashed 4718428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4728428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4738428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 47410352Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked 4758428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 47610352Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 443 # Number of cycles IEW is squashing 47710352Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 1002 # Number of cycles IEW is blocking 47810352Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking 47910352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 12999 # Number of instructions dispatched to IQ 48010352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch 48110352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2660 # Number of dispatched load instructions 48210352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1309 # Number of dispatched store instructions 48310352Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions 48410352Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall 48510352Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall 48610352Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations 48710352Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly 48810352Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 391 # Number of branches that were predicted not taken incorrectly 48910352Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 470 # Number of branch mispredicts detected at execute 49010352Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 10224 # Number of executed instructions 49110352Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2143 # Number of load instructions executed 49210352Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute 4938428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 4949729Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 89 # number of nop insts executed 49510352Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3244 # number of memory reference insts executed 49610352Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1603 # Number of branches executed 49710352Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1101 # Number of stores executed 49810352Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.248904 # Inst execution rate 49910352Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 9953 # cumulative count of insts sent to commit 50010352Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 9793 # cumulative count of insts written-back 50110352Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 5300 # num instructions producing a value 50210352Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 7279 # num instructions consuming a value 5038428SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 50410352Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.238412 # insts written-back per cycle 50510352Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.728122 # average fanout of values written-back 5068428SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 50710352Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6609 # The number of squashed insts skipped by commit 5088428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 50910352Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted 51010352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 13051 # Number of insts commited each cycle 51110352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.489541 # Number of insts commited each cycle 51210352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.404135 # Number of insts commited each cycle 5138428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 51410352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 10600 81.22% 81.22% # Number of insts commited each cycle 51510352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1162 8.90% 90.12% # Number of insts commited each cycle 51610352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 501 3.84% 93.96% # Number of insts commited each cycle 51710352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 211 1.62% 95.58% # Number of insts commited each cycle 51810352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 133 1.02% 96.60% # Number of insts commited each cycle 51910352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 75 0.57% 97.17% # Number of insts commited each cycle 52010352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 89 0.68% 97.85% # Number of insts commited each cycle 52110352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 89 0.68% 98.54% # Number of insts commited each cycle 52210352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 191 1.46% 100.00% # Number of insts commited each cycle 5238428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5248428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5258428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 52610352Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 13051 # Number of insts commited each cycle 5279150SAli.Saidi@ARM.comsystem.cpu.commit.committedInsts 6389 # Number of instructions committed 5289150SAli.Saidi@ARM.comsystem.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed 5298428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 5309150SAli.Saidi@ARM.comsystem.cpu.commit.refs 2048 # Number of memory references committed 5319150SAli.Saidi@ARM.comsystem.cpu.commit.loads 1183 # Number of loads committed 5328428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 5339150SAli.Saidi@ARM.comsystem.cpu.commit.branches 1050 # Number of branches committed 5348428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 5359150SAli.Saidi@ARM.comsystem.cpu.commit.int_insts 6307 # Number of committed integer instructions. 5368428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 53710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 53810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntAlu 4319 67.60% 67.90% # Class of committed instruction 53910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntMult 1 0.02% 67.91% # Class of committed instruction 54010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 67.91% # Class of committed instruction 54110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.94% # Class of committed instruction 54210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.94% # Class of committed instruction 54310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.94% # Class of committed instruction 54410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 67.94% # Class of committed instruction 54510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.94% # Class of committed instruction 54610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.94% # Class of committed instruction 54710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.94% # Class of committed instruction 54810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.94% # Class of committed instruction 54910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.94% # Class of committed instruction 55010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.94% # Class of committed instruction 55110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.94% # Class of committed instruction 55210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.94% # Class of committed instruction 55310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 67.94% # Class of committed instruction 55410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.94% # Class of committed instruction 55510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 67.94% # Class of committed instruction 55610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.94% # Class of committed instruction 55710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.94% # Class of committed instruction 55810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.94% # Class of committed instruction 55910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.94% # Class of committed instruction 56010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.94% # Class of committed instruction 56110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.94% # Class of committed instruction 56210220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.94% # Class of committed instruction 56310220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.94% # Class of committed instruction 56410220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.94% # Class of committed instruction 56510220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.94% # Class of committed instruction 56610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.94% # Class of committed instruction 56710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1183 18.52% 86.46% # Class of committed instruction 56810220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Class of committed instruction 56910220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 57010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 57110220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::total 6389 # Class of committed instruction 57210352Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 191 # number cycles where commit BW limit reached 5738428SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 57410352Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 25507 # The number of ROB reads 57510352Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 27214 # The number of ROB writes 57610352Sandreas.hansson@arm.comsystem.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself 57710352Sandreas.hansson@arm.comsystem.cpu.idleCycles 26821 # Total number of cycles that the CPU has spent unscheduled due to idling 5789150SAli.Saidi@ARM.comsystem.cpu.committedInsts 6372 # Number of Instructions Simulated 5799150SAli.Saidi@ARM.comsystem.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated 58010352Sandreas.hansson@arm.comsystem.cpu.cpi 6.446328 # CPI: Cycles Per Instruction 58110352Sandreas.hansson@arm.comsystem.cpu.cpi_total 6.446328 # CPI: Total CPI of All Threads 58210352Sandreas.hansson@arm.comsystem.cpu.ipc 0.155127 # IPC: Instructions Per Cycle 58310352Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.155127 # IPC: Total IPC of All Threads 58410352Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 12991 # number of integer regfile reads 58510352Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7455 # number of integer regfile writes 5868428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 5878428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 5888428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 5898428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 59010352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution 59110242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution 59210242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 59310242Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 59410352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) 5959838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) 59610352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) 59710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) 59810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) 59910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) 60010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 60110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram 60210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 60310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 60410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 60510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 60610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram 60710409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 60810409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 60910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 61010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 61110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram 61210352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) 6139729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 61410352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) 61510352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 61610352Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) 6179978Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 6189838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 61910352Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use 62010352Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. 6219838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. 62210352Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 5.471338 # Average number of references to valid blocks. 6239838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 62410352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 158.374396 # Average occupied blocks per requestor 62510352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.077331 # Average percentage of cache occupancy 62610352Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.077331 # Average percentage of cache occupancy 62710036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id 62810352Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id 62910352Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id 63010036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id 63110352Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 4706 # Number of tag accesses 63210352Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 4706 # Number of data accesses 63310352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1718 # number of ReadReq hits 63410352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1718 # number of ReadReq hits 63510352Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1718 # number of demand (read+write) hits 63610352Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1718 # number of demand (read+write) hits 63710352Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1718 # number of overall hits 63810352Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1718 # number of overall hits 63910352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses 64010352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses 64110352Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses 64210352Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses 64310352Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses 64410352Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 478 # number of overall misses 64510352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 31723500 # number of ReadReq miss cycles 64610352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 31723500 # number of ReadReq miss cycles 64710352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 31723500 # number of demand (read+write) miss cycles 64810352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 31723500 # number of demand (read+write) miss cycles 64910352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 31723500 # number of overall miss cycles 65010352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 31723500 # number of overall miss cycles 65110352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2196 # number of ReadReq accesses(hits+misses) 65210352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2196 # number of ReadReq accesses(hits+misses) 65310352Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2196 # number of demand (read+write) accesses 65410352Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2196 # number of demand (read+write) accesses 65510352Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2196 # number of overall (read+write) accesses 65610352Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2196 # number of overall (read+write) accesses 65710352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217668 # miss rate for ReadReq accesses 65810352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.217668 # miss rate for ReadReq accesses 65910352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.217668 # miss rate for demand accesses 66010352Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.217668 # miss rate for demand accesses 66110352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.217668 # miss rate for overall accesses 66210352Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.217668 # miss rate for overall accesses 66310352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66367.154812 # average ReadReq miss latency 66410352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 66367.154812 # average ReadReq miss latency 66510352Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency 66610352Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 66367.154812 # average overall miss latency 66710352Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency 66810352Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 66367.154812 # average overall miss latency 6698428SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6708428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6718428SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 6728428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 6738983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6748983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6758428SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 6768428SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 67710352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits 67810352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits 67910352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits 68010352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits 68110352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits 68210352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits 68310352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses 68410352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses 68510352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses 68610352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses 68710352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses 68810352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses 68910352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22315500 # number of ReadReq MSHR miss cycles 69010352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 22315500 # number of ReadReq MSHR miss cycles 69110352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 22315500 # number of demand (read+write) MSHR miss cycles 69210352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 22315500 # number of demand (read+write) MSHR miss cycles 69310352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 22315500 # number of overall MSHR miss cycles 69410352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 22315500 # number of overall MSHR miss cycles 69510352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for ReadReq accesses 69610352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.142987 # mshr miss rate for ReadReq accesses 69710352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for demand accesses 69810352Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.142987 # mshr miss rate for demand accesses 69910352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for overall accesses 70010352Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.142987 # mshr miss rate for overall accesses 70110352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71068.471338 # average ReadReq mshr miss latency 70210352Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71068.471338 # average ReadReq mshr miss latency 70310352Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency 70410352Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency 70510352Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency 70610352Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency 7078428SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 7089838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 70910352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 218.773509 # Cycle average of tags in use 7109838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 71110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.sampled_refs 415 # Sample count of references to valid blocks. 71210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. 7139838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 71410352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 158.460945 # Average occupied blocks per requestor 71510352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 60.312564 # Average occupied blocks per requestor 71610352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy 71710352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy 71810352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.006676 # Average percentage of cache occupancy 71910242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 415 # Occupied blocks per task id 72010352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 72110352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id 72210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.012665 # Percentage of cache occupancy per task id 72310352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 4391 # Number of tag accesses 72410352Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 4391 # Number of data accesses 7258835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 7268835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 7278835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 7288835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 7298835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 7308835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 73110352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses 73210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses 73310352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses 73410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 73510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 73610352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses 7379322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses 73810352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses 73910352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses 7409322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses 74110352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 487 # number of overall misses 74210352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21990500 # number of ReadReq miss cycles 74310352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 7915750 # number of ReadReq miss cycles 74410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 29906250 # number of ReadReq miss cycles 74510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5408750 # number of ReadExReq miss cycles 74610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 5408750 # number of ReadExReq miss cycles 74710352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 21990500 # number of demand (read+write) miss cycles 74810352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 13324500 # number of demand (read+write) miss cycles 74910352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 35315000 # number of demand (read+write) miss cycles 75010352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 21990500 # number of overall miss cycles 75110352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 13324500 # number of overall miss cycles 75210352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 35315000 # number of overall miss cycles 75310352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) 75410242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) 75510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) 75610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 75710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 75810352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses 7599322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses 76010352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 488 # number of demand (read+write) accesses 76110352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses 7629322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses 76310352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses 76410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses 7658835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 76610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses 7678835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 7689055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 76910352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses 7708835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 77110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses 77210352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses 7738835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 77410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses 77510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70257.188498 # average ReadReq miss latency 77610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77605.392157 # average ReadReq miss latency 77710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.253012 # average ReadReq miss latency 77810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75121.527778 # average ReadExReq miss latency 77910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 75121.527778 # average ReadExReq miss latency 78010352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency 78110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency 78210352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 72515.400411 # average overall miss latency 78310352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency 78410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency 78510352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 72515.400411 # average overall miss latency 7868428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7878428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 7888428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 7898428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 7908983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7918983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 7928428SN/Asystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 7938428SN/Asystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 79410352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses 79510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 79610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses 79710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 79810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 79910352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses 8009322Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 80110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses 80210352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses 8039322Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 80410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses 80510352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18043000 # number of ReadReq MSHR miss cycles 80610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6661250 # number of ReadReq MSHR miss cycles 80710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 24704250 # number of ReadReq MSHR miss cycles 80810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4522750 # number of ReadExReq MSHR miss cycles 80910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4522750 # number of ReadExReq MSHR miss cycles 81010352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18043000 # number of demand (read+write) MSHR miss cycles 81110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11184000 # number of demand (read+write) MSHR miss cycles 81210352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 29227000 # number of demand (read+write) MSHR miss cycles 81310352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18043000 # number of overall MSHR miss cycles 81410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11184000 # number of overall MSHR miss cycles 81510352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 29227000 # number of overall MSHR miss cycles 81610352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses 8178835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 81810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses 8198835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 8209055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 82110352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses 8228835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 82310352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses 82410352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses 8258835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 82610352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses 82710352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57645.367412 # average ReadReq mshr miss latency 82810352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65306.372549 # average ReadReq mshr miss latency 82910352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59528.313253 # average ReadReq mshr miss latency 83010352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62815.972222 # average ReadExReq mshr miss latency 83110352Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62815.972222 # average ReadExReq mshr miss latency 83210352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency 83310352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency 83410352Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency 83510352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency 83610352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency 83710352Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency 8388428SN/Asystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 8399838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 84010352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use 84110352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. 8429838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. 84310352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. 8449838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 84510352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor 84610352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy 84710352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy 84810036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id 84910352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id 85010352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id 85110036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id 85210352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses 85310352Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 5846 # Number of data accesses 85410352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits 85510352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits 8569348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits 8579348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits 85810352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits 85910352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits 86010352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits 86110352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2314 # number of overall hits 86210352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses 86310352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses 8649348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses 8659348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses 86610352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses 86710352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses 86810352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses 86910352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 522 # number of overall misses 87010352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles 87110352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles 87210352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles 87310352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles 87410352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles 87510352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles 87610352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles 87710352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles 87810352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) 87910352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) 8809348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 8819348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 88210352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses 88310352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses 88410352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses 88510352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses 88610352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses 88710352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses 8889348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 8899348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 89010352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses 89110352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses 89210352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses 89310352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses 89410352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency 89510352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency 89610352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency 89710352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency 89810352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency 89910352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency 90010352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency 90110352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency 90210352Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked 9039348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 90410352Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked 9059348SAli.Saidi@ARM.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 90610352Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked 9079348SAli.Saidi@ARM.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9089348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 9099348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 91010352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits 91110352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits 91210148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits 91310148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits 91410352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits 91510352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits 91610352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits 91710352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits 91810148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 91910148Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 92010148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 92110148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 9229348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses 9239348SAli.Saidi@ARM.comsystem.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses 9249348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses 9259348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses 92610352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles 92710352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles 92810352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles 92910352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles 93010352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles 93110352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles 93210352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles 93310352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles 93410352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses 93510352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses 93610148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 93710148Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 93810352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses 93910352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses 94010352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses 94110352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses 94210352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency 94310352Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency 94410352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency 94510352Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency 94610352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency 94710352Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency 94810352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency 94910352Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency 9509348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 9513096SN/A 9523096SN/A---------- End Simulation Statistics ---------- 953