stats.txt revision 11441:0edcf757b6a2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000037 # Number of seconds simulated 4sim_ticks 37494000 # Number of ticks simulated 5final_tick 37494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 257461 # Simulator instruction rate (inst/s) 8host_op_rate 257361 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1504149892 # Simulator tick rate (ticks/s) 10host_mem_usage 252900 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host 12sim_insts 6413 # Number of instructions simulated 13sim_ops 6413 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 23232 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory 18system.physmem.bytes_read::total 34048 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 23232 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 23232 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 363 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 532 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 619619139 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 288472822 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 908091961 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 619619139 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 619619139 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 619619139 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 288472822 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 908091961 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 532 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 532 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 34048 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 34048 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 73 # Per bank write bursts 45system.physmem.perBankRdBursts::1 39 # Per bank write bursts 46system.physmem.perBankRdBursts::2 36 # Per bank write bursts 47system.physmem.perBankRdBursts::3 54 # Per bank write bursts 48system.physmem.perBankRdBursts::4 45 # Per bank write bursts 49system.physmem.perBankRdBursts::5 21 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1 # Per bank write bursts 51system.physmem.perBankRdBursts::7 5 # Per bank write bursts 52system.physmem.perBankRdBursts::8 0 # Per bank write bursts 53system.physmem.perBankRdBursts::9 1 # Per bank write bursts 54system.physmem.perBankRdBursts::10 21 # Per bank write bursts 55system.physmem.perBankRdBursts::11 29 # Per bank write bursts 56system.physmem.perBankRdBursts::12 19 # Per bank write bursts 57system.physmem.perBankRdBursts::13 127 # Per bank write bursts 58system.physmem.perBankRdBursts::14 47 # Per bank write bursts 59system.physmem.perBankRdBursts::15 14 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 37389500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 532 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 443 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 84 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 387.902439 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 251.688412 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 333.441746 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 19 23.17% 23.17% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 18 21.95% 45.12% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 11 13.41% 58.54% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 10 12.20% 70.73% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 1 1.22% 71.95% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 6 7.32% 79.27% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 4 4.88% 84.15% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 5 6.10% 90.24% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 8 9.76% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation 203system.physmem.totQLat 3129000 # Total ticks spent queuing 204system.physmem.totMemAccLat 13104000 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2660000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 5881.58 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 24631.58 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 908.09 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 908.09 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 7.09 # Data bus utilization in percentage 215system.physmem.busUtilRead 7.09 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 438 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 82.33 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 70281.02 # Average gap between requests 224system.physmem.pageHitRate 82.33 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) 233system.physmem_0.averagePower 825.080242 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 16000 # Time in different power states 235system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1552200 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 20432790 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 920250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 25465305 # Total energy per rank (pJ) 247system.physmem_1.averagePower 810.835582 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 1481500 # Time in different power states 249system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 28986000 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 2009 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1241 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 379 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 1611 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 378 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 23.463687 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 234 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. 262system.cpu.branchPred.indirectLookups 338 # Number of indirect predictor lookups. 263system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 264system.cpu.branchPred.indirectMisses 325 # Number of indirect misses. 265system.cpu.branchPredindirectMispredicted 113 # Number of mispredicted indirect branches. 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.dtb.fetch_hits 0 # ITB hits 268system.cpu.dtb.fetch_misses 0 # ITB misses 269system.cpu.dtb.fetch_acv 0 # ITB acv 270system.cpu.dtb.fetch_accesses 0 # ITB accesses 271system.cpu.dtb.read_hits 1378 # DTB read hits 272system.cpu.dtb.read_misses 11 # DTB read misses 273system.cpu.dtb.read_acv 0 # DTB read access violations 274system.cpu.dtb.read_accesses 1389 # DTB read accesses 275system.cpu.dtb.write_hits 885 # DTB write hits 276system.cpu.dtb.write_misses 3 # DTB write misses 277system.cpu.dtb.write_acv 0 # DTB write access violations 278system.cpu.dtb.write_accesses 888 # DTB write accesses 279system.cpu.dtb.data_hits 2263 # DTB hits 280system.cpu.dtb.data_misses 14 # DTB misses 281system.cpu.dtb.data_acv 0 # DTB access violations 282system.cpu.dtb.data_accesses 2277 # DTB accesses 283system.cpu.itb.fetch_hits 2687 # ITB hits 284system.cpu.itb.fetch_misses 17 # ITB misses 285system.cpu.itb.fetch_acv 0 # ITB acv 286system.cpu.itb.fetch_accesses 2704 # ITB accesses 287system.cpu.itb.read_hits 0 # DTB read hits 288system.cpu.itb.read_misses 0 # DTB read misses 289system.cpu.itb.read_acv 0 # DTB read access violations 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_acv 0 # DTB write access violations 294system.cpu.itb.write_accesses 0 # DTB write accesses 295system.cpu.itb.data_hits 0 # DTB hits 296system.cpu.itb.data_misses 0 # DTB misses 297system.cpu.itb.data_acv 0 # DTB access violations 298system.cpu.itb.data_accesses 0 # DTB accesses 299system.cpu.workload.num_syscalls 17 # Number of system calls 300system.cpu.numCycles 74988 # number of cpu cycles simulated 301system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 302system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 303system.cpu.committedInsts 6413 # Number of instructions committed 304system.cpu.committedOps 6413 # Number of ops (including micro ops) committed 305system.cpu.discardedOps 1148 # Number of ops (including micro ops) which were discarded before commit 306system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 307system.cpu.cpi 11.693123 # CPI: cycles per instruction 308system.cpu.ipc 0.085520 # IPC: instructions per cycle 309system.cpu.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 310system.cpu.op_class_0::IntAlu 4331 67.53% 67.83% # Class of committed instruction 311system.cpu.op_class_0::IntMult 1 0.02% 67.85% # Class of committed instruction 312system.cpu.op_class_0::IntDiv 0 0.00% 67.85% # Class of committed instruction 313system.cpu.op_class_0::FloatAdd 2 0.03% 67.88% # Class of committed instruction 314system.cpu.op_class_0::FloatCmp 0 0.00% 67.88% # Class of committed instruction 315system.cpu.op_class_0::FloatCvt 0 0.00% 67.88% # Class of committed instruction 316system.cpu.op_class_0::FloatMult 0 0.00% 67.88% # Class of committed instruction 317system.cpu.op_class_0::FloatDiv 0 0.00% 67.88% # Class of committed instruction 318system.cpu.op_class_0::FloatSqrt 0 0.00% 67.88% # Class of committed instruction 319system.cpu.op_class_0::SimdAdd 0 0.00% 67.88% # Class of committed instruction 320system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction 321system.cpu.op_class_0::SimdAlu 0 0.00% 67.88% # Class of committed instruction 322system.cpu.op_class_0::SimdCmp 0 0.00% 67.88% # Class of committed instruction 323system.cpu.op_class_0::SimdCvt 0 0.00% 67.88% # Class of committed instruction 324system.cpu.op_class_0::SimdMisc 0 0.00% 67.88% # Class of committed instruction 325system.cpu.op_class_0::SimdMult 0 0.00% 67.88% # Class of committed instruction 326system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction 327system.cpu.op_class_0::SimdShift 0 0.00% 67.88% # Class of committed instruction 328system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction 329system.cpu.op_class_0::SimdSqrt 0 0.00% 67.88% # Class of committed instruction 330system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction 331system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction 332system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction 333system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction 334system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction 335system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction 336system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction 337system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction 338system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction 339system.cpu.op_class_0::MemRead 1192 18.59% 86.46% # Class of committed instruction 340system.cpu.op_class_0::MemWrite 868 13.54% 100.00% # Class of committed instruction 341system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 342system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 343system.cpu.op_class_0::total 6413 # Class of committed instruction 344system.cpu.tickCycles 12653 # Number of cycles that the object actually ticked 345system.cpu.idleCycles 62335 # Total number of cycles that the object has spent stopped 346system.cpu.dcache.tags.replacements 0 # number of replacements 347system.cpu.dcache.tags.tagsinuse 104.135823 # Cycle average of tags in use 348system.cpu.dcache.tags.total_refs 1980 # Total number of references to valid blocks. 349system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 350system.cpu.dcache.tags.avg_refs 11.715976 # Average number of references to valid blocks. 351system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 352system.cpu.dcache.tags.occ_blocks::cpu.data 104.135823 # Average occupied blocks per requestor 353system.cpu.dcache.tags.occ_percent::cpu.data 0.025424 # Average percentage of cache occupancy 354system.cpu.dcache.tags.occ_percent::total 0.025424 # Average percentage of cache occupancy 355system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 356system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 357system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id 358system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 359system.cpu.dcache.tags.tag_accesses 4583 # Number of tag accesses 360system.cpu.dcache.tags.data_accesses 4583 # Number of data accesses 361system.cpu.dcache.ReadReq_hits::cpu.data 1240 # number of ReadReq hits 362system.cpu.dcache.ReadReq_hits::total 1240 # number of ReadReq hits 363system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits 364system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits 365system.cpu.dcache.demand_hits::cpu.data 1980 # number of demand (read+write) hits 366system.cpu.dcache.demand_hits::total 1980 # number of demand (read+write) hits 367system.cpu.dcache.overall_hits::cpu.data 1980 # number of overall hits 368system.cpu.dcache.overall_hits::total 1980 # number of overall hits 369system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses 370system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses 371system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses 372system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses 373system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses 374system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses 375system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses 376system.cpu.dcache.overall_misses::total 227 # number of overall misses 377system.cpu.dcache.ReadReq_miss_latency::cpu.data 8280500 # number of ReadReq miss cycles 378system.cpu.dcache.ReadReq_miss_latency::total 8280500 # number of ReadReq miss cycles 379system.cpu.dcache.WriteReq_miss_latency::cpu.data 9164500 # number of WriteReq miss cycles 380system.cpu.dcache.WriteReq_miss_latency::total 9164500 # number of WriteReq miss cycles 381system.cpu.dcache.demand_miss_latency::cpu.data 17445000 # number of demand (read+write) miss cycles 382system.cpu.dcache.demand_miss_latency::total 17445000 # number of demand (read+write) miss cycles 383system.cpu.dcache.overall_miss_latency::cpu.data 17445000 # number of overall miss cycles 384system.cpu.dcache.overall_miss_latency::total 17445000 # number of overall miss cycles 385system.cpu.dcache.ReadReq_accesses::cpu.data 1342 # number of ReadReq accesses(hits+misses) 386system.cpu.dcache.ReadReq_accesses::total 1342 # number of ReadReq accesses(hits+misses) 387system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 388system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 389system.cpu.dcache.demand_accesses::cpu.data 2207 # number of demand (read+write) accesses 390system.cpu.dcache.demand_accesses::total 2207 # number of demand (read+write) accesses 391system.cpu.dcache.overall_accesses::cpu.data 2207 # number of overall (read+write) accesses 392system.cpu.dcache.overall_accesses::total 2207 # number of overall (read+write) accesses 393system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076006 # miss rate for ReadReq accesses 394system.cpu.dcache.ReadReq_miss_rate::total 0.076006 # miss rate for ReadReq accesses 395system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses 396system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses 397system.cpu.dcache.demand_miss_rate::cpu.data 0.102855 # miss rate for demand accesses 398system.cpu.dcache.demand_miss_rate::total 0.102855 # miss rate for demand accesses 399system.cpu.dcache.overall_miss_rate::cpu.data 0.102855 # miss rate for overall accesses 400system.cpu.dcache.overall_miss_rate::total 0.102855 # miss rate for overall accesses 401system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81181.372549 # average ReadReq miss latency 402system.cpu.dcache.ReadReq_avg_miss_latency::total 81181.372549 # average ReadReq miss latency 403system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73316 # average WriteReq miss latency 404system.cpu.dcache.WriteReq_avg_miss_latency::total 73316 # average WriteReq miss latency 405system.cpu.dcache.demand_avg_miss_latency::cpu.data 76850.220264 # average overall miss latency 406system.cpu.dcache.demand_avg_miss_latency::total 76850.220264 # average overall miss latency 407system.cpu.dcache.overall_avg_miss_latency::cpu.data 76850.220264 # average overall miss latency 408system.cpu.dcache.overall_avg_miss_latency::total 76850.220264 # average overall miss latency 409system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 413system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 414system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 415system.cpu.dcache.fast_writes 0 # number of fast writes performed 416system.cpu.dcache.cache_copies 0 # number of cache copies performed 417system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 418system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 419system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits 420system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits 421system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits 422system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits 423system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits 424system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits 425system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses 426system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 427system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 428system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 429system.cpu.dcache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 430system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 431system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 432system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses 433system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7723000 # number of ReadReq MSHR miss cycles 434system.cpu.dcache.ReadReq_mshr_miss_latency::total 7723000 # number of ReadReq MSHR miss cycles 435system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5385500 # number of WriteReq MSHR miss cycles 436system.cpu.dcache.WriteReq_mshr_miss_latency::total 5385500 # number of WriteReq MSHR miss cycles 437system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13108500 # number of demand (read+write) MSHR miss cycles 438system.cpu.dcache.demand_mshr_miss_latency::total 13108500 # number of demand (read+write) MSHR miss cycles 439system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13108500 # number of overall MSHR miss cycles 440system.cpu.dcache.overall_mshr_miss_latency::total 13108500 # number of overall MSHR miss cycles 441system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071535 # mshr miss rate for ReadReq accesses 442system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071535 # mshr miss rate for ReadReq accesses 443system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 444system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 445system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076575 # mshr miss rate for demand accesses 446system.cpu.dcache.demand_mshr_miss_rate::total 0.076575 # mshr miss rate for demand accesses 447system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076575 # mshr miss rate for overall accesses 448system.cpu.dcache.overall_mshr_miss_rate::total 0.076575 # mshr miss rate for overall accesses 449system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80447.916667 # average ReadReq mshr miss latency 450system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80447.916667 # average ReadReq mshr miss latency 451system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73773.972603 # average WriteReq mshr miss latency 452system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73773.972603 # average WriteReq mshr miss latency 453system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency 454system.cpu.dcache.demand_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency 455system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77565.088757 # average overall mshr miss latency 456system.cpu.dcache.overall_avg_mshr_miss_latency::total 77565.088757 # average overall mshr miss latency 457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 458system.cpu.icache.tags.replacements 0 # number of replacements 459system.cpu.icache.tags.tagsinuse 175.312988 # Cycle average of tags in use 460system.cpu.icache.tags.total_refs 2323 # Total number of references to valid blocks. 461system.cpu.icache.tags.sampled_refs 364 # Sample count of references to valid blocks. 462system.cpu.icache.tags.avg_refs 6.381868 # Average number of references to valid blocks. 463system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 464system.cpu.icache.tags.occ_blocks::cpu.inst 175.312988 # Average occupied blocks per requestor 465system.cpu.icache.tags.occ_percent::cpu.inst 0.085602 # Average percentage of cache occupancy 466system.cpu.icache.tags.occ_percent::total 0.085602 # Average percentage of cache occupancy 467system.cpu.icache.tags.occ_task_id_blocks::1024 364 # Occupied blocks per task id 468system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 469system.cpu.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id 470system.cpu.icache.tags.occ_task_id_percent::1024 0.177734 # Percentage of cache occupancy per task id 471system.cpu.icache.tags.tag_accesses 5738 # Number of tag accesses 472system.cpu.icache.tags.data_accesses 5738 # Number of data accesses 473system.cpu.icache.ReadReq_hits::cpu.inst 2323 # number of ReadReq hits 474system.cpu.icache.ReadReq_hits::total 2323 # number of ReadReq hits 475system.cpu.icache.demand_hits::cpu.inst 2323 # number of demand (read+write) hits 476system.cpu.icache.demand_hits::total 2323 # number of demand (read+write) hits 477system.cpu.icache.overall_hits::cpu.inst 2323 # number of overall hits 478system.cpu.icache.overall_hits::total 2323 # number of overall hits 479system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 480system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses 481system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 482system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses 483system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses 484system.cpu.icache.overall_misses::total 364 # number of overall misses 485system.cpu.icache.ReadReq_miss_latency::cpu.inst 27766000 # number of ReadReq miss cycles 486system.cpu.icache.ReadReq_miss_latency::total 27766000 # number of ReadReq miss cycles 487system.cpu.icache.demand_miss_latency::cpu.inst 27766000 # number of demand (read+write) miss cycles 488system.cpu.icache.demand_miss_latency::total 27766000 # number of demand (read+write) miss cycles 489system.cpu.icache.overall_miss_latency::cpu.inst 27766000 # number of overall miss cycles 490system.cpu.icache.overall_miss_latency::total 27766000 # number of overall miss cycles 491system.cpu.icache.ReadReq_accesses::cpu.inst 2687 # number of ReadReq accesses(hits+misses) 492system.cpu.icache.ReadReq_accesses::total 2687 # number of ReadReq accesses(hits+misses) 493system.cpu.icache.demand_accesses::cpu.inst 2687 # number of demand (read+write) accesses 494system.cpu.icache.demand_accesses::total 2687 # number of demand (read+write) accesses 495system.cpu.icache.overall_accesses::cpu.inst 2687 # number of overall (read+write) accesses 496system.cpu.icache.overall_accesses::total 2687 # number of overall (read+write) accesses 497system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.135467 # miss rate for ReadReq accesses 498system.cpu.icache.ReadReq_miss_rate::total 0.135467 # miss rate for ReadReq accesses 499system.cpu.icache.demand_miss_rate::cpu.inst 0.135467 # miss rate for demand accesses 500system.cpu.icache.demand_miss_rate::total 0.135467 # miss rate for demand accesses 501system.cpu.icache.overall_miss_rate::cpu.inst 0.135467 # miss rate for overall accesses 502system.cpu.icache.overall_miss_rate::total 0.135467 # miss rate for overall accesses 503system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76280.219780 # average ReadReq miss latency 504system.cpu.icache.ReadReq_avg_miss_latency::total 76280.219780 # average ReadReq miss latency 505system.cpu.icache.demand_avg_miss_latency::cpu.inst 76280.219780 # average overall miss latency 506system.cpu.icache.demand_avg_miss_latency::total 76280.219780 # average overall miss latency 507system.cpu.icache.overall_avg_miss_latency::cpu.inst 76280.219780 # average overall miss latency 508system.cpu.icache.overall_avg_miss_latency::total 76280.219780 # average overall miss latency 509system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 510system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 511system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 512system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 513system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 514system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 515system.cpu.icache.fast_writes 0 # number of fast writes performed 516system.cpu.icache.cache_copies 0 # number of cache copies performed 517system.cpu.icache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses 518system.cpu.icache.ReadReq_mshr_misses::total 364 # number of ReadReq MSHR misses 519system.cpu.icache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses 520system.cpu.icache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses 521system.cpu.icache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses 522system.cpu.icache.overall_mshr_misses::total 364 # number of overall MSHR misses 523system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27402000 # number of ReadReq MSHR miss cycles 524system.cpu.icache.ReadReq_mshr_miss_latency::total 27402000 # number of ReadReq MSHR miss cycles 525system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27402000 # number of demand (read+write) MSHR miss cycles 526system.cpu.icache.demand_mshr_miss_latency::total 27402000 # number of demand (read+write) MSHR miss cycles 527system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27402000 # number of overall MSHR miss cycles 528system.cpu.icache.overall_mshr_miss_latency::total 27402000 # number of overall MSHR miss cycles 529system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for ReadReq accesses 530system.cpu.icache.ReadReq_mshr_miss_rate::total 0.135467 # mshr miss rate for ReadReq accesses 531system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for demand accesses 532system.cpu.icache.demand_mshr_miss_rate::total 0.135467 # mshr miss rate for demand accesses 533system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135467 # mshr miss rate for overall accesses 534system.cpu.icache.overall_mshr_miss_rate::total 0.135467 # mshr miss rate for overall accesses 535system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75280.219780 # average ReadReq mshr miss latency 536system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75280.219780 # average ReadReq mshr miss latency 537system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency 538system.cpu.icache.demand_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency 539system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75280.219780 # average overall mshr miss latency 540system.cpu.icache.overall_avg_mshr_miss_latency::total 75280.219780 # average overall mshr miss latency 541system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 542system.cpu.l2cache.tags.replacements 0 # number of replacements 543system.cpu.l2cache.tags.tagsinuse 233.336913 # Cycle average of tags in use 544system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 545system.cpu.l2cache.tags.sampled_refs 459 # Sample count of references to valid blocks. 546system.cpu.l2cache.tags.avg_refs 0.002179 # Average number of references to valid blocks. 547system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 548system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.327844 # Average occupied blocks per requestor 549system.cpu.l2cache.tags.occ_blocks::cpu.data 58.009069 # Average occupied blocks per requestor 550system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005351 # Average percentage of cache occupancy 551system.cpu.l2cache.tags.occ_percent::cpu.data 0.001770 # Average percentage of cache occupancy 552system.cpu.l2cache.tags.occ_percent::total 0.007121 # Average percentage of cache occupancy 553system.cpu.l2cache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id 554system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 555system.cpu.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id 556system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014008 # Percentage of cache occupancy per task id 557system.cpu.l2cache.tags.tag_accesses 4796 # Number of tag accesses 558system.cpu.l2cache.tags.data_accesses 4796 # Number of data accesses 559system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 560system.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 561system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 562system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 563system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 564system.cpu.l2cache.overall_hits::total 1 # number of overall hits 565system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 566system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 567system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 363 # number of ReadCleanReq misses 568system.cpu.l2cache.ReadCleanReq_misses::total 363 # number of ReadCleanReq misses 569system.cpu.l2cache.ReadSharedReq_misses::cpu.data 96 # number of ReadSharedReq misses 570system.cpu.l2cache.ReadSharedReq_misses::total 96 # number of ReadSharedReq misses 571system.cpu.l2cache.demand_misses::cpu.inst 363 # number of demand (read+write) misses 572system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses 573system.cpu.l2cache.demand_misses::total 532 # number of demand (read+write) misses 574system.cpu.l2cache.overall_misses::cpu.inst 363 # number of overall misses 575system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses 576system.cpu.l2cache.overall_misses::total 532 # number of overall misses 577system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5275000 # number of ReadExReq miss cycles 578system.cpu.l2cache.ReadExReq_miss_latency::total 5275000 # number of ReadExReq miss cycles 579system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 26844000 # number of ReadCleanReq miss cycles 580system.cpu.l2cache.ReadCleanReq_miss_latency::total 26844000 # number of ReadCleanReq miss cycles 581system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7577500 # number of ReadSharedReq miss cycles 582system.cpu.l2cache.ReadSharedReq_miss_latency::total 7577500 # number of ReadSharedReq miss cycles 583system.cpu.l2cache.demand_miss_latency::cpu.inst 26844000 # number of demand (read+write) miss cycles 584system.cpu.l2cache.demand_miss_latency::cpu.data 12852500 # number of demand (read+write) miss cycles 585system.cpu.l2cache.demand_miss_latency::total 39696500 # number of demand (read+write) miss cycles 586system.cpu.l2cache.overall_miss_latency::cpu.inst 26844000 # number of overall miss cycles 587system.cpu.l2cache.overall_miss_latency::cpu.data 12852500 # number of overall miss cycles 588system.cpu.l2cache.overall_miss_latency::total 39696500 # number of overall miss cycles 589system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 590system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 591system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 364 # number of ReadCleanReq accesses(hits+misses) 592system.cpu.l2cache.ReadCleanReq_accesses::total 364 # number of ReadCleanReq accesses(hits+misses) 593system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 96 # number of ReadSharedReq accesses(hits+misses) 594system.cpu.l2cache.ReadSharedReq_accesses::total 96 # number of ReadSharedReq accesses(hits+misses) 595system.cpu.l2cache.demand_accesses::cpu.inst 364 # number of demand (read+write) accesses 596system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses 597system.cpu.l2cache.demand_accesses::total 533 # number of demand (read+write) accesses 598system.cpu.l2cache.overall_accesses::cpu.inst 364 # number of overall (read+write) accesses 599system.cpu.l2cache.overall_accesses::cpu.data 169 # number of overall (read+write) accesses 600system.cpu.l2cache.overall_accesses::total 533 # number of overall (read+write) accesses 601system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 602system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 603system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997253 # miss rate for ReadCleanReq accesses 604system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997253 # miss rate for ReadCleanReq accesses 605system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 606system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 607system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997253 # miss rate for demand accesses 608system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 609system.cpu.l2cache.demand_miss_rate::total 0.998124 # miss rate for demand accesses 610system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997253 # miss rate for overall accesses 611system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 612system.cpu.l2cache.overall_miss_rate::total 0.998124 # miss rate for overall accesses 613system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72260.273973 # average ReadExReq miss latency 614system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72260.273973 # average ReadExReq miss latency 615system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73950.413223 # average ReadCleanReq miss latency 616system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73950.413223 # average ReadCleanReq miss latency 617system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78932.291667 # average ReadSharedReq miss latency 618system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78932.291667 # average ReadSharedReq miss latency 619system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73950.413223 # average overall miss latency 620system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76050.295858 # average overall miss latency 621system.cpu.l2cache.demand_avg_miss_latency::total 74617.481203 # average overall miss latency 622system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73950.413223 # average overall miss latency 623system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76050.295858 # average overall miss latency 624system.cpu.l2cache.overall_avg_miss_latency::total 74617.481203 # average overall miss latency 625system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 626system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 627system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 628system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 629system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 630system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 631system.cpu.l2cache.fast_writes 0 # number of fast writes performed 632system.cpu.l2cache.cache_copies 0 # number of cache copies performed 633system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 634system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 635system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 363 # number of ReadCleanReq MSHR misses 636system.cpu.l2cache.ReadCleanReq_mshr_misses::total 363 # number of ReadCleanReq MSHR misses 637system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses 638system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses 639system.cpu.l2cache.demand_mshr_misses::cpu.inst 363 # number of demand (read+write) MSHR misses 640system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 641system.cpu.l2cache.demand_mshr_misses::total 532 # number of demand (read+write) MSHR misses 642system.cpu.l2cache.overall_mshr_misses::cpu.inst 363 # number of overall MSHR misses 643system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 644system.cpu.l2cache.overall_mshr_misses::total 532 # number of overall MSHR misses 645system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4545000 # number of ReadExReq MSHR miss cycles 646system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4545000 # number of ReadExReq MSHR miss cycles 647system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23214000 # number of ReadCleanReq MSHR miss cycles 648system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23214000 # number of ReadCleanReq MSHR miss cycles 649system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6617500 # number of ReadSharedReq MSHR miss cycles 650system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6617500 # number of ReadSharedReq MSHR miss cycles 651system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23214000 # number of demand (read+write) MSHR miss cycles 652system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11162500 # number of demand (read+write) MSHR miss cycles 653system.cpu.l2cache.demand_mshr_miss_latency::total 34376500 # number of demand (read+write) MSHR miss cycles 654system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23214000 # number of overall MSHR miss cycles 655system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11162500 # number of overall MSHR miss cycles 656system.cpu.l2cache.overall_mshr_miss_latency::total 34376500 # number of overall MSHR miss cycles 657system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 658system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 659system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for ReadCleanReq accesses 660system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997253 # mshr miss rate for ReadCleanReq accesses 661system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 662system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 663system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for demand accesses 664system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 665system.cpu.l2cache.demand_mshr_miss_rate::total 0.998124 # mshr miss rate for demand accesses 666system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997253 # mshr miss rate for overall accesses 667system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 668system.cpu.l2cache.overall_mshr_miss_rate::total 0.998124 # mshr miss rate for overall accesses 669system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62260.273973 # average ReadExReq mshr miss latency 670system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62260.273973 # average ReadExReq mshr miss latency 671system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 63950.413223 # average ReadCleanReq mshr miss latency 672system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63950.413223 # average ReadCleanReq mshr miss latency 673system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68932.291667 # average ReadSharedReq mshr miss latency 674system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68932.291667 # average ReadSharedReq mshr miss latency 675system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency 676system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency 677system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency 678system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63950.413223 # average overall mshr miss latency 679system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66050.295858 # average overall mshr miss latency 680system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64617.481203 # average overall mshr miss latency 681system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 682system.cpu.toL2Bus.snoop_filter.tot_requests 533 # Total number of requests made to the snoop filter. 683system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 684system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 685system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 686system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 687system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 688system.cpu.toL2Bus.trans_dist::ReadResp 460 # Transaction distribution 689system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 690system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 691system.cpu.toL2Bus.trans_dist::ReadCleanReq 364 # Transaction distribution 692system.cpu.toL2Bus.trans_dist::ReadSharedReq 96 # Transaction distribution 693system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 728 # Packet count per connected master and slave (bytes) 694system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 695system.cpu.toL2Bus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) 696system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23296 # Cumulative packet size per connected master and slave (bytes) 697system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) 698system.cpu.toL2Bus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) 699system.cpu.toL2Bus.snoops 0 # Total snoops (count) 700system.cpu.toL2Bus.snoop_fanout::samples 533 # Request fanout histogram 701system.cpu.toL2Bus.snoop_fanout::mean 0.001876 # Request fanout histogram 702system.cpu.toL2Bus.snoop_fanout::stdev 0.043315 # Request fanout histogram 703system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 704system.cpu.toL2Bus.snoop_fanout::0 532 99.81% 99.81% # Request fanout histogram 705system.cpu.toL2Bus.snoop_fanout::1 1 0.19% 100.00% # Request fanout histogram 706system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 707system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 708system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 709system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 710system.cpu.toL2Bus.snoop_fanout::total 533 # Request fanout histogram 711system.cpu.toL2Bus.reqLayer0.occupancy 266500 # Layer occupancy (ticks) 712system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 713system.cpu.toL2Bus.respLayer0.occupancy 546000 # Layer occupancy (ticks) 714system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) 715system.cpu.toL2Bus.respLayer1.occupancy 253500 # Layer occupancy (ticks) 716system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 717system.membus.trans_dist::ReadResp 459 # Transaction distribution 718system.membus.trans_dist::ReadExReq 73 # Transaction distribution 719system.membus.trans_dist::ReadExResp 73 # Transaction distribution 720system.membus.trans_dist::ReadSharedReq 459 # Transaction distribution 721system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1064 # Packet count per connected master and slave (bytes) 722system.membus.pkt_count::total 1064 # Packet count per connected master and slave (bytes) 723system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34048 # Cumulative packet size per connected master and slave (bytes) 724system.membus.pkt_size::total 34048 # Cumulative packet size per connected master and slave (bytes) 725system.membus.snoops 0 # Total snoops (count) 726system.membus.snoop_fanout::samples 532 # Request fanout histogram 727system.membus.snoop_fanout::mean 0 # Request fanout histogram 728system.membus.snoop_fanout::stdev 0 # Request fanout histogram 729system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 730system.membus.snoop_fanout::0 532 100.00% 100.00% # Request fanout histogram 731system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 732system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 733system.membus.snoop_fanout::min_value 0 # Request fanout histogram 734system.membus.snoop_fanout::max_value 0 # Request fanout histogram 735system.membus.snoop_fanout::total 532 # Request fanout histogram 736system.membus.reqLayer0.occupancy 602500 # Layer occupancy (ticks) 737system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) 738system.membus.respLayer1.occupancy 2826750 # Layer occupancy (ticks) 739system.membus.respLayer1.utilization 7.5 # Layer utilization (%) 740 741---------- End Simulation Statistics ---------- 742