stats.txt revision 10852:5b58b4cccfd7
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000038 # Number of seconds simulated 4sim_ticks 37930000 # Number of ticks simulated 5final_tick 37930000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 161486 # Simulator instruction rate (inst/s) 8host_op_rate 161429 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 956403338 # Simulator tick rate (ticks/s) 10host_mem_usage 294064 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host 12sim_insts 6400 # Number of instructions simulated 13sim_ops 6400 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 23296 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 10816 # Number of bytes read from this memory 18system.physmem.bytes_read::total 34112 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 23296 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 23296 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 533 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 614184023 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 285156868 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 899340891 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 614184023 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 614184023 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 614184023 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 285156868 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 899340891 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 533 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 34112 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 34112 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 73 # Per bank write bursts 45system.physmem.perBankRdBursts::1 39 # Per bank write bursts 46system.physmem.perBankRdBursts::2 36 # Per bank write bursts 47system.physmem.perBankRdBursts::3 54 # Per bank write bursts 48system.physmem.perBankRdBursts::4 45 # Per bank write bursts 49system.physmem.perBankRdBursts::5 21 # Per bank write bursts 50system.physmem.perBankRdBursts::6 1 # Per bank write bursts 51system.physmem.perBankRdBursts::7 5 # Per bank write bursts 52system.physmem.perBankRdBursts::8 0 # Per bank write bursts 53system.physmem.perBankRdBursts::9 1 # Per bank write bursts 54system.physmem.perBankRdBursts::10 22 # Per bank write bursts 55system.physmem.perBankRdBursts::11 29 # Per bank write bursts 56system.physmem.perBankRdBursts::12 19 # Per bank write bursts 57system.physmem.perBankRdBursts::13 127 # Per bank write bursts 58system.physmem.perBankRdBursts::14 47 # Per bank write bursts 59system.physmem.perBankRdBursts::15 14 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 37824500 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 533 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 442 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 86 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 381.714286 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 247.680361 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 333.730884 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 19 22.62% 22.62% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 20 23.81% 46.43% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 11 13.10% 71.43% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 4.76% 76.19% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 3 3.57% 79.76% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 2.38% 82.14% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 6 7.14% 89.29% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 9 10.71% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation 203system.physmem.totQLat 3251500 # Total ticks spent queuing 204system.physmem.totMemAccLat 13245250 # Total ticks spent from burst creation until serviced by the DRAM 205system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers 206system.physmem.avgQLat 6100.38 # Average queueing delay per DRAM burst 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 208system.physmem.avgMemAccLat 24850.38 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 899.34 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 899.34 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 7.03 # Data bus utilization in percentage 215system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 437 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 70965.29 # Average gap between requests 224system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) 233system.physmem_0.averagePower 825.080242 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 372750 # Time in different power states 235system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 20293425 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 1041750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 25416240 # Total energy per rank (pJ) 247system.physmem_1.averagePower 809.305525 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 1595750 # Time in different power states 249system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 28783000 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.cpu.branchPred.lookups 1964 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1204 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 1555 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 382 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 259system.cpu.branchPred.BTBHitPct 24.565916 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. 261system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dtb.fetch_hits 0 # ITB hits 264system.cpu.dtb.fetch_misses 0 # ITB misses 265system.cpu.dtb.fetch_acv 0 # ITB acv 266system.cpu.dtb.fetch_accesses 0 # ITB accesses 267system.cpu.dtb.read_hits 1371 # DTB read hits 268system.cpu.dtb.read_misses 11 # DTB read misses 269system.cpu.dtb.read_acv 0 # DTB read access violations 270system.cpu.dtb.read_accesses 1382 # DTB read accesses 271system.cpu.dtb.write_hits 884 # DTB write hits 272system.cpu.dtb.write_misses 3 # DTB write misses 273system.cpu.dtb.write_acv 0 # DTB write access violations 274system.cpu.dtb.write_accesses 887 # DTB write accesses 275system.cpu.dtb.data_hits 2255 # DTB hits 276system.cpu.dtb.data_misses 14 # DTB misses 277system.cpu.dtb.data_acv 0 # DTB access violations 278system.cpu.dtb.data_accesses 2269 # DTB accesses 279system.cpu.itb.fetch_hits 2638 # ITB hits 280system.cpu.itb.fetch_misses 17 # ITB misses 281system.cpu.itb.fetch_acv 0 # ITB acv 282system.cpu.itb.fetch_accesses 2655 # ITB accesses 283system.cpu.itb.read_hits 0 # DTB read hits 284system.cpu.itb.read_misses 0 # DTB read misses 285system.cpu.itb.read_acv 0 # DTB read access violations 286system.cpu.itb.read_accesses 0 # DTB read accesses 287system.cpu.itb.write_hits 0 # DTB write hits 288system.cpu.itb.write_misses 0 # DTB write misses 289system.cpu.itb.write_acv 0 # DTB write access violations 290system.cpu.itb.write_accesses 0 # DTB write accesses 291system.cpu.itb.data_hits 0 # DTB hits 292system.cpu.itb.data_misses 0 # DTB misses 293system.cpu.itb.data_acv 0 # DTB access violations 294system.cpu.itb.data_accesses 0 # DTB accesses 295system.cpu.workload.num_syscalls 17 # Number of system calls 296system.cpu.numCycles 75860 # number of cpu cycles simulated 297system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 298system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 299system.cpu.committedInsts 6400 # Number of instructions committed 300system.cpu.committedOps 6400 # Number of ops (including micro ops) committed 301system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit 302system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 303system.cpu.cpi 11.853125 # CPI: cycles per instruction 304system.cpu.ipc 0.084366 # IPC: instructions per cycle 305system.cpu.tickCycles 12560 # Number of cycles that the object actually ticked 306system.cpu.idleCycles 63300 # Total number of cycles that the object has spent stopped 307system.cpu.dcache.tags.replacements 0 # number of replacements 308system.cpu.dcache.tags.tagsinuse 103.899066 # Cycle average of tags in use 309system.cpu.dcache.tags.total_refs 1976 # Total number of references to valid blocks. 310system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. 311system.cpu.dcache.tags.avg_refs 11.692308 # Average number of references to valid blocks. 312system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 313system.cpu.dcache.tags.occ_blocks::cpu.data 103.899066 # Average occupied blocks per requestor 314system.cpu.dcache.tags.occ_percent::cpu.data 0.025366 # Average percentage of cache occupancy 315system.cpu.dcache.tags.occ_percent::total 0.025366 # Average percentage of cache occupancy 316system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id 317system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 318system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id 319system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id 320system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses 321system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses 322system.cpu.dcache.ReadReq_hits::cpu.data 1235 # number of ReadReq hits 323system.cpu.dcache.ReadReq_hits::total 1235 # number of ReadReq hits 324system.cpu.dcache.WriteReq_hits::cpu.data 741 # number of WriteReq hits 325system.cpu.dcache.WriteReq_hits::total 741 # number of WriteReq hits 326system.cpu.dcache.demand_hits::cpu.data 1976 # number of demand (read+write) hits 327system.cpu.dcache.demand_hits::total 1976 # number of demand (read+write) hits 328system.cpu.dcache.overall_hits::cpu.data 1976 # number of overall hits 329system.cpu.dcache.overall_hits::total 1976 # number of overall hits 330system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses 331system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses 332system.cpu.dcache.WriteReq_misses::cpu.data 124 # number of WriteReq misses 333system.cpu.dcache.WriteReq_misses::total 124 # number of WriteReq misses 334system.cpu.dcache.demand_misses::cpu.data 226 # number of demand (read+write) misses 335system.cpu.dcache.demand_misses::total 226 # number of demand (read+write) misses 336system.cpu.dcache.overall_misses::cpu.data 226 # number of overall misses 337system.cpu.dcache.overall_misses::total 226 # number of overall misses 338system.cpu.dcache.ReadReq_miss_latency::cpu.data 8144750 # number of ReadReq miss cycles 339system.cpu.dcache.ReadReq_miss_latency::total 8144750 # number of ReadReq miss cycles 340system.cpu.dcache.WriteReq_miss_latency::cpu.data 9233750 # number of WriteReq miss cycles 341system.cpu.dcache.WriteReq_miss_latency::total 9233750 # number of WriteReq miss cycles 342system.cpu.dcache.demand_miss_latency::cpu.data 17378500 # number of demand (read+write) miss cycles 343system.cpu.dcache.demand_miss_latency::total 17378500 # number of demand (read+write) miss cycles 344system.cpu.dcache.overall_miss_latency::cpu.data 17378500 # number of overall miss cycles 345system.cpu.dcache.overall_miss_latency::total 17378500 # number of overall miss cycles 346system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses) 347system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses) 348system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 349system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 350system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses 351system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses 352system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses 353system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses 354system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076290 # miss rate for ReadReq accesses 355system.cpu.dcache.ReadReq_miss_rate::total 0.076290 # miss rate for ReadReq accesses 356system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.143353 # miss rate for WriteReq accesses 357system.cpu.dcache.WriteReq_miss_rate::total 0.143353 # miss rate for WriteReq accesses 358system.cpu.dcache.demand_miss_rate::cpu.data 0.102634 # miss rate for demand accesses 359system.cpu.dcache.demand_miss_rate::total 0.102634 # miss rate for demand accesses 360system.cpu.dcache.overall_miss_rate::cpu.data 0.102634 # miss rate for overall accesses 361system.cpu.dcache.overall_miss_rate::total 0.102634 # miss rate for overall accesses 362system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79850.490196 # average ReadReq miss latency 363system.cpu.dcache.ReadReq_avg_miss_latency::total 79850.490196 # average ReadReq miss latency 364system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74465.725806 # average WriteReq miss latency 365system.cpu.dcache.WriteReq_avg_miss_latency::total 74465.725806 # average WriteReq miss latency 366system.cpu.dcache.demand_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency 367system.cpu.dcache.demand_avg_miss_latency::total 76896.017699 # average overall miss latency 368system.cpu.dcache.overall_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency 369system.cpu.dcache.overall_avg_miss_latency::total 76896.017699 # average overall miss latency 370system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 371system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 372system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 373system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 374system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 375system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 376system.cpu.dcache.fast_writes 0 # number of fast writes performed 377system.cpu.dcache.cache_copies 0 # number of cache copies performed 378system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 379system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 380system.cpu.dcache.WriteReq_mshr_hits::cpu.data 51 # number of WriteReq MSHR hits 381system.cpu.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits 382system.cpu.dcache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits 383system.cpu.dcache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits 384system.cpu.dcache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits 385system.cpu.dcache.overall_mshr_hits::total 57 # number of overall MSHR hits 386system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses 387system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses 388system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 389system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 390system.cpu.dcache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 391system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses 392system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 393system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses 394system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7564250 # number of ReadReq MSHR miss cycles 395system.cpu.dcache.ReadReq_mshr_miss_latency::total 7564250 # number of ReadReq MSHR miss cycles 396system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5364250 # number of WriteReq MSHR miss cycles 397system.cpu.dcache.WriteReq_mshr_miss_latency::total 5364250 # number of WriteReq MSHR miss cycles 398system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12928500 # number of demand (read+write) MSHR miss cycles 399system.cpu.dcache.demand_mshr_miss_latency::total 12928500 # number of demand (read+write) MSHR miss cycles 400system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12928500 # number of overall MSHR miss cycles 401system.cpu.dcache.overall_mshr_miss_latency::total 12928500 # number of overall MSHR miss cycles 402system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses 403system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses 404system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 405system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 406system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for demand accesses 407system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses 408system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses 409system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses 410system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78794.270833 # average ReadReq mshr miss latency 411system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78794.270833 # average ReadReq mshr miss latency 412system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73482.876712 # average WriteReq mshr miss latency 413system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73482.876712 # average WriteReq mshr miss latency 414system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency 415system.cpu.dcache.demand_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency 416system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency 417system.cpu.dcache.overall_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency 418system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 419system.cpu.icache.tags.replacements 0 # number of replacements 420system.cpu.icache.tags.tagsinuse 175.739822 # Cycle average of tags in use 421system.cpu.icache.tags.total_refs 2273 # Total number of references to valid blocks. 422system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. 423system.cpu.icache.tags.avg_refs 6.227397 # Average number of references to valid blocks. 424system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 425system.cpu.icache.tags.occ_blocks::cpu.inst 175.739822 # Average occupied blocks per requestor 426system.cpu.icache.tags.occ_percent::cpu.inst 0.085810 # Average percentage of cache occupancy 427system.cpu.icache.tags.occ_percent::total 0.085810 # Average percentage of cache occupancy 428system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id 429system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 430system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id 431system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id 432system.cpu.icache.tags.tag_accesses 5641 # Number of tag accesses 433system.cpu.icache.tags.data_accesses 5641 # Number of data accesses 434system.cpu.icache.ReadReq_hits::cpu.inst 2273 # number of ReadReq hits 435system.cpu.icache.ReadReq_hits::total 2273 # number of ReadReq hits 436system.cpu.icache.demand_hits::cpu.inst 2273 # number of demand (read+write) hits 437system.cpu.icache.demand_hits::total 2273 # number of demand (read+write) hits 438system.cpu.icache.overall_hits::cpu.inst 2273 # number of overall hits 439system.cpu.icache.overall_hits::total 2273 # number of overall hits 440system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses 441system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses 442system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 443system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses 444system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses 445system.cpu.icache.overall_misses::total 365 # number of overall misses 446system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333750 # number of ReadReq miss cycles 447system.cpu.icache.ReadReq_miss_latency::total 28333750 # number of ReadReq miss cycles 448system.cpu.icache.demand_miss_latency::cpu.inst 28333750 # number of demand (read+write) miss cycles 449system.cpu.icache.demand_miss_latency::total 28333750 # number of demand (read+write) miss cycles 450system.cpu.icache.overall_miss_latency::cpu.inst 28333750 # number of overall miss cycles 451system.cpu.icache.overall_miss_latency::total 28333750 # number of overall miss cycles 452system.cpu.icache.ReadReq_accesses::cpu.inst 2638 # number of ReadReq accesses(hits+misses) 453system.cpu.icache.ReadReq_accesses::total 2638 # number of ReadReq accesses(hits+misses) 454system.cpu.icache.demand_accesses::cpu.inst 2638 # number of demand (read+write) accesses 455system.cpu.icache.demand_accesses::total 2638 # number of demand (read+write) accesses 456system.cpu.icache.overall_accesses::cpu.inst 2638 # number of overall (read+write) accesses 457system.cpu.icache.overall_accesses::total 2638 # number of overall (read+write) accesses 458system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138362 # miss rate for ReadReq accesses 459system.cpu.icache.ReadReq_miss_rate::total 0.138362 # miss rate for ReadReq accesses 460system.cpu.icache.demand_miss_rate::cpu.inst 0.138362 # miss rate for demand accesses 461system.cpu.icache.demand_miss_rate::total 0.138362 # miss rate for demand accesses 462system.cpu.icache.overall_miss_rate::cpu.inst 0.138362 # miss rate for overall accesses 463system.cpu.icache.overall_miss_rate::total 0.138362 # miss rate for overall accesses 464system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77626.712329 # average ReadReq miss latency 465system.cpu.icache.ReadReq_avg_miss_latency::total 77626.712329 # average ReadReq miss latency 466system.cpu.icache.demand_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency 467system.cpu.icache.demand_avg_miss_latency::total 77626.712329 # average overall miss latency 468system.cpu.icache.overall_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency 469system.cpu.icache.overall_avg_miss_latency::total 77626.712329 # average overall miss latency 470system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 471system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 472system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 473system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 474system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 475system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 476system.cpu.icache.fast_writes 0 # number of fast writes performed 477system.cpu.icache.cache_copies 0 # number of cache copies performed 478system.cpu.icache.ReadReq_mshr_misses::cpu.inst 365 # number of ReadReq MSHR misses 479system.cpu.icache.ReadReq_mshr_misses::total 365 # number of ReadReq MSHR misses 480system.cpu.icache.demand_mshr_misses::cpu.inst 365 # number of demand (read+write) MSHR misses 481system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses 482system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses 483system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses 484system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622750 # number of ReadReq MSHR miss cycles 485system.cpu.icache.ReadReq_mshr_miss_latency::total 27622750 # number of ReadReq MSHR miss cycles 486system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622750 # number of demand (read+write) MSHR miss cycles 487system.cpu.icache.demand_mshr_miss_latency::total 27622750 # number of demand (read+write) MSHR miss cycles 488system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622750 # number of overall MSHR miss cycles 489system.cpu.icache.overall_mshr_miss_latency::total 27622750 # number of overall MSHR miss cycles 490system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for ReadReq accesses 491system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138362 # mshr miss rate for ReadReq accesses 492system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for demand accesses 493system.cpu.icache.demand_mshr_miss_rate::total 0.138362 # mshr miss rate for demand accesses 494system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for overall accesses 495system.cpu.icache.overall_mshr_miss_rate::total 0.138362 # mshr miss rate for overall accesses 496system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75678.767123 # average ReadReq mshr miss latency 497system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75678.767123 # average ReadReq mshr miss latency 498system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency 499system.cpu.icache.demand_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency 500system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency 501system.cpu.icache.overall_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency 502system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 503system.cpu.l2cache.tags.replacements 0 # number of replacements 504system.cpu.l2cache.tags.tagsinuse 233.394654 # Cycle average of tags in use 505system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 506system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. 507system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. 508system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 509system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.771828 # Average occupied blocks per requestor 510system.cpu.l2cache.tags.occ_blocks::cpu.data 57.622826 # Average occupied blocks per requestor 511system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005364 # Average percentage of cache occupancy 512system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy 513system.cpu.l2cache.tags.occ_percent::total 0.007123 # Average percentage of cache occupancy 514system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id 515system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id 516system.cpu.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id 517system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id 518system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses 519system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses 520system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits 521system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits 522system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 523system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 524system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 525system.cpu.l2cache.overall_hits::total 1 # number of overall hits 526system.cpu.l2cache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 527system.cpu.l2cache.ReadReq_misses::cpu.data 96 # number of ReadReq misses 528system.cpu.l2cache.ReadReq_misses::total 460 # number of ReadReq misses 529system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 530system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 531system.cpu.l2cache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 532system.cpu.l2cache.demand_misses::cpu.data 169 # number of demand (read+write) misses 533system.cpu.l2cache.demand_misses::total 533 # number of demand (read+write) misses 534system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses 535system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses 536system.cpu.l2cache.overall_misses::total 533 # number of overall misses 537system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246750 # number of ReadReq miss cycles 538system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7466750 # number of ReadReq miss cycles 539system.cpu.l2cache.ReadReq_miss_latency::total 34713500 # number of ReadReq miss cycles 540system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5290250 # number of ReadExReq miss cycles 541system.cpu.l2cache.ReadExReq_miss_latency::total 5290250 # number of ReadExReq miss cycles 542system.cpu.l2cache.demand_miss_latency::cpu.inst 27246750 # number of demand (read+write) miss cycles 543system.cpu.l2cache.demand_miss_latency::cpu.data 12757000 # number of demand (read+write) miss cycles 544system.cpu.l2cache.demand_miss_latency::total 40003750 # number of demand (read+write) miss cycles 545system.cpu.l2cache.overall_miss_latency::cpu.inst 27246750 # number of overall miss cycles 546system.cpu.l2cache.overall_miss_latency::cpu.data 12757000 # number of overall miss cycles 547system.cpu.l2cache.overall_miss_latency::total 40003750 # number of overall miss cycles 548system.cpu.l2cache.ReadReq_accesses::cpu.inst 365 # number of ReadReq accesses(hits+misses) 549system.cpu.l2cache.ReadReq_accesses::cpu.data 96 # number of ReadReq accesses(hits+misses) 550system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) 551system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 552system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 553system.cpu.l2cache.demand_accesses::cpu.inst 365 # number of demand (read+write) accesses 554system.cpu.l2cache.demand_accesses::cpu.data 169 # number of demand (read+write) accesses 555system.cpu.l2cache.demand_accesses::total 534 # number of demand (read+write) accesses 556system.cpu.l2cache.overall_accesses::cpu.inst 365 # number of overall (read+write) accesses 557system.cpu.l2cache.overall_accesses::cpu.data 169 # number of overall (read+write) accesses 558system.cpu.l2cache.overall_accesses::total 534 # number of overall (read+write) accesses 559system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.997260 # miss rate for ReadReq accesses 560system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses 561system.cpu.l2cache.ReadReq_miss_rate::total 0.997831 # miss rate for ReadReq accesses 562system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 563system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 564system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997260 # miss rate for demand accesses 565system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 566system.cpu.l2cache.demand_miss_rate::total 0.998127 # miss rate for demand accesses 567system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses 568system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 569system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses 570system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74853.708791 # average ReadReq miss latency 571system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77778.645833 # average ReadReq miss latency 572system.cpu.l2cache.ReadReq_avg_miss_latency::total 75464.130435 # average ReadReq miss latency 573system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72469.178082 # average ReadExReq miss latency 574system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72469.178082 # average ReadExReq miss latency 575system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency 576system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency 577system.cpu.l2cache.demand_avg_miss_latency::total 75053.939962 # average overall miss latency 578system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency 579system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency 580system.cpu.l2cache.overall_avg_miss_latency::total 75053.939962 # average overall miss latency 581system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 583system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 584system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 585system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 586system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 587system.cpu.l2cache.fast_writes 0 # number of fast writes performed 588system.cpu.l2cache.cache_copies 0 # number of cache copies performed 589system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 364 # number of ReadReq MSHR misses 590system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses 591system.cpu.l2cache.ReadReq_mshr_misses::total 460 # number of ReadReq MSHR misses 592system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 593system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 594system.cpu.l2cache.demand_mshr_misses::cpu.inst 364 # number of demand (read+write) MSHR misses 595system.cpu.l2cache.demand_mshr_misses::cpu.data 169 # number of demand (read+write) MSHR misses 596system.cpu.l2cache.demand_mshr_misses::total 533 # number of demand (read+write) MSHR misses 597system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses 598system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses 599system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses 600system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686750 # number of ReadReq MSHR miss cycles 601system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6260250 # number of ReadReq MSHR miss cycles 602system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28947000 # number of ReadReq MSHR miss cycles 603system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4378250 # number of ReadExReq MSHR miss cycles 604system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4378250 # number of ReadExReq MSHR miss cycles 605system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686750 # number of demand (read+write) MSHR miss cycles 606system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10638500 # number of demand (read+write) MSHR miss cycles 607system.cpu.l2cache.demand_mshr_miss_latency::total 33325250 # number of demand (read+write) MSHR miss cycles 608system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686750 # number of overall MSHR miss cycles 609system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10638500 # number of overall MSHR miss cycles 610system.cpu.l2cache.overall_mshr_miss_latency::total 33325250 # number of overall MSHR miss cycles 611system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadReq accesses 612system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 613system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses 614system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 615system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 616system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for demand accesses 617system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 618system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 # mshr miss rate for demand accesses 619system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses 620system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 621system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses 622system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62326.236264 # average ReadReq mshr miss latency 623system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65210.937500 # average ReadReq mshr miss latency 624system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62928.260870 # average ReadReq mshr miss latency 625system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59976.027397 # average ReadExReq mshr miss latency 626system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59976.027397 # average ReadExReq mshr miss latency 627system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency 628system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency 629system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency 630system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency 631system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency 632system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency 633system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 634system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution 635system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution 636system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 637system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 638system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 730 # Packet count per connected master and slave (bytes) 639system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 338 # Packet count per connected master and slave (bytes) 640system.cpu.toL2Bus.pkt_count::total 1068 # Packet count per connected master and slave (bytes) 641system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23360 # Cumulative packet size per connected master and slave (bytes) 642system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10816 # Cumulative packet size per connected master and slave (bytes) 643system.cpu.toL2Bus.pkt_size::total 34176 # Cumulative packet size per connected master and slave (bytes) 644system.cpu.toL2Bus.snoops 0 # Total snoops (count) 645system.cpu.toL2Bus.snoop_fanout::samples 534 # Request fanout histogram 646system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 647system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 648system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 649system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 650system.cpu.toL2Bus.snoop_fanout::1 534 100.00% 100.00% # Request fanout histogram 651system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 652system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 653system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 654system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 655system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram 656system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) 657system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 658system.cpu.toL2Bus.respLayer0.occupancy 629250 # Layer occupancy (ticks) 659system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) 660system.cpu.toL2Bus.respLayer1.occupancy 286000 # Layer occupancy (ticks) 661system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 662system.membus.trans_dist::ReadReq 460 # Transaction distribution 663system.membus.trans_dist::ReadResp 460 # Transaction distribution 664system.membus.trans_dist::ReadExReq 73 # Transaction distribution 665system.membus.trans_dist::ReadExResp 73 # Transaction distribution 666system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1066 # Packet count per connected master and slave (bytes) 667system.membus.pkt_count::total 1066 # Packet count per connected master and slave (bytes) 668system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34112 # Cumulative packet size per connected master and slave (bytes) 669system.membus.pkt_size::total 34112 # Cumulative packet size per connected master and slave (bytes) 670system.membus.snoops 0 # Total snoops (count) 671system.membus.snoop_fanout::samples 533 # Request fanout histogram 672system.membus.snoop_fanout::mean 0 # Request fanout histogram 673system.membus.snoop_fanout::stdev 0 # Request fanout histogram 674system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 675system.membus.snoop_fanout::0 533 100.00% 100.00% # Request fanout histogram 676system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 677system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 678system.membus.snoop_fanout::min_value 0 # Request fanout histogram 679system.membus.snoop_fanout::max_value 0 # Request fanout histogram 680system.membus.snoop_fanout::total 533 # Request fanout histogram 681system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) 682system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) 683system.membus.respLayer1.occupancy 2833250 # Layer occupancy (ticks) 684system.membus.respLayer1.utilization 7.5 # Layer utilization (%) 685 686---------- End Simulation Statistics ---------- 687