stats.txt revision 8802:ef66a9083bc4
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.195470 # Number of seconds simulated 4sim_ticks 5195470393000 # Number of ticks simulated 5final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1681123 # Simulator instruction rate (inst/s) 8host_tick_rate 32940960656 # Simulator tick rate (ticks/s) 9host_mem_usage 349824 # Number of bytes of host memory used 10host_seconds 157.72 # Real time elapsed on the host 11sim_insts 265147881 # Number of instructions simulated 12system.physmem.bytes_read 13764096 # Number of bytes read from this memory 13system.physmem.bytes_inst_read 974400 # Number of instructions bytes read from this memory 14system.physmem.bytes_written 10427072 # Number of bytes written to this memory 15system.physmem.num_reads 215064 # Number of read requests responded to by this memory 16system.physmem.num_writes 162923 # Number of write requests responded to by this memory 17system.physmem.num_other 0 # Number of other requests responded to by this memory 18system.physmem.bw_read 2649249 # Total read bandwidth from this memory (bytes/s) 19system.physmem.bw_inst_read 187548 # Instruction read bandwidth from this memory (bytes/s) 20system.physmem.bw_write 2006954 # Write bandwidth from this memory (bytes/s) 21system.physmem.bw_total 4656204 # Total bandwidth to/from this memory (bytes/s) 22system.l2c.replacements 136133 # number of replacements 23system.l2c.tagsinuse 31389.895470 # Cycle average of tags in use 24system.l2c.total_refs 3363370 # Total number of references to valid blocks. 25system.l2c.sampled_refs 168244 # Sample count of references to valid blocks. 26system.l2c.avg_refs 19.991025 # Average number of references to valid blocks. 27system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 28system.l2c.occ_blocks::0 7910.895776 # Average occupied blocks per context 29system.l2c.occ_blocks::1 23478.999694 # Average occupied blocks per context 30system.l2c.occ_percent::0 0.120711 # Average percentage of cache occupancy 31system.l2c.occ_percent::1 0.358261 # Average percentage of cache occupancy 32system.l2c.ReadReq_hits::0 2047882 # number of ReadReq hits 33system.l2c.ReadReq_hits::1 9561 # number of ReadReq hits 34system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits 35system.l2c.Writeback_hits::0 1534567 # number of Writeback hits 36system.l2c.Writeback_hits::total 1534567 # number of Writeback hits 37system.l2c.UpgradeReq_hits::0 320 # number of UpgradeReq hits 38system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits 39system.l2c.ReadExReq_hits::0 192958 # number of ReadExReq hits 40system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits 41system.l2c.demand_hits::0 2240840 # number of demand (read+write) hits 42system.l2c.demand_hits::1 9561 # number of demand (read+write) hits 43system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits 44system.l2c.overall_hits::0 2240840 # number of overall hits 45system.l2c.overall_hits::1 9561 # number of overall hits 46system.l2c.overall_hits::total 2250401 # number of overall hits 47system.l2c.ReadReq_misses::0 50807 # number of ReadReq misses 48system.l2c.ReadReq_misses::1 23 # number of ReadReq misses 49system.l2c.ReadReq_misses::total 50830 # number of ReadReq misses 50system.l2c.UpgradeReq_misses::0 1369 # number of UpgradeReq misses 51system.l2c.UpgradeReq_misses::total 1369 # number of UpgradeReq misses 52system.l2c.ReadExReq_misses::0 120168 # number of ReadExReq misses 53system.l2c.ReadExReq_misses::total 120168 # number of ReadExReq misses 54system.l2c.demand_misses::0 170975 # number of demand (read+write) misses 55system.l2c.demand_misses::1 23 # number of demand (read+write) misses 56system.l2c.demand_misses::total 170998 # number of demand (read+write) misses 57system.l2c.overall_misses::0 170975 # number of overall misses 58system.l2c.overall_misses::1 23 # number of overall misses 59system.l2c.overall_misses::total 170998 # number of overall misses 60system.l2c.ReadReq_miss_latency 2656122500 # number of ReadReq miss cycles 61system.l2c.UpgradeReq_miss_latency 33778000 # number of UpgradeReq miss cycles 62system.l2c.ReadExReq_miss_latency 6249324500 # number of ReadExReq miss cycles 63system.l2c.demand_miss_latency 8905447000 # number of demand (read+write) miss cycles 64system.l2c.overall_miss_latency 8905447000 # number of overall miss cycles 65system.l2c.ReadReq_accesses::0 2098689 # number of ReadReq accesses(hits+misses) 66system.l2c.ReadReq_accesses::1 9584 # number of ReadReq accesses(hits+misses) 67system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses) 68system.l2c.Writeback_accesses::0 1534567 # number of Writeback accesses(hits+misses) 69system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses) 70system.l2c.UpgradeReq_accesses::0 1689 # number of UpgradeReq accesses(hits+misses) 71system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses) 72system.l2c.ReadExReq_accesses::0 313126 # number of ReadExReq accesses(hits+misses) 73system.l2c.ReadExReq_accesses::total 313126 # number of ReadExReq accesses(hits+misses) 74system.l2c.demand_accesses::0 2411815 # number of demand (read+write) accesses 75system.l2c.demand_accesses::1 9584 # number of demand (read+write) accesses 76system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses 77system.l2c.overall_accesses::0 2411815 # number of overall (read+write) accesses 78system.l2c.overall_accesses::1 9584 # number of overall (read+write) accesses 79system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses 80system.l2c.ReadReq_miss_rate::0 0.024209 # miss rate for ReadReq accesses 81system.l2c.ReadReq_miss_rate::1 0.002400 # miss rate for ReadReq accesses 82system.l2c.ReadReq_miss_rate::total 0.026609 # miss rate for ReadReq accesses 83system.l2c.UpgradeReq_miss_rate::0 0.810539 # miss rate for UpgradeReq accesses 84system.l2c.ReadExReq_miss_rate::0 0.383769 # miss rate for ReadExReq accesses 85system.l2c.demand_miss_rate::0 0.070891 # miss rate for demand accesses 86system.l2c.demand_miss_rate::1 0.002400 # miss rate for demand accesses 87system.l2c.demand_miss_rate::total 0.073290 # miss rate for demand accesses 88system.l2c.overall_miss_rate::0 0.070891 # miss rate for overall accesses 89system.l2c.overall_miss_rate::1 0.002400 # miss rate for overall accesses 90system.l2c.overall_miss_rate::total 0.073290 # miss rate for overall accesses 91system.l2c.ReadReq_avg_miss_latency::0 52278.672230 # average ReadReq miss latency 92system.l2c.ReadReq_avg_miss_latency::1 115483586.956522 # average ReadReq miss latency 93system.l2c.ReadReq_avg_miss_latency::total 115535865.628752 # average ReadReq miss latency 94system.l2c.UpgradeReq_avg_miss_latency::0 24673.484295 # average UpgradeReq miss latency 95system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency 96system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency 97system.l2c.ReadExReq_avg_miss_latency::0 52004.897310 # average ReadExReq miss latency 98system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency 99system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency 100system.l2c.demand_avg_miss_latency::0 52086.252376 # average overall miss latency 101system.l2c.demand_avg_miss_latency::1 387193347.826087 # average overall miss latency 102system.l2c.demand_avg_miss_latency::total 387245434.078463 # average overall miss latency 103system.l2c.overall_avg_miss_latency::0 52086.252376 # average overall miss latency 104system.l2c.overall_avg_miss_latency::1 387193347.826087 # average overall miss latency 105system.l2c.overall_avg_miss_latency::total 387245434.078463 # average overall miss latency 106system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 107system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 108system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 109system.l2c.blocked::no_targets 0 # number of cycles access was blocked 110system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 111system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 112system.l2c.fast_writes 0 # number of fast writes performed 113system.l2c.cache_copies 0 # number of cache copies performed 114system.l2c.writebacks 116255 # number of writebacks 115system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 116system.l2c.overall_mshr_hits 0 # number of overall MSHR hits 117system.l2c.ReadReq_mshr_misses 50830 # number of ReadReq MSHR misses 118system.l2c.UpgradeReq_mshr_misses 1369 # number of UpgradeReq MSHR misses 119system.l2c.ReadExReq_mshr_misses 120168 # number of ReadExReq MSHR misses 120system.l2c.demand_mshr_misses 170998 # number of demand (read+write) MSHR misses 121system.l2c.overall_mshr_misses 170998 # number of overall MSHR misses 122system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 123system.l2c.ReadReq_mshr_miss_latency 2046144000 # number of ReadReq MSHR miss cycles 124system.l2c.UpgradeReq_mshr_miss_latency 55109000 # number of UpgradeReq MSHR miss cycles 125system.l2c.ReadExReq_mshr_miss_latency 4807305000 # number of ReadExReq MSHR miss cycles 126system.l2c.demand_mshr_miss_latency 6853449000 # number of demand (read+write) MSHR miss cycles 127system.l2c.overall_mshr_miss_latency 6853449000 # number of overall MSHR miss cycles 128system.l2c.ReadReq_mshr_uncacheable_latency 56051785000 # number of ReadReq MSHR uncacheable cycles 129system.l2c.WriteReq_mshr_uncacheable_latency 1218050000 # number of WriteReq MSHR uncacheable cycles 130system.l2c.overall_mshr_uncacheable_latency 57269835000 # number of overall MSHR uncacheable cycles 131system.l2c.ReadReq_mshr_miss_rate::0 0.024220 # mshr miss rate for ReadReq accesses 132system.l2c.ReadReq_mshr_miss_rate::1 5.303631 # mshr miss rate for ReadReq accesses 133system.l2c.ReadReq_mshr_miss_rate::total 5.327851 # mshr miss rate for ReadReq accesses 134system.l2c.UpgradeReq_mshr_miss_rate::0 0.810539 # mshr miss rate for UpgradeReq accesses 135system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses 136system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses 137system.l2c.ReadExReq_mshr_miss_rate::0 0.383769 # mshr miss rate for ReadExReq accesses 138system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses 139system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses 140system.l2c.demand_mshr_miss_rate::0 0.070900 # mshr miss rate for demand accesses 141system.l2c.demand_mshr_miss_rate::1 17.842028 # mshr miss rate for demand accesses 142system.l2c.demand_mshr_miss_rate::total 17.912929 # mshr miss rate for demand accesses 143system.l2c.overall_mshr_miss_rate::0 0.070900 # mshr miss rate for overall accesses 144system.l2c.overall_mshr_miss_rate::1 17.842028 # mshr miss rate for overall accesses 145system.l2c.overall_mshr_miss_rate::total 17.912929 # mshr miss rate for overall accesses 146system.l2c.ReadReq_avg_mshr_miss_latency 40254.652764 # average ReadReq mshr miss latency 147system.l2c.UpgradeReq_avg_mshr_miss_latency 40254.930606 # average UpgradeReq mshr miss latency 148system.l2c.ReadExReq_avg_mshr_miss_latency 40004.868185 # average ReadExReq mshr miss latency 149system.l2c.demand_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency 150system.l2c.overall_avg_mshr_miss_latency 40079.117884 # average overall mshr miss latency 151system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 152system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 153system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 154system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 155system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 156system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 157system.iocache.replacements 47510 # number of replacements 158system.iocache.tagsinuse 0.120586 # Cycle average of tags in use 159system.iocache.total_refs 0 # Total number of references to valid blocks. 160system.iocache.sampled_refs 47526 # Sample count of references to valid blocks. 161system.iocache.avg_refs 0 # Average number of references to valid blocks. 162system.iocache.warmup_cycle 5048756072000 # Cycle when the warmup percentage was hit. 163system.iocache.occ_blocks::1 0.120586 # Average occupied blocks per context 164system.iocache.occ_percent::1 0.007537 # Average percentage of cache occupancy 165system.iocache.demand_hits::0 0 # number of demand (read+write) hits 166system.iocache.demand_hits::1 0 # number of demand (read+write) hits 167system.iocache.demand_hits::total 0 # number of demand (read+write) hits 168system.iocache.overall_hits::0 0 # number of overall hits 169system.iocache.overall_hits::1 0 # number of overall hits 170system.iocache.overall_hits::total 0 # number of overall hits 171system.iocache.ReadReq_misses::1 844 # number of ReadReq misses 172system.iocache.ReadReq_misses::total 844 # number of ReadReq misses 173system.iocache.WriteReq_misses::1 46720 # number of WriteReq misses 174system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 175system.iocache.demand_misses::0 0 # number of demand (read+write) misses 176system.iocache.demand_misses::1 47564 # number of demand (read+write) misses 177system.iocache.demand_misses::total 47564 # number of demand (read+write) misses 178system.iocache.overall_misses::0 0 # number of overall misses 179system.iocache.overall_misses::1 47564 # number of overall misses 180system.iocache.overall_misses::total 47564 # number of overall misses 181system.iocache.ReadReq_miss_latency 106575932 # number of ReadReq miss cycles 182system.iocache.WriteReq_miss_latency 6391379160 # number of WriteReq miss cycles 183system.iocache.demand_miss_latency 6497955092 # number of demand (read+write) miss cycles 184system.iocache.overall_miss_latency 6497955092 # number of overall miss cycles 185system.iocache.ReadReq_accesses::1 844 # number of ReadReq accesses(hits+misses) 186system.iocache.ReadReq_accesses::total 844 # number of ReadReq accesses(hits+misses) 187system.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) 188system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 189system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 190system.iocache.demand_accesses::1 47564 # number of demand (read+write) accesses 191system.iocache.demand_accesses::total 47564 # number of demand (read+write) accesses 192system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 193system.iocache.overall_accesses::1 47564 # number of overall (read+write) accesses 194system.iocache.overall_accesses::total 47564 # number of overall (read+write) accesses 195system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 196system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 197system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 198system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 199system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 200system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 201system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 202system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 203system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency 204system.iocache.ReadReq_avg_miss_latency::1 126274.800948 # average ReadReq miss latency 205system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 206system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency 207system.iocache.WriteReq_avg_miss_latency::1 136801.779966 # average WriteReq miss latency 208system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 209system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency 210system.iocache.demand_avg_miss_latency::1 136614.983853 # average overall miss latency 211system.iocache.demand_avg_miss_latency::total inf # average overall miss latency 212system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency 213system.iocache.overall_avg_miss_latency::1 136614.983853 # average overall miss latency 214system.iocache.overall_avg_miss_latency::total inf # average overall miss latency 215system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked 216system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 217system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked 218system.iocache.blocked::no_targets 0 # number of cycles access was blocked 219system.iocache.avg_blocked_cycles::no_mshrs 6156.708027 # average number of cycles each access was blocked 220system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 221system.iocache.fast_writes 0 # number of fast writes performed 222system.iocache.cache_copies 0 # number of cache copies performed 223system.iocache.writebacks 46668 # number of writebacks 224system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 225system.iocache.overall_mshr_hits 0 # number of overall MSHR hits 226system.iocache.ReadReq_mshr_misses 844 # number of ReadReq MSHR misses 227system.iocache.WriteReq_mshr_misses 46720 # number of WriteReq MSHR misses 228system.iocache.demand_mshr_misses 47564 # number of demand (read+write) MSHR misses 229system.iocache.overall_mshr_misses 47564 # number of overall MSHR misses 230system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 231system.iocache.ReadReq_mshr_miss_latency 62666978 # number of ReadReq MSHR miss cycles 232system.iocache.WriteReq_mshr_miss_latency 3961676998 # number of WriteReq MSHR miss cycles 233system.iocache.demand_mshr_miss_latency 4024343976 # number of demand (read+write) MSHR miss cycles 234system.iocache.overall_mshr_miss_latency 4024343976 # number of overall MSHR miss cycles 235system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 236system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses 237system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses 238system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 239system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses 240system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses 241system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 242system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses 243system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses 244system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 245system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses 246system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses 247system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 248system.iocache.ReadReq_avg_mshr_miss_latency 74249.973934 # average ReadReq mshr miss latency 249system.iocache.WriteReq_avg_mshr_miss_latency 84796.168622 # average WriteReq mshr miss latency 250system.iocache.demand_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency 251system.iocache.overall_avg_mshr_miss_latency 84609.031536 # average overall mshr miss latency 252system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 253system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 254system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 255system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 256system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 257system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 258system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 259system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 260system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 261system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 262system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 263system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 264system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 265system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 266system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 267system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 268system.cpu.numCycles 10390940786 # number of cpu cycles simulated 269system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 270system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 271system.cpu.num_insts 265147881 # Number of instructions executed 272system.cpu.num_int_alu_accesses 249556386 # Number of integer alu accesses 273system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 274system.cpu.num_func_calls 0 # number of times a function call or return occured 275system.cpu.num_conditional_control_insts 24882695 # number of instructions that are conditional controls 276system.cpu.num_int_insts 249556386 # number of integer instructions 277system.cpu.num_fp_insts 0 # number of float instructions 278system.cpu.num_int_register_reads 543487907 # number of times the integer registers were read 279system.cpu.num_int_register_writes 266037487 # number of times the integer registers were written 280system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 281system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 282system.cpu.num_mem_refs 23169904 # number of memory refs 283system.cpu.num_load_insts 14812525 # Number of load instructions 284system.cpu.num_store_insts 8357379 # Number of store instructions 285system.cpu.num_idle_cycles 9787777240.878117 # Number of idle cycles 286system.cpu.num_busy_cycles 603163545.121884 # Number of busy cycles 287system.cpu.not_idle_fraction 0.058047 # Percentage of non-idle cycles 288system.cpu.idle_fraction 0.941953 # Percentage of idle cycles 289system.cpu.kern.inst.arm 0 # number of arm instructions executed 290system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 291system.cpu.icache.replacements 788139 # number of replacements 292system.cpu.icache.tagsinuse 510.361283 # Cycle average of tags in use 293system.cpu.icache.total_refs 158433932 # Total number of references to valid blocks. 294system.cpu.icache.sampled_refs 788651 # Sample count of references to valid blocks. 295system.cpu.icache.avg_refs 200.892324 # Average number of references to valid blocks. 296system.cpu.icache.warmup_cycle 160047116000 # Cycle when the warmup percentage was hit. 297system.cpu.icache.occ_blocks::0 510.361283 # Average occupied blocks per context 298system.cpu.icache.occ_percent::0 0.996799 # Average percentage of cache occupancy 299system.cpu.icache.ReadReq_hits::0 158433932 # number of ReadReq hits 300system.cpu.icache.ReadReq_hits::total 158433932 # number of ReadReq hits 301system.cpu.icache.demand_hits::0 158433932 # number of demand (read+write) hits 302system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 303system.cpu.icache.demand_hits::total 158433932 # number of demand (read+write) hits 304system.cpu.icache.overall_hits::0 158433932 # number of overall hits 305system.cpu.icache.overall_hits::1 0 # number of overall hits 306system.cpu.icache.overall_hits::total 158433932 # number of overall hits 307system.cpu.icache.ReadReq_misses::0 788658 # number of ReadReq misses 308system.cpu.icache.ReadReq_misses::total 788658 # number of ReadReq misses 309system.cpu.icache.demand_misses::0 788658 # number of demand (read+write) misses 310system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 311system.cpu.icache.demand_misses::total 788658 # number of demand (read+write) misses 312system.cpu.icache.overall_misses::0 788658 # number of overall misses 313system.cpu.icache.overall_misses::1 0 # number of overall misses 314system.cpu.icache.overall_misses::total 788658 # number of overall misses 315system.cpu.icache.ReadReq_miss_latency 11681762500 # number of ReadReq miss cycles 316system.cpu.icache.demand_miss_latency 11681762500 # number of demand (read+write) miss cycles 317system.cpu.icache.overall_miss_latency 11681762500 # number of overall miss cycles 318system.cpu.icache.ReadReq_accesses::0 159222590 # number of ReadReq accesses(hits+misses) 319system.cpu.icache.ReadReq_accesses::total 159222590 # number of ReadReq accesses(hits+misses) 320system.cpu.icache.demand_accesses::0 159222590 # number of demand (read+write) accesses 321system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 322system.cpu.icache.demand_accesses::total 159222590 # number of demand (read+write) accesses 323system.cpu.icache.overall_accesses::0 159222590 # number of overall (read+write) accesses 324system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 325system.cpu.icache.overall_accesses::total 159222590 # number of overall (read+write) accesses 326system.cpu.icache.ReadReq_miss_rate::0 0.004953 # miss rate for ReadReq accesses 327system.cpu.icache.demand_miss_rate::0 0.004953 # miss rate for demand accesses 328system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 329system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 330system.cpu.icache.overall_miss_rate::0 0.004953 # miss rate for overall accesses 331system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 332system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 333system.cpu.icache.ReadReq_avg_miss_latency::0 14812.203135 # average ReadReq miss latency 334system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 335system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 336system.cpu.icache.demand_avg_miss_latency::0 14812.203135 # average overall miss latency 337system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency 338system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency 339system.cpu.icache.overall_avg_miss_latency::0 14812.203135 # average overall miss latency 340system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency 341system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency 342system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 343system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 344system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 345system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 346system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 347system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 348system.cpu.icache.fast_writes 0 # number of fast writes performed 349system.cpu.icache.cache_copies 0 # number of cache copies performed 350system.cpu.icache.writebacks 805 # number of writebacks 351system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 352system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 353system.cpu.icache.ReadReq_mshr_misses 788658 # number of ReadReq MSHR misses 354system.cpu.icache.demand_mshr_misses 788658 # number of demand (read+write) MSHR misses 355system.cpu.icache.overall_mshr_misses 788658 # number of overall MSHR misses 356system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 357system.cpu.icache.ReadReq_mshr_miss_latency 9314744000 # number of ReadReq MSHR miss cycles 358system.cpu.icache.demand_mshr_miss_latency 9314744000 # number of demand (read+write) MSHR miss cycles 359system.cpu.icache.overall_mshr_miss_latency 9314744000 # number of overall MSHR miss cycles 360system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 361system.cpu.icache.ReadReq_mshr_miss_rate::0 0.004953 # mshr miss rate for ReadReq accesses 362system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 363system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 364system.cpu.icache.demand_mshr_miss_rate::0 0.004953 # mshr miss rate for demand accesses 365system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 366system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 367system.cpu.icache.overall_mshr_miss_rate::0 0.004953 # mshr miss rate for overall accesses 368system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 369system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 370system.cpu.icache.ReadReq_avg_mshr_miss_latency 11810.878733 # average ReadReq mshr miss latency 371system.cpu.icache.demand_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency 372system.cpu.icache.overall_avg_mshr_miss_latency 11810.878733 # average overall mshr miss latency 373system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 374system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 375system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 376system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 377system.cpu.itb_walker_cache.replacements 3754 # number of replacements 378system.cpu.itb_walker_cache.tagsinuse 3.070606 # Cycle average of tags in use 379system.cpu.itb_walker_cache.total_refs 7549 # Total number of references to valid blocks. 380system.cpu.itb_walker_cache.sampled_refs 3765 # Sample count of references to valid blocks. 381system.cpu.itb_walker_cache.avg_refs 2.005046 # Average number of references to valid blocks. 382system.cpu.itb_walker_cache.warmup_cycle 5178573163000 # Cycle when the warmup percentage was hit. 383system.cpu.itb_walker_cache.occ_blocks::1 3.070606 # Average occupied blocks per context 384system.cpu.itb_walker_cache.occ_percent::1 0.191913 # Average percentage of cache occupancy 385system.cpu.itb_walker_cache.ReadReq_hits::1 7619 # number of ReadReq hits 386system.cpu.itb_walker_cache.ReadReq_hits::total 7619 # number of ReadReq hits 387system.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits 388system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 389system.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits 390system.cpu.itb_walker_cache.demand_hits::1 7621 # number of demand (read+write) hits 391system.cpu.itb_walker_cache.demand_hits::total 7621 # number of demand (read+write) hits 392system.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits 393system.cpu.itb_walker_cache.overall_hits::1 7621 # number of overall hits 394system.cpu.itb_walker_cache.overall_hits::total 7621 # number of overall hits 395system.cpu.itb_walker_cache.ReadReq_misses::1 4602 # number of ReadReq misses 396system.cpu.itb_walker_cache.ReadReq_misses::total 4602 # number of ReadReq misses 397system.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses 398system.cpu.itb_walker_cache.demand_misses::1 4602 # number of demand (read+write) misses 399system.cpu.itb_walker_cache.demand_misses::total 4602 # number of demand (read+write) misses 400system.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses 401system.cpu.itb_walker_cache.overall_misses::1 4602 # number of overall misses 402system.cpu.itb_walker_cache.overall_misses::total 4602 # number of overall misses 403system.cpu.itb_walker_cache.ReadReq_miss_latency 50817000 # number of ReadReq miss cycles 404system.cpu.itb_walker_cache.demand_miss_latency 50817000 # number of demand (read+write) miss cycles 405system.cpu.itb_walker_cache.overall_miss_latency 50817000 # number of overall miss cycles 406system.cpu.itb_walker_cache.ReadReq_accesses::1 12221 # number of ReadReq accesses(hits+misses) 407system.cpu.itb_walker_cache.ReadReq_accesses::total 12221 # number of ReadReq accesses(hits+misses) 408system.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) 409system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 410system.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses 411system.cpu.itb_walker_cache.demand_accesses::1 12223 # number of demand (read+write) accesses 412system.cpu.itb_walker_cache.demand_accesses::total 12223 # number of demand (read+write) accesses 413system.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses 414system.cpu.itb_walker_cache.overall_accesses::1 12223 # number of overall (read+write) accesses 415system.cpu.itb_walker_cache.overall_accesses::total 12223 # number of overall (read+write) accesses 416system.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.376565 # miss rate for ReadReq accesses 417system.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses 418system.cpu.itb_walker_cache.demand_miss_rate::1 0.376503 # miss rate for demand accesses 419system.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses 420system.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses 421system.cpu.itb_walker_cache.overall_miss_rate::1 0.376503 # miss rate for overall accesses 422system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses 423system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency 424system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 11042.372881 # average ReadReq miss latency 425system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 426system.cpu.itb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency 427system.cpu.itb_walker_cache.demand_avg_miss_latency::1 11042.372881 # average overall miss latency 428system.cpu.itb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency 429system.cpu.itb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency 430system.cpu.itb_walker_cache.overall_avg_miss_latency::1 11042.372881 # average overall miss latency 431system.cpu.itb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency 432system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 433system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 434system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 435system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 436system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 437system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 438system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 439system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 440system.cpu.itb_walker_cache.writebacks 826 # number of writebacks 441system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 442system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits 443system.cpu.itb_walker_cache.ReadReq_mshr_misses 4602 # number of ReadReq MSHR misses 444system.cpu.itb_walker_cache.demand_mshr_misses 4602 # number of demand (read+write) MSHR misses 445system.cpu.itb_walker_cache.overall_mshr_misses 4602 # number of overall MSHR misses 446system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 447system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency 37011000 # number of ReadReq MSHR miss cycles 448system.cpu.itb_walker_cache.demand_mshr_miss_latency 37011000 # number of demand (read+write) MSHR miss cycles 449system.cpu.itb_walker_cache.overall_mshr_miss_latency 37011000 # number of overall MSHR miss cycles 450system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 451system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses 452system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1 0.376565 # mshr miss rate for ReadReq accesses 453system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 454system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses 455system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0.376503 # mshr miss rate for demand accesses 456system.cpu.itb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 457system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses 458system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0.376503 # mshr miss rate for overall accesses 459system.cpu.itb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 460system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency 8042.372881 # average ReadReq mshr miss latency 461system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency 462system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency 8042.372881 # average overall mshr miss latency 463system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 464system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated 465system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 466system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 467system.cpu.dtb_walker_cache.replacements 7704 # number of replacements 468system.cpu.dtb_walker_cache.tagsinuse 5.052403 # Cycle average of tags in use 469system.cpu.dtb_walker_cache.total_refs 13051 # Total number of references to valid blocks. 470system.cpu.dtb_walker_cache.sampled_refs 7716 # Sample count of references to valid blocks. 471system.cpu.dtb_walker_cache.avg_refs 1.691420 # Average number of references to valid blocks. 472system.cpu.dtb_walker_cache.warmup_cycle 5160674969000 # Cycle when the warmup percentage was hit. 473system.cpu.dtb_walker_cache.occ_blocks::1 5.052403 # Average occupied blocks per context 474system.cpu.dtb_walker_cache.occ_percent::1 0.315775 # Average percentage of cache occupancy 475system.cpu.dtb_walker_cache.ReadReq_hits::1 13051 # number of ReadReq hits 476system.cpu.dtb_walker_cache.ReadReq_hits::total 13051 # number of ReadReq hits 477system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits 478system.cpu.dtb_walker_cache.demand_hits::1 13051 # number of demand (read+write) hits 479system.cpu.dtb_walker_cache.demand_hits::total 13051 # number of demand (read+write) hits 480system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits 481system.cpu.dtb_walker_cache.overall_hits::1 13051 # number of overall hits 482system.cpu.dtb_walker_cache.overall_hits::total 13051 # number of overall hits 483system.cpu.dtb_walker_cache.ReadReq_misses::1 8896 # number of ReadReq misses 484system.cpu.dtb_walker_cache.ReadReq_misses::total 8896 # number of ReadReq misses 485system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses 486system.cpu.dtb_walker_cache.demand_misses::1 8896 # number of demand (read+write) misses 487system.cpu.dtb_walker_cache.demand_misses::total 8896 # number of demand (read+write) misses 488system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses 489system.cpu.dtb_walker_cache.overall_misses::1 8896 # number of overall misses 490system.cpu.dtb_walker_cache.overall_misses::total 8896 # number of overall misses 491system.cpu.dtb_walker_cache.ReadReq_miss_latency 103895500 # number of ReadReq miss cycles 492system.cpu.dtb_walker_cache.demand_miss_latency 103895500 # number of demand (read+write) miss cycles 493system.cpu.dtb_walker_cache.overall_miss_latency 103895500 # number of overall miss cycles 494system.cpu.dtb_walker_cache.ReadReq_accesses::1 21947 # number of ReadReq accesses(hits+misses) 495system.cpu.dtb_walker_cache.ReadReq_accesses::total 21947 # number of ReadReq accesses(hits+misses) 496system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses 497system.cpu.dtb_walker_cache.demand_accesses::1 21947 # number of demand (read+write) accesses 498system.cpu.dtb_walker_cache.demand_accesses::total 21947 # number of demand (read+write) accesses 499system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses 500system.cpu.dtb_walker_cache.overall_accesses::1 21947 # number of overall (read+write) accesses 501system.cpu.dtb_walker_cache.overall_accesses::total 21947 # number of overall (read+write) accesses 502system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.405340 # miss rate for ReadReq accesses 503system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses 504system.cpu.dtb_walker_cache.demand_miss_rate::1 0.405340 # miss rate for demand accesses 505system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses 506system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses 507system.cpu.dtb_walker_cache.overall_miss_rate::1 0.405340 # miss rate for overall accesses 508system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses 509system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency 510system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 11678.900629 # average ReadReq miss latency 511system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 512system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 inf # average overall miss latency 513system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 11678.900629 # average overall miss latency 514system.cpu.dtb_walker_cache.demand_avg_miss_latency::total inf # average overall miss latency 515system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 inf # average overall miss latency 516system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 11678.900629 # average overall miss latency 517system.cpu.dtb_walker_cache.overall_avg_miss_latency::total inf # average overall miss latency 518system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 519system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 520system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 521system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 522system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 523system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 524system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 525system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 526system.cpu.dtb_walker_cache.writebacks 2985 # number of writebacks 527system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 528system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits 529system.cpu.dtb_walker_cache.ReadReq_mshr_misses 8896 # number of ReadReq MSHR misses 530system.cpu.dtb_walker_cache.demand_mshr_misses 8896 # number of demand (read+write) MSHR misses 531system.cpu.dtb_walker_cache.overall_mshr_misses 8896 # number of overall MSHR misses 532system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 533system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency 77207000 # number of ReadReq MSHR miss cycles 534system.cpu.dtb_walker_cache.demand_mshr_miss_latency 77207000 # number of demand (read+write) MSHR miss cycles 535system.cpu.dtb_walker_cache.overall_mshr_miss_latency 77207000 # number of overall MSHR miss cycles 536system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 537system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses 538system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1 0.405340 # mshr miss rate for ReadReq accesses 539system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 540system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses 541system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0.405340 # mshr miss rate for demand accesses 542system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 543system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses 544system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0.405340 # mshr miss rate for overall accesses 545system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 546system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 8678.844424 # average ReadReq mshr miss latency 547system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency 548system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 8678.844424 # average overall mshr miss latency 549system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 550system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated 551system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 552system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 553system.cpu.dcache.replacements 1623424 # number of replacements 554system.cpu.dcache.tagsinuse 511.997312 # Cycle average of tags in use 555system.cpu.dcache.total_refs 20011404 # Total number of references to valid blocks. 556system.cpu.dcache.sampled_refs 1623936 # Sample count of references to valid blocks. 557system.cpu.dcache.avg_refs 12.322779 # Average number of references to valid blocks. 558system.cpu.dcache.warmup_cycle 44345000 # Cycle when the warmup percentage was hit. 559system.cpu.dcache.occ_blocks::0 511.997312 # Average occupied blocks per context 560system.cpu.dcache.occ_percent::0 0.999995 # Average percentage of cache occupancy 561system.cpu.dcache.ReadReq_hits::0 11977182 # number of ReadReq hits 562system.cpu.dcache.ReadReq_hits::total 11977182 # number of ReadReq hits 563system.cpu.dcache.WriteReq_hits::0 8032009 # number of WriteReq hits 564system.cpu.dcache.WriteReq_hits::total 8032009 # number of WriteReq hits 565system.cpu.dcache.demand_hits::0 20009191 # number of demand (read+write) hits 566system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 567system.cpu.dcache.demand_hits::total 20009191 # number of demand (read+write) hits 568system.cpu.dcache.overall_hits::0 20009191 # number of overall hits 569system.cpu.dcache.overall_hits::1 0 # number of overall hits 570system.cpu.dcache.overall_hits::total 20009191 # number of overall hits 571system.cpu.dcache.ReadReq_misses::0 1310824 # number of ReadReq misses 572system.cpu.dcache.ReadReq_misses::total 1310824 # number of ReadReq misses 573system.cpu.dcache.WriteReq_misses::0 315344 # number of WriteReq misses 574system.cpu.dcache.WriteReq_misses::total 315344 # number of WriteReq misses 575system.cpu.dcache.demand_misses::0 1626168 # number of demand (read+write) misses 576system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 577system.cpu.dcache.demand_misses::total 1626168 # number of demand (read+write) misses 578system.cpu.dcache.overall_misses::0 1626168 # number of overall misses 579system.cpu.dcache.overall_misses::1 0 # number of overall misses 580system.cpu.dcache.overall_misses::total 1626168 # number of overall misses 581system.cpu.dcache.ReadReq_miss_latency 19851809000 # number of ReadReq miss cycles 582system.cpu.dcache.WriteReq_miss_latency 9514837000 # number of WriteReq miss cycles 583system.cpu.dcache.demand_miss_latency 29366646000 # number of demand (read+write) miss cycles 584system.cpu.dcache.overall_miss_latency 29366646000 # number of overall miss cycles 585system.cpu.dcache.ReadReq_accesses::0 13288006 # number of ReadReq accesses(hits+misses) 586system.cpu.dcache.ReadReq_accesses::total 13288006 # number of ReadReq accesses(hits+misses) 587system.cpu.dcache.WriteReq_accesses::0 8347353 # number of WriteReq accesses(hits+misses) 588system.cpu.dcache.WriteReq_accesses::total 8347353 # number of WriteReq accesses(hits+misses) 589system.cpu.dcache.demand_accesses::0 21635359 # number of demand (read+write) accesses 590system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 591system.cpu.dcache.demand_accesses::total 21635359 # number of demand (read+write) accesses 592system.cpu.dcache.overall_accesses::0 21635359 # number of overall (read+write) accesses 593system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 594system.cpu.dcache.overall_accesses::total 21635359 # number of overall (read+write) accesses 595system.cpu.dcache.ReadReq_miss_rate::0 0.098647 # miss rate for ReadReq accesses 596system.cpu.dcache.WriteReq_miss_rate::0 0.037778 # miss rate for WriteReq accesses 597system.cpu.dcache.demand_miss_rate::0 0.075163 # miss rate for demand accesses 598system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 599system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 600system.cpu.dcache.overall_miss_rate::0 0.075163 # miss rate for overall accesses 601system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 602system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 603system.cpu.dcache.ReadReq_avg_miss_latency::0 15144.526649 # average ReadReq miss latency 604system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency 605system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency 606system.cpu.dcache.WriteReq_avg_miss_latency::0 30172.881044 # average WriteReq miss latency 607system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency 608system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency 609system.cpu.dcache.demand_avg_miss_latency::0 18058.802043 # average overall miss latency 610system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency 611system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency 612system.cpu.dcache.overall_avg_miss_latency::0 18058.802043 # average overall miss latency 613system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency 614system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency 615system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 616system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 617system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 618system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 619system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 620system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 621system.cpu.dcache.fast_writes 0 # number of fast writes performed 622system.cpu.dcache.cache_copies 0 # number of cache copies performed 623system.cpu.dcache.writebacks 1529951 # number of writebacks 624system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 625system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 626system.cpu.dcache.ReadReq_mshr_misses 1310824 # number of ReadReq MSHR misses 627system.cpu.dcache.WriteReq_mshr_misses 315344 # number of WriteReq MSHR misses 628system.cpu.dcache.demand_mshr_misses 1626168 # number of demand (read+write) MSHR misses 629system.cpu.dcache.overall_mshr_misses 1626168 # number of overall MSHR misses 630system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 631system.cpu.dcache.ReadReq_mshr_miss_latency 15919294500 # number of ReadReq MSHR miss cycles 632system.cpu.dcache.WriteReq_mshr_miss_latency 8568794500 # number of WriteReq MSHR miss cycles 633system.cpu.dcache.demand_mshr_miss_latency 24488089000 # number of demand (read+write) MSHR miss cycles 634system.cpu.dcache.overall_mshr_miss_latency 24488089000 # number of overall MSHR miss cycles 635system.cpu.dcache.ReadReq_mshr_uncacheable_latency 75925324500 # number of ReadReq MSHR uncacheable cycles 636system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1379728500 # number of WriteReq MSHR uncacheable cycles 637system.cpu.dcache.overall_mshr_uncacheable_latency 77305053000 # number of overall MSHR uncacheable cycles 638system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098647 # mshr miss rate for ReadReq accesses 639system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses 640system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses 641system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.037778 # mshr miss rate for WriteReq accesses 642system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses 643system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses 644system.cpu.dcache.demand_mshr_miss_rate::0 0.075163 # mshr miss rate for demand accesses 645system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses 646system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses 647system.cpu.dcache.overall_mshr_miss_rate::0 0.075163 # mshr miss rate for overall accesses 648system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses 649system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses 650system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12144.494227 # average ReadReq mshr miss latency 651system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27172.847747 # average WriteReq mshr miss latency 652system.cpu.dcache.demand_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency 653system.cpu.dcache.overall_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency 654system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency 655system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency 656system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency 657system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 658system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 659system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 660 661---------- End Simulation Statistics ---------- 662