stats.txt revision 11219:b65d4e878ed2
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.194978 # Number of seconds simulated 4sim_ticks 5194978362500 # Number of ticks simulated 5final_tick 5194978362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 576808 # Simulator instruction rate (inst/s) 8host_op_rate 1111789 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 23330637170 # Simulator tick rate (ticks/s) 10host_mem_usage 654084 # Number of bytes of host memory used 11host_seconds 222.67 # Real time elapsed on the host 12sim_insts 128436556 # Number of instructions simulated 13sim_ops 247559471 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 821184 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9031104 # Number of bytes read from this memory 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 21system.physmem.bytes_read::total 9881024 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 821184 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 821184 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 8151488 # Number of bytes written to this memory 25system.physmem.bytes_written::total 8151488 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 12831 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 141111 # Number of read requests responded to by this memory 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 154391 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 127367 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 127367 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.inst 158073 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 1738430 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5458 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 1902034 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 158073 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 158073 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1569109 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1569109 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1569109 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.inst 158073 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 1738430 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5458 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 3471143 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 154391 # Number of read requests accepted 52system.physmem.writeReqs 127367 # Number of write requests accepted 53system.physmem.readBursts 154391 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 127367 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 9871424 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue 57system.physmem.bytesWritten 8149376 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 9881024 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 8151488 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 55287 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 10087 # Per bank write bursts 64system.physmem.perBankRdBursts::1 9529 # Per bank write bursts 65system.physmem.perBankRdBursts::2 9814 # Per bank write bursts 66system.physmem.perBankRdBursts::3 9652 # Per bank write bursts 67system.physmem.perBankRdBursts::4 10130 # Per bank write bursts 68system.physmem.perBankRdBursts::5 9950 # Per bank write bursts 69system.physmem.perBankRdBursts::6 9317 # Per bank write bursts 70system.physmem.perBankRdBursts::7 9200 # Per bank write bursts 71system.physmem.perBankRdBursts::8 8918 # Per bank write bursts 72system.physmem.perBankRdBursts::9 9357 # Per bank write bursts 73system.physmem.perBankRdBursts::10 9066 # Per bank write bursts 74system.physmem.perBankRdBursts::11 9331 # Per bank write bursts 75system.physmem.perBankRdBursts::12 9713 # Per bank write bursts 76system.physmem.perBankRdBursts::13 9915 # Per bank write bursts 77system.physmem.perBankRdBursts::14 10131 # Per bank write bursts 78system.physmem.perBankRdBursts::15 10131 # Per bank write bursts 79system.physmem.perBankWrBursts::0 8252 # Per bank write bursts 80system.physmem.perBankWrBursts::1 7742 # Per bank write bursts 81system.physmem.perBankWrBursts::2 7578 # Per bank write bursts 82system.physmem.perBankWrBursts::3 7566 # Per bank write bursts 83system.physmem.perBankWrBursts::4 7987 # Per bank write bursts 84system.physmem.perBankWrBursts::5 8326 # Per bank write bursts 85system.physmem.perBankWrBursts::6 7980 # Per bank write bursts 86system.physmem.perBankWrBursts::7 7858 # Per bank write bursts 87system.physmem.perBankWrBursts::8 7446 # Per bank write bursts 88system.physmem.perBankWrBursts::9 8118 # Per bank write bursts 89system.physmem.perBankWrBursts::10 7706 # Per bank write bursts 90system.physmem.perBankWrBursts::11 7948 # Per bank write bursts 91system.physmem.perBankWrBursts::12 8417 # Per bank write bursts 92system.physmem.perBankWrBursts::13 8510 # Per bank write bursts 93system.physmem.perBankWrBursts::14 8023 # Per bank write bursts 94system.physmem.perBankWrBursts::15 7877 # Per bank write bursts 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 2 # Number of times write queue was full causing retry 97system.physmem.totGap 5194978301500 # Total gap between requests 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) 104system.physmem.readPktSize::6 154391 # Read request sizes (log2) 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) 111system.physmem.writePktSize::6 127367 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 151033 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 2781 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 39 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 34 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 38 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 27 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 144system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::15 2416 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 2856 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 6275 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 6125 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 6693 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 6750 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 8169 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 7450 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 8822 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 9011 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 8677 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 10497 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 7589 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 6906 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 7071 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 6415 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 6214 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 6089 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 334 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 218 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 191 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 167 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 179 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 131 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 116 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 124 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 159 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 116 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 154 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 97 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 148 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 159 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 88 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 69 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 16 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 41 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 56850 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 316.988566 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 188.998481 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 329.316521 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 20120 35.39% 35.39% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 13756 24.20% 59.59% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 6339 11.15% 70.74% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 3490 6.14% 76.88% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 2421 4.26% 81.14% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 1596 2.81% 83.94% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1162 2.04% 85.99% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 976 1.72% 87.70% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 6990 12.30% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 56850 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 5891 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 26.179766 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 623.896687 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 5890 99.98% 99.98% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::total 5891 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 5891 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 21.615006 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 19.434725 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 14.404388 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-19 4837 82.11% 82.11% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20-23 110 1.87% 83.98% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::24-27 36 0.61% 84.59% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::28-31 242 4.11% 88.69% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::32-35 18 0.31% 89.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::36-39 210 3.56% 92.56% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::40-43 69 1.17% 93.74% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::44-47 3 0.05% 93.79% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::48-51 13 0.22% 94.01% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::52-55 22 0.37% 94.38% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::56-59 8 0.14% 94.52% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::60-63 6 0.10% 94.62% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::64-67 244 4.14% 98.76% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::68-71 5 0.08% 98.85% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::72-75 4 0.07% 98.91% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::76-79 27 0.46% 99.37% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::80-83 2 0.03% 99.41% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::84-87 2 0.03% 99.44% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::88-91 1 0.02% 99.46% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::100-103 2 0.03% 99.49% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::104-107 1 0.02% 99.51% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::112-115 2 0.03% 99.54% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::124-127 1 0.02% 99.56% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::128-131 18 0.31% 99.86% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::132-135 1 0.02% 99.88% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::136-139 1 0.02% 99.90% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::152-155 1 0.02% 99.92% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::156-159 2 0.03% 99.95% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::164-167 3 0.05% 100.00% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::total 5891 # Writes before turning the bus around for reads 262system.physmem.totQLat 1582264251 # Total ticks spent queuing 263system.physmem.totMemAccLat 4474283001 # Total ticks spent from burst creation until serviced by the DRAM 264system.physmem.totBusLat 771205000 # Total ticks spent in databus transfers 265system.physmem.avgQLat 10258.39 # Average queueing delay per DRAM burst 266system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 267system.physmem.avgMemAccLat 29008.39 # Average memory access latency per DRAM burst 268system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s 269system.physmem.avgWrBW 1.57 # Average achieved write bandwidth in MiByte/s 270system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s 271system.physmem.avgWrBWSys 1.57 # Average system write bandwidth in MiByte/s 272system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 273system.physmem.busUtil 0.03 # Data bus utilization in percentage 274system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 275system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 276system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 277system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing 278system.physmem.readRowHits 125535 # Number of row buffer hits during reads 279system.physmem.writeRowHits 99190 # Number of row buffer hits during writes 280system.physmem.readRowHitRate 81.39 # Row buffer hit rate for reads 281system.physmem.writeRowHitRate 77.88 # Row buffer hit rate for writes 282system.physmem.avgGap 18437731.32 # Average gap between requests 283system.physmem.pageHitRate 79.80 # Row buffer hit rate, read and write combined 284system.physmem_0.actEnergy 210712320 # Energy for activate commands per rank (pJ) 285system.physmem_0.preEnergy 114972000 # Energy for precharge commands per rank (pJ) 286system.physmem_0.readEnergy 605896200 # Energy for read commands per rank (pJ) 287system.physmem_0.writeEnergy 410112720 # Energy for write commands per rank (pJ) 288system.physmem_0.refreshEnergy 339310723440 # Energy for refresh commands per rank (pJ) 289system.physmem_0.actBackEnergy 137072385045 # Energy for active background per rank (pJ) 290system.physmem_0.preBackEnergy 2996748141750 # Energy for precharge background per rank (pJ) 291system.physmem_0.totalEnergy 3474472943475 # Total energy per rank (pJ) 292system.physmem_0.averagePower 668.813734 # Core power per rank (mW) 293system.physmem_0.memoryStateTime::IDLE 4985245725974 # Time in different power states 294system.physmem_0.memoryStateTime::REF 173471480000 # Time in different power states 295system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 296system.physmem_0.memoryStateTime::ACT 36261007776 # Time in different power states 297system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 298system.physmem_1.actEnergy 219073680 # Energy for activate commands per rank (pJ) 299system.physmem_1.preEnergy 119534250 # Energy for precharge commands per rank (pJ) 300system.physmem_1.readEnergy 597183600 # Energy for read commands per rank (pJ) 301system.physmem_1.writeEnergy 415011600 # Energy for write commands per rank (pJ) 302system.physmem_1.refreshEnergy 339310723440 # Energy for refresh commands per rank (pJ) 303system.physmem_1.actBackEnergy 137522699865 # Energy for active background per rank (pJ) 304system.physmem_1.preBackEnergy 2996353144500 # Energy for precharge background per rank (pJ) 305system.physmem_1.totalEnergy 3474537370935 # Total energy per rank (pJ) 306system.physmem_1.averagePower 668.826133 # Core power per rank (mW) 307system.physmem_1.memoryStateTime::IDLE 4984581893484 # Time in different power states 308system.physmem_1.memoryStateTime::REF 173471480000 # Time in different power states 309system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 310system.physmem_1.memoryStateTime::ACT 36924866266 # Time in different power states 311system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 312system.cpu_clk_domain.clock 500 # Clock period in ticks 313system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 314system.cpu.numCycles 10389956725 # number of cpu cycles simulated 315system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 316system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 317system.cpu.kern.inst.arm 0 # number of arm instructions executed 318system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 319system.cpu.committedInsts 128436556 # Number of instructions committed 320system.cpu.committedOps 247559471 # Number of ops (including micro ops) committed 321system.cpu.num_int_alu_accesses 232158304 # Number of integer alu accesses 322system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses 323system.cpu.num_func_calls 2315823 # number of times a function call or return occured 324system.cpu.num_conditional_control_insts 23152915 # number of instructions that are conditional controls 325system.cpu.num_int_insts 232158304 # number of integer instructions 326system.cpu.num_fp_insts 48 # number of float instructions 327system.cpu.num_int_register_reads 434959162 # number of times the integer registers were read 328system.cpu.num_int_register_writes 197962951 # number of times the integer registers were written 329system.cpu.num_fp_register_reads 48 # number of times the floating registers were read 330system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 331system.cpu.num_cc_register_reads 132872909 # number of times the CC registers were read 332system.cpu.num_cc_register_writes 95460932 # number of times the CC registers were written 333system.cpu.num_mem_refs 22321110 # number of memory refs 334system.cpu.num_load_insts 13911495 # Number of load instructions 335system.cpu.num_store_insts 8409615 # Number of store instructions 336system.cpu.num_idle_cycles 9773995534.086119 # Number of idle cycles 337system.cpu.num_busy_cycles 615961190.913881 # Number of busy cycles 338system.cpu.not_idle_fraction 0.059284 # Percentage of non-idle cycles 339system.cpu.idle_fraction 0.940716 # Percentage of idle cycles 340system.cpu.Branches 26327381 # Number of branches fetched 341system.cpu.op_class::No_OpClass 172225 0.07% 0.07% # Class of executed instruction 342system.cpu.op_class::IntAlu 224809718 90.81% 90.88% # Class of executed instruction 343system.cpu.op_class::IntMult 140099 0.06% 90.94% # Class of executed instruction 344system.cpu.op_class::IntDiv 122811 0.05% 90.99% # Class of executed instruction 345system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction 346system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction 347system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction 348system.cpu.op_class::FloatMult 0 0.00% 90.99% # Class of executed instruction 349system.cpu.op_class::FloatDiv 0 0.00% 90.99% # Class of executed instruction 350system.cpu.op_class::FloatSqrt 0 0.00% 90.99% # Class of executed instruction 351system.cpu.op_class::SimdAdd 0 0.00% 90.99% # Class of executed instruction 352system.cpu.op_class::SimdAddAcc 0 0.00% 90.99% # Class of executed instruction 353system.cpu.op_class::SimdAlu 0 0.00% 90.99% # Class of executed instruction 354system.cpu.op_class::SimdCmp 0 0.00% 90.99% # Class of executed instruction 355system.cpu.op_class::SimdCvt 0 0.00% 90.99% # Class of executed instruction 356system.cpu.op_class::SimdMisc 0 0.00% 90.99% # Class of executed instruction 357system.cpu.op_class::SimdMult 0 0.00% 90.99% # Class of executed instruction 358system.cpu.op_class::SimdMultAcc 0 0.00% 90.99% # Class of executed instruction 359system.cpu.op_class::SimdShift 0 0.00% 90.99% # Class of executed instruction 360system.cpu.op_class::SimdShiftAcc 0 0.00% 90.99% # Class of executed instruction 361system.cpu.op_class::SimdSqrt 0 0.00% 90.99% # Class of executed instruction 362system.cpu.op_class::SimdFloatAdd 0 0.00% 90.99% # Class of executed instruction 363system.cpu.op_class::SimdFloatAlu 0 0.00% 90.99% # Class of executed instruction 364system.cpu.op_class::SimdFloatCmp 0 0.00% 90.99% # Class of executed instruction 365system.cpu.op_class::SimdFloatCvt 0 0.00% 90.99% # Class of executed instruction 366system.cpu.op_class::SimdFloatDiv 0 0.00% 90.99% # Class of executed instruction 367system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Class of executed instruction 368system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction 369system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction 370system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction 371system.cpu.op_class::MemRead 13906523 5.62% 96.60% # Class of executed instruction 372system.cpu.op_class::MemWrite 8409615 3.40% 100.00% # Class of executed instruction 373system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 374system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 375system.cpu.op_class::total 247561007 # Class of executed instruction 376system.cpu.dcache.tags.replacements 1623701 # number of replacements 377system.cpu.dcache.tags.tagsinuse 511.995481 # Cycle average of tags in use 378system.cpu.dcache.tags.total_refs 20139430 # Total number of references to valid blocks. 379system.cpu.dcache.tags.sampled_refs 1624213 # Sample count of references to valid blocks. 380system.cpu.dcache.tags.avg_refs 12.399501 # Average number of references to valid blocks. 381system.cpu.dcache.tags.warmup_cycle 81561500 # Cycle when the warmup percentage was hit. 382system.cpu.dcache.tags.occ_blocks::cpu.data 511.995481 # Average occupied blocks per requestor 383system.cpu.dcache.tags.occ_percent::cpu.data 0.999991 # Average percentage of cache occupancy 384system.cpu.dcache.tags.occ_percent::total 0.999991 # Average percentage of cache occupancy 385system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 386system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 387system.cpu.dcache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id 388system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id 389system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 390system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 391system.cpu.dcache.tags.tag_accesses 88718098 # Number of tag accesses 392system.cpu.dcache.tags.data_accesses 88718098 # Number of data accesses 393system.cpu.dcache.ReadReq_hits::cpu.data 12002647 # number of ReadReq hits 394system.cpu.dcache.ReadReq_hits::total 12002647 # number of ReadReq hits 395system.cpu.dcache.WriteReq_hits::cpu.data 8075474 # number of WriteReq hits 396system.cpu.dcache.WriteReq_hits::total 8075474 # number of WriteReq hits 397system.cpu.dcache.SoftPFReq_hits::cpu.data 59092 # number of SoftPFReq hits 398system.cpu.dcache.SoftPFReq_hits::total 59092 # number of SoftPFReq hits 399system.cpu.dcache.demand_hits::cpu.data 20078121 # number of demand (read+write) hits 400system.cpu.dcache.demand_hits::total 20078121 # number of demand (read+write) hits 401system.cpu.dcache.overall_hits::cpu.data 20137213 # number of overall hits 402system.cpu.dcache.overall_hits::total 20137213 # number of overall hits 403system.cpu.dcache.ReadReq_misses::cpu.data 907310 # number of ReadReq misses 404system.cpu.dcache.ReadReq_misses::total 907310 # number of ReadReq misses 405system.cpu.dcache.WriteReq_misses::cpu.data 326145 # number of WriteReq misses 406system.cpu.dcache.WriteReq_misses::total 326145 # number of WriteReq misses 407system.cpu.dcache.SoftPFReq_misses::cpu.data 402797 # number of SoftPFReq misses 408system.cpu.dcache.SoftPFReq_misses::total 402797 # number of SoftPFReq misses 409system.cpu.dcache.demand_misses::cpu.data 1233455 # number of demand (read+write) misses 410system.cpu.dcache.demand_misses::total 1233455 # number of demand (read+write) misses 411system.cpu.dcache.overall_misses::cpu.data 1636252 # number of overall misses 412system.cpu.dcache.overall_misses::total 1636252 # number of overall misses 413system.cpu.dcache.ReadReq_miss_latency::cpu.data 13562374500 # number of ReadReq miss cycles 414system.cpu.dcache.ReadReq_miss_latency::total 13562374500 # number of ReadReq miss cycles 415system.cpu.dcache.WriteReq_miss_latency::cpu.data 18447994471 # number of WriteReq miss cycles 416system.cpu.dcache.WriteReq_miss_latency::total 18447994471 # number of WriteReq miss cycles 417system.cpu.dcache.demand_miss_latency::cpu.data 32010368971 # number of demand (read+write) miss cycles 418system.cpu.dcache.demand_miss_latency::total 32010368971 # number of demand (read+write) miss cycles 419system.cpu.dcache.overall_miss_latency::cpu.data 32010368971 # number of overall miss cycles 420system.cpu.dcache.overall_miss_latency::total 32010368971 # number of overall miss cycles 421system.cpu.dcache.ReadReq_accesses::cpu.data 12909957 # number of ReadReq accesses(hits+misses) 422system.cpu.dcache.ReadReq_accesses::total 12909957 # number of ReadReq accesses(hits+misses) 423system.cpu.dcache.WriteReq_accesses::cpu.data 8401619 # number of WriteReq accesses(hits+misses) 424system.cpu.dcache.WriteReq_accesses::total 8401619 # number of WriteReq accesses(hits+misses) 425system.cpu.dcache.SoftPFReq_accesses::cpu.data 461889 # number of SoftPFReq accesses(hits+misses) 426system.cpu.dcache.SoftPFReq_accesses::total 461889 # number of SoftPFReq accesses(hits+misses) 427system.cpu.dcache.demand_accesses::cpu.data 21311576 # number of demand (read+write) accesses 428system.cpu.dcache.demand_accesses::total 21311576 # number of demand (read+write) accesses 429system.cpu.dcache.overall_accesses::cpu.data 21773465 # number of overall (read+write) accesses 430system.cpu.dcache.overall_accesses::total 21773465 # number of overall (read+write) accesses 431system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070280 # miss rate for ReadReq accesses 432system.cpu.dcache.ReadReq_miss_rate::total 0.070280 # miss rate for ReadReq accesses 433system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038819 # miss rate for WriteReq accesses 434system.cpu.dcache.WriteReq_miss_rate::total 0.038819 # miss rate for WriteReq accesses 435system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872065 # miss rate for SoftPFReq accesses 436system.cpu.dcache.SoftPFReq_miss_rate::total 0.872065 # miss rate for SoftPFReq accesses 437system.cpu.dcache.demand_miss_rate::cpu.data 0.057877 # miss rate for demand accesses 438system.cpu.dcache.demand_miss_rate::total 0.057877 # miss rate for demand accesses 439system.cpu.dcache.overall_miss_rate::cpu.data 0.075149 # miss rate for overall accesses 440system.cpu.dcache.overall_miss_rate::total 0.075149 # miss rate for overall accesses 441system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14947.894876 # average ReadReq miss latency 442system.cpu.dcache.ReadReq_avg_miss_latency::total 14947.894876 # average ReadReq miss latency 443system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56563.781358 # average WriteReq miss latency 444system.cpu.dcache.WriteReq_avg_miss_latency::total 56563.781358 # average WriteReq miss latency 445system.cpu.dcache.demand_avg_miss_latency::cpu.data 25951.793110 # average overall miss latency 446system.cpu.dcache.demand_avg_miss_latency::total 25951.793110 # average overall miss latency 447system.cpu.dcache.overall_avg_miss_latency::cpu.data 19563.226796 # average overall miss latency 448system.cpu.dcache.overall_avg_miss_latency::total 19563.226796 # average overall miss latency 449system.cpu.dcache.blocked_cycles::no_mshrs 18014 # number of cycles access was blocked 450system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 451system.cpu.dcache.blocked::no_mshrs 511 # number of cycles access was blocked 452system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 453system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.252446 # average number of cycles each access was blocked 454system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 455system.cpu.dcache.fast_writes 0 # number of fast writes performed 456system.cpu.dcache.cache_copies 0 # number of cache copies performed 457system.cpu.dcache.writebacks::writebacks 1540806 # number of writebacks 458system.cpu.dcache.writebacks::total 1540806 # number of writebacks 459system.cpu.dcache.ReadReq_mshr_hits::cpu.data 287 # number of ReadReq MSHR hits 460system.cpu.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits 461system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9476 # number of WriteReq MSHR hits 462system.cpu.dcache.WriteReq_mshr_hits::total 9476 # number of WriteReq MSHR hits 463system.cpu.dcache.demand_mshr_hits::cpu.data 9763 # number of demand (read+write) MSHR hits 464system.cpu.dcache.demand_mshr_hits::total 9763 # number of demand (read+write) MSHR hits 465system.cpu.dcache.overall_mshr_hits::cpu.data 9763 # number of overall MSHR hits 466system.cpu.dcache.overall_mshr_hits::total 9763 # number of overall MSHR hits 467system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907023 # number of ReadReq MSHR misses 468system.cpu.dcache.ReadReq_mshr_misses::total 907023 # number of ReadReq MSHR misses 469system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316669 # number of WriteReq MSHR misses 470system.cpu.dcache.WriteReq_mshr_misses::total 316669 # number of WriteReq MSHR misses 471system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402763 # number of SoftPFReq MSHR misses 472system.cpu.dcache.SoftPFReq_mshr_misses::total 402763 # number of SoftPFReq MSHR misses 473system.cpu.dcache.demand_mshr_misses::cpu.data 1223692 # number of demand (read+write) MSHR misses 474system.cpu.dcache.demand_mshr_misses::total 1223692 # number of demand (read+write) MSHR misses 475system.cpu.dcache.overall_mshr_misses::cpu.data 1626455 # number of overall MSHR misses 476system.cpu.dcache.overall_mshr_misses::total 1626455 # number of overall MSHR misses 477system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable 478system.cpu.dcache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable 479system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable 480system.cpu.dcache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable 481system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses 482system.cpu.dcache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses 483system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12653263500 # number of ReadReq MSHR miss cycles 484system.cpu.dcache.ReadReq_mshr_miss_latency::total 12653263500 # number of ReadReq MSHR miss cycles 485system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17148578471 # number of WriteReq MSHR miss cycles 486system.cpu.dcache.WriteReq_mshr_miss_latency::total 17148578471 # number of WriteReq MSHR miss cycles 487system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 6516458500 # number of SoftPFReq MSHR miss cycles 488system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 6516458500 # number of SoftPFReq MSHR miss cycles 489system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29801841971 # number of demand (read+write) MSHR miss cycles 490system.cpu.dcache.demand_mshr_miss_latency::total 29801841971 # number of demand (read+write) MSHR miss cycles 491system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36318300471 # number of overall MSHR miss cycles 492system.cpu.dcache.overall_mshr_miss_latency::total 36318300471 # number of overall MSHR miss cycles 493system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 95164003500 # number of ReadReq MSHR uncacheable cycles 494system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 95164003500 # number of ReadReq MSHR uncacheable cycles 495system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2786304500 # number of WriteReq MSHR uncacheable cycles 496system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2786304500 # number of WriteReq MSHR uncacheable cycles 497system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 97950308000 # number of overall MSHR uncacheable cycles 498system.cpu.dcache.overall_mshr_uncacheable_latency::total 97950308000 # number of overall MSHR uncacheable cycles 499system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070258 # mshr miss rate for ReadReq accesses 500system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070258 # mshr miss rate for ReadReq accesses 501system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037691 # mshr miss rate for WriteReq accesses 502system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037691 # mshr miss rate for WriteReq accesses 503system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871991 # mshr miss rate for SoftPFReq accesses 504system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871991 # mshr miss rate for SoftPFReq accesses 505system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057419 # mshr miss rate for demand accesses 506system.cpu.dcache.demand_mshr_miss_rate::total 0.057419 # mshr miss rate for demand accesses 507system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074699 # mshr miss rate for overall accesses 508system.cpu.dcache.overall_mshr_miss_rate::total 0.074699 # mshr miss rate for overall accesses 509system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13950.322649 # average ReadReq mshr miss latency 510system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13950.322649 # average ReadReq mshr miss latency 511system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54153.006676 # average WriteReq mshr miss latency 512system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54153.006676 # average WriteReq mshr miss latency 513system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16179.387133 # average SoftPFReq mshr miss latency 514system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16179.387133 # average SoftPFReq mshr miss latency 515system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24354.038411 # average overall mshr miss latency 516system.cpu.dcache.demand_avg_mshr_miss_latency::total 24354.038411 # average overall mshr miss latency 517system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22329.729670 # average overall mshr miss latency 518system.cpu.dcache.overall_avg_mshr_miss_latency::total 22329.729670 # average overall mshr miss latency 519system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 174182.667211 # average ReadReq mshr uncacheable latency 520system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174182.667211 # average ReadReq mshr uncacheable latency 521system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 200165.553161 # average WriteReq mshr uncacheable latency 522system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 200165.553161 # average WriteReq mshr uncacheable latency 523system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 174828.220881 # average overall mshr uncacheable latency 524system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 174828.220881 # average overall mshr uncacheable latency 525system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 526system.cpu.dtb_walker_cache.tags.replacements 7583 # number of replacements 527system.cpu.dtb_walker_cache.tags.tagsinuse 5.052194 # Cycle average of tags in use 528system.cpu.dtb_walker_cache.tags.total_refs 13349 # Total number of references to valid blocks. 529system.cpu.dtb_walker_cache.tags.sampled_refs 7599 # Sample count of references to valid blocks. 530system.cpu.dtb_walker_cache.tags.avg_refs 1.756679 # Average number of references to valid blocks. 531system.cpu.dtb_walker_cache.tags.warmup_cycle 5163389935000 # Cycle when the warmup percentage was hit. 532system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.052194 # Average occupied blocks per requestor 533system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315762 # Average percentage of cache occupancy 534system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315762 # Average percentage of cache occupancy 535system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id 536system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 537system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 538system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 539system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 540system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 541system.cpu.dtb_walker_cache.tags.tag_accesses 53077 # Number of tag accesses 542system.cpu.dtb_walker_cache.tags.data_accesses 53077 # Number of data accesses 543system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13349 # number of ReadReq hits 544system.cpu.dtb_walker_cache.ReadReq_hits::total 13349 # number of ReadReq hits 545system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13349 # number of demand (read+write) hits 546system.cpu.dtb_walker_cache.demand_hits::total 13349 # number of demand (read+write) hits 547system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13349 # number of overall hits 548system.cpu.dtb_walker_cache.overall_hits::total 13349 # number of overall hits 549system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8793 # number of ReadReq misses 550system.cpu.dtb_walker_cache.ReadReq_misses::total 8793 # number of ReadReq misses 551system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8793 # number of demand (read+write) misses 552system.cpu.dtb_walker_cache.demand_misses::total 8793 # number of demand (read+write) misses 553system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8793 # number of overall misses 554system.cpu.dtb_walker_cache.overall_misses::total 8793 # number of overall misses 555system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 96493000 # number of ReadReq miss cycles 556system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 96493000 # number of ReadReq miss cycles 557system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 96493000 # number of demand (read+write) miss cycles 558system.cpu.dtb_walker_cache.demand_miss_latency::total 96493000 # number of demand (read+write) miss cycles 559system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 96493000 # number of overall miss cycles 560system.cpu.dtb_walker_cache.overall_miss_latency::total 96493000 # number of overall miss cycles 561system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22142 # number of ReadReq accesses(hits+misses) 562system.cpu.dtb_walker_cache.ReadReq_accesses::total 22142 # number of ReadReq accesses(hits+misses) 563system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22142 # number of demand (read+write) accesses 564system.cpu.dtb_walker_cache.demand_accesses::total 22142 # number of demand (read+write) accesses 565system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22142 # number of overall (read+write) accesses 566system.cpu.dtb_walker_cache.overall_accesses::total 22142 # number of overall (read+write) accesses 567system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.397119 # miss rate for ReadReq accesses 568system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.397119 # miss rate for ReadReq accesses 569system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.397119 # miss rate for demand accesses 570system.cpu.dtb_walker_cache.demand_miss_rate::total 0.397119 # miss rate for demand accesses 571system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.397119 # miss rate for overall accesses 572system.cpu.dtb_walker_cache.overall_miss_rate::total 0.397119 # miss rate for overall accesses 573system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10973.842830 # average ReadReq miss latency 574system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10973.842830 # average ReadReq miss latency 575system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10973.842830 # average overall miss latency 576system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10973.842830 # average overall miss latency 577system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10973.842830 # average overall miss latency 578system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10973.842830 # average overall miss latency 579system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 580system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 581system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 582system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 583system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 584system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 585system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 586system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 587system.cpu.dtb_walker_cache.writebacks::writebacks 2984 # number of writebacks 588system.cpu.dtb_walker_cache.writebacks::total 2984 # number of writebacks 589system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8793 # number of ReadReq MSHR misses 590system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8793 # number of ReadReq MSHR misses 591system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8793 # number of demand (read+write) MSHR misses 592system.cpu.dtb_walker_cache.demand_mshr_misses::total 8793 # number of demand (read+write) MSHR misses 593system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8793 # number of overall MSHR misses 594system.cpu.dtb_walker_cache.overall_mshr_misses::total 8793 # number of overall MSHR misses 595system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 87700000 # number of ReadReq MSHR miss cycles 596system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 87700000 # number of ReadReq MSHR miss cycles 597system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 87700000 # number of demand (read+write) MSHR miss cycles 598system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 87700000 # number of demand (read+write) MSHR miss cycles 599system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 87700000 # number of overall MSHR miss cycles 600system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 87700000 # number of overall MSHR miss cycles 601system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for ReadReq accesses 602system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.397119 # mshr miss rate for ReadReq accesses 603system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for demand accesses 604system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.397119 # mshr miss rate for demand accesses 605system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.397119 # mshr miss rate for overall accesses 606system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.397119 # mshr miss rate for overall accesses 607system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average ReadReq mshr miss latency 608system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9973.842830 # average ReadReq mshr miss latency 609system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average overall mshr miss latency 610system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 9973.842830 # average overall mshr miss latency 611system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 9973.842830 # average overall mshr miss latency 612system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 9973.842830 # average overall mshr miss latency 613system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 614system.cpu.icache.tags.replacements 790533 # number of replacements 615system.cpu.icache.tags.tagsinuse 510.212427 # Cycle average of tags in use 616system.cpu.icache.tags.total_refs 144635656 # Total number of references to valid blocks. 617system.cpu.icache.tags.sampled_refs 791045 # Sample count of references to valid blocks. 618system.cpu.icache.tags.avg_refs 182.841249 # Average number of references to valid blocks. 619system.cpu.icache.tags.warmup_cycle 164582664500 # Cycle when the warmup percentage was hit. 620system.cpu.icache.tags.occ_blocks::cpu.inst 510.212427 # Average occupied blocks per requestor 621system.cpu.icache.tags.occ_percent::cpu.inst 0.996509 # Average percentage of cache occupancy 622system.cpu.icache.tags.occ_percent::total 0.996509 # Average percentage of cache occupancy 623system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 624system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id 625system.cpu.icache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id 626system.cpu.icache.tags.age_task_id_blocks_1024::2 292 # Occupied blocks per task id 627system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id 628system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 629system.cpu.icache.tags.tag_accesses 146217760 # Number of tag accesses 630system.cpu.icache.tags.data_accesses 146217760 # Number of data accesses 631system.cpu.icache.ReadReq_hits::cpu.inst 144635656 # number of ReadReq hits 632system.cpu.icache.ReadReq_hits::total 144635656 # number of ReadReq hits 633system.cpu.icache.demand_hits::cpu.inst 144635656 # number of demand (read+write) hits 634system.cpu.icache.demand_hits::total 144635656 # number of demand (read+write) hits 635system.cpu.icache.overall_hits::cpu.inst 144635656 # number of overall hits 636system.cpu.icache.overall_hits::total 144635656 # number of overall hits 637system.cpu.icache.ReadReq_misses::cpu.inst 791052 # number of ReadReq misses 638system.cpu.icache.ReadReq_misses::total 791052 # number of ReadReq misses 639system.cpu.icache.demand_misses::cpu.inst 791052 # number of demand (read+write) misses 640system.cpu.icache.demand_misses::total 791052 # number of demand (read+write) misses 641system.cpu.icache.overall_misses::cpu.inst 791052 # number of overall misses 642system.cpu.icache.overall_misses::total 791052 # number of overall misses 643system.cpu.icache.ReadReq_miss_latency::cpu.inst 11850841500 # number of ReadReq miss cycles 644system.cpu.icache.ReadReq_miss_latency::total 11850841500 # number of ReadReq miss cycles 645system.cpu.icache.demand_miss_latency::cpu.inst 11850841500 # number of demand (read+write) miss cycles 646system.cpu.icache.demand_miss_latency::total 11850841500 # number of demand (read+write) miss cycles 647system.cpu.icache.overall_miss_latency::cpu.inst 11850841500 # number of overall miss cycles 648system.cpu.icache.overall_miss_latency::total 11850841500 # number of overall miss cycles 649system.cpu.icache.ReadReq_accesses::cpu.inst 145426708 # number of ReadReq accesses(hits+misses) 650system.cpu.icache.ReadReq_accesses::total 145426708 # number of ReadReq accesses(hits+misses) 651system.cpu.icache.demand_accesses::cpu.inst 145426708 # number of demand (read+write) accesses 652system.cpu.icache.demand_accesses::total 145426708 # number of demand (read+write) accesses 653system.cpu.icache.overall_accesses::cpu.inst 145426708 # number of overall (read+write) accesses 654system.cpu.icache.overall_accesses::total 145426708 # number of overall (read+write) accesses 655system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005440 # miss rate for ReadReq accesses 656system.cpu.icache.ReadReq_miss_rate::total 0.005440 # miss rate for ReadReq accesses 657system.cpu.icache.demand_miss_rate::cpu.inst 0.005440 # miss rate for demand accesses 658system.cpu.icache.demand_miss_rate::total 0.005440 # miss rate for demand accesses 659system.cpu.icache.overall_miss_rate::cpu.inst 0.005440 # miss rate for overall accesses 660system.cpu.icache.overall_miss_rate::total 0.005440 # miss rate for overall accesses 661system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14981.115654 # average ReadReq miss latency 662system.cpu.icache.ReadReq_avg_miss_latency::total 14981.115654 # average ReadReq miss latency 663system.cpu.icache.demand_avg_miss_latency::cpu.inst 14981.115654 # average overall miss latency 664system.cpu.icache.demand_avg_miss_latency::total 14981.115654 # average overall miss latency 665system.cpu.icache.overall_avg_miss_latency::cpu.inst 14981.115654 # average overall miss latency 666system.cpu.icache.overall_avg_miss_latency::total 14981.115654 # average overall miss latency 667system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 668system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 669system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 670system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 671system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 672system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 673system.cpu.icache.fast_writes 0 # number of fast writes performed 674system.cpu.icache.cache_copies 0 # number of cache copies performed 675system.cpu.icache.writebacks::writebacks 790533 # number of writebacks 676system.cpu.icache.writebacks::total 790533 # number of writebacks 677system.cpu.icache.ReadReq_mshr_misses::cpu.inst 791052 # number of ReadReq MSHR misses 678system.cpu.icache.ReadReq_mshr_misses::total 791052 # number of ReadReq MSHR misses 679system.cpu.icache.demand_mshr_misses::cpu.inst 791052 # number of demand (read+write) MSHR misses 680system.cpu.icache.demand_mshr_misses::total 791052 # number of demand (read+write) MSHR misses 681system.cpu.icache.overall_mshr_misses::cpu.inst 791052 # number of overall MSHR misses 682system.cpu.icache.overall_mshr_misses::total 791052 # number of overall MSHR misses 683system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11059789500 # number of ReadReq MSHR miss cycles 684system.cpu.icache.ReadReq_mshr_miss_latency::total 11059789500 # number of ReadReq MSHR miss cycles 685system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11059789500 # number of demand (read+write) MSHR miss cycles 686system.cpu.icache.demand_mshr_miss_latency::total 11059789500 # number of demand (read+write) MSHR miss cycles 687system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11059789500 # number of overall MSHR miss cycles 688system.cpu.icache.overall_mshr_miss_latency::total 11059789500 # number of overall MSHR miss cycles 689system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for ReadReq accesses 690system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005440 # mshr miss rate for ReadReq accesses 691system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for demand accesses 692system.cpu.icache.demand_mshr_miss_rate::total 0.005440 # mshr miss rate for demand accesses 693system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005440 # mshr miss rate for overall accesses 694system.cpu.icache.overall_mshr_miss_rate::total 0.005440 # mshr miss rate for overall accesses 695system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13981.115654 # average ReadReq mshr miss latency 696system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13981.115654 # average ReadReq mshr miss latency 697system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13981.115654 # average overall mshr miss latency 698system.cpu.icache.demand_avg_mshr_miss_latency::total 13981.115654 # average overall mshr miss latency 699system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13981.115654 # average overall mshr miss latency 700system.cpu.icache.overall_avg_mshr_miss_latency::total 13981.115654 # average overall mshr miss latency 701system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 702system.cpu.itb_walker_cache.tags.replacements 3383 # number of replacements 703system.cpu.itb_walker_cache.tags.tagsinuse 3.069439 # Cycle average of tags in use 704system.cpu.itb_walker_cache.tags.total_refs 7971 # Total number of references to valid blocks. 705system.cpu.itb_walker_cache.tags.sampled_refs 3396 # Sample count of references to valid blocks. 706system.cpu.itb_walker_cache.tags.avg_refs 2.347173 # Average number of references to valid blocks. 707system.cpu.itb_walker_cache.tags.warmup_cycle 5168995728500 # Cycle when the warmup percentage was hit. 708system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069439 # Average occupied blocks per requestor 709system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191840 # Average percentage of cache occupancy 710system.cpu.itb_walker_cache.tags.occ_percent::total 0.191840 # Average percentage of cache occupancy 711system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id 712system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 713system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 714system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 715system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 716system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 717system.cpu.itb_walker_cache.tags.tag_accesses 28685 # Number of tag accesses 718system.cpu.itb_walker_cache.tags.data_accesses 28685 # Number of data accesses 719system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7970 # number of ReadReq hits 720system.cpu.itb_walker_cache.ReadReq_hits::total 7970 # number of ReadReq hits 721system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 722system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 723system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7972 # number of demand (read+write) hits 724system.cpu.itb_walker_cache.demand_hits::total 7972 # number of demand (read+write) hits 725system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7972 # number of overall hits 726system.cpu.itb_walker_cache.overall_hits::total 7972 # number of overall hits 727system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4247 # number of ReadReq misses 728system.cpu.itb_walker_cache.ReadReq_misses::total 4247 # number of ReadReq misses 729system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4247 # number of demand (read+write) misses 730system.cpu.itb_walker_cache.demand_misses::total 4247 # number of demand (read+write) misses 731system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4247 # number of overall misses 732system.cpu.itb_walker_cache.overall_misses::total 4247 # number of overall misses 733system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 44886000 # number of ReadReq miss cycles 734system.cpu.itb_walker_cache.ReadReq_miss_latency::total 44886000 # number of ReadReq miss cycles 735system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 44886000 # number of demand (read+write) miss cycles 736system.cpu.itb_walker_cache.demand_miss_latency::total 44886000 # number of demand (read+write) miss cycles 737system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 44886000 # number of overall miss cycles 738system.cpu.itb_walker_cache.overall_miss_latency::total 44886000 # number of overall miss cycles 739system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12217 # number of ReadReq accesses(hits+misses) 740system.cpu.itb_walker_cache.ReadReq_accesses::total 12217 # number of ReadReq accesses(hits+misses) 741system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 742system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 743system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12219 # number of demand (read+write) accesses 744system.cpu.itb_walker_cache.demand_accesses::total 12219 # number of demand (read+write) accesses 745system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12219 # number of overall (read+write) accesses 746system.cpu.itb_walker_cache.overall_accesses::total 12219 # number of overall (read+write) accesses 747system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.347630 # miss rate for ReadReq accesses 748system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.347630 # miss rate for ReadReq accesses 749system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.347573 # miss rate for demand accesses 750system.cpu.itb_walker_cache.demand_miss_rate::total 0.347573 # miss rate for demand accesses 751system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.347573 # miss rate for overall accesses 752system.cpu.itb_walker_cache.overall_miss_rate::total 0.347573 # miss rate for overall accesses 753system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10568.872145 # average ReadReq miss latency 754system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10568.872145 # average ReadReq miss latency 755system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10568.872145 # average overall miss latency 756system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10568.872145 # average overall miss latency 757system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10568.872145 # average overall miss latency 758system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10568.872145 # average overall miss latency 759system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 760system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 761system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 762system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 763system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 764system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 765system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 766system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 767system.cpu.itb_walker_cache.writebacks::writebacks 773 # number of writebacks 768system.cpu.itb_walker_cache.writebacks::total 773 # number of writebacks 769system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4247 # number of ReadReq MSHR misses 770system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4247 # number of ReadReq MSHR misses 771system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4247 # number of demand (read+write) MSHR misses 772system.cpu.itb_walker_cache.demand_mshr_misses::total 4247 # number of demand (read+write) MSHR misses 773system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4247 # number of overall MSHR misses 774system.cpu.itb_walker_cache.overall_mshr_misses::total 4247 # number of overall MSHR misses 775system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 40639000 # number of ReadReq MSHR miss cycles 776system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 40639000 # number of ReadReq MSHR miss cycles 777system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 40639000 # number of demand (read+write) MSHR miss cycles 778system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 40639000 # number of demand (read+write) MSHR miss cycles 779system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 40639000 # number of overall MSHR miss cycles 780system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 40639000 # number of overall MSHR miss cycles 781system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.347630 # mshr miss rate for ReadReq accesses 782system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.347630 # mshr miss rate for ReadReq accesses 783system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for demand accesses 784system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.347573 # mshr miss rate for demand accesses 785system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.347573 # mshr miss rate for overall accesses 786system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.347573 # mshr miss rate for overall accesses 787system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9568.872145 # average ReadReq mshr miss latency 788system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9568.872145 # average ReadReq mshr miss latency 789system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9568.872145 # average overall mshr miss latency 790system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9568.872145 # average overall mshr miss latency 791system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9568.872145 # average overall mshr miss latency 792system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9568.872145 # average overall mshr miss latency 793system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 794system.cpu.l2cache.tags.replacements 87285 # number of replacements 795system.cpu.l2cache.tags.tagsinuse 64590.293077 # Cycle average of tags in use 796system.cpu.l2cache.tags.total_refs 4366421 # Total number of references to valid blocks. 797system.cpu.l2cache.tags.sampled_refs 151981 # Sample count of references to valid blocks. 798system.cpu.l2cache.tags.avg_refs 28.730045 # Average number of references to valid blocks. 799system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 800system.cpu.l2cache.tags.occ_blocks::writebacks 50117.072106 # Average occupied blocks per requestor 801system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006346 # Average occupied blocks per requestor 802system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.146905 # Average occupied blocks per requestor 803system.cpu.l2cache.tags.occ_blocks::cpu.inst 3409.574017 # Average occupied blocks per requestor 804system.cpu.l2cache.tags.occ_blocks::cpu.data 11063.493703 # Average occupied blocks per requestor 805system.cpu.l2cache.tags.occ_percent::writebacks 0.764726 # Average percentage of cache occupancy 806system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 807system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 808system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052026 # Average percentage of cache occupancy 809system.cpu.l2cache.tags.occ_percent::cpu.data 0.168816 # Average percentage of cache occupancy 810system.cpu.l2cache.tags.occ_percent::total 0.985570 # Average percentage of cache occupancy 811system.cpu.l2cache.tags.occ_task_id_blocks::1024 64696 # Occupied blocks per task id 812system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 813system.cpu.l2cache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id 814system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2800 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5473 # Occupied blocks per task id 816system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56265 # Occupied blocks per task id 817system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987183 # Percentage of cache occupancy per task id 818system.cpu.l2cache.tags.tag_accesses 39229745 # Number of tag accesses 819system.cpu.l2cache.tags.data_accesses 39229745 # Number of data accesses 820system.cpu.l2cache.WritebackDirty_hits::writebacks 1544563 # number of WritebackDirty hits 821system.cpu.l2cache.WritebackDirty_hits::total 1544563 # number of WritebackDirty hits 822system.cpu.l2cache.WritebackClean_hits::writebacks 790520 # number of WritebackClean hits 823system.cpu.l2cache.WritebackClean_hits::total 790520 # number of WritebackClean hits 824system.cpu.l2cache.UpgradeReq_hits::cpu.data 320 # number of UpgradeReq hits 825system.cpu.l2cache.UpgradeReq_hits::total 320 # number of UpgradeReq hits 826system.cpu.l2cache.ReadExReq_hits::cpu.data 200934 # number of ReadExReq hits 827system.cpu.l2cache.ReadExReq_hits::total 200934 # number of ReadExReq hits 828system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 778207 # number of ReadCleanReq hits 829system.cpu.l2cache.ReadCleanReq_hits::total 778207 # number of ReadCleanReq hits 830system.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6472 # number of ReadSharedReq hits 831system.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2856 # number of ReadSharedReq hits 832system.cpu.l2cache.ReadSharedReq_hits::cpu.data 1280544 # number of ReadSharedReq hits 833system.cpu.l2cache.ReadSharedReq_hits::total 1289872 # number of ReadSharedReq hits 834system.cpu.l2cache.demand_hits::cpu.dtb.walker 6472 # number of demand (read+write) hits 835system.cpu.l2cache.demand_hits::cpu.itb.walker 2856 # number of demand (read+write) hits 836system.cpu.l2cache.demand_hits::cpu.inst 778207 # number of demand (read+write) hits 837system.cpu.l2cache.demand_hits::cpu.data 1481478 # number of demand (read+write) hits 838system.cpu.l2cache.demand_hits::total 2269013 # number of demand (read+write) hits 839system.cpu.l2cache.overall_hits::cpu.dtb.walker 6472 # number of overall hits 840system.cpu.l2cache.overall_hits::cpu.itb.walker 2856 # number of overall hits 841system.cpu.l2cache.overall_hits::cpu.inst 778207 # number of overall hits 842system.cpu.l2cache.overall_hits::cpu.data 1481478 # number of overall hits 843system.cpu.l2cache.overall_hits::total 2269013 # number of overall hits 844system.cpu.l2cache.UpgradeReq_misses::cpu.data 1406 # number of UpgradeReq misses 845system.cpu.l2cache.UpgradeReq_misses::total 1406 # number of UpgradeReq misses 846system.cpu.l2cache.ReadExReq_misses::cpu.data 113512 # number of ReadExReq misses 847system.cpu.l2cache.ReadExReq_misses::total 113512 # number of ReadExReq misses 848system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 12832 # number of ReadCleanReq misses 849system.cpu.l2cache.ReadCleanReq_misses::total 12832 # number of ReadCleanReq misses 850system.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses 851system.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses 852system.cpu.l2cache.ReadSharedReq_misses::cpu.data 28494 # number of ReadSharedReq misses 853system.cpu.l2cache.ReadSharedReq_misses::total 28500 # number of ReadSharedReq misses 854system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 855system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 856system.cpu.l2cache.demand_misses::cpu.inst 12832 # number of demand (read+write) misses 857system.cpu.l2cache.demand_misses::cpu.data 142006 # number of demand (read+write) misses 858system.cpu.l2cache.demand_misses::total 154844 # number of demand (read+write) misses 859system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 860system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 861system.cpu.l2cache.overall_misses::cpu.inst 12832 # number of overall misses 862system.cpu.l2cache.overall_misses::cpu.data 142006 # number of overall misses 863system.cpu.l2cache.overall_misses::total 154844 # number of overall misses 864system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 53960000 # number of UpgradeReq miss cycles 865system.cpu.l2cache.UpgradeReq_miss_latency::total 53960000 # number of UpgradeReq miss cycles 866system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14442230500 # number of ReadExReq miss cycles 867system.cpu.l2cache.ReadExReq_miss_latency::total 14442230500 # number of ReadExReq miss cycles 868system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1691982000 # number of ReadCleanReq miss cycles 869system.cpu.l2cache.ReadCleanReq_miss_latency::total 1691982000 # number of ReadCleanReq miss cycles 870system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.dtb.walker 147000 # number of ReadSharedReq miss cycles 871system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.itb.walker 637500 # number of ReadSharedReq miss cycles 872system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3748921500 # number of ReadSharedReq miss cycles 873system.cpu.l2cache.ReadSharedReq_miss_latency::total 3749706000 # number of ReadSharedReq miss cycles 874system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 147000 # number of demand (read+write) miss cycles 875system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 637500 # number of demand (read+write) miss cycles 876system.cpu.l2cache.demand_miss_latency::cpu.inst 1691982000 # number of demand (read+write) miss cycles 877system.cpu.l2cache.demand_miss_latency::cpu.data 18191152000 # number of demand (read+write) miss cycles 878system.cpu.l2cache.demand_miss_latency::total 19883918500 # number of demand (read+write) miss cycles 879system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 147000 # number of overall miss cycles 880system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 637500 # number of overall miss cycles 881system.cpu.l2cache.overall_miss_latency::cpu.inst 1691982000 # number of overall miss cycles 882system.cpu.l2cache.overall_miss_latency::cpu.data 18191152000 # number of overall miss cycles 883system.cpu.l2cache.overall_miss_latency::total 19883918500 # number of overall miss cycles 884system.cpu.l2cache.WritebackDirty_accesses::writebacks 1544563 # number of WritebackDirty accesses(hits+misses) 885system.cpu.l2cache.WritebackDirty_accesses::total 1544563 # number of WritebackDirty accesses(hits+misses) 886system.cpu.l2cache.WritebackClean_accesses::writebacks 790520 # number of WritebackClean accesses(hits+misses) 887system.cpu.l2cache.WritebackClean_accesses::total 790520 # number of WritebackClean accesses(hits+misses) 888system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1726 # number of UpgradeReq accesses(hits+misses) 889system.cpu.l2cache.UpgradeReq_accesses::total 1726 # number of UpgradeReq accesses(hits+misses) 890system.cpu.l2cache.ReadExReq_accesses::cpu.data 314446 # number of ReadExReq accesses(hits+misses) 891system.cpu.l2cache.ReadExReq_accesses::total 314446 # number of ReadExReq accesses(hits+misses) 892system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 791039 # number of ReadCleanReq accesses(hits+misses) 893system.cpu.l2cache.ReadCleanReq_accesses::total 791039 # number of ReadCleanReq accesses(hits+misses) 894system.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6473 # number of ReadSharedReq accesses(hits+misses) 895system.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2861 # number of ReadSharedReq accesses(hits+misses) 896system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1309038 # number of ReadSharedReq accesses(hits+misses) 897system.cpu.l2cache.ReadSharedReq_accesses::total 1318372 # number of ReadSharedReq accesses(hits+misses) 898system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6473 # number of demand (read+write) accesses 899system.cpu.l2cache.demand_accesses::cpu.itb.walker 2861 # number of demand (read+write) accesses 900system.cpu.l2cache.demand_accesses::cpu.inst 791039 # number of demand (read+write) accesses 901system.cpu.l2cache.demand_accesses::cpu.data 1623484 # number of demand (read+write) accesses 902system.cpu.l2cache.demand_accesses::total 2423857 # number of demand (read+write) accesses 903system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6473 # number of overall (read+write) accesses 904system.cpu.l2cache.overall_accesses::cpu.itb.walker 2861 # number of overall (read+write) accesses 905system.cpu.l2cache.overall_accesses::cpu.inst 791039 # number of overall (read+write) accesses 906system.cpu.l2cache.overall_accesses::cpu.data 1623484 # number of overall (read+write) accesses 907system.cpu.l2cache.overall_accesses::total 2423857 # number of overall (read+write) accesses 908system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.814600 # miss rate for UpgradeReq accesses 909system.cpu.l2cache.UpgradeReq_miss_rate::total 0.814600 # miss rate for UpgradeReq accesses 910system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.360990 # miss rate for ReadExReq accesses 911system.cpu.l2cache.ReadExReq_miss_rate::total 0.360990 # miss rate for ReadExReq accesses 912system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016222 # miss rate for ReadCleanReq accesses 913system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016222 # miss rate for ReadCleanReq accesses 914system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadSharedReq accesses 915system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001748 # miss rate for ReadSharedReq accesses 916system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.021767 # miss rate for ReadSharedReq accesses 917system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.021618 # miss rate for ReadSharedReq accesses 918system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses 919system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001748 # miss rate for demand accesses 920system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016222 # miss rate for demand accesses 921system.cpu.l2cache.demand_miss_rate::cpu.data 0.087470 # miss rate for demand accesses 922system.cpu.l2cache.demand_miss_rate::total 0.063883 # miss rate for demand accesses 923system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses 924system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001748 # miss rate for overall accesses 925system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016222 # miss rate for overall accesses 926system.cpu.l2cache.overall_miss_rate::cpu.data 0.087470 # miss rate for overall accesses 927system.cpu.l2cache.overall_miss_rate::total 0.063883 # miss rate for overall accesses 928system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 38378.378378 # average UpgradeReq miss latency 929system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 38378.378378 # average UpgradeReq miss latency 930system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127230.869864 # average ReadExReq miss latency 931system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127230.869864 # average ReadExReq miss latency 932system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 131856.452618 # average ReadCleanReq miss latency 933system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 131856.452618 # average ReadCleanReq miss latency 934system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.dtb.walker 147000 # average ReadSharedReq miss latency 935system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.itb.walker 127500 # average ReadSharedReq miss latency 936system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 131568.803959 # average ReadSharedReq miss latency 937system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 131568.631579 # average ReadSharedReq miss latency 938system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 147000 # average overall miss latency 939system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency 940system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 131856.452618 # average overall miss latency 941system.cpu.l2cache.demand_avg_miss_latency::cpu.data 128101.291495 # average overall miss latency 942system.cpu.l2cache.demand_avg_miss_latency::total 128412.586216 # average overall miss latency 943system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 147000 # average overall miss latency 944system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 127500 # average overall miss latency 945system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 131856.452618 # average overall miss latency 946system.cpu.l2cache.overall_avg_miss_latency::cpu.data 128101.291495 # average overall miss latency 947system.cpu.l2cache.overall_avg_miss_latency::total 128412.586216 # average overall miss latency 948system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 949system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 950system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 951system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 952system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 953system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 954system.cpu.l2cache.fast_writes 0 # number of fast writes performed 955system.cpu.l2cache.cache_copies 0 # number of cache copies performed 956system.cpu.l2cache.writebacks::writebacks 80700 # number of writebacks 957system.cpu.l2cache.writebacks::total 80700 # number of writebacks 958system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses 959system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses 960system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1406 # number of UpgradeReq MSHR misses 961system.cpu.l2cache.UpgradeReq_mshr_misses::total 1406 # number of UpgradeReq MSHR misses 962system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113512 # number of ReadExReq MSHR misses 963system.cpu.l2cache.ReadExReq_mshr_misses::total 113512 # number of ReadExReq MSHR misses 964system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 12832 # number of ReadCleanReq MSHR misses 965system.cpu.l2cache.ReadCleanReq_mshr_misses::total 12832 # number of ReadCleanReq MSHR misses 966system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.dtb.walker 1 # number of ReadSharedReq MSHR misses 967system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.itb.walker 5 # number of ReadSharedReq MSHR misses 968system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 28494 # number of ReadSharedReq MSHR misses 969system.cpu.l2cache.ReadSharedReq_mshr_misses::total 28500 # number of ReadSharedReq MSHR misses 970system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses 971system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 972system.cpu.l2cache.demand_mshr_misses::cpu.inst 12832 # number of demand (read+write) MSHR misses 973system.cpu.l2cache.demand_mshr_misses::cpu.data 142006 # number of demand (read+write) MSHR misses 974system.cpu.l2cache.demand_mshr_misses::total 154844 # number of demand (read+write) MSHR misses 975system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses 976system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 977system.cpu.l2cache.overall_mshr_misses::cpu.inst 12832 # number of overall MSHR misses 978system.cpu.l2cache.overall_mshr_misses::cpu.data 142006 # number of overall MSHR misses 979system.cpu.l2cache.overall_mshr_misses::total 154844 # number of overall MSHR misses 980system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 546346 # number of ReadReq MSHR uncacheable 981system.cpu.l2cache.ReadReq_mshr_uncacheable::total 546346 # number of ReadReq MSHR uncacheable 982system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 13920 # number of WriteReq MSHR uncacheable 983system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13920 # number of WriteReq MSHR uncacheable 984system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 560266 # number of overall MSHR uncacheable misses 985system.cpu.l2cache.overall_mshr_uncacheable_misses::total 560266 # number of overall MSHR uncacheable misses 986system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100407500 # number of UpgradeReq MSHR miss cycles 987system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100407500 # number of UpgradeReq MSHR miss cycles 988system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13307110500 # number of ReadExReq MSHR miss cycles 989system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13307110500 # number of ReadExReq MSHR miss cycles 990system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1563662000 # number of ReadCleanReq MSHR miss cycles 991system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1563662000 # number of ReadCleanReq MSHR miss cycles 992system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.dtb.walker 137000 # number of ReadSharedReq MSHR miss cycles 993system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.itb.walker 587500 # number of ReadSharedReq MSHR miss cycles 994system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3463981500 # number of ReadSharedReq MSHR miss cycles 995system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3464706000 # number of ReadSharedReq MSHR miss cycles 996system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 137000 # number of demand (read+write) MSHR miss cycles 997system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 587500 # number of demand (read+write) MSHR miss cycles 998system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1563662000 # number of demand (read+write) MSHR miss cycles 999system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16771092000 # number of demand (read+write) MSHR miss cycles 1000system.cpu.l2cache.demand_mshr_miss_latency::total 18335478500 # number of demand (read+write) MSHR miss cycles 1001system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 137000 # number of overall MSHR miss cycles 1002system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 587500 # number of overall MSHR miss cycles 1003system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1563662000 # number of overall MSHR miss cycles 1004system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16771092000 # number of overall MSHR miss cycles 1005system.cpu.l2cache.overall_mshr_miss_latency::total 18335478500 # number of overall MSHR miss cycles 1006system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88334673500 # number of ReadReq MSHR uncacheable cycles 1007system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88334673500 # number of ReadReq MSHR uncacheable cycles 1008system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2626222500 # number of WriteReq MSHR uncacheable cycles 1009system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2626222500 # number of WriteReq MSHR uncacheable cycles 1010system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90960896000 # number of overall MSHR uncacheable cycles 1011system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90960896000 # number of overall MSHR uncacheable cycles 1012system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1013system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1014system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.814600 # mshr miss rate for UpgradeReq accesses 1015system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.814600 # mshr miss rate for UpgradeReq accesses 1016system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.360990 # mshr miss rate for ReadExReq accesses 1017system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.360990 # mshr miss rate for ReadExReq accesses 1018system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for ReadCleanReq accesses 1019system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.016222 # mshr miss rate for ReadCleanReq accesses 1020system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for ReadSharedReq accesses 1021system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for ReadSharedReq accesses 1022system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.021767 # mshr miss rate for ReadSharedReq accesses 1023system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.021618 # mshr miss rate for ReadSharedReq accesses 1024system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for demand accesses 1025system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for demand accesses 1026system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for demand accesses 1027system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087470 # mshr miss rate for demand accesses 1028system.cpu.l2cache.demand_mshr_miss_rate::total 0.063883 # mshr miss rate for demand accesses 1029system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000154 # mshr miss rate for overall accesses 1030system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001748 # mshr miss rate for overall accesses 1031system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016222 # mshr miss rate for overall accesses 1032system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087470 # mshr miss rate for overall accesses 1033system.cpu.l2cache.overall_mshr_miss_rate::total 0.063883 # mshr miss rate for overall accesses 1034system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 71413.584637 # average UpgradeReq mshr miss latency 1035system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 71413.584637 # average UpgradeReq mshr miss latency 1036system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 117230.869864 # average ReadExReq mshr miss latency 1037system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 117230.869864 # average ReadExReq mshr miss latency 1038system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 121856.452618 # average ReadCleanReq mshr miss latency 1039system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 121856.452618 # average ReadCleanReq mshr miss latency 1040system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average ReadSharedReq mshr miss latency 1041system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.itb.walker 117500 # average ReadSharedReq mshr miss latency 1042system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 121568.803959 # average ReadSharedReq mshr miss latency 1043system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 121568.631579 # average ReadSharedReq mshr miss latency 1044system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency 1045system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency 1046system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 121856.452618 # average overall mshr miss latency 1047system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118101.291495 # average overall mshr miss latency 1048system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118412.586216 # average overall mshr miss latency 1049system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 137000 # average overall mshr miss latency 1050system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 117500 # average overall mshr miss latency 1051system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 121856.452618 # average overall mshr miss latency 1052system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118101.291495 # average overall mshr miss latency 1053system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118412.586216 # average overall mshr miss latency 1054system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 161682.658059 # average ReadReq mshr uncacheable latency 1055system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161682.658059 # average ReadReq mshr uncacheable latency 1056system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 188665.409483 # average WriteReq mshr uncacheable latency 1057system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 188665.409483 # average WriteReq mshr uncacheable latency 1058system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162353.053728 # average overall mshr uncacheable latency 1059system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 162353.053728 # average overall mshr uncacheable latency 1060system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1061system.cpu.toL2Bus.snoop_filter.tot_requests 4855760 # Total number of requests made to the snoop filter. 1062system.cpu.toL2Bus.snoop_filter.hit_single_requests 2425141 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1063system.cpu.toL2Bus.snoop_filter.hit_multi_requests 11068 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1064system.cpu.toL2Bus.snoop_filter.tot_snoops 1020 # Total number of snoops made to the snoop filter. 1065system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1020 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1066system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1067system.cpu.toL2Bus.trans_dist::ReadReq 546346 # Transaction distribution 1068system.cpu.toL2Bus.trans_dist::ReadResp 2660535 # Transaction distribution 1069system.cpu.toL2Bus.trans_dist::WriteReq 13920 # Transaction distribution 1070system.cpu.toL2Bus.trans_dist::WriteResp 13920 # Transaction distribution 1071system.cpu.toL2Bus.trans_dist::WritebackDirty 1671932 # Transaction distribution 1072system.cpu.toL2Bus.trans_dist::WritebackClean 790520 # Transaction distribution 1073system.cpu.toL2Bus.trans_dist::CleanEvict 91754 # Transaction distribution 1074system.cpu.toL2Bus.trans_dist::UpgradeReq 2230 # Transaction distribution 1075system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution 1076system.cpu.toL2Bus.trans_dist::ReadExReq 314452 # Transaction distribution 1077system.cpu.toL2Bus.trans_dist::ReadExResp 314452 # Transaction distribution 1078system.cpu.toL2Bus.trans_dist::ReadCleanReq 791052 # Transaction distribution 1079system.cpu.toL2Bus.trans_dist::ReadSharedReq 1323668 # Transaction distribution 1080system.cpu.toL2Bus.trans_dist::MessageReq 1654 # Transaction distribution 1081system.cpu.toL2Bus.trans_dist::InvalidateReq 46720 # Transaction distribution 1082system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2372611 # Packet count per connected master and slave (bytes) 1083system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5995602 # Packet count per connected master and slave (bytes) 1084system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8612 # Packet count per connected master and slave (bytes) 1085system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 19573 # Packet count per connected master and slave (bytes) 1086system.cpu.toL2Bus.pkt_count::total 8396398 # Packet count per connected master and slave (bytes) 1087system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101219776 # Cumulative packet size per connected master and slave (bytes) 1088system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204103208 # Cumulative packet size per connected master and slave (bytes) 1089system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 232576 # Cumulative packet size per connected master and slave (bytes) 1090system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 605248 # Cumulative packet size per connected master and slave (bytes) 1091system.cpu.toL2Bus.pkt_size::total 306160808 # Cumulative packet size per connected master and slave (bytes) 1092system.cpu.toL2Bus.snoops 189298 # Total snoops (count) 1093system.cpu.toL2Bus.snoop_fanout::samples 3174836 # Request fanout histogram 1094system.cpu.toL2Bus.snoop_fanout::mean 0.004492 # Request fanout histogram 1095system.cpu.toL2Bus.snoop_fanout::stdev 0.077863 # Request fanout histogram 1096system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1097system.cpu.toL2Bus.snoop_fanout::0 3163102 99.63% 99.63% # Request fanout histogram 1098system.cpu.toL2Bus.snoop_fanout::1 9208 0.29% 99.92% # Request fanout histogram 1099system.cpu.toL2Bus.snoop_fanout::2 2526 0.08% 100.00% # Request fanout histogram 1100system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram 1101system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 1102system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1103system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1104system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1105system.cpu.toL2Bus.snoop_fanout::total 3174836 # Request fanout histogram 1106system.cpu.toL2Bus.reqLayer0.occupancy 5050069000 # Layer occupancy (ticks) 1107system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1108system.cpu.toL2Bus.snoopLayer0.occupancy 571290 # Layer occupancy (ticks) 1109system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1110system.cpu.toL2Bus.respLayer0.occupancy 1186578000 # Layer occupancy (ticks) 1111system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1112system.cpu.toL2Bus.respLayer1.occupancy 2990781992 # Layer occupancy (ticks) 1113system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1114system.cpu.toL2Bus.respLayer2.occupancy 6370500 # Layer occupancy (ticks) 1115system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1116system.cpu.toL2Bus.respLayer3.occupancy 13189500 # Layer occupancy (ticks) 1117system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1118system.iobus.trans_dist::ReadReq 216035 # Transaction distribution 1119system.iobus.trans_dist::ReadResp 216035 # Transaction distribution 1120system.iobus.trans_dist::WriteReq 57726 # Transaction distribution 1121system.iobus.trans_dist::WriteResp 57726 # Transaction distribution 1122system.iobus.trans_dist::MessageReq 1654 # Transaction distribution 1123system.iobus.trans_dist::MessageResp 1654 # Transaction distribution 1124system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1125system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1126system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) 1127system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1128system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1129system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 1130system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1131system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1132system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 408166 # Packet count per connected master and slave (bytes) 1133system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1134system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1135system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1136system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) 1137system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1138system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1139system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1140system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1141system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 1142system.iobus.pkt_count_system.bridge.master::total 452398 # Packet count per connected master and slave (bytes) 1143system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95124 # Packet count per connected master and slave (bytes) 1144system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95124 # Packet count per connected master and slave (bytes) 1145system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes) 1146system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes) 1147system.iobus.pkt_count::total 550830 # Packet count per connected master and slave (bytes) 1148system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1149system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1150system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) 1151system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1152system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1153system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 1154system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1155system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1156system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 204083 # Cumulative packet size per connected master and slave (bytes) 1157system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1158system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1159system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1160system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) 1161system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1162system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1163system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1164system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1165system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 1166system.iobus.pkt_size_system.bridge.master::total 232479 # Cumulative packet size per connected master and slave (bytes) 1167system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027280 # Cumulative packet size per connected master and slave (bytes) 1168system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027280 # Cumulative packet size per connected master and slave (bytes) 1169system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes) 1170system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes) 1171system.iobus.pkt_size::total 3266375 # Cumulative packet size per connected master and slave (bytes) 1172system.iobus.reqLayer0.occupancy 4013816 # Layer occupancy (ticks) 1173system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1174system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1175system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1176system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1177system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1178system.iobus.reqLayer3.occupancy 10045000 # Layer occupancy (ticks) 1179system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1180system.iobus.reqLayer4.occupancy 149500 # Layer occupancy (ticks) 1181system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1182system.iobus.reqLayer5.occupancy 1094500 # Layer occupancy (ticks) 1183system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1184system.iobus.reqLayer6.occupancy 79000 # Layer occupancy (ticks) 1185system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1186system.iobus.reqLayer7.occupancy 50500 # Layer occupancy (ticks) 1187system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1188system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1189system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1190system.iobus.reqLayer9.occupancy 306124500 # Layer occupancy (ticks) 1191system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1192system.iobus.reqLayer10.occupancy 1113000 # Layer occupancy (ticks) 1193system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1194system.iobus.reqLayer11.occupancy 177500 # Layer occupancy (ticks) 1195system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1196system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) 1197system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1198system.iobus.reqLayer14.occupancy 24284500 # Layer occupancy (ticks) 1199system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1200system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 1201system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1202system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) 1203system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1204system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) 1205system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1206system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1207system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1208system.iobus.reqLayer19.occupancy 240815899 # Layer occupancy (ticks) 1209system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1210system.iobus.reqLayer20.occupancy 1067000 # Layer occupancy (ticks) 1211system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1212system.iobus.respLayer0.occupancy 441392000 # Layer occupancy (ticks) 1213system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1214system.iobus.respLayer1.occupancy 50036000 # Layer occupancy (ticks) 1215system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1216system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks) 1217system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 1218system.iocache.tags.replacements 47507 # number of replacements 1219system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use 1220system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1221system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks. 1222system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1223system.iocache.tags.warmup_cycle 5048362105000 # Cycle when the warmup percentage was hit. 1224system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor 1225system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy 1226system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy 1227system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1228system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1229system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1230system.iocache.tags.tag_accesses 428058 # Number of tag accesses 1231system.iocache.tags.data_accesses 428058 # Number of data accesses 1232system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses 1233system.iocache.ReadReq_misses::total 842 # number of ReadReq misses 1234system.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 1235system.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses 1236system.iocache.demand_misses::pc.south_bridge.ide 842 # number of demand (read+write) misses 1237system.iocache.demand_misses::total 842 # number of demand (read+write) misses 1238system.iocache.overall_misses::pc.south_bridge.ide 842 # number of overall misses 1239system.iocache.overall_misses::total 842 # number of overall misses 1240system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 141163690 # number of ReadReq miss cycles 1241system.iocache.ReadReq_miss_latency::total 141163690 # number of ReadReq miss cycles 1242system.iocache.WriteLineReq_miss_latency::pc.south_bridge.ide 6072614209 # number of WriteLineReq miss cycles 1243system.iocache.WriteLineReq_miss_latency::total 6072614209 # number of WriteLineReq miss cycles 1244system.iocache.demand_miss_latency::pc.south_bridge.ide 141163690 # number of demand (read+write) miss cycles 1245system.iocache.demand_miss_latency::total 141163690 # number of demand (read+write) miss cycles 1246system.iocache.overall_miss_latency::pc.south_bridge.ide 141163690 # number of overall miss cycles 1247system.iocache.overall_miss_latency::total 141163690 # number of overall miss cycles 1248system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses) 1249system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses) 1250system.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 1251system.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) 1252system.iocache.demand_accesses::pc.south_bridge.ide 842 # number of demand (read+write) accesses 1253system.iocache.demand_accesses::total 842 # number of demand (read+write) accesses 1254system.iocache.overall_accesses::pc.south_bridge.ide 842 # number of overall (read+write) accesses 1255system.iocache.overall_accesses::total 842 # number of overall (read+write) accesses 1256system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1257system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1258system.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 1259system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1260system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1261system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1262system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1263system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1264system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average ReadReq miss latency 1265system.iocache.ReadReq_avg_miss_latency::total 167652.838480 # average ReadReq miss latency 1266system.iocache.WriteLineReq_avg_miss_latency::pc.south_bridge.ide 129978.900021 # average WriteLineReq miss latency 1267system.iocache.WriteLineReq_avg_miss_latency::total 129978.900021 # average WriteLineReq miss latency 1268system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average overall miss latency 1269system.iocache.demand_avg_miss_latency::total 167652.838480 # average overall miss latency 1270system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167652.838480 # average overall miss latency 1271system.iocache.overall_avg_miss_latency::total 167652.838480 # average overall miss latency 1272system.iocache.blocked_cycles::no_mshrs 694 # number of cycles access was blocked 1273system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1274system.iocache.blocked::no_mshrs 67 # number of cycles access was blocked 1275system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1276system.iocache.avg_blocked_cycles::no_mshrs 10.358209 # average number of cycles each access was blocked 1277system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1278system.iocache.fast_writes 0 # number of fast writes performed 1279system.iocache.cache_copies 0 # number of cache copies performed 1280system.iocache.writebacks::writebacks 46667 # number of writebacks 1281system.iocache.writebacks::total 46667 # number of writebacks 1282system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses 1283system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses 1284system.iocache.WriteLineReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteLineReq MSHR misses 1285system.iocache.WriteLineReq_mshr_misses::total 46720 # number of WriteLineReq MSHR misses 1286system.iocache.demand_mshr_misses::pc.south_bridge.ide 842 # number of demand (read+write) MSHR misses 1287system.iocache.demand_mshr_misses::total 842 # number of demand (read+write) MSHR misses 1288system.iocache.overall_mshr_misses::pc.south_bridge.ide 842 # number of overall MSHR misses 1289system.iocache.overall_mshr_misses::total 842 # number of overall MSHR misses 1290system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of ReadReq MSHR miss cycles 1291system.iocache.ReadReq_mshr_miss_latency::total 99063690 # number of ReadReq MSHR miss cycles 1292system.iocache.WriteLineReq_mshr_miss_latency::pc.south_bridge.ide 3736614209 # number of WriteLineReq MSHR miss cycles 1293system.iocache.WriteLineReq_mshr_miss_latency::total 3736614209 # number of WriteLineReq MSHR miss cycles 1294system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of demand (read+write) MSHR miss cycles 1295system.iocache.demand_mshr_miss_latency::total 99063690 # number of demand (read+write) MSHR miss cycles 1296system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 99063690 # number of overall MSHR miss cycles 1297system.iocache.overall_mshr_miss_latency::total 99063690 # number of overall MSHR miss cycles 1298system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1299system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1300system.iocache.WriteLineReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteLineReq accesses 1301system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1302system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1303system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1304system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1305system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1306system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average ReadReq mshr miss latency 1307system.iocache.ReadReq_avg_mshr_miss_latency::total 117652.838480 # average ReadReq mshr miss latency 1308system.iocache.WriteLineReq_avg_mshr_miss_latency::pc.south_bridge.ide 79978.900021 # average WriteLineReq mshr miss latency 1309system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79978.900021 # average WriteLineReq mshr miss latency 1310system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average overall mshr miss latency 1311system.iocache.demand_avg_mshr_miss_latency::total 117652.838480 # average overall mshr miss latency 1312system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 117652.838480 # average overall mshr miss latency 1313system.iocache.overall_avg_mshr_miss_latency::total 117652.838480 # average overall mshr miss latency 1314system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1315system.membus.trans_dist::ReadReq 546346 # Transaction distribution 1316system.membus.trans_dist::ReadResp 588520 # Transaction distribution 1317system.membus.trans_dist::WriteReq 13920 # Transaction distribution 1318system.membus.trans_dist::WriteResp 13920 # Transaction distribution 1319system.membus.trans_dist::WritebackDirty 127367 # Transaction distribution 1320system.membus.trans_dist::CleanEvict 6933 # Transaction distribution 1321system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution 1322system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution 1323system.membus.trans_dist::ReadExReq 113266 # Transaction distribution 1324system.membus.trans_dist::ReadExResp 113266 # Transaction distribution 1325system.membus.trans_dist::ReadSharedReq 42174 # Transaction distribution 1326system.membus.trans_dist::MessageReq 1654 # Transaction distribution 1327system.membus.trans_dist::MessageResp 1654 # Transaction distribution 1328system.membus.trans_dist::InvalidateReq 46720 # Transaction distribution 1329system.membus.trans_dist::InvalidateResp 46720 # Transaction distribution 1330system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes) 1331system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes) 1332system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 452398 # Packet count per connected master and slave (bytes) 1333system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 668134 # Packet count per connected master and slave (bytes) 1334system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 399599 # Packet count per connected master and slave (bytes) 1335system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1520131 # Packet count per connected master and slave (bytes) 1336system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141762 # Packet count per connected master and slave (bytes) 1337system.membus.pkt_count_system.iocache.mem_side::total 141762 # Packet count per connected master and slave (bytes) 1338system.membus.pkt_count::total 1665201 # Packet count per connected master and slave (bytes) 1339system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes) 1340system.membus.pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes) 1341system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 232479 # Cumulative packet size per connected master and slave (bytes) 1342system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1336265 # Cumulative packet size per connected master and slave (bytes) 1343system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15017472 # Cumulative packet size per connected master and slave (bytes) 1344system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16586216 # Cumulative packet size per connected master and slave (bytes) 1345system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3015040 # Cumulative packet size per connected master and slave (bytes) 1346system.membus.pkt_size_system.iocache.mem_side::total 3015040 # Cumulative packet size per connected master and slave (bytes) 1347system.membus.pkt_size::total 19607872 # Cumulative packet size per connected master and slave (bytes) 1348system.membus.snoops 1571 # Total snoops (count) 1349system.membus.snoop_fanout::samples 901008 # Request fanout histogram 1350system.membus.snoop_fanout::mean 1.001836 # Request fanout histogram 1351system.membus.snoop_fanout::stdev 0.042806 # Request fanout histogram 1352system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1353system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1354system.membus.snoop_fanout::1 899354 99.82% 99.82% # Request fanout histogram 1355system.membus.snoop_fanout::2 1654 0.18% 100.00% # Request fanout histogram 1356system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1357system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1358system.membus.snoop_fanout::max_value 2 # Request fanout histogram 1359system.membus.snoop_fanout::total 901008 # Request fanout histogram 1360system.membus.reqLayer0.occupancy 344294500 # Layer occupancy (ticks) 1361system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1362system.membus.reqLayer1.occupancy 503567500 # Layer occupancy (ticks) 1363system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1364system.membus.reqLayer2.occupancy 4013184 # Layer occupancy (ticks) 1365system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1366system.membus.reqLayer3.occupancy 852595093 # Layer occupancy (ticks) 1367system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1368system.membus.respLayer0.occupancy 2359184 # Layer occupancy (ticks) 1369system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 1370system.membus.respLayer2.occupancy 1928197366 # Layer occupancy (ticks) 1371system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1372system.membus.respLayer4.occupancy 85638132 # Layer occupancy (ticks) 1373system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1374system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1375system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1376system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1377system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1378system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1379system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1380system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1381system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1382system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1383system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1384system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1385system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1386 1387---------- End Simulation Statistics ---------- 1388