stats.txt revision 9962:7aef35367a21
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.112126 # Number of seconds simulated 4sim_ticks 5112126264500 # Number of ticks simulated 5final_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1904189 # Simulator instruction rate (inst/s) 8host_op_rate 3898708 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 48689346278 # Simulator tick rate (ticks/s) 10host_mem_usage 587596 # Number of bytes of host memory used 11host_seconds 104.99 # Real time elapsed on the host 12sim_insts 199929810 # Number of instructions simulated 13sim_ops 409343850 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory 19system.physmem.bytes_read::total 13883648 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9268672 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 216932 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 144823 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2715827 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s) 49system.membus.throughput 9634332 # Throughput (bytes/s) 50system.membus.data_through_bus 49251923 # Total data (bytes) 51system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 52system.iocache.tags.replacements 47569 # number of replacements 53system.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use 54system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 55system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 56system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 57system.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit. 58system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor 59system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 60system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 61system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 62system.iocache.ReadReq_misses::total 904 # number of ReadReq misses 63system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 64system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 65system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses 66system.iocache.demand_misses::total 47624 # number of demand (read+write) misses 67system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses 68system.iocache.overall_misses::total 47624 # number of overall misses 69system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 70system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) 71system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 72system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 73system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses 74system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses 75system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses 76system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses 77system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 78system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 79system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 80system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 81system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 82system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 83system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 84system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 85system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 88system.iocache.blocked::no_targets 0 # number of cycles access was blocked 89system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 90system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 91system.iocache.fast_writes 0 # number of fast writes performed 92system.iocache.cache_copies 0 # number of cache copies performed 93system.iocache.writebacks::writebacks 46667 # number of writebacks 94system.iocache.writebacks::total 46667 # number of writebacks 95system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 96system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 97system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 98system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 99system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 100system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 101system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 102system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 103system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 104system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 105system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 106system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 107system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 108system.iobus.throughput 2555207 # Throughput (bytes/s) 109system.iobus.data_through_bus 13062542 # Total data (bytes) 110system.cpu.numCycles 10224252551 # number of cpu cycles simulated 111system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 112system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 113system.cpu.committedInsts 199929810 # Number of instructions committed 114system.cpu.committedOps 409343850 # Number of ops (including micro ops) committed 115system.cpu.num_int_alu_accesses 374364636 # Number of integer alu accesses 116system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 117system.cpu.num_func_calls 2307717 # number of times a function call or return occured 118system.cpu.num_conditional_control_insts 39976328 # number of instructions that are conditional controls 119system.cpu.num_int_insts 374364636 # number of integer instructions 120system.cpu.num_fp_insts 0 # number of float instructions 121system.cpu.num_int_register_reads 682285475 # number of times the integer registers were read 122system.cpu.num_int_register_writes 323369236 # number of times the integer registers were written 123system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 124system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 125system.cpu.num_cc_register_reads 233715040 # number of times the CC registers were read 126system.cpu.num_cc_register_writes 157233555 # number of times the CC registers were written 127system.cpu.num_mem_refs 35660913 # number of memory refs 128system.cpu.num_load_insts 27238816 # Number of load instructions 129system.cpu.num_store_insts 8422097 # Number of store instructions 130system.cpu.num_idle_cycles 9770516920.735764 # Number of idle cycles 131system.cpu.num_busy_cycles 453735630.264235 # Number of busy cycles 132system.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles 133system.cpu.idle_fraction 0.955622 # Percentage of idle cycles 134system.cpu.kern.inst.arm 0 # number of arm instructions executed 135system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 136system.cpu.icache.tags.replacements 790558 # number of replacements 137system.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use 138system.cpu.icache.tags.total_refs 243525778 # Total number of references to valid blocks. 139system.cpu.icache.tags.sampled_refs 791070 # Sample count of references to valid blocks. 140system.cpu.icache.tags.avg_refs 307.843526 # Average number of references to valid blocks. 141system.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. 142system.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor 143system.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy 144system.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy 145system.cpu.icache.ReadReq_hits::cpu.inst 243525778 # number of ReadReq hits 146system.cpu.icache.ReadReq_hits::total 243525778 # number of ReadReq hits 147system.cpu.icache.demand_hits::cpu.inst 243525778 # number of demand (read+write) hits 148system.cpu.icache.demand_hits::total 243525778 # number of demand (read+write) hits 149system.cpu.icache.overall_hits::cpu.inst 243525778 # number of overall hits 150system.cpu.icache.overall_hits::total 243525778 # number of overall hits 151system.cpu.icache.ReadReq_misses::cpu.inst 791077 # number of ReadReq misses 152system.cpu.icache.ReadReq_misses::total 791077 # number of ReadReq misses 153system.cpu.icache.demand_misses::cpu.inst 791077 # number of demand (read+write) misses 154system.cpu.icache.demand_misses::total 791077 # number of demand (read+write) misses 155system.cpu.icache.overall_misses::cpu.inst 791077 # number of overall misses 156system.cpu.icache.overall_misses::total 791077 # number of overall misses 157system.cpu.icache.ReadReq_accesses::cpu.inst 244316855 # number of ReadReq accesses(hits+misses) 158system.cpu.icache.ReadReq_accesses::total 244316855 # number of ReadReq accesses(hits+misses) 159system.cpu.icache.demand_accesses::cpu.inst 244316855 # number of demand (read+write) accesses 160system.cpu.icache.demand_accesses::total 244316855 # number of demand (read+write) accesses 161system.cpu.icache.overall_accesses::cpu.inst 244316855 # number of overall (read+write) accesses 162system.cpu.icache.overall_accesses::total 244316855 # number of overall (read+write) accesses 163system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 164system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 165system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 166system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 167system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 168system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 169system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 170system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 171system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 172system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 173system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 174system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 175system.cpu.icache.fast_writes 0 # number of fast writes performed 176system.cpu.icache.cache_copies 0 # number of cache copies performed 177system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 178system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements 179system.cpu.itb_walker_cache.tags.tagsinuse 3.026303 # Cycle average of tags in use 180system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. 181system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. 182system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. 183system.cpu.itb_walker_cache.tags.warmup_cycle 5102116468000 # Cycle when the warmup percentage was hit. 184system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026303 # Average occupied blocks per requestor 185system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy 186system.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy 187system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 188system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits 189system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 190system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 191system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits 192system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits 193system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits 194system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits 195system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses 196system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses 197system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses 198system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses 199system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses 200system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses 201system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) 202system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) 203system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 204system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 205system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses 206system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses 207system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses 208system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses 209system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses 210system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses 211system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses 212system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses 213system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses 214system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses 215system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 216system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 217system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 218system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 219system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 220system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 221system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 222system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 223system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 224system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 225system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 226system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements 227system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use 228system.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks. 229system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. 230system.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks. 231system.cpu.dtb_walker_cache.tags.warmup_cycle 5100462243000 # Cycle when the warmup percentage was hit. 232system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor 233system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy 234system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy 235system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits 236system.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits 237system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits 238system.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits 239system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits 240system.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits 241system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses 242system.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses 243system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses 244system.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses 245system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses 246system.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses 247system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses) 248system.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses) 249system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses 250system.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses 251system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses 252system.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses 253system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses 254system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses 255system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses 256system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses 257system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses 258system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses 259system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 260system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 261system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 262system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 263system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 264system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 265system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 266system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 267system.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks 268system.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks 269system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 270system.cpu.dcache.tags.replacements 1622097 # number of replacements 271system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use 272system.cpu.dcache.tags.total_refs 20175179 # Total number of references to valid blocks. 273system.cpu.dcache.tags.sampled_refs 1622609 # Sample count of references to valid blocks. 274system.cpu.dcache.tags.avg_refs 12.433790 # Average number of references to valid blocks. 275system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 276system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor 277system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 278system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 279system.cpu.dcache.ReadReq_hits::cpu.data 12077531 # number of ReadReq hits 280system.cpu.dcache.ReadReq_hits::total 12077531 # number of ReadReq hits 281system.cpu.dcache.WriteReq_hits::cpu.data 8095378 # number of WriteReq hits 282system.cpu.dcache.WriteReq_hits::total 8095378 # number of WriteReq hits 283system.cpu.dcache.demand_hits::cpu.data 20172909 # number of demand (read+write) hits 284system.cpu.dcache.demand_hits::total 20172909 # number of demand (read+write) hits 285system.cpu.dcache.overall_hits::cpu.data 20172909 # number of overall hits 286system.cpu.dcache.overall_hits::total 20172909 # number of overall hits 287system.cpu.dcache.ReadReq_misses::cpu.data 1308430 # number of ReadReq misses 288system.cpu.dcache.ReadReq_misses::total 1308430 # number of ReadReq misses 289system.cpu.dcache.WriteReq_misses::cpu.data 316465 # number of WriteReq misses 290system.cpu.dcache.WriteReq_misses::total 316465 # number of WriteReq misses 291system.cpu.dcache.demand_misses::cpu.data 1624895 # number of demand (read+write) misses 292system.cpu.dcache.demand_misses::total 1624895 # number of demand (read+write) misses 293system.cpu.dcache.overall_misses::cpu.data 1624895 # number of overall misses 294system.cpu.dcache.overall_misses::total 1624895 # number of overall misses 295system.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses) 296system.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses) 297system.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses) 298system.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses) 299system.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses 300system.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses 301system.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses 302system.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses 303system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses 304system.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses 305system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses 306system.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses 307system.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses 308system.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses 309system.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses 310system.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses 311system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 312system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 313system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 314system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 315system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 316system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 317system.cpu.dcache.fast_writes 0 # number of fast writes performed 318system.cpu.dcache.cache_copies 0 # number of cache copies performed 319system.cpu.dcache.writebacks::writebacks 1535825 # number of writebacks 320system.cpu.dcache.writebacks::total 1535825 # number of writebacks 321system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 322system.cpu.toL2Bus.throughput 54625221 # Throughput (bytes/s) 323system.cpu.toL2Bus.data_through_bus 279225555 # Total data (bytes) 324system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) 325system.cpu.l2cache.tags.replacements 105999 # number of replacements 326system.cpu.l2cache.tags.tagsinuse 64822.034013 # Cycle average of tags in use 327system.cpu.l2cache.tags.total_refs 3456623 # Total number of references to valid blocks. 328system.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks. 329system.cpu.l2cache.tags.avg_refs 20.317898 # Average number of references to valid blocks. 330system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 331system.cpu.l2cache.tags.occ_blocks::writebacks 51908.839094 # Average occupied blocks per requestor 332system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor 333system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor 334system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.539598 # Average occupied blocks per requestor 335system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.520587 # Average occupied blocks per requestor 336system.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy 337system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 338system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 339system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 340system.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy 341system.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy 342system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits 343system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits 344system.cpu.l2cache.ReadReq_hits::cpu.inst 777739 # number of ReadReq hits 345system.cpu.l2cache.ReadReq_hits::cpu.data 1275554 # number of ReadReq hits 346system.cpu.l2cache.ReadReq_hits::total 2062599 # number of ReadReq hits 347system.cpu.l2cache.Writeback_hits::writebacks 1538784 # number of Writeback hits 348system.cpu.l2cache.Writeback_hits::total 1538784 # number of Writeback hits 349system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 350system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits 351system.cpu.l2cache.ReadExReq_hits::cpu.data 179732 # number of ReadExReq hits 352system.cpu.l2cache.ReadExReq_hits::total 179732 # number of ReadExReq hits 353system.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits 354system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits 355system.cpu.l2cache.demand_hits::cpu.inst 777739 # number of demand (read+write) hits 356system.cpu.l2cache.demand_hits::cpu.data 1455286 # number of demand (read+write) hits 357system.cpu.l2cache.demand_hits::total 2242331 # number of demand (read+write) hits 358system.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits 359system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits 360system.cpu.l2cache.overall_hits::cpu.inst 777739 # number of overall hits 361system.cpu.l2cache.overall_hits::cpu.data 1455286 # number of overall hits 362system.cpu.l2cache.overall_hits::total 2242331 # number of overall hits 363system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 364system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 365system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 366system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 367system.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses 368system.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses 369system.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses 370system.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses 371system.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses 372system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 373system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 374system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses 375system.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses 376system.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses 377system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 378system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 379system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 380system.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses 381system.cpu.l2cache.overall_misses::total 180035 # number of overall misses 382system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses) 383system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) 384system.cpu.l2cache.ReadReq_accesses::cpu.inst 791064 # number of ReadReq accesses(hits+misses) 385system.cpu.l2cache.ReadReq_accesses::cpu.data 1307800 # number of ReadReq accesses(hits+misses) 386system.cpu.l2cache.ReadReq_accesses::total 2108176 # number of ReadReq accesses(hits+misses) 387system.cpu.l2cache.Writeback_accesses::writebacks 1538784 # number of Writeback accesses(hits+misses) 388system.cpu.l2cache.Writeback_accesses::total 1538784 # number of Writeback accesses(hits+misses) 389system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) 390system.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) 391system.cpu.l2cache.ReadExReq_accesses::cpu.data 314190 # number of ReadExReq accesses(hits+misses) 392system.cpu.l2cache.ReadExReq_accesses::total 314190 # number of ReadExReq accesses(hits+misses) 393system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses 394system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses 395system.cpu.l2cache.demand_accesses::cpu.inst 791064 # number of demand (read+write) accesses 396system.cpu.l2cache.demand_accesses::cpu.data 1621990 # number of demand (read+write) accesses 397system.cpu.l2cache.demand_accesses::total 2422366 # number of demand (read+write) accesses 398system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses 399system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses 400system.cpu.l2cache.overall_accesses::cpu.inst 791064 # number of overall (read+write) accesses 401system.cpu.l2cache.overall_accesses::cpu.data 1621990 # number of overall (read+write) accesses 402system.cpu.l2cache.overall_accesses::total 2422366 # number of overall (read+write) accesses 403system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses 404system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses 405system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses 406system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses 407system.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses 408system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses 409system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses 410system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427951 # miss rate for ReadExReq accesses 411system.cpu.l2cache.ReadExReq_miss_rate::total 0.427951 # miss rate for ReadExReq accesses 412system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses 413system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses 414system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses 415system.cpu.l2cache.demand_miss_rate::cpu.data 0.102777 # miss rate for demand accesses 416system.cpu.l2cache.demand_miss_rate::total 0.074322 # miss rate for demand accesses 417system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses 418system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses 419system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses 420system.cpu.l2cache.overall_miss_rate::cpu.data 0.102777 # miss rate for overall accesses 421system.cpu.l2cache.overall_miss_rate::total 0.074322 # miss rate for overall accesses 422system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 423system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 424system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 425system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 426system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 427system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 428system.cpu.l2cache.fast_writes 0 # number of fast writes performed 429system.cpu.l2cache.cache_copies 0 # number of cache copies performed 430system.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks 431system.cpu.l2cache.writebacks::total 98156 # number of writebacks 432system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 433 434---------- End Simulation Statistics ---------- 435