stats.txt revision 9838:43d22d746e7a
19241Sandreas.hansson@arm.com 29717Sandreas.hansson@arm.com---------- Begin Simulation Statistics ---------- 39241Sandreas.hansson@arm.comsim_seconds 5.112102 # Number of seconds simulated 49241Sandreas.hansson@arm.comsim_ticks 5112102211000 # Number of ticks simulated 59241Sandreas.hansson@arm.comfinal_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 69241Sandreas.hansson@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 79241Sandreas.hansson@arm.comhost_inst_rate 856407 # Simulator instruction rate (inst/s) 89241Sandreas.hansson@arm.comhost_op_rate 1753461 # Simulator op (including micro ops) rate (op/s) 99241Sandreas.hansson@arm.comhost_tick_rate 21900233108 # Simulator tick rate (ticks/s) 109241Sandreas.hansson@arm.comhost_mem_usage 584104 # Number of bytes of host memory used 119241Sandreas.hansson@arm.comhost_seconds 233.43 # Real time elapsed on the host 129241Sandreas.hansson@arm.comsim_insts 199908396 # Number of instructions simulated 139241Sandreas.hansson@arm.comsim_ops 409304707 # Number of ops (including micro ops) simulated 149241Sandreas.hansson@arm.comsystem.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory 159241Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 169241Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 179241Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 189241Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 10605120 # Number of bytes read from this memory 199241Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 13879360 # Number of bytes read from this memory 209241Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 219241Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory 229241Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 9264512 # Number of bytes written to this memory 239241Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 9264512 # Number of bytes written to this memory 249241Sandreas.hansson@arm.comsystem.physmem.num_reads::pc.south_bridge.ide 37829 # Number of read requests responded to by this memory 259241Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory 269241Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 279241Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory 289241Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 165705 # Number of read requests responded to by this memory 299241Sandreas.hansson@arm.comsystem.physmem.num_reads::total 216865 # Number of read requests responded to by this memory 309241Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 144758 # Number of write requests responded to by this memory 319241Sandreas.hansson@arm.comsystem.physmem.num_writes::total 144758 # Number of write requests responded to by this memory 329241Sandreas.hansson@arm.comsystem.physmem.bw_read::pc.south_bridge.ide 473593 # Total read bandwidth from this memory (bytes/s) 339241Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) 349241Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 359241Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) 369241Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 2074513 # Total read bandwidth from this memory (bytes/s) 379241Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2715000 # Total read bandwidth from this memory (bytes/s) 389241Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) 399241Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) 409241Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1812270 # Write bandwidth from this memory (bytes/s) 419666Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1812270 # Write bandwidth from this memory (bytes/s) 429666Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1812270 # Total bandwidth to/from this memory (bytes/s) 439241Sandreas.hansson@arm.comsystem.physmem.bw_total::pc.south_bridge.ide 473593 # Total bandwidth to/from this memory (bytes/s) 449241Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 459666Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 469241Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) 479241Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s) 489241Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s) 499241Sandreas.hansson@arm.comsystem.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller 509241Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 519241Sandreas.hansson@arm.comsystem.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 529717Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 539717Sandreas.hansson@arm.comsystem.physmem.bytesRead 0 # Total number of bytes read from memory 549717Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 559717Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 569717Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 579717Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 589241Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 599241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 609241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 619241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 629241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 639241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 649241Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 659717Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 669717Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 679717Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 689717Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 699717Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 709717Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 719717Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 729717Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 739717Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 749717Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 759717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 769717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 779718Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 789717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 799717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 809717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 819717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 829717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 839717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 849718Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 859717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 869717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 879717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 889717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 899717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 909717Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 919717Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 929718Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 939717Sandreas.hansson@arm.comsystem.physmem.totGap 0 # Total gap between requests 949717Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 959717Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 969717Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 979717Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 989717Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 999717Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 1009717Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 0 # Categorize read packet sizes 1019717Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 1029717Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 1039717Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 1049717Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 1059717Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 1069717Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 1079717Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Categorize write packet sizes 1089717Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 1099241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 1109241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 1119241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 1129241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 1139241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1149241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1159241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1169241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1179241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1189241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1199718Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1209718Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1219718Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1229718Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1239718Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1249717Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1259717Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1269241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1279717Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1289717Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1299241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1309717Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1319717Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1329241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1339717Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1349717Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1359241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1369717Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1379241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1389241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1399241Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1409241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1419241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1429557Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1439241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1449241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1459241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1469241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1479241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1489241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1499241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1509241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1519241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1529241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1539241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1549241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1559717Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1569241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1579241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1589717Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1599717Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1609241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1619241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1629241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1639241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1649241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1659241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1669241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1679241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1689294Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1699294Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1709241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1719241Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1729241Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation 1739241Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation 1749241Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation 1759342SAndreas.Sandberg@arm.comsystem.physmem.totQLat 0 # Total cycles spent in queuing delays 1769241Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 0 # Sum of mem lat for all requests 1779241Sandreas.hansson@arm.comsystem.physmem.totBusLat 0 # Total cycles spent in databus access 1789241Sandreas.hansson@arm.comsystem.physmem.totBankLat 0 # Total cycles spent in bank access 1799241Sandreas.hansson@arm.comsystem.physmem.avgQLat nan # Average queueing delay per request 1809241Sandreas.hansson@arm.comsystem.physmem.avgBankLat nan # Average bank access latency per request 1819241Sandreas.hansson@arm.comsystem.physmem.avgBusLat nan # Average bus latency per request 1829241Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat nan # Average memory access latency 1839666Sandreas.hansson@arm.comsystem.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 184system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 185system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 186system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 187system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 188system.physmem.busUtil 0.00 # Data bus utilization in percentage 189system.physmem.avgRdQLen 0.00 # Average read queue length over time 190system.physmem.avgWrQLen 0.00 # Average write queue length over time 191system.physmem.readRowHits 0 # Number of row buffer hits during reads 192system.physmem.writeRowHits 0 # Number of row buffer hits during writes 193system.physmem.readRowHitRate nan # Row buffer hit rate for reads 194system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 195system.physmem.avgGap nan # Average gap between requests 196system.membus.throughput 9632725 # Throughput (bytes/s) 197system.membus.data_through_bus 49243475 # Total data (bytes) 198system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 199system.iocache.tags.replacements 47569 # number of replacements 200system.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use 201system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 202system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 203system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 204system.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit. 205system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor 206system.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 207system.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 208system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 209system.iocache.ReadReq_misses::total 904 # number of ReadReq misses 210system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 211system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 212system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses 213system.iocache.demand_misses::total 47624 # number of demand (read+write) misses 214system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses 215system.iocache.overall_misses::total 47624 # number of overall misses 216system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 217system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) 218system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 219system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 220system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses 221system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses 222system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses 223system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses 224system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 225system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 226system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 227system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 228system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 229system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 230system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 231system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 232system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 233system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 234system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 235system.iocache.blocked::no_targets 0 # number of cycles access was blocked 236system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 237system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 238system.iocache.fast_writes 0 # number of fast writes performed 239system.iocache.cache_copies 0 # number of cache copies performed 240system.iocache.writebacks::writebacks 46667 # number of writebacks 241system.iocache.writebacks::total 46667 # number of writebacks 242system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 243system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 244system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 245system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 246system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 247system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 248system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 249system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 250system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 251system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 252system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 253system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 254system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 255system.iobus.throughput 2555194 # Throughput (bytes/s) 256system.iobus.data_through_bus 13062414 # Total data (bytes) 257system.cpu.numCycles 10224204444 # number of cpu cycles simulated 258system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 259system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 260system.cpu.committedInsts 199908396 # Number of instructions committed 261system.cpu.committedOps 409304707 # Number of ops (including micro ops) committed 262system.cpu.num_int_alu_accesses 374467605 # Number of integer alu accesses 263system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 264system.cpu.num_func_calls 2307395 # number of times a function call or return occured 265system.cpu.num_conditional_control_insts 39972475 # number of instructions that are conditional controls 266system.cpu.num_int_insts 374467605 # number of integer instructions 267system.cpu.num_fp_insts 0 # number of float instructions 268system.cpu.num_int_register_reads 915905592 # number of times the integer registers were read 269system.cpu.num_int_register_writes 480549431 # number of times the integer registers were written 270system.cpu.num_fp_register_reads 0 # number of times the floating registers were read 271system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 272system.cpu.num_mem_refs 35655576 # number of memory refs 273system.cpu.num_load_insts 27235236 # Number of load instructions 274system.cpu.num_store_insts 8420340 # Number of store instructions 275system.cpu.num_idle_cycles 9770516372.735863 # Number of idle cycles 276system.cpu.num_busy_cycles 453688071.264138 # Number of busy cycles 277system.cpu.not_idle_fraction 0.044374 # Percentage of non-idle cycles 278system.cpu.idle_fraction 0.955626 # Percentage of idle cycles 279system.cpu.kern.inst.arm 0 # number of arm instructions executed 280system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 281system.cpu.icache.tags.replacements 790522 # number of replacements 282system.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use 283system.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks. 284system.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks. 285system.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks. 286system.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. 287system.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor 288system.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy 289system.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy 290system.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits 291system.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits 292system.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits 293system.cpu.icache.demand_hits::total 243495984 # number of demand (read+write) hits 294system.cpu.icache.overall_hits::cpu.inst 243495984 # number of overall hits 295system.cpu.icache.overall_hits::total 243495984 # number of overall hits 296system.cpu.icache.ReadReq_misses::cpu.inst 791041 # number of ReadReq misses 297system.cpu.icache.ReadReq_misses::total 791041 # number of ReadReq misses 298system.cpu.icache.demand_misses::cpu.inst 791041 # number of demand (read+write) misses 299system.cpu.icache.demand_misses::total 791041 # number of demand (read+write) misses 300system.cpu.icache.overall_misses::cpu.inst 791041 # number of overall misses 301system.cpu.icache.overall_misses::total 791041 # number of overall misses 302system.cpu.icache.ReadReq_accesses::cpu.inst 244287025 # number of ReadReq accesses(hits+misses) 303system.cpu.icache.ReadReq_accesses::total 244287025 # number of ReadReq accesses(hits+misses) 304system.cpu.icache.demand_accesses::cpu.inst 244287025 # number of demand (read+write) accesses 305system.cpu.icache.demand_accesses::total 244287025 # number of demand (read+write) accesses 306system.cpu.icache.overall_accesses::cpu.inst 244287025 # number of overall (read+write) accesses 307system.cpu.icache.overall_accesses::total 244287025 # number of overall (read+write) accesses 308system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 309system.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 310system.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 311system.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 312system.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 313system.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 314system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 315system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 316system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 317system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 318system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 319system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 320system.cpu.icache.fast_writes 0 # number of fast writes performed 321system.cpu.icache.cache_copies 0 # number of cache copies performed 322system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 323system.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements 324system.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use 325system.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. 326system.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. 327system.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. 328system.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit. 329system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor 330system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy 331system.cpu.itb_walker_cache.tags.occ_percent::total 0.189143 # Average percentage of cache occupancy 332system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 333system.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits 334system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 335system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 336system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits 337system.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits 338system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits 339system.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits 340system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses 341system.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses 342system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses 343system.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses 344system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses 345system.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses 346system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) 347system.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) 348system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 349system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 350system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses 351system.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses 352system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses 353system.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses 354system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses 355system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses 356system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses 357system.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses 358system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses 359system.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses 360system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 361system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 362system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 363system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 364system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 365system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 366system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 367system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 368system.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 369system.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 370system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 371system.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements 372system.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use 373system.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks. 374system.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. 375system.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks. 376system.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit. 377system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor 378system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy 379system.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy 380system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12956 # number of ReadReq hits 381system.cpu.dtb_walker_cache.ReadReq_hits::total 12956 # number of ReadReq hits 382system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12956 # number of demand (read+write) hits 383system.cpu.dtb_walker_cache.demand_hits::total 12956 # number of demand (read+write) hits 384system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12956 # number of overall hits 385system.cpu.dtb_walker_cache.overall_hits::total 12956 # number of overall hits 386system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8822 # number of ReadReq misses 387system.cpu.dtb_walker_cache.ReadReq_misses::total 8822 # number of ReadReq misses 388system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8822 # number of demand (read+write) misses 389system.cpu.dtb_walker_cache.demand_misses::total 8822 # number of demand (read+write) misses 390system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8822 # number of overall misses 391system.cpu.dtb_walker_cache.overall_misses::total 8822 # number of overall misses 392system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21778 # number of ReadReq accesses(hits+misses) 393system.cpu.dtb_walker_cache.ReadReq_accesses::total 21778 # number of ReadReq accesses(hits+misses) 394system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21778 # number of demand (read+write) accesses 395system.cpu.dtb_walker_cache.demand_accesses::total 21778 # number of demand (read+write) accesses 396system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21778 # number of overall (read+write) accesses 397system.cpu.dtb_walker_cache.overall_accesses::total 21778 # number of overall (read+write) accesses 398system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405088 # miss rate for ReadReq accesses 399system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405088 # miss rate for ReadReq accesses 400system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405088 # miss rate for demand accesses 401system.cpu.dtb_walker_cache.demand_miss_rate::total 0.405088 # miss rate for demand accesses 402system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405088 # miss rate for overall accesses 403system.cpu.dtb_walker_cache.overall_miss_rate::total 0.405088 # miss rate for overall accesses 404system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 405system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 406system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 407system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 408system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 409system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 410system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 411system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 412system.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks 413system.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks 414system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 415system.cpu.dcache.tags.replacements 1622027 # number of replacements 416system.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use 417system.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks. 418system.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks. 419system.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks. 420system.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 421system.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor 422system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 423system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 424system.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits 425system.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits 426system.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits 427system.cpu.dcache.WriteReq_hits::total 8093747 # number of WriteReq hits 428system.cpu.dcache.demand_hits::cpu.data 20167772 # number of demand (read+write) hits 429system.cpu.dcache.demand_hits::total 20167772 # number of demand (read+write) hits 430system.cpu.dcache.overall_hits::cpu.data 20167772 # number of overall hits 431system.cpu.dcache.overall_hits::total 20167772 # number of overall hits 432system.cpu.dcache.ReadReq_misses::cpu.data 1308420 # number of ReadReq misses 433system.cpu.dcache.ReadReq_misses::total 1308420 # number of ReadReq misses 434system.cpu.dcache.WriteReq_misses::cpu.data 316403 # number of WriteReq misses 435system.cpu.dcache.WriteReq_misses::total 316403 # number of WriteReq misses 436system.cpu.dcache.demand_misses::cpu.data 1624823 # number of demand (read+write) misses 437system.cpu.dcache.demand_misses::total 1624823 # number of demand (read+write) misses 438system.cpu.dcache.overall_misses::cpu.data 1624823 # number of overall misses 439system.cpu.dcache.overall_misses::total 1624823 # number of overall misses 440system.cpu.dcache.ReadReq_accesses::cpu.data 13382445 # number of ReadReq accesses(hits+misses) 441system.cpu.dcache.ReadReq_accesses::total 13382445 # number of ReadReq accesses(hits+misses) 442system.cpu.dcache.WriteReq_accesses::cpu.data 8410150 # number of WriteReq accesses(hits+misses) 443system.cpu.dcache.WriteReq_accesses::total 8410150 # number of WriteReq accesses(hits+misses) 444system.cpu.dcache.demand_accesses::cpu.data 21792595 # number of demand (read+write) accesses 445system.cpu.dcache.demand_accesses::total 21792595 # number of demand (read+write) accesses 446system.cpu.dcache.overall_accesses::cpu.data 21792595 # number of overall (read+write) accesses 447system.cpu.dcache.overall_accesses::total 21792595 # number of overall (read+write) accesses 448system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097771 # miss rate for ReadReq accesses 449system.cpu.dcache.ReadReq_miss_rate::total 0.097771 # miss rate for ReadReq accesses 450system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses 451system.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses 452system.cpu.dcache.demand_miss_rate::cpu.data 0.074558 # miss rate for demand accesses 453system.cpu.dcache.demand_miss_rate::total 0.074558 # miss rate for demand accesses 454system.cpu.dcache.overall_miss_rate::cpu.data 0.074558 # miss rate for overall accesses 455system.cpu.dcache.overall_miss_rate::total 0.074558 # miss rate for overall accesses 456system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 457system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 458system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 459system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 460system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 461system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 462system.cpu.dcache.fast_writes 0 # number of fast writes performed 463system.cpu.dcache.cache_copies 0 # number of cache copies performed 464system.cpu.dcache.writebacks::writebacks 1535756 # number of writebacks 465system.cpu.dcache.writebacks::total 1535756 # number of writebacks 466system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 467system.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s) 468system.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes) 469system.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) 470system.cpu.l2cache.tags.replacements 105931 # number of replacements 471system.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use 472system.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks. 473system.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks. 474system.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks. 475system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 476system.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor 477system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor 478system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor 479system.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor 480system.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor 481system.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy 482system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 483system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 484system.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 485system.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy 486system.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy 487system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits 488system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits 489system.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits 490system.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits 491system.cpu.l2cache.ReadReq_hits::total 2062551 # number of ReadReq hits 492system.cpu.l2cache.Writeback_hits::writebacks 1538695 # number of Writeback hits 493system.cpu.l2cache.Writeback_hits::total 1538695 # number of Writeback hits 494system.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 495system.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits 496system.cpu.l2cache.ReadExReq_hits::cpu.data 179738 # number of ReadExReq hits 497system.cpu.l2cache.ReadExReq_hits::total 179738 # number of ReadExReq hits 498system.cpu.l2cache.demand_hits::cpu.dtb.walker 6502 # number of demand (read+write) hits 499system.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits 500system.cpu.l2cache.demand_hits::cpu.inst 777703 # number of demand (read+write) hits 501system.cpu.l2cache.demand_hits::cpu.data 1455282 # number of demand (read+write) hits 502system.cpu.l2cache.demand_hits::total 2242289 # number of demand (read+write) hits 503system.cpu.l2cache.overall_hits::cpu.dtb.walker 6502 # number of overall hits 504system.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits 505system.cpu.l2cache.overall_hits::cpu.inst 777703 # number of overall hits 506system.cpu.l2cache.overall_hits::cpu.data 1455282 # number of overall hits 507system.cpu.l2cache.overall_hits::total 2242289 # number of overall hits 508system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 509system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 510system.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 511system.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 512system.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses 513system.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses 514system.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses 515system.cpu.l2cache.ReadExReq_misses::cpu.data 134392 # number of ReadExReq misses 516system.cpu.l2cache.ReadExReq_misses::total 134392 # number of ReadExReq misses 517system.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 518system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 519system.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses 520system.cpu.l2cache.demand_misses::cpu.data 166638 # number of demand (read+write) misses 521system.cpu.l2cache.demand_misses::total 179970 # number of demand (read+write) misses 522system.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 523system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 524system.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 525system.cpu.l2cache.overall_misses::cpu.data 166638 # number of overall misses 526system.cpu.l2cache.overall_misses::total 179970 # number of overall misses 527system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6504 # number of ReadReq accesses(hits+misses) 528system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) 529system.cpu.l2cache.ReadReq_accesses::cpu.inst 791028 # number of ReadReq accesses(hits+misses) 530system.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses) 531system.cpu.l2cache.ReadReq_accesses::total 2108129 # number of ReadReq accesses(hits+misses) 532system.cpu.l2cache.Writeback_accesses::writebacks 1538695 # number of Writeback accesses(hits+misses) 533system.cpu.l2cache.Writeback_accesses::total 1538695 # number of Writeback accesses(hits+misses) 534system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) 535system.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) 536system.cpu.l2cache.ReadExReq_accesses::cpu.data 314130 # number of ReadExReq accesses(hits+misses) 537system.cpu.l2cache.ReadExReq_accesses::total 314130 # number of ReadExReq accesses(hits+misses) 538system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6504 # number of demand (read+write) accesses 539system.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses 540system.cpu.l2cache.demand_accesses::cpu.inst 791028 # number of demand (read+write) accesses 541system.cpu.l2cache.demand_accesses::cpu.data 1621920 # number of demand (read+write) accesses 542system.cpu.l2cache.demand_accesses::total 2422259 # number of demand (read+write) accesses 543system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6504 # number of overall (read+write) accesses 544system.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses 545system.cpu.l2cache.overall_accesses::cpu.inst 791028 # number of overall (read+write) accesses 546system.cpu.l2cache.overall_accesses::cpu.data 1621920 # number of overall (read+write) accesses 547system.cpu.l2cache.overall_accesses::total 2422259 # number of overall (read+write) accesses 548system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses 549system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses 550system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016845 # miss rate for ReadReq accesses 551system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses 552system.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses 553system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses 554system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses 555system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427823 # miss rate for ReadExReq accesses 556system.cpu.l2cache.ReadExReq_miss_rate::total 0.427823 # miss rate for ReadExReq accesses 557system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses 558system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses 559system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016845 # miss rate for demand accesses 560system.cpu.l2cache.demand_miss_rate::cpu.data 0.102741 # miss rate for demand accesses 561system.cpu.l2cache.demand_miss_rate::total 0.074298 # miss rate for demand accesses 562system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses 563system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses 564system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016845 # miss rate for overall accesses 565system.cpu.l2cache.overall_miss_rate::cpu.data 0.102741 # miss rate for overall accesses 566system.cpu.l2cache.overall_miss_rate::total 0.074298 # miss rate for overall accesses 567system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 568system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 569system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 570system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 571system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 572system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 573system.cpu.l2cache.fast_writes 0 # number of fast writes performed 574system.cpu.l2cache.cache_copies 0 # number of cache copies performed 575system.cpu.l2cache.writebacks::writebacks 98091 # number of writebacks 576system.cpu.l2cache.writebacks::total 98091 # number of writebacks 577system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 578 579---------- End Simulation Statistics ---------- 580