stats.txt revision 8613
14309Sgblack@eecs.umich.edu 24309Sgblack@eecs.umich.edu---------- Begin Simulation Statistics ---------- 34309Sgblack@eecs.umich.edusim_seconds 5.112037 # Number of seconds simulated 44309Sgblack@eecs.umich.edusim_ticks 5112036996000 # Number of ticks simulated 54309Sgblack@eecs.umich.edusim_freq 1000000000000 # Frequency of simulated ticks 64309Sgblack@eecs.umich.eduhost_inst_rate 2883648 # Simulator instruction rate (inst/s) 74309Sgblack@eecs.umich.eduhost_tick_rate 36256565088 # Simulator tick rate (ticks/s) 84309Sgblack@eecs.umich.eduhost_mem_usage 375496 # Number of bytes of host memory used 94309Sgblack@eecs.umich.eduhost_seconds 141.00 # Real time elapsed on the host 104309Sgblack@eecs.umich.edusim_insts 406583262 # Number of instructions simulated 114309Sgblack@eecs.umich.edusystem.l2c.replacements 163860 # number of replacements 124309Sgblack@eecs.umich.edusystem.l2c.tagsinuse 36838.766351 # Cycle average of tags in use 134309Sgblack@eecs.umich.edusystem.l2c.total_refs 3334365 # Total number of references to valid blocks. 144309Sgblack@eecs.umich.edusystem.l2c.sampled_refs 195829 # Sample count of references to valid blocks. 154309Sgblack@eecs.umich.edusystem.l2c.avg_refs 17.026921 # Average number of references to valid blocks. 164309Sgblack@eecs.umich.edusystem.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 174309Sgblack@eecs.umich.edusystem.l2c.occ_blocks::0 9696.304444 # Average occupied blocks per context 184309Sgblack@eecs.umich.edusystem.l2c.occ_blocks::1 27142.461907 # Average occupied blocks per context 194309Sgblack@eecs.umich.edusystem.l2c.occ_percent::0 0.147954 # Average percentage of cache occupancy 204309Sgblack@eecs.umich.edusystem.l2c.occ_percent::1 0.414161 # Average percentage of cache occupancy 214309Sgblack@eecs.umich.edusystem.l2c.ReadReq_hits::0 2042982 # number of ReadReq hits 224309Sgblack@eecs.umich.edusystem.l2c.ReadReq_hits::1 10263 # number of ReadReq hits 234309Sgblack@eecs.umich.edusystem.l2c.ReadReq_hits::total 2053245 # number of ReadReq hits 244309Sgblack@eecs.umich.edusystem.l2c.Writeback_hits::0 1528802 # number of Writeback hits 254309Sgblack@eecs.umich.edusystem.l2c.Writeback_hits::total 1528802 # number of Writeback hits 264309Sgblack@eecs.umich.edusystem.l2c.UpgradeReq_hits::0 28 # number of UpgradeReq hits 274309Sgblack@eecs.umich.edusystem.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits 284309Sgblack@eecs.umich.edusystem.l2c.ReadExReq_hits::0 168885 # number of ReadExReq hits 294309Sgblack@eecs.umich.edusystem.l2c.ReadExReq_hits::total 168885 # number of ReadExReq hits 304309Sgblack@eecs.umich.edusystem.l2c.demand_hits::0 2211867 # number of demand (read+write) hits 314309Sgblack@eecs.umich.edusystem.l2c.demand_hits::1 10263 # number of demand (read+write) hits 324309Sgblack@eecs.umich.edusystem.l2c.demand_hits::total 2222130 # number of demand (read+write) hits 334309Sgblack@eecs.umich.edusystem.l2c.overall_hits::0 2211867 # number of overall hits 344309Sgblack@eecs.umich.edusystem.l2c.overall_hits::1 10263 # number of overall hits 354309Sgblack@eecs.umich.edusystem.l2c.overall_hits::total 2222130 # number of overall hits 364309Sgblack@eecs.umich.edusystem.l2c.ReadReq_misses::0 56047 # number of ReadReq misses 374309Sgblack@eecs.umich.edusystem.l2c.ReadReq_misses::1 29 # number of ReadReq misses 384309Sgblack@eecs.umich.edusystem.l2c.ReadReq_misses::total 56076 # number of ReadReq misses 394309Sgblack@eecs.umich.edusystem.l2c.UpgradeReq_misses::0 1784 # number of UpgradeReq misses 404309Sgblack@eecs.umich.edusystem.l2c.UpgradeReq_misses::total 1784 # number of UpgradeReq misses 414309Sgblack@eecs.umich.edusystem.l2c.ReadExReq_misses::0 144391 # number of ReadExReq misses 424309Sgblack@eecs.umich.edusystem.l2c.ReadExReq_misses::total 144391 # number of ReadExReq misses 434309Sgblack@eecs.umich.edusystem.l2c.demand_misses::0 200438 # number of demand (read+write) misses 444309Sgblack@eecs.umich.edusystem.l2c.demand_misses::1 29 # number of demand (read+write) misses 454309Sgblack@eecs.umich.edusystem.l2c.demand_misses::total 200467 # number of demand (read+write) misses 464309Sgblack@eecs.umich.edusystem.l2c.overall_misses::0 200438 # number of overall misses 474309Sgblack@eecs.umich.edusystem.l2c.overall_misses::1 29 # number of overall misses 484309Sgblack@eecs.umich.edusystem.l2c.overall_misses::total 200467 # number of overall misses 494309Sgblack@eecs.umich.edusystem.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles 504309Sgblack@eecs.umich.edusystem.l2c.overall_miss_latency 0 # number of overall miss cycles 514309Sgblack@eecs.umich.edusystem.l2c.ReadReq_accesses::0 2099029 # number of ReadReq accesses(hits+misses) 524309Sgblack@eecs.umich.edusystem.l2c.ReadReq_accesses::1 10292 # number of ReadReq accesses(hits+misses) 534309Sgblack@eecs.umich.edusystem.l2c.ReadReq_accesses::total 2109321 # number of ReadReq accesses(hits+misses) 544309Sgblack@eecs.umich.edusystem.l2c.Writeback_accesses::0 1528802 # number of Writeback accesses(hits+misses) 554309Sgblack@eecs.umich.edusystem.l2c.Writeback_accesses::total 1528802 # number of Writeback accesses(hits+misses) 564309Sgblack@eecs.umich.edusystem.l2c.UpgradeReq_accesses::0 1812 # number of UpgradeReq accesses(hits+misses) 574309Sgblack@eecs.umich.edusystem.l2c.UpgradeReq_accesses::total 1812 # number of UpgradeReq accesses(hits+misses) 584309Sgblack@eecs.umich.edusystem.l2c.ReadExReq_accesses::0 313276 # number of ReadExReq accesses(hits+misses) 594309Sgblack@eecs.umich.edusystem.l2c.ReadExReq_accesses::total 313276 # number of ReadExReq accesses(hits+misses) 604336Sgblack@eecs.umich.edusystem.l2c.demand_accesses::0 2412305 # number of demand (read+write) accesses 614336Sgblack@eecs.umich.edusystem.l2c.demand_accesses::1 10292 # number of demand (read+write) accesses 624309Sgblack@eecs.umich.edusystem.l2c.demand_accesses::total 2422597 # number of demand (read+write) accesses 634309Sgblack@eecs.umich.edusystem.l2c.overall_accesses::0 2412305 # number of overall (read+write) accesses 644309Sgblack@eecs.umich.edusystem.l2c.overall_accesses::1 10292 # number of overall (read+write) accesses 654336Sgblack@eecs.umich.edusystem.l2c.overall_accesses::total 2422597 # number of overall (read+write) accesses 664336Sgblack@eecs.umich.edusystem.l2c.ReadReq_miss_rate::0 0.026701 # miss rate for ReadReq accesses 674336Sgblack@eecs.umich.edusystem.l2c.ReadReq_miss_rate::1 0.002818 # miss rate for ReadReq accesses 684336Sgblack@eecs.umich.edusystem.l2c.ReadReq_miss_rate::total 0.029519 # miss rate for ReadReq accesses 694336Sgblack@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::0 0.984547 # miss rate for UpgradeReq accesses 704336Sgblack@eecs.umich.edusystem.l2c.ReadExReq_miss_rate::0 0.460907 # miss rate for ReadExReq accesses 714336Sgblack@eecs.umich.edusystem.l2c.demand_miss_rate::0 0.083090 # miss rate for demand accesses 724336Sgblack@eecs.umich.edusystem.l2c.demand_miss_rate::1 0.002818 # miss rate for demand accesses 734336Sgblack@eecs.umich.edusystem.l2c.demand_miss_rate::total 0.085908 # miss rate for demand accesses 744336Sgblack@eecs.umich.edusystem.l2c.overall_miss_rate::0 0.083090 # miss rate for overall accesses 754336Sgblack@eecs.umich.edusystem.l2c.overall_miss_rate::1 0.002818 # miss rate for overall accesses 764336Sgblack@eecs.umich.edusystem.l2c.overall_miss_rate::total 0.085908 # miss rate for overall accesses 774336Sgblack@eecs.umich.edusystem.l2c.demand_avg_miss_latency::0 0 # average overall miss latency 784336Sgblack@eecs.umich.edusystem.l2c.demand_avg_miss_latency::1 0 # average overall miss latency 794336Sgblack@eecs.umich.edusystem.l2c.demand_avg_miss_latency::total 0 # average overall miss latency 804336Sgblack@eecs.umich.edusystem.l2c.overall_avg_miss_latency::0 0 # average overall miss latency 814336Sgblack@eecs.umich.edusystem.l2c.overall_avg_miss_latency::1 0 # average overall miss latency 824336Sgblack@eecs.umich.edusystem.l2c.overall_avg_miss_latency::total 0 # average overall miss latency 834336Sgblack@eecs.umich.edusystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 844336Sgblack@eecs.umich.edusystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 854336Sgblack@eecs.umich.edusystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 864336Sgblack@eecs.umich.edusystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 874336Sgblack@eecs.umich.edusystem.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 884336Sgblack@eecs.umich.edusystem.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 894336Sgblack@eecs.umich.edusystem.l2c.fast_writes 0 # number of fast writes performed 904336Sgblack@eecs.umich.edusystem.l2c.cache_copies 0 # number of cache copies performed 914336Sgblack@eecs.umich.edusystem.l2c.writebacks 144360 # number of writebacks 924336Sgblack@eecs.umich.edusystem.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 934336Sgblack@eecs.umich.edusystem.l2c.overall_mshr_hits 0 # number of overall MSHR hits 944336Sgblack@eecs.umich.edusystem.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 954336Sgblack@eecs.umich.edusystem.l2c.overall_mshr_misses 0 # number of overall MSHR misses 964336Sgblack@eecs.umich.edusystem.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 974336Sgblack@eecs.umich.edusystem.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 984336Sgblack@eecs.umich.edusystem.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 994336Sgblack@eecs.umich.edusystem.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 1004336Sgblack@eecs.umich.edusystem.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 1014336Sgblack@eecs.umich.edusystem.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 1024336Sgblack@eecs.umich.edusystem.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses 1034336Sgblack@eecs.umich.edusystem.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 1044336Sgblack@eecs.umich.edusystem.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 1054336Sgblack@eecs.umich.edusystem.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses 1064336Sgblack@eecs.umich.edusystem.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 1074336Sgblack@eecs.umich.edusystem.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 1084336Sgblack@eecs.umich.edusystem.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 1094336Sgblack@eecs.umich.edusystem.l2c.mshr_cap_events 0 # number of times MSHR cap was activated 1104336Sgblack@eecs.umich.edusystem.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1114336Sgblack@eecs.umich.edusystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1124336Sgblack@eecs.umich.edusystem.iocache.replacements 47572 # number of replacements 1134336Sgblack@eecs.umich.edusystem.iocache.tagsinuse 0.042404 # Cycle average of tags in use 1144336Sgblack@eecs.umich.edusystem.iocache.total_refs 0 # Total number of references to valid blocks. 1154336Sgblack@eecs.umich.edusystem.iocache.sampled_refs 47588 # Sample count of references to valid blocks. 1164336Sgblack@eecs.umich.edusystem.iocache.avg_refs 0 # Average number of references to valid blocks. 1174336Sgblack@eecs.umich.edusystem.iocache.warmup_cycle 4994772178509 # Cycle when the warmup percentage was hit. 1184336Sgblack@eecs.umich.edusystem.iocache.occ_blocks::1 0.042404 # Average occupied blocks per context 1194336Sgblack@eecs.umich.edusystem.iocache.occ_percent::1 0.002650 # Average percentage of cache occupancy 1204336Sgblack@eecs.umich.edusystem.iocache.demand_hits::0 0 # number of demand (read+write) hits 1214336Sgblack@eecs.umich.edusystem.iocache.demand_hits::1 0 # number of demand (read+write) hits 1224336Sgblack@eecs.umich.edusystem.iocache.demand_hits::total 0 # number of demand (read+write) hits 1234336Sgblack@eecs.umich.edusystem.iocache.overall_hits::0 0 # number of overall hits 1244336Sgblack@eecs.umich.edusystem.iocache.overall_hits::1 0 # number of overall hits 1254336Sgblack@eecs.umich.edusystem.iocache.overall_hits::total 0 # number of overall hits 1264336Sgblack@eecs.umich.edusystem.iocache.ReadReq_misses::1 907 # number of ReadReq misses 1274336Sgblack@eecs.umich.edusystem.iocache.ReadReq_misses::total 907 # number of ReadReq misses 1284336Sgblack@eecs.umich.edusystem.iocache.WriteReq_misses::1 46720 # number of WriteReq misses 1294336Sgblack@eecs.umich.edusystem.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 1304336Sgblack@eecs.umich.edusystem.iocache.demand_misses::0 0 # number of demand (read+write) misses 1314336Sgblack@eecs.umich.edusystem.iocache.demand_misses::1 47627 # number of demand (read+write) misses 1324336Sgblack@eecs.umich.edusystem.iocache.demand_misses::total 47627 # number of demand (read+write) misses 1334336Sgblack@eecs.umich.edusystem.iocache.overall_misses::0 0 # number of overall misses 1344336Sgblack@eecs.umich.edusystem.iocache.overall_misses::1 47627 # number of overall misses 1354336Sgblack@eecs.umich.edusystem.iocache.overall_misses::total 47627 # number of overall misses 1364336Sgblack@eecs.umich.edusystem.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles 1374336Sgblack@eecs.umich.edusystem.iocache.overall_miss_latency 0 # number of overall miss cycles 1384336Sgblack@eecs.umich.edusystem.iocache.ReadReq_accesses::1 907 # number of ReadReq accesses(hits+misses) 1394336Sgblack@eecs.umich.edusystem.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) 1404336Sgblack@eecs.umich.edusystem.iocache.WriteReq_accesses::1 46720 # number of WriteReq accesses(hits+misses) 1414336Sgblack@eecs.umich.edusystem.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 1424336Sgblack@eecs.umich.edusystem.iocache.demand_accesses::0 0 # number of demand (read+write) accesses 1434336Sgblack@eecs.umich.edusystem.iocache.demand_accesses::1 47627 # number of demand (read+write) accesses 1444336Sgblack@eecs.umich.edusystem.iocache.demand_accesses::total 47627 # number of demand (read+write) accesses 1454336Sgblack@eecs.umich.edusystem.iocache.overall_accesses::0 0 # number of overall (read+write) accesses 1464336Sgblack@eecs.umich.edusystem.iocache.overall_accesses::1 47627 # number of overall (read+write) accesses 1474336Sgblack@eecs.umich.edusystem.iocache.overall_accesses::total 47627 # number of overall (read+write) accesses 1484336Sgblack@eecs.umich.edusystem.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses 1494336Sgblack@eecs.umich.edusystem.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses 1504336Sgblack@eecs.umich.edusystem.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses 1514336Sgblack@eecs.umich.edusystem.iocache.demand_miss_rate::1 1 # miss rate for demand accesses 1524336Sgblack@eecs.umich.edusystem.iocache.demand_miss_rate::total no_value # miss rate for demand accesses 1534336Sgblack@eecs.umich.edusystem.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses 1544336Sgblack@eecs.umich.edusystem.iocache.overall_miss_rate::1 1 # miss rate for overall accesses 1554336Sgblack@eecs.umich.edusystem.iocache.overall_miss_rate::total no_value # miss rate for overall accesses 1564336Sgblack@eecs.umich.edusystem.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency 1574336Sgblack@eecs.umich.edusystem.iocache.demand_avg_miss_latency::1 0 # average overall miss latency 1584336Sgblack@eecs.umich.edusystem.iocache.demand_avg_miss_latency::total no_value # average overall miss latency 1594336Sgblack@eecs.umich.edusystem.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency 1604336Sgblack@eecs.umich.edusystem.iocache.overall_avg_miss_latency::1 0 # average overall miss latency 1614336Sgblack@eecs.umich.edusystem.iocache.overall_avg_miss_latency::total no_value # average overall miss latency 1624336Sgblack@eecs.umich.edusystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1634336Sgblack@eecs.umich.edusystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1644336Sgblack@eecs.umich.edusystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1654336Sgblack@eecs.umich.edusystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 1664336Sgblack@eecs.umich.edusystem.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 1674336Sgblack@eecs.umich.edusystem.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 1684336Sgblack@eecs.umich.edusystem.iocache.fast_writes 0 # number of fast writes performed 1694336Sgblack@eecs.umich.edusystem.iocache.cache_copies 0 # number of cache copies performed 1704336Sgblack@eecs.umich.edusystem.iocache.writebacks 46667 # number of writebacks 1714336Sgblack@eecs.umich.edusystem.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 1724336Sgblack@eecs.umich.edusystem.iocache.overall_mshr_hits 0 # number of overall MSHR hits 1734336Sgblack@eecs.umich.edusystem.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 1744336Sgblack@eecs.umich.edusystem.iocache.overall_mshr_misses 0 # number of overall MSHR misses 1754336Sgblack@eecs.umich.edusystem.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 1764336Sgblack@eecs.umich.edusystem.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 1774336Sgblack@eecs.umich.edusystem.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 1784336Sgblack@eecs.umich.edusystem.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 1794336Sgblack@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 1804336Sgblack@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 1814336Sgblack@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 1824336Sgblack@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 1834336Sgblack@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 1844336Sgblack@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 1854336Sgblack@eecs.umich.edusystem.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 1864336Sgblack@eecs.umich.edusystem.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 1874336Sgblack@eecs.umich.edusystem.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 1884336Sgblack@eecs.umich.edusystem.iocache.mshr_cap_events 0 # number of times MSHR cap was activated 1894336Sgblack@eecs.umich.edusystem.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 1904336Sgblack@eecs.umich.edusystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1914336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1924336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1934336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 1944336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1954336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1964336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1974336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1984336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1994336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2004336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 2014336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 2024336Sgblack@eecs.umich.edusystem.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 2034336Sgblack@eecs.umich.edusystem.cpu.numCycles 10224074013 # number of cpu cycles simulated 2044336Sgblack@eecs.umich.edusystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2054336Sgblack@eecs.umich.edusystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2064336Sgblack@eecs.umich.edusystem.cpu.num_insts 406583262 # Number of instructions executed 2074336Sgblack@eecs.umich.edusystem.cpu.num_int_alu_accesses 391790000 # Number of integer alu accesses 2084309Sgblack@eecs.umich.edusystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 2094309Sgblack@eecs.umich.edusystem.cpu.num_func_calls 0 # number of times a function call or return occured 2104309Sgblack@eecs.umich.edusystem.cpu.num_conditional_control_insts 42454615 # number of instructions that are conditional controls 2114309Sgblack@eecs.umich.edusystem.cpu.num_int_insts 391790000 # number of integer instructions 2124309Sgblack@eecs.umich.edusystem.cpu.num_fp_insts 0 # number of float instructions 2134323Sgblack@eecs.umich.edusystem.cpu.num_int_register_reads 836247135 # number of times the integer registers were read 2144323Sgblack@eecs.umich.edusystem.cpu.num_int_register_writes 419118732 # number of times the integer registers were written 2154323Sgblack@eecs.umich.edusystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 2164323Sgblack@eecs.umich.edusystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 2174323Sgblack@eecs.umich.edusystem.cpu.num_mem_refs 38123075 # number of memory refs 2184323Sgblack@eecs.umich.edusystem.cpu.num_load_insts 29716799 # Number of load instructions 2194323Sgblack@eecs.umich.edusystem.cpu.num_store_insts 8406276 # Number of store instructions 2204323Sgblack@eecs.umich.edusystem.cpu.num_idle_cycles 9770647500.086761 # Number of idle cycles 2214323Sgblack@eecs.umich.edusystem.cpu.num_busy_cycles 453426512.913238 # Number of busy cycles 2224323Sgblack@eecs.umich.edusystem.cpu.not_idle_fraction 0.044349 # Percentage of non-idle cycles 2234323Sgblack@eecs.umich.edusystem.cpu.idle_fraction 0.955651 # Percentage of idle cycles 2244323Sgblack@eecs.umich.edusystem.cpu.kern.inst.arm 0 # number of arm instructions executed 2254309Sgblack@eecs.umich.edusystem.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 2264309Sgblack@eecs.umich.edusystem.cpu.icache.replacements 790768 # number of replacements 2274309Sgblack@eecs.umich.edusystem.cpu.icache.tagsinuse 510.627880 # Cycle average of tags in use 2284309Sgblack@eecs.umich.edusystem.cpu.icache.total_refs 253353258 # Total number of references to valid blocks. 2294309Sgblack@eecs.umich.edusystem.cpu.icache.sampled_refs 791280 # Sample count of references to valid blocks. 2304309Sgblack@eecs.umich.edusystem.cpu.icache.avg_refs 320.181551 # Average number of references to valid blocks. 2314309Sgblack@eecs.umich.edusystem.cpu.icache.warmup_cycle 148756117000 # Cycle when the warmup percentage was hit. 2324323Sgblack@eecs.umich.edusystem.cpu.icache.occ_blocks::0 510.627880 # Average occupied blocks per context 2334309Sgblack@eecs.umich.edusystem.cpu.icache.occ_percent::0 0.997320 # Average percentage of cache occupancy 2344323Sgblack@eecs.umich.edusystem.cpu.icache.ReadReq_hits::0 253353258 # number of ReadReq hits 2354323Sgblack@eecs.umich.edusystem.cpu.icache.ReadReq_hits::total 253353258 # number of ReadReq hits 2364323Sgblack@eecs.umich.edusystem.cpu.icache.demand_hits::0 253353258 # number of demand (read+write) hits 2374309Sgblack@eecs.umich.edusystem.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits 2384323Sgblack@eecs.umich.edusystem.cpu.icache.demand_hits::total 253353258 # number of demand (read+write) hits 2394323Sgblack@eecs.umich.edusystem.cpu.icache.overall_hits::0 253353258 # number of overall hits 2404323Sgblack@eecs.umich.edusystem.cpu.icache.overall_hits::1 0 # number of overall hits 2414323Sgblack@eecs.umich.edusystem.cpu.icache.overall_hits::total 253353258 # number of overall hits 2424323Sgblack@eecs.umich.edusystem.cpu.icache.ReadReq_misses::0 791287 # number of ReadReq misses 2434323Sgblack@eecs.umich.edusystem.cpu.icache.ReadReq_misses::total 791287 # number of ReadReq misses 2444323Sgblack@eecs.umich.edusystem.cpu.icache.demand_misses::0 791287 # number of demand (read+write) misses 2454323Sgblack@eecs.umich.edusystem.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses 2464323Sgblack@eecs.umich.edusystem.cpu.icache.demand_misses::total 791287 # number of demand (read+write) misses 2474336Sgblack@eecs.umich.edusystem.cpu.icache.overall_misses::0 791287 # number of overall misses 2484309Sgblack@eecs.umich.edusystem.cpu.icache.overall_misses::1 0 # number of overall misses 2494336Sgblack@eecs.umich.edusystem.cpu.icache.overall_misses::total 791287 # number of overall misses 2504309Sgblack@eecs.umich.edusystem.cpu.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles 2514309Sgblack@eecs.umich.edusystem.cpu.icache.overall_miss_latency 0 # number of overall miss cycles 2524309Sgblack@eecs.umich.edusystem.cpu.icache.ReadReq_accesses::0 254144545 # number of ReadReq accesses(hits+misses) 2534309Sgblack@eecs.umich.edusystem.cpu.icache.ReadReq_accesses::total 254144545 # number of ReadReq accesses(hits+misses) 2544309Sgblack@eecs.umich.edusystem.cpu.icache.demand_accesses::0 254144545 # number of demand (read+write) accesses 2554309Sgblack@eecs.umich.edusystem.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses 2564309Sgblack@eecs.umich.edusystem.cpu.icache.demand_accesses::total 254144545 # number of demand (read+write) accesses 2574309Sgblack@eecs.umich.edusystem.cpu.icache.overall_accesses::0 254144545 # number of overall (read+write) accesses 2584309Sgblack@eecs.umich.edusystem.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses 2594309Sgblack@eecs.umich.edusystem.cpu.icache.overall_accesses::total 254144545 # number of overall (read+write) accesses 2604309Sgblack@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::0 0.003114 # miss rate for ReadReq accesses 2614309Sgblack@eecs.umich.edusystem.cpu.icache.demand_miss_rate::0 0.003114 # miss rate for demand accesses 2624309Sgblack@eecs.umich.edusystem.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses 2634309Sgblack@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses 2644309Sgblack@eecs.umich.edusystem.cpu.icache.overall_miss_rate::0 0.003114 # miss rate for overall accesses 2654309Sgblack@eecs.umich.edusystem.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses 2664309Sgblack@eecs.umich.edusystem.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses 2674309Sgblack@eecs.umich.edusystem.cpu.icache.demand_avg_miss_latency::0 0 # average overall miss latency 2684309Sgblack@eecs.umich.edusystem.cpu.icache.demand_avg_miss_latency::1 no_value # average overall miss latency 2694309Sgblack@eecs.umich.edusystem.cpu.icache.demand_avg_miss_latency::total no_value # average overall miss latency 2704309Sgblack@eecs.umich.edusystem.cpu.icache.overall_avg_miss_latency::0 0 # average overall miss latency 2714309Sgblack@eecs.umich.edusystem.cpu.icache.overall_avg_miss_latency::1 no_value # average overall miss latency 2724309Sgblack@eecs.umich.edusystem.cpu.icache.overall_avg_miss_latency::total no_value # average overall miss latency 2734309Sgblack@eecs.umich.edusystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2744309Sgblack@eecs.umich.edusystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2754309Sgblack@eecs.umich.edusystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2764309Sgblack@eecs.umich.edusystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 2774309Sgblack@eecs.umich.edusystem.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 2784309Sgblack@eecs.umich.edusystem.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 2794309Sgblack@eecs.umich.edusystem.cpu.icache.fast_writes 0 # number of fast writes performed 2804323Sgblack@eecs.umich.edusystem.cpu.icache.cache_copies 0 # number of cache copies performed 2814323Sgblack@eecs.umich.edusystem.cpu.icache.writebacks 806 # number of writebacks 2824309Sgblack@eecs.umich.edusystem.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 2834309Sgblack@eecs.umich.edusystem.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits 2844309Sgblack@eecs.umich.edusystem.cpu.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 2854309Sgblack@eecs.umich.edusystem.cpu.icache.overall_mshr_misses 0 # number of overall MSHR misses 2864309Sgblack@eecs.umich.edusystem.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 2874309Sgblack@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 2884323Sgblack@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 2894309Sgblack@eecs.umich.edusystem.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 2904309Sgblack@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 2914309Sgblack@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 2924309Sgblack@eecs.umich.edusystem.cpu.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 2934309Sgblack@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 2944309Sgblack@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 2954323Sgblack@eecs.umich.edusystem.cpu.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 2964323Sgblack@eecs.umich.edusystem.cpu.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 2974309Sgblack@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 2984309Sgblack@eecs.umich.edusystem.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 2994323Sgblack@eecs.umich.edusystem.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated 3004309Sgblack@eecs.umich.edusystem.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 3014309Sgblack@eecs.umich.edusystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3024309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.replacements 3656 # number of replacements 3034309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.tagsinuse 3.021422 # Cycle average of tags in use 3044309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.total_refs 7713 # Total number of references to valid blocks. 3054309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.sampled_refs 3666 # Sample count of references to valid blocks. 3064309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.avg_refs 2.103928 # Average number of references to valid blocks. 3074309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.warmup_cycle 5105310674000 # Cycle when the warmup percentage was hit. 3084309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.occ_blocks::1 3.021422 # Average occupied blocks per context 3094309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.occ_percent::1 0.188839 # Average percentage of cache occupancy 3104309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.ReadReq_hits::1 7719 # number of ReadReq hits 3114309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.ReadReq_hits::total 7719 # number of ReadReq hits 3124309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.WriteReq_hits::1 2 # number of WriteReq hits 3134309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 3144309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits 3154309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_hits::1 7721 # number of demand (read+write) hits 3164309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_hits::total 7721 # number of demand (read+write) hits 3174323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.overall_hits::0 0 # number of overall hits 3184323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.overall_hits::1 7721 # number of overall hits 3194309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.overall_hits::total 7721 # number of overall hits 3204323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.ReadReq_misses::1 4507 # number of ReadReq misses 3214309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.ReadReq_misses::total 4507 # number of ReadReq misses 3224323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses 3234309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_misses::1 4507 # number of demand (read+write) misses 3244309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_misses::total 4507 # number of demand (read+write) misses 3254309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.overall_misses::0 0 # number of overall misses 3264309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.overall_misses::1 4507 # number of overall misses 3274309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.overall_misses::total 4507 # number of overall misses 3284309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles 3294323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.overall_miss_latency 0 # number of overall miss cycles 3304323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.ReadReq_accesses::1 12226 # number of ReadReq accesses(hits+misses) 3314323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.ReadReq_accesses::total 12226 # number of ReadReq accesses(hits+misses) 3324323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.WriteReq_accesses::1 2 # number of WriteReq accesses(hits+misses) 3334323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 3344323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses 3354323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_accesses::1 12228 # number of demand (read+write) accesses 3364323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_accesses::total 12228 # number of demand (read+write) accesses 3374323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses 3384323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.overall_accesses::1 12228 # number of overall (read+write) accesses 3394323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.overall_accesses::total 12228 # number of overall (read+write) accesses 3404323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.ReadReq_miss_rate::1 0.368641 # miss rate for ReadReq accesses 3414323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses 3424323Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_miss_rate::1 0.368580 # miss rate for demand accesses 3434309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses 3444309Sgblack@eecs.umich.edusystem.cpu.itb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses 345system.cpu.itb_walker_cache.overall_miss_rate::1 0.368580 # miss rate for overall accesses 346system.cpu.itb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses 347system.cpu.itb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency 348system.cpu.itb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency 349system.cpu.itb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency 350system.cpu.itb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency 351system.cpu.itb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency 352system.cpu.itb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency 353system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 354system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 355system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 356system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 357system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 358system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 359system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 360system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 361system.cpu.itb_walker_cache.writebacks 405 # number of writebacks 362system.cpu.itb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 363system.cpu.itb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits 364system.cpu.itb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 365system.cpu.itb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses 366system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 367system.cpu.itb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 368system.cpu.itb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 369system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 370system.cpu.itb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 371system.cpu.itb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 372system.cpu.itb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 373system.cpu.itb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 374system.cpu.itb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 375system.cpu.itb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 376system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 377system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 378system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 379system.cpu.itb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated 380system.cpu.itb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 381system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 382system.cpu.dtb_walker_cache.replacements 8177 # number of replacements 383system.cpu.dtb_walker_cache.tagsinuse 5.011395 # Cycle average of tags in use 384system.cpu.dtb_walker_cache.total_refs 12378 # Total number of references to valid blocks. 385system.cpu.dtb_walker_cache.sampled_refs 8191 # Sample count of references to valid blocks. 386system.cpu.dtb_walker_cache.avg_refs 1.511171 # Average number of references to valid blocks. 387system.cpu.dtb_walker_cache.warmup_cycle 5101233676500 # Cycle when the warmup percentage was hit. 388system.cpu.dtb_walker_cache.occ_blocks::1 5.011395 # Average occupied blocks per context 389system.cpu.dtb_walker_cache.occ_percent::1 0.313212 # Average percentage of cache occupancy 390system.cpu.dtb_walker_cache.ReadReq_hits::1 12392 # number of ReadReq hits 391system.cpu.dtb_walker_cache.ReadReq_hits::total 12392 # number of ReadReq hits 392system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits 393system.cpu.dtb_walker_cache.demand_hits::1 12392 # number of demand (read+write) hits 394system.cpu.dtb_walker_cache.demand_hits::total 12392 # number of demand (read+write) hits 395system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits 396system.cpu.dtb_walker_cache.overall_hits::1 12392 # number of overall hits 397system.cpu.dtb_walker_cache.overall_hits::total 12392 # number of overall hits 398system.cpu.dtb_walker_cache.ReadReq_misses::1 9345 # number of ReadReq misses 399system.cpu.dtb_walker_cache.ReadReq_misses::total 9345 # number of ReadReq misses 400system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses 401system.cpu.dtb_walker_cache.demand_misses::1 9345 # number of demand (read+write) misses 402system.cpu.dtb_walker_cache.demand_misses::total 9345 # number of demand (read+write) misses 403system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses 404system.cpu.dtb_walker_cache.overall_misses::1 9345 # number of overall misses 405system.cpu.dtb_walker_cache.overall_misses::total 9345 # number of overall misses 406system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles 407system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles 408system.cpu.dtb_walker_cache.ReadReq_accesses::1 21737 # number of ReadReq accesses(hits+misses) 409system.cpu.dtb_walker_cache.ReadReq_accesses::total 21737 # number of ReadReq accesses(hits+misses) 410system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses 411system.cpu.dtb_walker_cache.demand_accesses::1 21737 # number of demand (read+write) accesses 412system.cpu.dtb_walker_cache.demand_accesses::total 21737 # number of demand (read+write) accesses 413system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses 414system.cpu.dtb_walker_cache.overall_accesses::1 21737 # number of overall (read+write) accesses 415system.cpu.dtb_walker_cache.overall_accesses::total 21737 # number of overall (read+write) accesses 416system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.429912 # miss rate for ReadReq accesses 417system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses 418system.cpu.dtb_walker_cache.demand_miss_rate::1 0.429912 # miss rate for demand accesses 419system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses 420system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses 421system.cpu.dtb_walker_cache.overall_miss_rate::1 0.429912 # miss rate for overall accesses 422system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses 423system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency 424system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency 425system.cpu.dtb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency 426system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency 427system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency 428system.cpu.dtb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency 429system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 430system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 431system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 432system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 433system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 434system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 435system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 436system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 437system.cpu.dtb_walker_cache.writebacks 2332 # number of writebacks 438system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 439system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits 440system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 441system.cpu.dtb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses 442system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 443system.cpu.dtb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 444system.cpu.dtb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 445system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 446system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses 447system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses 448system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 449system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses 450system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses 451system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 452system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 453system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 454system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 455system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated 456system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 457system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 458system.cpu.dcache.replacements 1621118 # number of replacements 459system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use 460system.cpu.dcache.total_refs 20138941 # Total number of references to valid blocks. 461system.cpu.dcache.sampled_refs 1621630 # Sample count of references to valid blocks. 462system.cpu.dcache.avg_refs 12.418949 # Average number of references to valid blocks. 463system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 464system.cpu.dcache.occ_blocks::0 511.999417 # Average occupied blocks per context 465system.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy 466system.cpu.dcache.ReadReq_hits::0 12055886 # number of ReadReq hits 467system.cpu.dcache.ReadReq_hits::total 12055886 # number of ReadReq hits 468system.cpu.dcache.WriteReq_hits::0 8080806 # number of WriteReq hits 469system.cpu.dcache.WriteReq_hits::total 8080806 # number of WriteReq hits 470system.cpu.dcache.demand_hits::0 20136692 # number of demand (read+write) hits 471system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits 472system.cpu.dcache.demand_hits::total 20136692 # number of demand (read+write) hits 473system.cpu.dcache.overall_hits::0 20136692 # number of overall hits 474system.cpu.dcache.overall_hits::1 0 # number of overall hits 475system.cpu.dcache.overall_hits::total 20136692 # number of overall hits 476system.cpu.dcache.ReadReq_misses::0 1308365 # number of ReadReq misses 477system.cpu.dcache.ReadReq_misses::total 1308365 # number of ReadReq misses 478system.cpu.dcache.WriteReq_misses::0 315530 # number of WriteReq misses 479system.cpu.dcache.WriteReq_misses::total 315530 # number of WriteReq misses 480system.cpu.dcache.demand_misses::0 1623895 # number of demand (read+write) misses 481system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses 482system.cpu.dcache.demand_misses::total 1623895 # number of demand (read+write) misses 483system.cpu.dcache.overall_misses::0 1623895 # number of overall misses 484system.cpu.dcache.overall_misses::1 0 # number of overall misses 485system.cpu.dcache.overall_misses::total 1623895 # number of overall misses 486system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles 487system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles 488system.cpu.dcache.ReadReq_accesses::0 13364251 # number of ReadReq accesses(hits+misses) 489system.cpu.dcache.ReadReq_accesses::total 13364251 # number of ReadReq accesses(hits+misses) 490system.cpu.dcache.WriteReq_accesses::0 8396336 # number of WriteReq accesses(hits+misses) 491system.cpu.dcache.WriteReq_accesses::total 8396336 # number of WriteReq accesses(hits+misses) 492system.cpu.dcache.demand_accesses::0 21760587 # number of demand (read+write) accesses 493system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses 494system.cpu.dcache.demand_accesses::total 21760587 # number of demand (read+write) accesses 495system.cpu.dcache.overall_accesses::0 21760587 # number of overall (read+write) accesses 496system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses 497system.cpu.dcache.overall_accesses::total 21760587 # number of overall (read+write) accesses 498system.cpu.dcache.ReadReq_miss_rate::0 0.097900 # miss rate for ReadReq accesses 499system.cpu.dcache.WriteReq_miss_rate::0 0.037579 # miss rate for WriteReq accesses 500system.cpu.dcache.demand_miss_rate::0 0.074626 # miss rate for demand accesses 501system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses 502system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses 503system.cpu.dcache.overall_miss_rate::0 0.074626 # miss rate for overall accesses 504system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses 505system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses 506system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency 507system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency 508system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency 509system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency 510system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency 511system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency 512system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 513system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 514system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 515system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 516system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 517system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 518system.cpu.dcache.fast_writes 0 # number of fast writes performed 519system.cpu.dcache.cache_copies 0 # number of cache copies performed 520system.cpu.dcache.writebacks 1525259 # number of writebacks 521system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits 522system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits 523system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses 524system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses 525system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses 526system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles 527system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles 528system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles 529system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses 530system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses 531system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses 532system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses 533system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses 534system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses 535system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency 536system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency 537system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency 538system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated 539system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions 540system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 541 542---------- End Simulation Statistics ---------- 543