stats.txt revision 9962
17927SN/A 27927SN/A---------- Begin Simulation Statistics ---------- 39901Sandreas@sandberg.pp.sesim_seconds 5.112126 # Number of seconds simulated 49962Sandreas.hansson@arm.comsim_ticks 5112126264500 # Number of ticks simulated 59962Sandreas.hansson@arm.comfinal_tick 5112126264500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67927SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79962Sandreas.hansson@arm.comhost_inst_rate 1904189 # Simulator instruction rate (inst/s) 89962Sandreas.hansson@arm.comhost_op_rate 3898708 # Simulator op (including micro ops) rate (op/s) 99962Sandreas.hansson@arm.comhost_tick_rate 48689346278 # Simulator tick rate (ticks/s) 109962Sandreas.hansson@arm.comhost_mem_usage 587596 # Number of bytes of host memory used 119962Sandreas.hansson@arm.comhost_seconds 104.99 # Real time elapsed on the host 129901Sandreas@sandberg.pp.sesim_insts 199929810 # Number of instructions simulated 139962Sandreas.hansson@arm.comsim_ops 409343850 # Number of ops (including micro ops) simulated 149901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory 159901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 169079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 179625Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 189901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory 199901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::total 13883648 # Number of bytes read from this memory 209625Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 219625Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory 229901Sandreas@sandberg.pp.sesystem.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory 239901Sandreas@sandberg.pp.sesystem.physmem.bytes_written::total 9268672 # Number of bytes written to this memory 249901Sandreas@sandberg.pp.sesystem.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory 259901Sandreas@sandberg.pp.sesystem.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 269079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 279625Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory 289901Sandreas@sandberg.pp.sesystem.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory 299901Sandreas@sandberg.pp.sesystem.physmem.num_reads::total 216932 # Number of read requests responded to by this memory 309901Sandreas@sandberg.pp.sesystem.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory 319901Sandreas@sandberg.pp.sesystem.physmem.num_writes::total 144823 # Number of write requests responded to by this memory 329901Sandreas@sandberg.pp.sesystem.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s) 339901Sandreas@sandberg.pp.sesystem.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 349079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 359625Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) 369901Sandreas@sandberg.pp.sesystem.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s) 379962Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2715827 # Total read bandwidth from this memory (bytes/s) 389625Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) 399625Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) 409901Sandreas@sandberg.pp.sesystem.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s) 419901Sandreas@sandberg.pp.sesystem.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s) 429901Sandreas@sandberg.pp.sesystem.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s) 439901Sandreas@sandberg.pp.sesystem.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s) 449901Sandreas@sandberg.pp.sesystem.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 459079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 469625Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) 479901Sandreas@sandberg.pp.sesystem.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s) 489901Sandreas@sandberg.pp.sesystem.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s) 499901Sandreas@sandberg.pp.sesystem.membus.throughput 9634332 # Throughput (bytes/s) 509901Sandreas@sandberg.pp.sesystem.membus.data_through_bus 49251923 # Total data (bytes) 519729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 529838Sandreas.hansson@arm.comsystem.iocache.tags.replacements 47569 # number of replacements 539901Sandreas@sandberg.pp.sesystem.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use 549838Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 559838Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 569838Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 579901Sandreas@sandberg.pp.sesystem.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit. 589901Sandreas@sandberg.pp.sesystem.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor 599797Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 609838Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 619797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 629797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 904 # number of ReadReq misses 638835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 648613SN/Asystem.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 659797Sandreas.hansson@arm.comsystem.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses 669797Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 47624 # number of demand (read+write) misses 679797Sandreas.hansson@arm.comsystem.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses 689797Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 47624 # number of overall misses 699797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 709797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) 718835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 728613SN/Asystem.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 739797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses 749797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses 759797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses 769797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses 778835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 789055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 798835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 809055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 818835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 829055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 838835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 849055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 858613SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 868613SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 878613SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 888613SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 898983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 908983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 918613SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 928613SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 938835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 46667 # number of writebacks 948835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 46667 # number of writebacks 958613SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 968613SN/Asystem.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 978613SN/Asystem.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 989797Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 998613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1008613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1018613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1028613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1038613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1048613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1058613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1068613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1078613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1089901Sandreas@sandberg.pp.sesystem.iobus.throughput 2555207 # Throughput (bytes/s) 1099901Sandreas@sandberg.pp.sesystem.iobus.data_through_bus 13062542 # Total data (bytes) 1109962Sandreas.hansson@arm.comsystem.cpu.numCycles 10224252551 # number of cpu cycles simulated 1118613SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 1128613SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 1139901Sandreas@sandberg.pp.sesystem.cpu.committedInsts 199929810 # Number of instructions committed 1149962Sandreas.hansson@arm.comsystem.cpu.committedOps 409343850 # Number of ops (including micro ops) committed 1159962Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 374364636 # Number of integer alu accesses 1168613SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 1179901Sandreas@sandberg.pp.sesystem.cpu.num_func_calls 2307717 # number of times a function call or return occured 1189962Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 39976328 # number of instructions that are conditional controls 1199962Sandreas.hansson@arm.comsystem.cpu.num_int_insts 374364636 # number of integer instructions 1208613SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 1219962Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 682285475 # number of times the integer registers were read 1229962Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 323369236 # number of times the integer registers were written 1238613SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 1248613SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 1259962Sandreas.hansson@arm.comsystem.cpu.num_cc_register_reads 233715040 # number of times the CC registers were read 1269962Sandreas.hansson@arm.comsystem.cpu.num_cc_register_writes 157233555 # number of times the CC registers were written 1279901Sandreas@sandberg.pp.sesystem.cpu.num_mem_refs 35660913 # number of memory refs 1289901Sandreas@sandberg.pp.sesystem.cpu.num_load_insts 27238816 # Number of load instructions 1299901Sandreas@sandberg.pp.sesystem.cpu.num_store_insts 8422097 # Number of store instructions 1309962Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 9770516920.735764 # Number of idle cycles 1319962Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 453735630.264235 # Number of busy cycles 1329901Sandreas@sandberg.pp.sesystem.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles 1339901Sandreas@sandberg.pp.sesystem.cpu.idle_fraction 0.955622 # Percentage of idle cycles 1348613SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 1358613SN/Asystem.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1369962Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 790558 # number of replacements 1379901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use 1389962Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 243525778 # Total number of references to valid blocks. 1399962Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 791070 # Sample count of references to valid blocks. 1409962Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 307.843526 # Average number of references to valid blocks. 1419901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. 1429901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor 1439901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy 1449901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy 1459962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 243525778 # number of ReadReq hits 1469962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 243525778 # number of ReadReq hits 1479962Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 243525778 # number of demand (read+write) hits 1489962Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 243525778 # number of demand (read+write) hits 1499962Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 243525778 # number of overall hits 1509962Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 243525778 # number of overall hits 1519962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 791077 # number of ReadReq misses 1529962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 791077 # number of ReadReq misses 1539962Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 791077 # number of demand (read+write) misses 1549962Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 791077 # number of demand (read+write) misses 1559962Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 791077 # number of overall misses 1569962Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 791077 # number of overall misses 1579962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 244316855 # number of ReadReq accesses(hits+misses) 1589962Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 244316855 # number of ReadReq accesses(hits+misses) 1599962Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 244316855 # number of demand (read+write) accesses 1609962Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 244316855 # number of demand (read+write) accesses 1619962Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 244316855 # number of overall (read+write) accesses 1629962Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 244316855 # number of overall (read+write) accesses 1639625Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 1649625Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 1659625Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 1669625Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 1679625Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 1689625Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 1698613SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1708613SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1718613SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1728613SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1738983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1748983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1758613SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 1768613SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 1778613SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1789797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements 1799962Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.tagsinuse 3.026303 # Cycle average of tags in use 1809838Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. 1819797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. 1829838Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. 1839962Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.warmup_cycle 5102116468000 # Cycle when the warmup percentage was hit. 1849962Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026303 # Average occupied blocks per requestor 1859901Sandreas@sandberg.pp.sesystem.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy 1869901Sandreas@sandberg.pp.sesystem.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy 1879625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 1889625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits 1898835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 1908613SN/Asystem.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 1919625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits 1929625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits 1939625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits 1949625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits 1959625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses 1969625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses 1979625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses 1989625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses 1999625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses 2009625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses 2019625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) 2029625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) 2038835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 2048613SN/Asystem.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 2059625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses 2069625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses 2079625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses 2089625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses 2099625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses 2109625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses 2119625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses 2129625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses 2139625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses 2149625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses 2158613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2168613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2178613SN/Asystem.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 2188613SN/Asystem.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 2198983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2208983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2218613SN/Asystem.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 2228613SN/Asystem.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 2239625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 2249625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 2258613SN/Asystem.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 2269797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements 2279962Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use 2289901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks. 2299797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. 2309901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks. 2319962Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.warmup_cycle 5100462243000 # Cycle when the warmup percentage was hit. 2329962Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor 2339797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy 2349797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy 2359901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits 2369901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits 2379901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits 2389901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits 2399901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits 2409901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits 2419901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses 2429901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses 2439901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses 2449901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses 2459901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses 2469901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses 2479901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses) 2489901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses) 2499901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses 2509901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses 2519901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses 2529901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses 2539901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses 2549901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses 2559901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses 2569901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses 2579901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses 2589901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses 2598613SN/Asystem.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2608613SN/Asystem.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2618613SN/Asystem.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 2628613SN/Asystem.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 2638983Snate@binkert.orgsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2648983Snate@binkert.orgsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2658613SN/Asystem.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 2668613SN/Asystem.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 2679901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks 2689901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks 2698613SN/Asystem.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 2709962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1622097 # number of replacements 2719838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use 2729962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 20175179 # Total number of references to valid blocks. 2739962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1622609 # Sample count of references to valid blocks. 2749962Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 12.433790 # Average number of references to valid blocks. 2759838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 2769838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor 2779838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 2789838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 2799962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 12077531 # number of ReadReq hits 2809962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 12077531 # number of ReadReq hits 2819962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 8095378 # number of WriteReq hits 2829962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 8095378 # number of WriteReq hits 2839962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 20172909 # number of demand (read+write) hits 2849962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 20172909 # number of demand (read+write) hits 2859962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 20172909 # number of overall hits 2869962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 20172909 # number of overall hits 2879962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1308430 # number of ReadReq misses 2889962Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1308430 # number of ReadReq misses 2899962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 316465 # number of WriteReq misses 2909962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 316465 # number of WriteReq misses 2919962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1624895 # number of demand (read+write) misses 2929962Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 1624895 # number of demand (read+write) misses 2939962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1624895 # number of overall misses 2949962Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 1624895 # number of overall misses 2959901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses) 2969901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses) 2979901Sandreas@sandberg.pp.sesystem.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses) 2989901Sandreas@sandberg.pp.sesystem.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses) 2999901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses 3009901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses 3019901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses 3029901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses 3039901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses 3049901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses 3059962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037621 # miss rate for WriteReq accesses 3069962Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.037621 # miss rate for WriteReq accesses 3079901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses 3089901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses 3099901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses 3109901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses 3118613SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3128613SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3138613SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 3148613SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 3158983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3168983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3178613SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 3188613SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 3199962Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 1535825 # number of writebacks 3209962Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 1535825 # number of writebacks 3218613SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 3229962Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 54625221 # Throughput (bytes/s) 3239962Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 279225555 # Total data (bytes) 3249797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) 3259901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.replacements 105999 # number of replacements 3269962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 64822.034013 # Cycle average of tags in use 3279962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 3456623 # Total number of references to valid blocks. 3289901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks. 3299962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 20.317898 # Average number of references to valid blocks. 3309838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3319962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 51908.839094 # Average occupied blocks per requestor 3329901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor 3339901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor 3349962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.539598 # Average occupied blocks per requestor 3359962Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 10422.520587 # Average occupied blocks per requestor 3369901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy 3379797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 3389797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 3399797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 3409901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy 3419901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy 3429901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits 3439625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits 3449962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 777739 # number of ReadReq hits 3459962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 1275554 # number of ReadReq hits 3469962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 2062599 # number of ReadReq hits 3479962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 1538784 # number of Writeback hits 3489962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 1538784 # number of Writeback hits 3499625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 3509625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits 3519962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 179732 # number of ReadExReq hits 3529962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 179732 # number of ReadExReq hits 3539901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits 3549625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits 3559962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 777739 # number of demand (read+write) hits 3569962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1455286 # number of demand (read+write) hits 3579962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2242331 # number of demand (read+write) hits 3589901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits 3599625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits 3609962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 777739 # number of overall hits 3619962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1455286 # number of overall hits 3629962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2242331 # number of overall hits 3639901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 3649289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 3659625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 3669672Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 3679901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses 3689901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses 3699901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses 3709901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses 3719901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses 3729901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 3739289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 3749625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses 3759901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses 3769901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses 3779901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 3789289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 3799625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 3809901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses 3819901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::total 180035 # number of overall misses 3829901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses) 3839625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) 3849962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 791064 # number of ReadReq accesses(hits+misses) 3859962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1307800 # number of ReadReq accesses(hits+misses) 3869962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2108176 # number of ReadReq accesses(hits+misses) 3879962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 1538784 # number of Writeback accesses(hits+misses) 3889962Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 1538784 # number of Writeback accesses(hits+misses) 3899901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) 3909901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) 3919962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 314190 # number of ReadExReq accesses(hits+misses) 3929962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 314190 # number of ReadExReq accesses(hits+misses) 3939901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses 3949625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses 3959962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 791064 # number of demand (read+write) accesses 3969962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1621990 # number of demand (read+write) accesses 3979962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2422366 # number of demand (read+write) accesses 3989901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses 3999625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses 4009962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 791064 # number of overall (read+write) accesses 4019962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1621990 # number of overall (read+write) accesses 4029962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2422366 # number of overall (read+write) accesses 4039901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses 4049625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses 4059962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016844 # miss rate for ReadReq accesses 4069797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses 4079901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses 4089901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses 4099901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses 4109962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427951 # miss rate for ReadExReq accesses 4119962Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.427951 # miss rate for ReadExReq accesses 4129901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses 4139625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses 4149962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.016844 # miss rate for demand accesses 4159962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.102777 # miss rate for demand accesses 4169962Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.074322 # miss rate for demand accesses 4179901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses 4189625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses 4199962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.016844 # miss rate for overall accesses 4209962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.102777 # miss rate for overall accesses 4219962Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.074322 # miss rate for overall accesses 4229289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4239289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4249289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 4259289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 4269289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4279289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4289289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 4299289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 4309901Sandreas@sandberg.pp.sesystem.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks 4319901Sandreas@sandberg.pp.sesystem.cpu.l2cache.writebacks::total 98156 # number of writebacks 4329289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 4337927SN/A 4347927SN/A---------- End Simulation Statistics ---------- 435