stats.txt revision 9901
17927SN/A 27927SN/A---------- Begin Simulation Statistics ---------- 39901Sandreas@sandberg.pp.sesim_seconds 5.112126 # Number of seconds simulated 49901Sandreas@sandberg.pp.sesim_ticks 5112126311000 # Number of ticks simulated 59901Sandreas@sandberg.pp.sefinal_tick 5112126311000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67927SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79901Sandreas@sandberg.pp.sehost_inst_rate 1020096 # Simulator instruction rate (inst/s) 89901Sandreas@sandberg.pp.sehost_op_rate 2088583 # Simulator op (including micro ops) rate (op/s) 99901Sandreas@sandberg.pp.sehost_tick_rate 26083435490 # Simulator tick rate (ticks/s) 109901Sandreas@sandberg.pp.sehost_mem_usage 587152 # Number of bytes of host memory used 119901Sandreas@sandberg.pp.sehost_seconds 195.99 # Real time elapsed on the host 129901Sandreas@sandberg.pp.sesim_insts 199929810 # Number of instructions simulated 139901Sandreas@sandberg.pp.sesim_ops 409343980 # Number of ops (including micro ops) simulated 149901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::pc.south_bridge.ide 2421184 # Number of bytes read from this memory 159901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 169079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 179625Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 189901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::cpu.data 10609344 # Number of bytes read from this memory 199901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::total 13883648 # Number of bytes read from this memory 209625Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 219625Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory 229901Sandreas@sandberg.pp.sesystem.physmem.bytes_written::writebacks 9268672 # Number of bytes written to this memory 239901Sandreas@sandberg.pp.sesystem.physmem.bytes_written::total 9268672 # Number of bytes written to this memory 249901Sandreas@sandberg.pp.sesystem.physmem.num_reads::pc.south_bridge.ide 37831 # Number of read requests responded to by this memory 259901Sandreas@sandberg.pp.sesystem.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 269079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 279625Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory 289901Sandreas@sandberg.pp.sesystem.physmem.num_reads::cpu.data 165771 # Number of read requests responded to by this memory 299901Sandreas@sandberg.pp.sesystem.physmem.num_reads::total 216932 # Number of read requests responded to by this memory 309901Sandreas@sandberg.pp.sesystem.physmem.num_writes::writebacks 144823 # Number of write requests responded to by this memory 319901Sandreas@sandberg.pp.sesystem.physmem.num_writes::total 144823 # Number of write requests responded to by this memory 329901Sandreas@sandberg.pp.sesystem.physmem.bw_read::pc.south_bridge.ide 473616 # Total read bandwidth from this memory (bytes/s) 339901Sandreas@sandberg.pp.sesystem.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 349079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 359625Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) 369901Sandreas@sandberg.pp.sesystem.physmem.bw_read::cpu.data 2075329 # Total read bandwidth from this memory (bytes/s) 379901Sandreas@sandberg.pp.sesystem.physmem.bw_read::total 2715826 # Total read bandwidth from this memory (bytes/s) 389625Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) 399625Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) 409901Sandreas@sandberg.pp.sesystem.physmem.bw_write::writebacks 1813076 # Write bandwidth from this memory (bytes/s) 419901Sandreas@sandberg.pp.sesystem.physmem.bw_write::total 1813076 # Write bandwidth from this memory (bytes/s) 429901Sandreas@sandberg.pp.sesystem.physmem.bw_total::writebacks 1813076 # Total bandwidth to/from this memory (bytes/s) 439901Sandreas@sandberg.pp.sesystem.physmem.bw_total::pc.south_bridge.ide 473616 # Total bandwidth to/from this memory (bytes/s) 449901Sandreas@sandberg.pp.sesystem.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 459079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 469625Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) 479901Sandreas@sandberg.pp.sesystem.physmem.bw_total::cpu.data 2075329 # Total bandwidth to/from this memory (bytes/s) 489901Sandreas@sandberg.pp.sesystem.physmem.bw_total::total 4528902 # Total bandwidth to/from this memory (bytes/s) 499838Sandreas.hansson@arm.comsystem.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller 509838Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 519838Sandreas.hansson@arm.comsystem.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 529838Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 539312Sandreas.hansson@arm.comsystem.physmem.bytesRead 0 # Total number of bytes read from memory 549312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 559312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 569312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 579838Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 589312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 599312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 729312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 739312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 749312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 759312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 769312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 779312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 789312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 799312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 809312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 819312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 829312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 839312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 849312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 859312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 869312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 879312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 889312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 899312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 909312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 919312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 929312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 939312Sandreas.hansson@arm.comsystem.physmem.totGap 0 # Total gap between requests 949312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 1009312Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 0 # Categorize read packet sizes 1019568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 1029568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 1039568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 1049568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 1059568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 1069568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 1079568Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Categorize write packet sizes 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1679312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1689312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1699312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1709312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1719312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1729729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation 1739729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation 1749729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation 1759312Sandreas.hansson@arm.comsystem.physmem.totQLat 0 # Total cycles spent in queuing delays 1769312Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 0 # Sum of mem lat for all requests 1779312Sandreas.hansson@arm.comsystem.physmem.totBusLat 0 # Total cycles spent in databus access 1789312Sandreas.hansson@arm.comsystem.physmem.totBankLat 0 # Total cycles spent in bank access 1799312Sandreas.hansson@arm.comsystem.physmem.avgQLat nan # Average queueing delay per request 1809312Sandreas.hansson@arm.comsystem.physmem.avgBankLat nan # Average bank access latency per request 1819312Sandreas.hansson@arm.comsystem.physmem.avgBusLat nan # Average bus latency per request 1829312Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat nan # Average memory access latency 1839312Sandreas.hansson@arm.comsystem.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 1849312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1859312Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 1869312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1879490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 1889312Sandreas.hansson@arm.comsystem.physmem.busUtil 0.00 # Data bus utilization in percentage 1899312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.00 # Average read queue length over time 1909312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1919312Sandreas.hansson@arm.comsystem.physmem.readRowHits 0 # Number of row buffer hits during reads 1929312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1939312Sandreas.hansson@arm.comsystem.physmem.readRowHitRate nan # Row buffer hit rate for reads 1949312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1959312Sandreas.hansson@arm.comsystem.physmem.avgGap nan # Average gap between requests 1969901Sandreas@sandberg.pp.sesystem.membus.throughput 9634332 # Throughput (bytes/s) 1979901Sandreas@sandberg.pp.sesystem.membus.data_through_bus 49251923 # Total data (bytes) 1989729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 1999838Sandreas.hansson@arm.comsystem.iocache.tags.replacements 47569 # number of replacements 2009901Sandreas@sandberg.pp.sesystem.iocache.tags.tagsinuse 0.042448 # Cycle average of tags in use 2019838Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2029838Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 2039838Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2049901Sandreas@sandberg.pp.sesystem.iocache.tags.warmup_cycle 4994846763009 # Cycle when the warmup percentage was hit. 2059901Sandreas@sandberg.pp.sesystem.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042448 # Average occupied blocks per requestor 2069797Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 2079838Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 2089797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 2099797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 904 # number of ReadReq misses 2108835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 2118613SN/Asystem.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 2129797Sandreas.hansson@arm.comsystem.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses 2139797Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 47624 # number of demand (read+write) misses 2149797Sandreas.hansson@arm.comsystem.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses 2159797Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 47624 # number of overall misses 2169797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 2179797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) 2188835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 2198613SN/Asystem.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 2209797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses 2219797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses 2229797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses 2239797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses 2248835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 2259055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2268835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 2279055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2288835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 2299055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2308835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 2319055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2328613SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2338613SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2348613SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2358613SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2368983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2378983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2388613SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 2398613SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2408835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 46667 # number of writebacks 2418835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 46667 # number of writebacks 2428613SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2438613SN/Asystem.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2448613SN/Asystem.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 2459797Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 2468613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 2478613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 2488613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 2498613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2508613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2518613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2528613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 2538613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 2548613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 2559901Sandreas@sandberg.pp.sesystem.iobus.throughput 2555207 # Throughput (bytes/s) 2569901Sandreas@sandberg.pp.sesystem.iobus.data_through_bus 13062542 # Total data (bytes) 2579901Sandreas@sandberg.pp.sesystem.cpu.numCycles 10224252644 # number of cpu cycles simulated 2588613SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2598613SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2609901Sandreas@sandberg.pp.sesystem.cpu.committedInsts 199929810 # Number of instructions committed 2619901Sandreas@sandberg.pp.sesystem.cpu.committedOps 409343980 # Number of ops (including micro ops) committed 2629901Sandreas@sandberg.pp.sesystem.cpu.num_int_alu_accesses 374506599 # Number of integer alu accesses 2638613SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 2649901Sandreas@sandberg.pp.sesystem.cpu.num_func_calls 2307717 # number of times a function call or return occured 2659901Sandreas@sandberg.pp.sesystem.cpu.num_conditional_control_insts 39976354 # number of instructions that are conditional controls 2669901Sandreas@sandberg.pp.sesystem.cpu.num_int_insts 374506599 # number of integer instructions 2678613SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 2689901Sandreas@sandberg.pp.sesystem.cpu.num_int_register_reads 916001165 # number of times the integer registers were read 2699901Sandreas@sandberg.pp.sesystem.cpu.num_int_register_writes 480603129 # number of times the integer registers were written 2708613SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 2718613SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 2729901Sandreas@sandberg.pp.sesystem.cpu.num_mem_refs 35660913 # number of memory refs 2739901Sandreas@sandberg.pp.sesystem.cpu.num_load_insts 27238816 # Number of load instructions 2749901Sandreas@sandberg.pp.sesystem.cpu.num_store_insts 8422097 # Number of store instructions 2759901Sandreas@sandberg.pp.sesystem.cpu.num_idle_cycles 9770516880.735765 # Number of idle cycles 2769901Sandreas@sandberg.pp.sesystem.cpu.num_busy_cycles 453735763.264236 # Number of busy cycles 2779901Sandreas@sandberg.pp.sesystem.cpu.not_idle_fraction 0.044378 # Percentage of non-idle cycles 2789901Sandreas@sandberg.pp.sesystem.cpu.idle_fraction 0.955622 # Percentage of idle cycles 2798613SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 2808613SN/Asystem.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 2819901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.replacements 790541 # number of replacements 2829901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.tagsinuse 510.665021 # Cycle average of tags in use 2839901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.total_refs 243525798 # Total number of references to valid blocks. 2849901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.sampled_refs 791053 # Sample count of references to valid blocks. 2859901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.avg_refs 307.850167 # Average number of references to valid blocks. 2869901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.warmup_cycle 148848615500 # Cycle when the warmup percentage was hit. 2879901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.occ_blocks::cpu.inst 510.665021 # Average occupied blocks per requestor 2889901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.occ_percent::cpu.inst 0.997393 # Average percentage of cache occupancy 2899901Sandreas@sandberg.pp.sesystem.cpu.icache.tags.occ_percent::total 0.997393 # Average percentage of cache occupancy 2909901Sandreas@sandberg.pp.sesystem.cpu.icache.ReadReq_hits::cpu.inst 243525798 # number of ReadReq hits 2919901Sandreas@sandberg.pp.sesystem.cpu.icache.ReadReq_hits::total 243525798 # number of ReadReq hits 2929901Sandreas@sandberg.pp.sesystem.cpu.icache.demand_hits::cpu.inst 243525798 # number of demand (read+write) hits 2939901Sandreas@sandberg.pp.sesystem.cpu.icache.demand_hits::total 243525798 # number of demand (read+write) hits 2949901Sandreas@sandberg.pp.sesystem.cpu.icache.overall_hits::cpu.inst 243525798 # number of overall hits 2959901Sandreas@sandberg.pp.sesystem.cpu.icache.overall_hits::total 243525798 # number of overall hits 2969901Sandreas@sandberg.pp.sesystem.cpu.icache.ReadReq_misses::cpu.inst 791060 # number of ReadReq misses 2979901Sandreas@sandberg.pp.sesystem.cpu.icache.ReadReq_misses::total 791060 # number of ReadReq misses 2989901Sandreas@sandberg.pp.sesystem.cpu.icache.demand_misses::cpu.inst 791060 # number of demand (read+write) misses 2999901Sandreas@sandberg.pp.sesystem.cpu.icache.demand_misses::total 791060 # number of demand (read+write) misses 3009901Sandreas@sandberg.pp.sesystem.cpu.icache.overall_misses::cpu.inst 791060 # number of overall misses 3019901Sandreas@sandberg.pp.sesystem.cpu.icache.overall_misses::total 791060 # number of overall misses 3029901Sandreas@sandberg.pp.sesystem.cpu.icache.ReadReq_accesses::cpu.inst 244316858 # number of ReadReq accesses(hits+misses) 3039901Sandreas@sandberg.pp.sesystem.cpu.icache.ReadReq_accesses::total 244316858 # number of ReadReq accesses(hits+misses) 3049901Sandreas@sandberg.pp.sesystem.cpu.icache.demand_accesses::cpu.inst 244316858 # number of demand (read+write) accesses 3059901Sandreas@sandberg.pp.sesystem.cpu.icache.demand_accesses::total 244316858 # number of demand (read+write) accesses 3069901Sandreas@sandberg.pp.sesystem.cpu.icache.overall_accesses::cpu.inst 244316858 # number of overall (read+write) accesses 3079901Sandreas@sandberg.pp.sesystem.cpu.icache.overall_accesses::total 244316858 # number of overall (read+write) accesses 3089625Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 3099625Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 3109625Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 3119625Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 3129625Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 3139625Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 3148613SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3158613SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3168613SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3178613SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3188983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3198983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3208613SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3218613SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3228613SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3239797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements 3249901Sandreas@sandberg.pp.sesystem.cpu.itb_walker_cache.tags.tagsinuse 3.026300 # Cycle average of tags in use 3259838Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. 3269797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. 3279838Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. 3289901Sandreas@sandberg.pp.sesystem.cpu.itb_walker_cache.tags.warmup_cycle 5102118322000 # Cycle when the warmup percentage was hit. 3299901Sandreas@sandberg.pp.sesystem.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026300 # Average occupied blocks per requestor 3309901Sandreas@sandberg.pp.sesystem.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189144 # Average percentage of cache occupancy 3319901Sandreas@sandberg.pp.sesystem.cpu.itb_walker_cache.tags.occ_percent::total 0.189144 # Average percentage of cache occupancy 3329625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 3339625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits 3348835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 3358613SN/Asystem.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 3369625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits 3379625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits 3389625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits 3399625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits 3409625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses 3419625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses 3429625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses 3439625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses 3449625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses 3459625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses 3469625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) 3479625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) 3488835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 3498613SN/Asystem.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 3509625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses 3519625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses 3529625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses 3539625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses 3549625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses 3559625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses 3569625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses 3579625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses 3589625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses 3599625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses 3608613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3618613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3628613SN/Asystem.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 3638613SN/Asystem.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 3648983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3658983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3668613SN/Asystem.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 3678613SN/Asystem.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 3689625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 3699625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 3708613SN/Asystem.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 3719797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements 3729901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.tags.tagsinuse 5.014180 # Cycle average of tags in use 3739901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.tags.total_refs 12955 # Total number of references to valid blocks. 3749797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. 3759901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.tags.avg_refs 1.694793 # Average number of references to valid blocks. 3769901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.tags.warmup_cycle 5100463009500 # Cycle when the warmup percentage was hit. 3779901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014180 # Average occupied blocks per requestor 3789797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy 3799797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy 3809901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12963 # number of ReadReq hits 3819901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_hits::total 12963 # number of ReadReq hits 3829901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12963 # number of demand (read+write) hits 3839901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_hits::total 12963 # number of demand (read+write) hits 3849901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12963 # number of overall hits 3859901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_hits::total 12963 # number of overall hits 3869901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8824 # number of ReadReq misses 3879901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_misses::total 8824 # number of ReadReq misses 3889901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8824 # number of demand (read+write) misses 3899901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_misses::total 8824 # number of demand (read+write) misses 3909901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8824 # number of overall misses 3919901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_misses::total 8824 # number of overall misses 3929901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21787 # number of ReadReq accesses(hits+misses) 3939901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_accesses::total 21787 # number of ReadReq accesses(hits+misses) 3949901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21787 # number of demand (read+write) accesses 3959901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_accesses::total 21787 # number of demand (read+write) accesses 3969901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21787 # number of overall (read+write) accesses 3979901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_accesses::total 21787 # number of overall (read+write) accesses 3989901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405012 # miss rate for ReadReq accesses 3999901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405012 # miss rate for ReadReq accesses 4009901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405012 # miss rate for demand accesses 4019901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.demand_miss_rate::total 0.405012 # miss rate for demand accesses 4029901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405012 # miss rate for overall accesses 4039901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.overall_miss_rate::total 0.405012 # miss rate for overall accesses 4048613SN/Asystem.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4058613SN/Asystem.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4068613SN/Asystem.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 4078613SN/Asystem.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 4088983Snate@binkert.orgsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4098983Snate@binkert.orgsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4108613SN/Asystem.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 4118613SN/Asystem.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 4129901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.writebacks::writebacks 2433 # number of writebacks 4139901Sandreas@sandberg.pp.sesystem.cpu.dtb_walker_cache.writebacks::total 2433 # number of writebacks 4148613SN/Asystem.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 4159901Sandreas@sandberg.pp.sesystem.cpu.dcache.tags.replacements 1622093 # number of replacements 4169838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use 4179901Sandreas@sandberg.pp.sesystem.cpu.dcache.tags.total_refs 20175183 # Total number of references to valid blocks. 4189901Sandreas@sandberg.pp.sesystem.cpu.dcache.tags.sampled_refs 1622605 # Sample count of references to valid blocks. 4199901Sandreas@sandberg.pp.sesystem.cpu.dcache.tags.avg_refs 12.433823 # Average number of references to valid blocks. 4209838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 4219838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor 4229838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 4239838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 4249901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_hits::cpu.data 12077542 # number of ReadReq hits 4259901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_hits::total 12077542 # number of ReadReq hits 4269901Sandreas@sandberg.pp.sesystem.cpu.dcache.WriteReq_hits::cpu.data 8095371 # number of WriteReq hits 4279901Sandreas@sandberg.pp.sesystem.cpu.dcache.WriteReq_hits::total 8095371 # number of WriteReq hits 4289901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_hits::cpu.data 20172913 # number of demand (read+write) hits 4299901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_hits::total 20172913 # number of demand (read+write) hits 4309901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_hits::cpu.data 20172913 # number of overall hits 4319901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_hits::total 20172913 # number of overall hits 4329901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_misses::cpu.data 1308419 # number of ReadReq misses 4339901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_misses::total 1308419 # number of ReadReq misses 4349901Sandreas@sandberg.pp.sesystem.cpu.dcache.WriteReq_misses::cpu.data 316472 # number of WriteReq misses 4359901Sandreas@sandberg.pp.sesystem.cpu.dcache.WriteReq_misses::total 316472 # number of WriteReq misses 4369901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_misses::cpu.data 1624891 # number of demand (read+write) misses 4379901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_misses::total 1624891 # number of demand (read+write) misses 4389901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_misses::cpu.data 1624891 # number of overall misses 4399901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_misses::total 1624891 # number of overall misses 4409901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_accesses::cpu.data 13385961 # number of ReadReq accesses(hits+misses) 4419901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_accesses::total 13385961 # number of ReadReq accesses(hits+misses) 4429901Sandreas@sandberg.pp.sesystem.cpu.dcache.WriteReq_accesses::cpu.data 8411843 # number of WriteReq accesses(hits+misses) 4439901Sandreas@sandberg.pp.sesystem.cpu.dcache.WriteReq_accesses::total 8411843 # number of WriteReq accesses(hits+misses) 4449901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_accesses::cpu.data 21797804 # number of demand (read+write) accesses 4459901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_accesses::total 21797804 # number of demand (read+write) accesses 4469901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_accesses::cpu.data 21797804 # number of overall (read+write) accesses 4479901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_accesses::total 21797804 # number of overall (read+write) accesses 4489901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097746 # miss rate for ReadReq accesses 4499901Sandreas@sandberg.pp.sesystem.cpu.dcache.ReadReq_miss_rate::total 0.097746 # miss rate for ReadReq accesses 4509672Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses 4519672Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses 4529901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_miss_rate::cpu.data 0.074544 # miss rate for demand accesses 4539901Sandreas@sandberg.pp.sesystem.cpu.dcache.demand_miss_rate::total 0.074544 # miss rate for demand accesses 4549901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_miss_rate::cpu.data 0.074544 # miss rate for overall accesses 4559901Sandreas@sandberg.pp.sesystem.cpu.dcache.overall_miss_rate::total 0.074544 # miss rate for overall accesses 4568613SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4578613SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4588613SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4598613SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4608983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4618983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4628613SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4638613SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4649901Sandreas@sandberg.pp.sesystem.cpu.dcache.writebacks::writebacks 1535822 # number of writebacks 4659901Sandreas@sandberg.pp.sesystem.cpu.dcache.writebacks::total 1535822 # number of writebacks 4668613SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4679901Sandreas@sandberg.pp.sesystem.cpu.toL2Bus.throughput 54624920 # Throughput (bytes/s) 4689901Sandreas@sandberg.pp.sesystem.cpu.toL2Bus.data_through_bus 279224019 # Total data (bytes) 4699797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) 4709901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.replacements 105999 # number of replacements 4719901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.tagsinuse 64822.033663 # Cycle average of tags in use 4729901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.total_refs 3456588 # Total number of references to valid blocks. 4739901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.sampled_refs 170127 # Sample count of references to valid blocks. 4749901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.avg_refs 20.317692 # Average number of references to valid blocks. 4759838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4769901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_blocks::writebacks 51908.841728 # Average occupied blocks per requestor 4779901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor 4789901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132255 # Average occupied blocks per requestor 4799901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.538603 # Average occupied blocks per requestor 4809901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_blocks::cpu.data 10422.518599 # Average occupied blocks per requestor 4819901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_percent::writebacks 0.792066 # Average percentage of cache occupancy 4829797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 4839797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 4849797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 4859901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_percent::cpu.data 0.159035 # Average percentage of cache occupancy 4869901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_percent::total 0.989106 # Average percentage of cache occupancy 4879901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6504 # number of ReadReq hits 4889625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits 4899901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_hits::cpu.inst 777722 # number of ReadReq hits 4909901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_hits::cpu.data 1275543 # number of ReadReq hits 4919901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_hits::total 2062571 # number of ReadReq hits 4929901Sandreas@sandberg.pp.sesystem.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits 4939901Sandreas@sandberg.pp.sesystem.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits 4949625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 4959625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits 4969901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_hits::cpu.data 179739 # number of ReadExReq hits 4979901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_hits::total 179739 # number of ReadExReq hits 4989901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_hits::cpu.dtb.walker 6504 # number of demand (read+write) hits 4999625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits 5009901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_hits::cpu.inst 777722 # number of demand (read+write) hits 5019797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1455282 # number of demand (read+write) hits 5029901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_hits::total 2242310 # number of demand (read+write) hits 5039901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_hits::cpu.dtb.walker 6504 # number of overall hits 5049625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits 5059901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_hits::cpu.inst 777722 # number of overall hits 5069797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1455282 # number of overall hits 5079901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_hits::total 2242310 # number of overall hits 5089901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 5099289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 5109625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 5119672Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 5129901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_misses::total 45577 # number of ReadReq misses 5139901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1805 # number of UpgradeReq misses 5149901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_misses::total 1805 # number of UpgradeReq misses 5159901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_misses::cpu.data 134458 # number of ReadExReq misses 5169901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_misses::total 134458 # number of ReadExReq misses 5179901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 5189289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 5199625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses 5209901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::cpu.data 166704 # number of demand (read+write) misses 5219901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::total 180035 # number of demand (read+write) misses 5229901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 5239289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 5249625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 5259901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::cpu.data 166704 # number of overall misses 5269901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::total 180035 # number of overall misses 5279901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6505 # number of ReadReq accesses(hits+misses) 5289625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) 5299901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_accesses::cpu.inst 791047 # number of ReadReq accesses(hits+misses) 5309901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_accesses::cpu.data 1307789 # number of ReadReq accesses(hits+misses) 5319901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_accesses::total 2108148 # number of ReadReq accesses(hits+misses) 5329901Sandreas@sandberg.pp.sesystem.cpu.l2cache.Writeback_accesses::writebacks 1538781 # number of Writeback accesses(hits+misses) 5339901Sandreas@sandberg.pp.sesystem.cpu.l2cache.Writeback_accesses::total 1538781 # number of Writeback accesses(hits+misses) 5349901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 1825 # number of UpgradeReq accesses(hits+misses) 5359901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_accesses::total 1825 # number of UpgradeReq accesses(hits+misses) 5369901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_accesses::cpu.data 314197 # number of ReadExReq accesses(hits+misses) 5379901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_accesses::total 314197 # number of ReadExReq accesses(hits+misses) 5389901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 6505 # number of demand (read+write) accesses 5399625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses 5409901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_accesses::cpu.inst 791047 # number of demand (read+write) accesses 5419901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_accesses::cpu.data 1621986 # number of demand (read+write) accesses 5429901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_accesses::total 2422345 # number of demand (read+write) accesses 5439901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 6505 # number of overall (read+write) accesses 5449625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses 5459901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_accesses::cpu.inst 791047 # number of overall (read+write) accesses 5469901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_accesses::cpu.data 1621986 # number of overall (read+write) accesses 5479901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_accesses::total 2422345 # number of overall (read+write) accesses 5489901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000154 # miss rate for ReadReq accesses 5499625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses 5509797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016845 # miss rate for ReadReq accesses 5519797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses 5529901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_miss_rate::total 0.021619 # miss rate for ReadReq accesses 5539901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989041 # miss rate for UpgradeReq accesses 5549901Sandreas@sandberg.pp.sesystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.989041 # miss rate for UpgradeReq accesses 5559901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427942 # miss rate for ReadExReq accesses 5569901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadExReq_miss_rate::total 0.427942 # miss rate for ReadExReq accesses 5579901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000154 # miss rate for demand accesses 5589625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses 5599797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.016845 # miss rate for demand accesses 5609901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_miss_rate::cpu.data 0.102778 # miss rate for demand accesses 5619901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_miss_rate::total 0.074323 # miss rate for demand accesses 5629901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000154 # miss rate for overall accesses 5639625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses 5649797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.016845 # miss rate for overall accesses 5659901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_miss_rate::cpu.data 0.102778 # miss rate for overall accesses 5669901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_miss_rate::total 0.074323 # miss rate for overall accesses 5679289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5689289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5699289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5709289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5719289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5729289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5739289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5749289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 5759901Sandreas@sandberg.pp.sesystem.cpu.l2cache.writebacks::writebacks 98156 # number of writebacks 5769901Sandreas@sandberg.pp.sesystem.cpu.l2cache.writebacks::total 98156 # number of writebacks 5779289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 5787927SN/A 5797927SN/A---------- End Simulation Statistics ---------- 580