stats.txt revision 9797
17927SN/A 27927SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comsim_seconds 5.112102 # Number of seconds simulated 49797Sandreas.hansson@arm.comsim_ticks 5112102211000 # Number of ticks simulated 59797Sandreas.hansson@arm.comfinal_tick 5112102211000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67927SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79797Sandreas.hansson@arm.comhost_inst_rate 878832 # Simulator instruction rate (inst/s) 89797Sandreas.hansson@arm.comhost_op_rate 1799374 # Simulator op (including micro ops) rate (op/s) 99797Sandreas.hansson@arm.comhost_tick_rate 22473674513 # Simulator tick rate (ticks/s) 109797Sandreas.hansson@arm.comhost_mem_usage 586256 # Number of bytes of host memory used 119797Sandreas.hansson@arm.comhost_seconds 227.47 # Real time elapsed on the host 129797Sandreas.hansson@arm.comsim_insts 199908396 # Number of instructions simulated 139797Sandreas.hansson@arm.comsim_ops 409304707 # Number of ops (including micro ops) simulated 149797Sandreas.hansson@arm.comsystem.physmem.bytes_read::pc.south_bridge.ide 2421056 # Number of bytes read from this memory 159079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 169079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 179625Snilay@cs.wisc.edusystem.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory 189797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 10605120 # Number of bytes read from this memory 199797Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 13879360 # Number of bytes read from this memory 209625Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory 219625Snilay@cs.wisc.edusystem.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory 229797Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 9264512 # Number of bytes written to this memory 239797Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 9264512 # Number of bytes written to this memory 249797Sandreas.hansson@arm.comsystem.physmem.num_reads::pc.south_bridge.ide 37829 # Number of read requests responded to by this memory 259079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory 269079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 279625Snilay@cs.wisc.edusystem.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory 289797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 165705 # Number of read requests responded to by this memory 299797Sandreas.hansson@arm.comsystem.physmem.num_reads::total 216865 # Number of read requests responded to by this memory 309797Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 144758 # Number of write requests responded to by this memory 319797Sandreas.hansson@arm.comsystem.physmem.num_writes::total 144758 # Number of write requests responded to by this memory 329797Sandreas.hansson@arm.comsystem.physmem.bw_read::pc.south_bridge.ide 473593 # Total read bandwidth from this memory (bytes/s) 339079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) 349079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 359625Snilay@cs.wisc.edusystem.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s) 369797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 2074513 # Total read bandwidth from this memory (bytes/s) 379797Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2715000 # Total read bandwidth from this memory (bytes/s) 389625Snilay@cs.wisc.edusystem.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s) 399625Snilay@cs.wisc.edusystem.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s) 409797Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1812270 # Write bandwidth from this memory (bytes/s) 419797Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1812270 # Write bandwidth from this memory (bytes/s) 429797Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1812270 # Total bandwidth to/from this memory (bytes/s) 439797Sandreas.hansson@arm.comsystem.physmem.bw_total::pc.south_bridge.ide 473593 # Total bandwidth to/from this memory (bytes/s) 449079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 459079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 469625Snilay@cs.wisc.edusystem.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s) 479797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 2074513 # Total bandwidth to/from this memory (bytes/s) 489797Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4527271 # Total bandwidth to/from this memory (bytes/s) 499312Sandreas.hansson@arm.comsystem.physmem.readReqs 0 # Total number of read requests seen 509312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 519312Sandreas.hansson@arm.comsystem.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady 529312Sandreas.hansson@arm.comsystem.physmem.bytesRead 0 # Total number of bytes read from memory 539312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 549312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 559312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 569312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 579312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 589312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 729312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 739312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 749312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 759312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 769312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 779312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 789312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 799312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 809312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 819312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 829312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 839312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 849312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 859312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 869312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 879312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 889312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 899312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 909312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 919312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 929312Sandreas.hansson@arm.comsystem.physmem.totGap 0 # Total gap between requests 939312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 0 # Categorize read packet sizes 1009568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 1019568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 1029568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 1039568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 1049568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 1059568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 1069568Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Categorize write packet sizes 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1679312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1689312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1699312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1709312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1719729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation 1729729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation 1739729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation 1749312Sandreas.hansson@arm.comsystem.physmem.totQLat 0 # Total cycles spent in queuing delays 1759312Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 0 # Sum of mem lat for all requests 1769312Sandreas.hansson@arm.comsystem.physmem.totBusLat 0 # Total cycles spent in databus access 1779312Sandreas.hansson@arm.comsystem.physmem.totBankLat 0 # Total cycles spent in bank access 1789312Sandreas.hansson@arm.comsystem.physmem.avgQLat nan # Average queueing delay per request 1799312Sandreas.hansson@arm.comsystem.physmem.avgBankLat nan # Average bank access latency per request 1809312Sandreas.hansson@arm.comsystem.physmem.avgBusLat nan # Average bus latency per request 1819312Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat nan # Average memory access latency 1829312Sandreas.hansson@arm.comsystem.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 1839312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1849312Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 1859312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1869490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 1879312Sandreas.hansson@arm.comsystem.physmem.busUtil 0.00 # Data bus utilization in percentage 1889312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.00 # Average read queue length over time 1899312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1909312Sandreas.hansson@arm.comsystem.physmem.readRowHits 0 # Number of row buffer hits during reads 1919312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1929312Sandreas.hansson@arm.comsystem.physmem.readRowHitRate nan # Row buffer hit rate for reads 1939312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1949312Sandreas.hansson@arm.comsystem.physmem.avgGap nan # Average gap between requests 1959797Sandreas.hansson@arm.comsystem.membus.throughput 9632725 # Throughput (bytes/s) 1969797Sandreas.hansson@arm.comsystem.membus.data_through_bus 49243475 # Total data (bytes) 1979729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 1989797Sandreas.hansson@arm.comsystem.iocache.tags.replacements 47569 # number of replacements 1999797Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.042449 # Cycle average of tags in use 2009797Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2019797Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. 2029797Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2039797Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 4994822663009 # Cycle when the warmup percentage was hit. 2049797Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042449 # Average occupied blocks per requestor 2059797Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 2069797Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 2079797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 2089797Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 904 # number of ReadReq misses 2098835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 2108613SN/Asystem.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 2119797Sandreas.hansson@arm.comsystem.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses 2129797Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 47624 # number of demand (read+write) misses 2139797Sandreas.hansson@arm.comsystem.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses 2149797Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 47624 # number of overall misses 2159797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 2169797Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) 2178835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 2188613SN/Asystem.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 2199797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses 2209797Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses 2219797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses 2229797Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses 2238835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 2249055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2258835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 2269055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2278835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 2289055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2298835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 2309055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2318613SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2328613SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2338613SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2348613SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2358983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2368983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2378613SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 2388613SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2398835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 46667 # number of writebacks 2408835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 46667 # number of writebacks 2418613SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2428613SN/Asystem.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2438613SN/Asystem.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 2449797Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 2458613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 2468613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 2478613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 2488613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2498613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2508613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2518613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 2528613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 2538613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 2549729Sandreas.hansson@arm.comsystem.iobus.throughput 2555194 # Throughput (bytes/s) 2559797Sandreas.hansson@arm.comsystem.iobus.data_through_bus 13062414 # Total data (bytes) 2569797Sandreas.hansson@arm.comsystem.cpu.numCycles 10224204444 # number of cpu cycles simulated 2578613SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2588613SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2599797Sandreas.hansson@arm.comsystem.cpu.committedInsts 199908396 # Number of instructions committed 2609797Sandreas.hansson@arm.comsystem.cpu.committedOps 409304707 # Number of ops (including micro ops) committed 2619797Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 374467605 # Number of integer alu accesses 2628613SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 2639797Sandreas.hansson@arm.comsystem.cpu.num_func_calls 2307395 # number of times a function call or return occured 2649797Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 39972475 # number of instructions that are conditional controls 2659797Sandreas.hansson@arm.comsystem.cpu.num_int_insts 374467605 # number of integer instructions 2668613SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 2679797Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 915905592 # number of times the integer registers were read 2689797Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 480549431 # number of times the integer registers were written 2698613SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 2708613SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 2719797Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 35655576 # number of memory refs 2729797Sandreas.hansson@arm.comsystem.cpu.num_load_insts 27235236 # Number of load instructions 2739797Sandreas.hansson@arm.comsystem.cpu.num_store_insts 8420340 # Number of store instructions 2749797Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 9770516372.735863 # Number of idle cycles 2759797Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 453688071.264138 # Number of busy cycles 2769797Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.044374 # Percentage of non-idle cycles 2779797Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.955626 # Percentage of idle cycles 2788613SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 2798613SN/Asystem.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 2809797Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 790522 # number of replacements 2819797Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 510.666660 # Cycle average of tags in use 2829797Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 243495984 # Total number of references to valid blocks. 2839797Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 791034 # Sample count of references to valid blocks. 2849797Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 307.819871 # Average number of references to valid blocks. 2859797Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 148824778500 # Cycle when the warmup percentage was hit. 2869797Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 510.666660 # Average occupied blocks per requestor 2879797Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.997396 # Average percentage of cache occupancy 2889797Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.997396 # Average percentage of cache occupancy 2899797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 243495984 # number of ReadReq hits 2909797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 243495984 # number of ReadReq hits 2919797Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 243495984 # number of demand (read+write) hits 2929797Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 243495984 # number of demand (read+write) hits 2939797Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 243495984 # number of overall hits 2949797Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 243495984 # number of overall hits 2959797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 791041 # number of ReadReq misses 2969797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 791041 # number of ReadReq misses 2979797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 791041 # number of demand (read+write) misses 2989797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 791041 # number of demand (read+write) misses 2999797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 791041 # number of overall misses 3009797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 791041 # number of overall misses 3019797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 244287025 # number of ReadReq accesses(hits+misses) 3029797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 244287025 # number of ReadReq accesses(hits+misses) 3039797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 244287025 # number of demand (read+write) accesses 3049797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 244287025 # number of demand (read+write) accesses 3059797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 244287025 # number of overall (read+write) accesses 3069797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 244287025 # number of overall (read+write) accesses 3079625Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003238 # miss rate for ReadReq accesses 3089625Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.003238 # miss rate for ReadReq accesses 3099625Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.003238 # miss rate for demand accesses 3109625Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.003238 # miss rate for demand accesses 3119625Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.003238 # miss rate for overall accesses 3129625Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.003238 # miss rate for overall accesses 3138613SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3148613SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3158613SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3168613SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3178983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3188983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3198613SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3208613SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3218613SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3229797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.replacements 3477 # number of replacements 3239797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.tagsinuse 3.026296 # Cycle average of tags in use 3249797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.total_refs 7886 # Total number of references to valid blocks. 3259797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.sampled_refs 3489 # Sample count of references to valid blocks. 3269797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.avg_refs 2.260246 # Average number of references to valid blocks. 3279797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.warmup_cycle 5102094222000 # Cycle when the warmup percentage was hit. 3289797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026296 # Average occupied blocks per requestor 3299797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189143 # Average percentage of cache occupancy 3309797Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_percent::total 0.189143 # Average percentage of cache occupancy 3319625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7887 # number of ReadReq hits 3329625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_hits::total 7887 # number of ReadReq hits 3338835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 3348613SN/Asystem.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 3359625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7889 # number of demand (read+write) hits 3369625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_hits::total 7889 # number of demand (read+write) hits 3379625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7889 # number of overall hits 3389625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_hits::total 7889 # number of overall hits 3399625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4332 # number of ReadReq misses 3409625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_misses::total 4332 # number of ReadReq misses 3419625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4332 # number of demand (read+write) misses 3429625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_misses::total 4332 # number of demand (read+write) misses 3439625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4332 # number of overall misses 3449625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_misses::total 4332 # number of overall misses 3459625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12219 # number of ReadReq accesses(hits+misses) 3469625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_accesses::total 12219 # number of ReadReq accesses(hits+misses) 3478835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 3488613SN/Asystem.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 3499625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12221 # number of demand (read+write) accesses 3509625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_accesses::total 12221 # number of demand (read+write) accesses 3519625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12221 # number of overall (read+write) accesses 3529625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_accesses::total 12221 # number of overall (read+write) accesses 3539625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.354530 # miss rate for ReadReq accesses 3549625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.354530 # miss rate for ReadReq accesses 3559625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.354472 # miss rate for demand accesses 3569625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.demand_miss_rate::total 0.354472 # miss rate for demand accesses 3579625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.354472 # miss rate for overall accesses 3589625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.overall_miss_rate::total 0.354472 # miss rate for overall accesses 3598613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3608613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3618613SN/Asystem.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 3628613SN/Asystem.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 3638983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3648983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3658613SN/Asystem.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 3668613SN/Asystem.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 3679625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.writebacks::writebacks 526 # number of writebacks 3689625Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.writebacks::total 526 # number of writebacks 3698613SN/Asystem.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 3709797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.replacements 7632 # number of replacements 3719797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.tagsinuse 5.014181 # Cycle average of tags in use 3729797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.total_refs 12948 # Total number of references to valid blocks. 3739797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.sampled_refs 7644 # Sample count of references to valid blocks. 3749797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.avg_refs 1.693878 # Average number of references to valid blocks. 3759797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.warmup_cycle 5100438909500 # Cycle when the warmup percentage was hit. 3769797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014181 # Average occupied blocks per requestor 3779797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313386 # Average percentage of cache occupancy 3789797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::total 0.313386 # Average percentage of cache occupancy 3799797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12956 # number of ReadReq hits 3809797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_hits::total 12956 # number of ReadReq hits 3819797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12956 # number of demand (read+write) hits 3829797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::total 12956 # number of demand (read+write) hits 3839797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12956 # number of overall hits 3849797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::total 12956 # number of overall hits 3859797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8822 # number of ReadReq misses 3869797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_misses::total 8822 # number of ReadReq misses 3879797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8822 # number of demand (read+write) misses 3889797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_misses::total 8822 # number of demand (read+write) misses 3899797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8822 # number of overall misses 3909797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_misses::total 8822 # number of overall misses 3919797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21778 # number of ReadReq accesses(hits+misses) 3929797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_accesses::total 21778 # number of ReadReq accesses(hits+misses) 3939797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21778 # number of demand (read+write) accesses 3949797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_accesses::total 21778 # number of demand (read+write) accesses 3959797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21778 # number of overall (read+write) accesses 3969797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_accesses::total 21778 # number of overall (read+write) accesses 3979797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.405088 # miss rate for ReadReq accesses 3989797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.405088 # miss rate for ReadReq accesses 3999797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.405088 # miss rate for demand accesses 4009797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::total 0.405088 # miss rate for demand accesses 4019797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.405088 # miss rate for overall accesses 4029797Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::total 0.405088 # miss rate for overall accesses 4038613SN/Asystem.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4048613SN/Asystem.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4058613SN/Asystem.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 4068613SN/Asystem.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 4078983Snate@binkert.orgsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4088983Snate@binkert.orgsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4098613SN/Asystem.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 4108613SN/Asystem.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 4119625Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.writebacks::writebacks 2413 # number of writebacks 4129625Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.writebacks::total 2413 # number of writebacks 4138613SN/Asystem.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 4149797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1622027 # number of replacements 4159797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.999424 # Cycle average of tags in use 4169797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 20170040 # Total number of references to valid blocks. 4179797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1622539 # Sample count of references to valid blocks. 4189797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 12.431159 # Average number of references to valid blocks. 4199797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 4209797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.999424 # Average occupied blocks per requestor 4219797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 4229797Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 4239797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 12074025 # number of ReadReq hits 4249797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 12074025 # number of ReadReq hits 4259797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 8093747 # number of WriteReq hits 4269797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 8093747 # number of WriteReq hits 4279797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 20167772 # number of demand (read+write) hits 4289797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 20167772 # number of demand (read+write) hits 4299797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 20167772 # number of overall hits 4309797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 20167772 # number of overall hits 4319797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1308420 # number of ReadReq misses 4329797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1308420 # number of ReadReq misses 4339797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 316403 # number of WriteReq misses 4349797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 316403 # number of WriteReq misses 4359797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1624823 # number of demand (read+write) misses 4369797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 1624823 # number of demand (read+write) misses 4379797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1624823 # number of overall misses 4389797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 1624823 # number of overall misses 4399797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 13382445 # number of ReadReq accesses(hits+misses) 4409797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 13382445 # number of ReadReq accesses(hits+misses) 4419797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 8410150 # number of WriteReq accesses(hits+misses) 4429797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 8410150 # number of WriteReq accesses(hits+misses) 4439797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 21792595 # number of demand (read+write) accesses 4449797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 21792595 # number of demand (read+write) accesses 4459797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 21792595 # number of overall (read+write) accesses 4469797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 21792595 # number of overall (read+write) accesses 4479797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097771 # miss rate for ReadReq accesses 4489797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.097771 # miss rate for ReadReq accesses 4499672Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037622 # miss rate for WriteReq accesses 4509672Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.037622 # miss rate for WriteReq accesses 4519797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.074558 # miss rate for demand accesses 4529797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.074558 # miss rate for demand accesses 4539797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.074558 # miss rate for overall accesses 4549797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.074558 # miss rate for overall accesses 4558613SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4568613SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4578613SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4588613SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4598983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4608983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4618613SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4628613SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4639797Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 1535756 # number of writebacks 4649797Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 1535756 # number of writebacks 4658613SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4669797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 54622987 # Throughput (bytes/s) 4679797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 279212819 # Total data (bytes) 4689797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 25472 # Total snoop data (bytes) 4699797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 105931 # number of replacements 4709797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 64819.947299 # Cycle average of tags in use 4719797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 3456551 # Total number of references to valid blocks. 4729797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 170059 # Sample count of references to valid blocks. 4739797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 20.325599 # Average number of references to valid blocks. 4749797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4759797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 51906.795355 # Average occupied blocks per requestor 4769797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.004959 # Average occupied blocks per requestor 4779797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132237 # Average occupied blocks per requestor 4789797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.582004 # Average occupied blocks per requestor 4799797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 10422.432745 # Average occupied blocks per requestor 4809797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.792035 # Average percentage of cache occupancy 4819797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 4829797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 4839797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.038003 # Average percentage of cache occupancy 4849797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.159034 # Average percentage of cache occupancy 4859797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.989074 # Average percentage of cache occupancy 4869797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6502 # number of ReadReq hits 4879625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2802 # number of ReadReq hits 4889797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 777703 # number of ReadReq hits 4899797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 1275544 # number of ReadReq hits 4909797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 2062551 # number of ReadReq hits 4919797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 1538695 # number of Writeback hits 4929797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 1538695 # number of Writeback hits 4939625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::cpu.data 20 # number of UpgradeReq hits 4949625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_hits::total 20 # number of UpgradeReq hits 4959797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 179738 # number of ReadExReq hits 4969797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 179738 # number of ReadExReq hits 4979797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 6502 # number of demand (read+write) hits 4989625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.itb.walker 2802 # number of demand (read+write) hits 4999797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 777703 # number of demand (read+write) hits 5009797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1455282 # number of demand (read+write) hits 5019797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2242289 # number of demand (read+write) hits 5029797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 6502 # number of overall hits 5039625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.itb.walker 2802 # number of overall hits 5049797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 777703 # number of overall hits 5059797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1455282 # number of overall hits 5069797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2242289 # number of overall hits 5079289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 5089289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 5099625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.inst 13325 # number of ReadReq misses 5109672Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.data 32246 # number of ReadReq misses 5119672Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::total 45578 # number of ReadReq misses 5129625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1803 # number of UpgradeReq misses 5139625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_misses::total 1803 # number of UpgradeReq misses 5149797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 134392 # number of ReadExReq misses 5159797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 134392 # number of ReadExReq misses 5169289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 5179289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 5189625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.inst 13325 # number of demand (read+write) misses 5199797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 166638 # number of demand (read+write) misses 5209797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 179970 # number of demand (read+write) misses 5219289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 5229289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 5239625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.inst 13325 # number of overall misses 5249797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 166638 # number of overall misses 5259797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 179970 # number of overall misses 5269797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6504 # number of ReadReq accesses(hits+misses) 5279625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2807 # number of ReadReq accesses(hits+misses) 5289797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 791028 # number of ReadReq accesses(hits+misses) 5299797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1307790 # number of ReadReq accesses(hits+misses) 5309797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2108129 # number of ReadReq accesses(hits+misses) 5319797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 1538695 # number of Writeback accesses(hits+misses) 5329797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 1538695 # number of Writeback accesses(hits+misses) 5339625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses) 5349625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses) 5359797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 314130 # number of ReadExReq accesses(hits+misses) 5369797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 314130 # number of ReadExReq accesses(hits+misses) 5379797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 6504 # number of demand (read+write) accesses 5389625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.itb.walker 2807 # number of demand (read+write) accesses 5399797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 791028 # number of demand (read+write) accesses 5409797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1621920 # number of demand (read+write) accesses 5419797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2422259 # number of demand (read+write) accesses 5429797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 6504 # number of overall (read+write) accesses 5439625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.itb.walker 2807 # number of overall (read+write) accesses 5449797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 791028 # number of overall (read+write) accesses 5459797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1621920 # number of overall (read+write) accesses 5469797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2422259 # number of overall (read+write) accesses 5479625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000308 # miss rate for ReadReq accesses 5489625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001781 # miss rate for ReadReq accesses 5499797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016845 # miss rate for ReadReq accesses 5509797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024657 # miss rate for ReadReq accesses 5519625Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::total 0.021620 # miss rate for ReadReq accesses 5529625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989029 # miss rate for UpgradeReq accesses 5539625Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.989029 # miss rate for UpgradeReq accesses 5549797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.427823 # miss rate for ReadExReq accesses 5559797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.427823 # miss rate for ReadExReq accesses 5569625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000308 # miss rate for demand accesses 5579625Snilay@cs.wisc.edusystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001781 # miss rate for demand accesses 5589797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.016845 # miss rate for demand accesses 5599797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.102741 # miss rate for demand accesses 5609797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.074298 # miss rate for demand accesses 5619625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000308 # miss rate for overall accesses 5629625Snilay@cs.wisc.edusystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001781 # miss rate for overall accesses 5639797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.016845 # miss rate for overall accesses 5649797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.102741 # miss rate for overall accesses 5659797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.074298 # miss rate for overall accesses 5669289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5679289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5689289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5699289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5709289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5719289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5729289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5739289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 5749797Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 98091 # number of writebacks 5759797Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 98091 # number of writebacks 5769289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 5777927SN/A 5787927SN/A---------- End Simulation Statistics ---------- 579