stats.txt revision 9568
17927SN/A 27927SN/A---------- Begin Simulation Statistics ---------- 39289Sandreas.hansson@arm.comsim_seconds 5.112041 # Number of seconds simulated 49474Snilay@cs.wisc.edusim_ticks 5112040970500 # Number of ticks simulated 59474Snilay@cs.wisc.edufinal_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67927SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79568Sandreas.hansson@arm.comhost_inst_rate 1074050 # Simulator instruction rate (inst/s) 89568Sandreas.hansson@arm.comhost_op_rate 2199194 # Simulator op (including micro ops) rate (op/s) 99568Sandreas.hansson@arm.comhost_tick_rate 27479001055 # Simulator tick rate (ticks/s) 109568Sandreas.hansson@arm.comhost_mem_usage 583620 # Number of bytes of host memory used 119568Sandreas.hansson@arm.comhost_seconds 186.03 # Real time elapsed on the host 129474Snilay@cs.wisc.edusim_insts 199810242 # Number of instructions simulated 139490Sandreas.hansson@arm.comsim_ops 409125913 # Number of ops (including micro ops) simulated 149289Sandreas.hansson@arm.comsystem.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory 159079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory 169079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 179079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory 189289Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory 199289Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 13919040 # Number of bytes read from this memory 209079SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory 219079SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory 229289Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory 239289Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 9292608 # Number of bytes written to this memory 249289Sandreas.hansson@arm.comsystem.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory 259079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory 269079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 279079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory 289289Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory 299289Sandreas.hansson@arm.comsystem.physmem.num_reads::total 217485 # Number of read requests responded to by this memory 309289Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory 319289Sandreas.hansson@arm.comsystem.physmem.num_writes::total 145197 # Number of write requests responded to by this memory 329289Sandreas.hansson@arm.comsystem.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s) 339079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s) 349079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 359079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s) 369289Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s) 379289Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s) 389079SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s) 399079SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s) 409289Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s) 419289Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s) 429289Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s) 439289Sandreas.hansson@arm.comsystem.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s) 449079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s) 459079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 469079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s) 479289Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s) 489289Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s) 499312Sandreas.hansson@arm.comsystem.physmem.readReqs 0 # Total number of read requests seen 509312Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Total number of write requests seen 519312Sandreas.hansson@arm.comsystem.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady 529312Sandreas.hansson@arm.comsystem.physmem.bytesRead 0 # Total number of bytes read from memory 539312Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to memory 549312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 559312Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 569312Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 579312Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 589312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 599312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 609312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 619312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 629312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 639312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 649312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 659312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 669312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 679312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 689312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 699312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 709312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 719312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 729312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 739312Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 749312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 759312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 769312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 779312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 789312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 799312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 809312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 819312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 829312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 839312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 849312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 859312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 869312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 879312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 889312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 899312Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 909312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 919312Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 929312Sandreas.hansson@arm.comsystem.physmem.totGap 0 # Total gap between requests 939312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 949312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 959312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 969312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 979312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 989312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 999312Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 0 # Categorize read packet sizes 1009568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 1019568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 1029568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 1039568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 1049568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 1059568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 1069568Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Categorize write packet sizes 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1589312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1599312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1609312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1619312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1629312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1639312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1649312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1659312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1669312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1679312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1689312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1699312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1709312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 1719312Sandreas.hansson@arm.comsystem.physmem.totQLat 0 # Total cycles spent in queuing delays 1729312Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 0 # Sum of mem lat for all requests 1739312Sandreas.hansson@arm.comsystem.physmem.totBusLat 0 # Total cycles spent in databus access 1749312Sandreas.hansson@arm.comsystem.physmem.totBankLat 0 # Total cycles spent in bank access 1759312Sandreas.hansson@arm.comsystem.physmem.avgQLat nan # Average queueing delay per request 1769312Sandreas.hansson@arm.comsystem.physmem.avgBankLat nan # Average bank access latency per request 1779312Sandreas.hansson@arm.comsystem.physmem.avgBusLat nan # Average bus latency per request 1789312Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat nan # Average memory access latency 1799312Sandreas.hansson@arm.comsystem.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 1809312Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 1819312Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 1829312Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 1839490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 1849312Sandreas.hansson@arm.comsystem.physmem.busUtil 0.00 # Data bus utilization in percentage 1859312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.00 # Average read queue length over time 1869312Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length over time 1879312Sandreas.hansson@arm.comsystem.physmem.readRowHits 0 # Number of row buffer hits during reads 1889312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 1899312Sandreas.hansson@arm.comsystem.physmem.readRowHitRate nan # Row buffer hit rate for reads 1909312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 1919312Sandreas.hansson@arm.comsystem.physmem.avgGap nan # Average gap between requests 1929289Sandreas.hansson@arm.comsystem.iocache.replacements 47569 # number of replacements 1939289Sandreas.hansson@arm.comsystem.iocache.tagsinuse 0.042402 # Cycle average of tags in use 1948613SN/Asystem.iocache.total_refs 0 # Total number of references to valid blocks. 1959289Sandreas.hansson@arm.comsystem.iocache.sampled_refs 47585 # Sample count of references to valid blocks. 1968613SN/Asystem.iocache.avg_refs 0 # Average number of references to valid blocks. 1979474Snilay@cs.wisc.edusystem.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit. 1989289Sandreas.hansson@arm.comsystem.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor 1999289Sandreas.hansson@arm.comsystem.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy 2009289Sandreas.hansson@arm.comsystem.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy 2019289Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses 2029289Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 904 # number of ReadReq misses 2038835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 2048613SN/Asystem.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 2059289Sandreas.hansson@arm.comsystem.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses 2069289Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 47624 # number of demand (read+write) misses 2079289Sandreas.hansson@arm.comsystem.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses 2089289Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 47624 # number of overall misses 2099289Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) 2109289Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) 2118835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 2128613SN/Asystem.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 2139289Sandreas.hansson@arm.comsystem.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses 2149289Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses 2159289Sandreas.hansson@arm.comsystem.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses 2169289Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses 2178835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 2189055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2198835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 2209055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2218835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 2229055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2238835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 2249055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2258613SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2268613SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2278613SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 2288613SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 2298983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2308983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2318613SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 2328613SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 2338835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 46667 # number of writebacks 2348835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 46667 # number of writebacks 2358613SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2368613SN/Asystem.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2378613SN/Asystem.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 2389289Sandreas.hansson@arm.comsystem.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 2398613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 2408613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 2418613SN/Asystem.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 2428613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2438613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2448613SN/Asystem.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2458613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 2468613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 2478613SN/Asystem.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 2489474Snilay@cs.wisc.edusystem.cpu.numCycles 10224081964 # number of cpu cycles simulated 2498613SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2508613SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 2519474Snilay@cs.wisc.edusystem.cpu.committedInsts 199810242 # Number of instructions committed 2529490Sandreas.hansson@arm.comsystem.cpu.committedOps 409125913 # Number of ops (including micro ops) committed 2539490Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses 2548613SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 2558613SN/Asystem.cpu.num_func_calls 0 # number of times a function call or return occured 2569490Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls 2579490Sandreas.hansson@arm.comsystem.cpu.num_int_insts 374289904 # number of integer instructions 2588613SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 2599490Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 915450656 # number of times the integer registers were read 2609490Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 480322719 # number of times the integer registers were written 2618613SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 2628613SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 2639474Snilay@cs.wisc.edusystem.cpu.num_mem_refs 35624590 # number of memory refs 2649289Sandreas.hansson@arm.comsystem.cpu.num_load_insts 27216588 # Number of load instructions 2659474Snilay@cs.wisc.edusystem.cpu.num_store_insts 8408002 # Number of store instructions 2669490Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles 2679490Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles 2689289Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles 2699289Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.955647 # Percentage of idle cycles 2708613SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 2718613SN/Asystem.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 2729289Sandreas.hansson@arm.comsystem.cpu.icache.replacements 790732 # number of replacements 2739474Snilay@cs.wisc.edusystem.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use 2749474Snilay@cs.wisc.edusystem.cpu.icache.total_refs 243360727 # Total number of references to valid blocks. 2759289Sandreas.hansson@arm.comsystem.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks. 2769474Snilay@cs.wisc.edusystem.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks. 2779474Snilay@cs.wisc.edusystem.cpu.icache.warmup_cycle 148763114500 # Cycle when the warmup percentage was hit. 2789474Snilay@cs.wisc.edusystem.cpu.icache.occ_blocks::cpu.inst 510.627675 # Average occupied blocks per requestor 2798835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::cpu.inst 0.997320 # Average percentage of cache occupancy 2808835SAli.Saidi@ARM.comsystem.cpu.icache.occ_percent::total 0.997320 # Average percentage of cache occupancy 2819474Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::cpu.inst 243360727 # number of ReadReq hits 2829474Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::total 243360727 # number of ReadReq hits 2839474Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::cpu.inst 243360727 # number of demand (read+write) hits 2849474Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::total 243360727 # number of demand (read+write) hits 2859474Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::cpu.inst 243360727 # number of overall hits 2869474Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::total 243360727 # number of overall hits 2879289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 791251 # number of ReadReq misses 2889289Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 791251 # number of ReadReq misses 2899289Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 791251 # number of demand (read+write) misses 2909289Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 791251 # number of demand (read+write) misses 2919289Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 791251 # number of overall misses 2929289Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 791251 # number of overall misses 2939474Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 244151978 # number of ReadReq accesses(hits+misses) 2949474Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::total 244151978 # number of ReadReq accesses(hits+misses) 2959474Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::cpu.inst 244151978 # number of demand (read+write) accesses 2969474Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::total 244151978 # number of demand (read+write) accesses 2979474Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::cpu.inst 244151978 # number of overall (read+write) accesses 2989474Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::total 244151978 # number of overall (read+write) accesses 2998835SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003241 # miss rate for ReadReq accesses 3009055Ssaidi@eecs.umich.edusystem.cpu.icache.ReadReq_miss_rate::total 0.003241 # miss rate for ReadReq accesses 3018835SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.003241 # miss rate for demand accesses 3029055Ssaidi@eecs.umich.edusystem.cpu.icache.demand_miss_rate::total 0.003241 # miss rate for demand accesses 3038835SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.003241 # miss rate for overall accesses 3049055Ssaidi@eecs.umich.edusystem.cpu.icache.overall_miss_rate::total 0.003241 # miss rate for overall accesses 3058613SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3068613SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3078613SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3088613SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3098983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3108983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3118613SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3128613SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3138613SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3149079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.replacements 3335 # number of replacements 3159289Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tagsinuse 3.026483 # Cycle average of tags in use 3169079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.total_refs 8029 # Total number of references to valid blocks. 3179079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.sampled_refs 3346 # Sample count of references to valid blocks. 3189079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.avg_refs 2.399582 # Average number of references to valid blocks. 3199490Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.warmup_cycle 5102019607500 # Cycle when the warmup percentage was hit. 3209289Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 3.026483 # Average occupied blocks per requestor 3219289Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.189155 # Average percentage of cache occupancy 3229289Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.occ_percent::total 0.189155 # Average percentage of cache occupancy 3239079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 8031 # number of ReadReq hits 3249079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.ReadReq_hits::total 8031 # number of ReadReq hits 3258835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 3268613SN/Asystem.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 3279079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 8033 # number of demand (read+write) hits 3289079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.demand_hits::total 8033 # number of demand (read+write) hits 3299079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 8033 # number of overall hits 3309079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.overall_hits::total 8033 # number of overall hits 3319079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4194 # number of ReadReq misses 3329079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.ReadReq_misses::total 4194 # number of ReadReq misses 3339079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4194 # number of demand (read+write) misses 3349079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.demand_misses::total 4194 # number of demand (read+write) misses 3359079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4194 # number of overall misses 3369079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.overall_misses::total 4194 # number of overall misses 3378835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12225 # number of ReadReq accesses(hits+misses) 3388673SN/Asystem.cpu.itb_walker_cache.ReadReq_accesses::total 12225 # number of ReadReq accesses(hits+misses) 3398835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 3408613SN/Asystem.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 3418835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12227 # number of demand (read+write) accesses 3428673SN/Asystem.cpu.itb_walker_cache.demand_accesses::total 12227 # number of demand (read+write) accesses 3438835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12227 # number of overall (read+write) accesses 3448673SN/Asystem.cpu.itb_walker_cache.overall_accesses::total 12227 # number of overall (read+write) accesses 3459079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.343067 # miss rate for ReadReq accesses 3469079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.343067 # miss rate for ReadReq accesses 3479079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.343011 # miss rate for demand accesses 3489079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.demand_miss_rate::total 0.343011 # miss rate for demand accesses 3499079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.343011 # miss rate for overall accesses 3509079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.overall_miss_rate::total 0.343011 # miss rate for overall accesses 3518613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3528613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3538613SN/Asystem.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 3548613SN/Asystem.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 3558983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3568983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3578613SN/Asystem.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 3588613SN/Asystem.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 3599079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.writebacks::writebacks 593 # number of writebacks 3609079SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.writebacks::total 593 # number of writebacks 3618613SN/Asystem.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 3629289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.replacements 7597 # number of replacements 3639289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tagsinuse 5.013746 # Cycle average of tags in use 3649289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.total_refs 13015 # Total number of references to valid blocks. 3659289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.sampled_refs 7611 # Sample count of references to valid blocks. 3669289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.avg_refs 1.710025 # Average number of references to valid blocks. 3679490Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.warmup_cycle 5101206385500 # Cycle when the warmup percentage was hit. 3689289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.013746 # Average occupied blocks per requestor 3699289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313359 # Average percentage of cache occupancy 3709289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.occ_percent::total 0.313359 # Average percentage of cache occupancy 3719289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13017 # number of ReadReq hits 3729289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_hits::total 13017 # number of ReadReq hits 3739289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13017 # number of demand (read+write) hits 3749289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::total 13017 # number of demand (read+write) hits 3759289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13017 # number of overall hits 3769289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::total 13017 # number of overall hits 3779289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8791 # number of ReadReq misses 3789289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_misses::total 8791 # number of ReadReq misses 3799289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8791 # number of demand (read+write) misses 3809289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_misses::total 8791 # number of demand (read+write) misses 3819289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8791 # number of overall misses 3829289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_misses::total 8791 # number of overall misses 3838835SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses) 3848673SN/Asystem.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses) 3858835SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses 3868673SN/Asystem.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses 3878835SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses 3888673SN/Asystem.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses 3899289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.403109 # miss rate for ReadReq accesses 3909289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.403109 # miss rate for ReadReq accesses 3919289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.403109 # miss rate for demand accesses 3929289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::total 0.403109 # miss rate for demand accesses 3939289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.403109 # miss rate for overall accesses 3949289Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::total 0.403109 # miss rate for overall accesses 3958613SN/Asystem.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3968613SN/Asystem.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3978613SN/Asystem.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 3988613SN/Asystem.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 3998983Snate@binkert.orgsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4008983Snate@binkert.orgsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4018613SN/Asystem.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 4028613SN/Asystem.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 4039079SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.writebacks::writebacks 2556 # number of writebacks 4049079SAli.Saidi@ARM.comsystem.cpu.dtb_walker_cache.writebacks::total 2556 # number of writebacks 4058613SN/Asystem.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 4069289Sandreas.hansson@arm.comsystem.cpu.dcache.replacements 1621135 # number of replacements 4079079SAli.Saidi@ARM.comsystem.cpu.dcache.tagsinuse 511.999456 # Cycle average of tags in use 4089474Snilay@cs.wisc.edusystem.cpu.dcache.total_refs 20140431 # Total number of references to valid blocks. 4099289Sandreas.hansson@arm.comsystem.cpu.dcache.sampled_refs 1621647 # Sample count of references to valid blocks. 4109474Snilay@cs.wisc.edusystem.cpu.dcache.avg_refs 12.419738 # Average number of references to valid blocks. 4118613SN/Asystem.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 4129079SAli.Saidi@ARM.comsystem.cpu.dcache.occ_blocks::cpu.data 511.999456 # Average occupied blocks per requestor 4138835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 4148835SAli.Saidi@ARM.comsystem.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy 4159289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 12055941 # number of ReadReq hits 4169289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 12055941 # number of ReadReq hits 4179474Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 8082228 # number of WriteReq hits 4189474Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 8082228 # number of WriteReq hits 4199474Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 20138169 # number of demand (read+write) hits 4209474Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 20138169 # number of demand (read+write) hits 4219474Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 20138169 # number of overall hits 4229474Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 20138169 # number of overall hits 4239289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1308091 # number of ReadReq misses 4249289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1308091 # number of ReadReq misses 4259289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 315828 # number of WriteReq misses 4269289Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 315828 # number of WriteReq misses 4279289Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1623919 # number of demand (read+write) misses 4289289Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 1623919 # number of demand (read+write) misses 4299289Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1623919 # number of overall misses 4309289Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 1623919 # number of overall misses 4319289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 13364032 # number of ReadReq accesses(hits+misses) 4329289Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 13364032 # number of ReadReq accesses(hits+misses) 4339474Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 8398056 # number of WriteReq accesses(hits+misses) 4349474Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 8398056 # number of WriteReq accesses(hits+misses) 4359474Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 21762088 # number of demand (read+write) accesses 4369474Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 21762088 # number of demand (read+write) accesses 4379474Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 21762088 # number of overall (read+write) accesses 4389474Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 21762088 # number of overall (read+write) accesses 4398835SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses 4409055Ssaidi@eecs.umich.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.097881 # miss rate for ReadReq accesses 4418835SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses 4429055Ssaidi@eecs.umich.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.037607 # miss rate for WriteReq accesses 4438835SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses 4449055Ssaidi@eecs.umich.edusystem.cpu.dcache.demand_miss_rate::total 0.074621 # miss rate for demand accesses 4458835SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses 4469055Ssaidi@eecs.umich.edusystem.cpu.dcache.overall_miss_rate::total 0.074621 # miss rate for overall accesses 4478613SN/Asystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4488613SN/Asystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4498613SN/Asystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4508613SN/Asystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 4518983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4528983Snate@binkert.orgsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4538613SN/Asystem.cpu.dcache.fast_writes 0 # number of fast writes performed 4548613SN/Asystem.cpu.dcache.cache_copies 0 # number of cache copies performed 4559289Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 1534848 # number of writebacks 4569289Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 1534848 # number of writebacks 4578613SN/Asystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4589289Sandreas.hansson@arm.comsystem.cpu.l2cache.replacements 106558 # number of replacements 4599490Sandreas.hansson@arm.comsystem.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use 4609289Sandreas.hansson@arm.comsystem.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks. 4619289Sandreas.hansson@arm.comsystem.cpu.l2cache.sampled_refs 170677 # Sample count of references to valid blocks. 4629289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_refs 20.250086 # Average number of references to valid blocks. 4639289Sandreas.hansson@arm.comsystem.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 4649474Snilay@cs.wisc.edusystem.cpu.l2cache.occ_blocks::writebacks 51981.453118 # Average occupied blocks per requestor 4659289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor 4669289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.itb.walker 0.132114 # Average occupied blocks per requestor 4679490Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.inst 2434.994083 # Average occupied blocks per requestor 4689490Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_blocks::cpu.data 10405.564952 # Average occupied blocks per requestor 4699289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::writebacks 0.793174 # Average percentage of cache occupancy 4709289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 4719289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 4729289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.inst 0.037155 # Average percentage of cache occupancy 4739289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::cpu.data 0.158776 # Average percentage of cache occupancy 4749289Sandreas.hansson@arm.comsystem.cpu.l2cache.occ_percent::total 0.989108 # Average percentage of cache occupancy 4759289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6578 # number of ReadReq hits 4769289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2700 # number of ReadReq hits 4779289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 777896 # number of ReadReq hits 4789289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 1275281 # number of ReadReq hits 4799289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 2062455 # number of ReadReq hits 4809289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 1537997 # number of Writeback hits 4819289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 1537997 # number of Writeback hits 4829289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 4839289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 4849289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 179183 # number of ReadExReq hits 4859289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 179183 # number of ReadExReq hits 4869289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 6578 # number of demand (read+write) hits 4879289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 2700 # number of demand (read+write) hits 4889289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 777896 # number of demand (read+write) hits 4899289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1454464 # number of demand (read+write) hits 4909289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2241638 # number of demand (read+write) hits 4919289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 6578 # number of overall hits 4929289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 2700 # number of overall hits 4939289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 777896 # number of overall hits 4949289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1454464 # number of overall hits 4959289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2241638 # number of overall hits 4969289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 2 # number of ReadReq misses 4979289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 4989289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 13342 # number of ReadReq misses 4999289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 32182 # number of ReadReq misses 5009289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 45531 # number of ReadReq misses 5019289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1796 # number of UpgradeReq misses 5029289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 1796 # number of UpgradeReq misses 5039289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 134378 # number of ReadExReq misses 5049289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 134378 # number of ReadExReq misses 5059289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 2 # number of demand (read+write) misses 5069289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 5079289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 13342 # number of demand (read+write) misses 5089289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 166560 # number of demand (read+write) misses 5099289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 179909 # number of demand (read+write) misses 5109289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 2 # number of overall misses 5119289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 5129289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 13342 # number of overall misses 5139289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 166560 # number of overall misses 5149289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 179909 # number of overall misses 5159289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6580 # number of ReadReq accesses(hits+misses) 5169289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2705 # number of ReadReq accesses(hits+misses) 5179289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 791238 # number of ReadReq accesses(hits+misses) 5189289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1307463 # number of ReadReq accesses(hits+misses) 5199289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2107986 # number of ReadReq accesses(hits+misses) 5209289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 1537997 # number of Writeback accesses(hits+misses) 5219289Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 1537997 # number of Writeback accesses(hits+misses) 5229289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) 5239289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) 5249289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 313561 # number of ReadExReq accesses(hits+misses) 5259289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 313561 # number of ReadExReq accesses(hits+misses) 5269289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 6580 # number of demand (read+write) accesses 5279289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 2705 # number of demand (read+write) accesses 5289289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 791238 # number of demand (read+write) accesses 5299289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1621024 # number of demand (read+write) accesses 5309289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2421547 # number of demand (read+write) accesses 5319289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 6580 # number of overall (read+write) accesses 5329289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 2705 # number of overall (read+write) accesses 5339289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 791238 # number of overall (read+write) accesses 5349289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1621024 # number of overall (read+write) accesses 5359289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2421547 # number of overall (read+write) accesses 5369289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000304 # miss rate for ReadReq accesses 5379289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001848 # miss rate for ReadReq accesses 5389289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016862 # miss rate for ReadReq accesses 5399289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024614 # miss rate for ReadReq accesses 5409289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses 5419289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.984649 # miss rate for UpgradeReq accesses 5429289Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.984649 # miss rate for UpgradeReq accesses 5439289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428555 # miss rate for ReadExReq accesses 5449289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.428555 # miss rate for ReadExReq accesses 5459289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000304 # miss rate for demand accesses 5469289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001848 # miss rate for demand accesses 5479289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.016862 # miss rate for demand accesses 5489289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.102750 # miss rate for demand accesses 5499289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.074295 # miss rate for demand accesses 5509289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000304 # miss rate for overall accesses 5519289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001848 # miss rate for overall accesses 5529289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.016862 # miss rate for overall accesses 5539289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.102750 # miss rate for overall accesses 5549289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.074295 # miss rate for overall accesses 5559289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5569289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5579289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5589289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5599289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5609289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5619289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5629289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 5639289Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 98530 # number of writebacks 5649289Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 98530 # number of writebacks 5659289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 5667927SN/A 5677927SN/A---------- End Simulation Statistics ---------- 568