stats.txt revision 11201
17927SN/A 27927SN/A---------- Begin Simulation Statistics ---------- 310639Sgabeblack@google.comsim_seconds 5.112152 # Number of seconds simulated 410645Snilay@cs.wisc.edusim_ticks 5112152301500 # Number of ticks simulated 510645Snilay@cs.wisc.edufinal_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67927SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711201Sandreas.hansson@arm.comhost_inst_rate 1265336 # Simulator instruction rate (inst/s) 811201Sandreas.hansson@arm.comhost_op_rate 2590419 # Simulator op (including micro ops) rate (op/s) 911201Sandreas.hansson@arm.comhost_tick_rate 32332152611 # Simulator tick rate (ticks/s) 1011201Sandreas.hansson@arm.comhost_mem_usage 659496 # Number of bytes of host memory used 1111201Sandreas.hansson@arm.comhost_seconds 158.11 # Real time elapsed on the host 1210645Snilay@cs.wisc.edusim_insts 200066731 # Number of instructions simulated 1310645Snilay@cs.wisc.edusim_ops 409580371 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 179079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 1811201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 846912 # Number of bytes read from this memory 1911201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 10615104 # Number of bytes read from this memory 2010540Sgabeblack@google.comsystem.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11490752 # Number of bytes read from this memory 2211201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 846912 # Number of instructions bytes read from this memory 2311201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 846912 # Number of instructions bytes read from this memory 2411201Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 9270016 # Number of bytes written to this memory 2511201Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 9270016 # Number of bytes written to this memory 269901Sandreas@sandberg.pp.sesystem.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 279079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 2811201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 13233 # Number of read requests responded to by this memory 2911201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 165861 # Number of read requests responded to by this memory 3010540Sgabeblack@google.comsystem.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 3111201Sandreas.hansson@arm.comsystem.physmem.num_reads::total 179543 # Number of read requests responded to by this memory 3211201Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 144844 # Number of write requests responded to by this memory 3311201Sandreas.hansson@arm.comsystem.physmem.num_writes::total 144844 # Number of write requests responded to by this memory 349901Sandreas@sandberg.pp.sesystem.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 359079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 3611201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 165666 # Total read bandwidth from this memory (bytes/s) 3711201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 2076445 # Total read bandwidth from this memory (bytes/s) 3810540Sgabeblack@google.comsystem.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) 3911201Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2247733 # Total read bandwidth from this memory (bytes/s) 4011201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 165666 # Instruction read bandwidth from this memory (bytes/s) 4111201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 165666 # Instruction read bandwidth from this memory (bytes/s) 4211201Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1813329 # Write bandwidth from this memory (bytes/s) 4311201Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1813329 # Write bandwidth from this memory (bytes/s) 4411201Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1813329 # Total bandwidth to/from this memory (bytes/s) 459901Sandreas@sandberg.pp.sesystem.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 469079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 4711201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 165666 # Total bandwidth to/from this memory (bytes/s) 4811201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 2076445 # Total bandwidth to/from this memory (bytes/s) 4910585Sandreas.hansson@arm.comsystem.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s) 5011201Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4061062 # Total bandwidth to/from this memory (bytes/s) 5110036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 5210036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 5310645Snilay@cs.wisc.edusystem.cpu.numCycles 10224308568 # number of cpu cycles simulated 548613SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 558613SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 5611201Sandreas.hansson@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 5711201Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 5810645Snilay@cs.wisc.edusystem.cpu.committedInsts 200066731 # Number of instructions committed 5910645Snilay@cs.wisc.edusystem.cpu.committedOps 409580371 # Number of ops (including micro ops) committed 6010645Snilay@cs.wisc.edusystem.cpu.num_int_alu_accesses 374583495 # Number of integer alu accesses 6110645Snilay@cs.wisc.edusystem.cpu.num_fp_alu_accesses 48 # Number of float alu accesses 6210645Snilay@cs.wisc.edusystem.cpu.num_func_calls 2308877 # number of times a function call or return occured 6310645Snilay@cs.wisc.edusystem.cpu.num_conditional_control_insts 40001070 # number of instructions that are conditional controls 6410645Snilay@cs.wisc.edusystem.cpu.num_int_insts 374583495 # number of integer instructions 6510645Snilay@cs.wisc.edusystem.cpu.num_fp_insts 48 # number of float instructions 6610645Snilay@cs.wisc.edusystem.cpu.num_int_register_reads 682689563 # number of times the integer registers were read 6710645Snilay@cs.wisc.edusystem.cpu.num_int_register_writes 323557658 # number of times the integer registers were written 6810645Snilay@cs.wisc.edusystem.cpu.num_fp_register_reads 48 # number of times the floating registers were read 698613SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 7010645Snilay@cs.wisc.edusystem.cpu.num_cc_register_reads 233837318 # number of times the CC registers were read 7110645Snilay@cs.wisc.edusystem.cpu.num_cc_register_writes 157316420 # number of times the CC registers were written 7210645Snilay@cs.wisc.edusystem.cpu.num_mem_refs 35667022 # number of memory refs 7310645Snilay@cs.wisc.edusystem.cpu.num_load_insts 27243255 # Number of load instructions 7410645Snilay@cs.wisc.edusystem.cpu.num_store_insts 8423767 # Number of store instructions 7510645Snilay@cs.wisc.edusystem.cpu.num_idle_cycles 9770324721.656570 # Number of idle cycles 7610645Snilay@cs.wisc.edusystem.cpu.num_busy_cycles 453983846.343430 # Number of busy cycles 7710639Sgabeblack@google.comsystem.cpu.not_idle_fraction 0.044402 # Percentage of non-idle cycles 7810639Sgabeblack@google.comsystem.cpu.idle_fraction 0.955598 # Percentage of idle cycles 7910645Snilay@cs.wisc.edusystem.cpu.Branches 43152159 # Number of branches fetched 8010645Snilay@cs.wisc.edusystem.cpu.op_class::No_OpClass 172754 0.04% 0.04% # Class of executed instruction 8110645Snilay@cs.wisc.edusystem.cpu.op_class::IntAlu 373476545 91.18% 91.23% # Class of executed instruction 8210639Sgabeblack@google.comsystem.cpu.op_class::IntMult 144577 0.04% 91.26% # Class of executed instruction 8310645Snilay@cs.wisc.edusystem.cpu.op_class::IntDiv 123078 0.03% 91.29% # Class of executed instruction 8410220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction 8510220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction 8610645Snilay@cs.wisc.edusystem.cpu.op_class::FloatCvt 16 0.00% 91.29% # Class of executed instruction 8710220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction 8810220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction 8910220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction 9010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction 9110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction 9210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 91.29% # Class of executed instruction 9310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 91.29% # Class of executed instruction 9410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 91.29% # Class of executed instruction 9510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 91.29% # Class of executed instruction 9610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 91.29% # Class of executed instruction 9710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 91.29% # Class of executed instruction 9810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 91.29% # Class of executed instruction 9910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 91.29% # Class of executed instruction 10010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 91.29% # Class of executed instruction 10110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 91.29% # Class of executed instruction 10210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction 10310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction 10410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction 10510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction 10610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction 10710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction 10810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction 10910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction 11010645Snilay@cs.wisc.edusystem.cpu.op_class::MemRead 27240665 6.65% 97.94% # Class of executed instruction 11110645Snilay@cs.wisc.edusystem.cpu.op_class::MemWrite 8423767 2.06% 100.00% # Class of executed instruction 11210220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 11310220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 11410645Snilay@cs.wisc.edusystem.cpu.op_class::total 409581402 # Class of executed instruction 11510645Snilay@cs.wisc.edusystem.cpu.dcache.tags.replacements 1621902 # number of replacements 11610639Sgabeblack@google.comsystem.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use 11710645Snilay@cs.wisc.edusystem.cpu.dcache.tags.total_refs 20181182 # Total number of references to valid blocks. 11810645Snilay@cs.wisc.edusystem.cpu.dcache.tags.sampled_refs 1622414 # Sample count of references to valid blocks. 11910645Snilay@cs.wisc.edusystem.cpu.dcache.tags.avg_refs 12.438984 # Average number of references to valid blocks. 12010540Sgabeblack@google.comsystem.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 12110639Sgabeblack@google.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor 12210540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 12310540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 12410540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 12510639Sgabeblack@google.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id 12610639Sgabeblack@google.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id 12710540Sgabeblack@google.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 12810540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 12910645Snilay@cs.wisc.edusystem.cpu.dcache.tags.tag_accesses 88836888 # Number of tag accesses 13010645Snilay@cs.wisc.edusystem.cpu.dcache.tags.data_accesses 88836888 # Number of data accesses 13110645Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::cpu.data 12023339 # number of ReadReq hits 13210645Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_hits::total 12023339 # number of ReadReq hits 13310645Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::cpu.data 8096662 # number of WriteReq hits 13410645Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_hits::total 8096662 # number of WriteReq hits 13510645Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_hits::cpu.data 58900 # number of SoftPFReq hits 13610645Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_hits::total 58900 # number of SoftPFReq hits 13710645Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::cpu.data 20120001 # number of demand (read+write) hits 13810645Snilay@cs.wisc.edusystem.cpu.dcache.demand_hits::total 20120001 # number of demand (read+write) hits 13910645Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::cpu.data 20178901 # number of overall hits 14010645Snilay@cs.wisc.edusystem.cpu.dcache.overall_hits::total 20178901 # number of overall hits 14110645Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::cpu.data 905249 # number of ReadReq misses 14210645Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_misses::total 905249 # number of ReadReq misses 14310645Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::cpu.data 316707 # number of WriteReq misses 14410645Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_misses::total 316707 # number of WriteReq misses 14510645Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_misses::cpu.data 402757 # number of SoftPFReq misses 14610645Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_misses::total 402757 # number of SoftPFReq misses 14710645Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::cpu.data 1221956 # number of demand (read+write) misses 14810645Snilay@cs.wisc.edusystem.cpu.dcache.demand_misses::total 1221956 # number of demand (read+write) misses 14910645Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::cpu.data 1624713 # number of overall misses 15010645Snilay@cs.wisc.edusystem.cpu.dcache.overall_misses::total 1624713 # number of overall misses 15110645Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::cpu.data 12928588 # number of ReadReq accesses(hits+misses) 15210645Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_accesses::total 12928588 # number of ReadReq accesses(hits+misses) 15310645Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::cpu.data 8413369 # number of WriteReq accesses(hits+misses) 15410645Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_accesses::total 8413369 # number of WriteReq accesses(hits+misses) 15510639Sgabeblack@google.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 461657 # number of SoftPFReq accesses(hits+misses) 15610639Sgabeblack@google.comsystem.cpu.dcache.SoftPFReq_accesses::total 461657 # number of SoftPFReq accesses(hits+misses) 15710645Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::cpu.data 21341957 # number of demand (read+write) accesses 15810645Snilay@cs.wisc.edusystem.cpu.dcache.demand_accesses::total 21341957 # number of demand (read+write) accesses 15910645Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::cpu.data 21803614 # number of overall (read+write) accesses 16010645Snilay@cs.wisc.edusystem.cpu.dcache.overall_accesses::total 21803614 # number of overall (read+write) accesses 16110645Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070019 # miss rate for ReadReq accesses 16210645Snilay@cs.wisc.edusystem.cpu.dcache.ReadReq_miss_rate::total 0.070019 # miss rate for ReadReq accesses 16310645Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037643 # miss rate for WriteReq accesses 16410645Snilay@cs.wisc.edusystem.cpu.dcache.WriteReq_miss_rate::total 0.037643 # miss rate for WriteReq accesses 16510645Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872416 # miss rate for SoftPFReq accesses 16610645Snilay@cs.wisc.edusystem.cpu.dcache.SoftPFReq_miss_rate::total 0.872416 # miss rate for SoftPFReq accesses 16710645Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::cpu.data 0.057256 # miss rate for demand accesses 16810645Snilay@cs.wisc.edusystem.cpu.dcache.demand_miss_rate::total 0.057256 # miss rate for demand accesses 16910645Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::cpu.data 0.074516 # miss rate for overall accesses 17010645Snilay@cs.wisc.edusystem.cpu.dcache.overall_miss_rate::total 0.074516 # miss rate for overall accesses 17110540Sgabeblack@google.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 17210540Sgabeblack@google.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 17310540Sgabeblack@google.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 17410540Sgabeblack@google.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 17510540Sgabeblack@google.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 17610540Sgabeblack@google.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 17710540Sgabeblack@google.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 17810540Sgabeblack@google.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 17910892Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 1535779 # number of writebacks 18010892Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 1535779 # number of writebacks 18110540Sgabeblack@google.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 18210645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements 18310645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.tagsinuse 5.013997 # Cycle average of tags in use 18410645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.total_refs 12940 # Total number of references to valid blocks. 18510645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.sampled_refs 7763 # Sample count of references to valid blocks. 18610645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.avg_refs 1.666881 # Average number of references to valid blocks. 18710645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.warmup_cycle 5100454141000 # Cycle when the warmup percentage was hit. 18810645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013997 # Average occupied blocks per requestor 18910645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313375 # Average percentage of cache occupancy 19010645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.occ_percent::total 0.313375 # Average percentage of cache occupancy 19110540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id 19210639Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 19310540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 19410639Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 19510540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id 19610645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.tag_accesses 52753 # Number of tag accesses 19710645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.data_accesses 52753 # Number of data accesses 19810645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12941 # number of ReadReq hits 19910645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.ReadReq_hits::total 12941 # number of ReadReq hits 20010645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12941 # number of demand (read+write) hits 20110645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.demand_hits::total 12941 # number of demand (read+write) hits 20210645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12941 # number of overall hits 20310645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.overall_hits::total 12941 # number of overall hits 20410645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8957 # number of ReadReq misses 20510645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.ReadReq_misses::total 8957 # number of ReadReq misses 20610645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8957 # number of demand (read+write) misses 20710645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.demand_misses::total 8957 # number of demand (read+write) misses 20810645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8957 # number of overall misses 20910645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.overall_misses::total 8957 # number of overall misses 21010645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21898 # number of ReadReq accesses(hits+misses) 21110645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.ReadReq_accesses::total 21898 # number of ReadReq accesses(hits+misses) 21210645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21898 # number of demand (read+write) accesses 21310645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.demand_accesses::total 21898 # number of demand (read+write) accesses 21410645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21898 # number of overall (read+write) accesses 21510645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.overall_accesses::total 21898 # number of overall (read+write) accesses 21610645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409033 # miss rate for ReadReq accesses 21710645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409033 # miss rate for ReadReq accesses 21810645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409033 # miss rate for demand accesses 21910645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.demand_miss_rate::total 0.409033 # miss rate for demand accesses 22010645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409033 # miss rate for overall accesses 22110645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.overall_miss_rate::total 0.409033 # miss rate for overall accesses 22210540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 22310540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 22410540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 22510540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 22610540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 22710540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 22810540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 22910540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 23010645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.writebacks::writebacks 2453 # number of writebacks 23110645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.writebacks::total 2453 # number of writebacks 23210540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 23310645Snilay@cs.wisc.edusystem.cpu.icache.tags.replacements 792216 # number of replacements 23410645Snilay@cs.wisc.edusystem.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use 23510645Snilay@cs.wisc.edusystem.cpu.icache.tags.total_refs 243675150 # Total number of references to valid blocks. 23610645Snilay@cs.wisc.edusystem.cpu.icache.tags.sampled_refs 792728 # Sample count of references to valid blocks. 23710645Snilay@cs.wisc.edusystem.cpu.icache.tags.avg_refs 307.388095 # Average number of references to valid blocks. 23810645Snilay@cs.wisc.edusystem.cpu.icache.tags.warmup_cycle 148913118500 # Cycle when the warmup percentage was hit. 23910645Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_blocks::cpu.inst 510.662956 # Average occupied blocks per requestor 24010451Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy 24110451Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy 24210036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 24310639Sgabeblack@google.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id 24410639Sgabeblack@google.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id 24510639Sgabeblack@google.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id 24610639Sgabeblack@google.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 24710036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 24810645Snilay@cs.wisc.edusystem.cpu.icache.tags.tag_accesses 245260620 # Number of tag accesses 24910645Snilay@cs.wisc.edusystem.cpu.icache.tags.data_accesses 245260620 # Number of data accesses 25010645Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::cpu.inst 243675150 # number of ReadReq hits 25110645Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_hits::total 243675150 # number of ReadReq hits 25210645Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::cpu.inst 243675150 # number of demand (read+write) hits 25310645Snilay@cs.wisc.edusystem.cpu.icache.demand_hits::total 243675150 # number of demand (read+write) hits 25410645Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::cpu.inst 243675150 # number of overall hits 25510645Snilay@cs.wisc.edusystem.cpu.icache.overall_hits::total 243675150 # number of overall hits 25610645Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::cpu.inst 792735 # number of ReadReq misses 25710645Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_misses::total 792735 # number of ReadReq misses 25810645Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::cpu.inst 792735 # number of demand (read+write) misses 25910645Snilay@cs.wisc.edusystem.cpu.icache.demand_misses::total 792735 # number of demand (read+write) misses 26010645Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::cpu.inst 792735 # number of overall misses 26110645Snilay@cs.wisc.edusystem.cpu.icache.overall_misses::total 792735 # number of overall misses 26210645Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::cpu.inst 244467885 # number of ReadReq accesses(hits+misses) 26310645Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_accesses::total 244467885 # number of ReadReq accesses(hits+misses) 26410645Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::cpu.inst 244467885 # number of demand (read+write) accesses 26510645Snilay@cs.wisc.edusystem.cpu.icache.demand_accesses::total 244467885 # number of demand (read+write) accesses 26610645Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::cpu.inst 244467885 # number of overall (read+write) accesses 26710645Snilay@cs.wisc.edusystem.cpu.icache.overall_accesses::total 244467885 # number of overall (read+write) accesses 26810639Sgabeblack@google.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses 26910639Sgabeblack@google.comsystem.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses 27010639Sgabeblack@google.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses 27110639Sgabeblack@google.comsystem.cpu.icache.demand_miss_rate::total 0.003243 # miss rate for demand accesses 27210639Sgabeblack@google.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses 27310639Sgabeblack@google.comsystem.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses 2748613SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2758613SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2768613SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2778613SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 2788983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2798983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2808613SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 2818613SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 28211201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 792216 # number of writebacks 28311201Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 792216 # number of writebacks 2848613SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 28510639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements 28610639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.tagsinuse 3.026546 # Cycle average of tags in use 28710639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks. 28810639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks. 28910639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks. 29010645Snilay@cs.wisc.edusystem.cpu.itb_walker_cache.tags.warmup_cycle 5102144896000 # Cycle when the warmup percentage was hit. 29110639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026546 # Average occupied blocks per requestor 29210639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189159 # Average percentage of cache occupancy 29310639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.occ_percent::total 0.189159 # Average percentage of cache occupancy 29410639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id 29510639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 29610639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 29710409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 29810639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id 29910639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.tag_accesses 28899 # Number of tag accesses 30010639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.data_accesses 28899 # Number of data accesses 30110639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7765 # number of ReadReq hits 30210639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_hits::total 7765 # number of ReadReq hits 3038835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 3048613SN/Asystem.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 30510639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7767 # number of demand (read+write) hits 30610639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_hits::total 7767 # number of demand (read+write) hits 30710639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7767 # number of overall hits 30810639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_hits::total 7767 # number of overall hits 30910639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4455 # number of ReadReq misses 31010639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_misses::total 4455 # number of ReadReq misses 31110639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4455 # number of demand (read+write) misses 31210639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_misses::total 4455 # number of demand (read+write) misses 31310639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4455 # number of overall misses 31410639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_misses::total 4455 # number of overall misses 31510409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses) 31610409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses) 3178835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 3188613SN/Asystem.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 31910409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses 32010409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses 32110409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses 32210409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses 32310639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.364566 # miss rate for ReadReq accesses 32410639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.364566 # miss rate for ReadReq accesses 32510639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.364507 # miss rate for demand accesses 32610639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_miss_rate::total 0.364507 # miss rate for demand accesses 32710639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.364507 # miss rate for overall accesses 32810639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_miss_rate::total 0.364507 # miss rate for overall accesses 3298613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3308613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3318613SN/Asystem.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 3328613SN/Asystem.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 3338983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3348983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3358613SN/Asystem.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 3368613SN/Asystem.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 33710639Sgabeblack@google.comsystem.cpu.itb_walker_cache.writebacks::writebacks 545 # number of writebacks 33810639Sgabeblack@google.comsystem.cpu.itb_walker_cache.writebacks::total 545 # number of writebacks 3398613SN/Asystem.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 34011201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 106204 # number of replacements 34111201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 64823.931309 # Cycle average of tags in use 34211201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 4340224 # Total number of references to valid blocks. 34311201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks. 34411201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 25.506423 # Average number of references to valid blocks. 3459838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 34611201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 51928.965552 # Average occupied blocks per requestor 34710639Sgabeblack@google.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor 34810892Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135113 # Average occupied blocks per requestor 34911201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.314401 # Average occupied blocks per requestor 35011201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 10436.513764 # Average occupied blocks per requestor 35111201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.792373 # Average percentage of cache occupancy 3529797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 3539797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 35411201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.037511 # Average percentage of cache occupancy 35511201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.159249 # Average percentage of cache occupancy 35610639Sgabeblack@google.comsystem.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy 35710639Sgabeblack@google.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 63958 # Occupied blocks per task id 35810639Sgabeblack@google.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 35910639Sgabeblack@google.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id 36010639Sgabeblack@google.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3349 # Occupied blocks per task id 36110639Sgabeblack@google.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 20908 # Occupied blocks per task id 36210639Sgabeblack@google.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 39411 # Occupied blocks per task id 36310639Sgabeblack@google.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.975922 # Percentage of cache occupancy per task id 36411201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 39255979 # Number of tag accesses 36511201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 39255979 # Number of data accesses 36611201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 1538777 # number of WritebackDirty hits 36711201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 1538777 # number of WritebackDirty hits 36811201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 792205 # number of WritebackClean hits 36911201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 792205 # number of WritebackClean hits 37010827Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits 37110827Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits 37211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 179774 # number of ReadExReq hits 37311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 179774 # number of ReadExReq hits 37411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779488 # number of ReadCleanReq hits 37511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 779488 # number of ReadCleanReq hits 37610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6656 # number of ReadSharedReq hits 37710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2896 # number of ReadSharedReq hits 37811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275198 # number of ReadSharedReq hits 37911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 1284750 # number of ReadSharedReq hits 38010645Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits 38110639Sgabeblack@google.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 2896 # number of demand (read+write) hits 38211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 779488 # number of demand (read+write) hits 38311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1454972 # number of demand (read+write) hits 38411201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2244012 # number of demand (read+write) hits 38510645Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.dtb.walker 6656 # number of overall hits 38610639Sgabeblack@google.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 2896 # number of overall hits 38711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 779488 # number of overall hits 38811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1454972 # number of overall hits 38911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2244012 # number of overall hits 39010827Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1808 # number of UpgradeReq misses 39110827Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 1808 # number of UpgradeReq misses 39211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 134647 # number of ReadExReq misses 39311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 134647 # number of ReadExReq misses 39411201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13234 # number of ReadCleanReq misses 39511201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 13234 # number of ReadCleanReq misses 39610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses 39710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses 39811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 32164 # number of ReadSharedReq misses 39911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 32170 # number of ReadSharedReq misses 4009901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 4019289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 40211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 13234 # number of demand (read+write) misses 40311201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 166811 # number of demand (read+write) misses 40411201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 180051 # number of demand (read+write) misses 4059901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 4069289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 40711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 13234 # number of overall misses 40811201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 166811 # number of overall misses 40911201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 180051 # number of overall misses 41011201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 1538777 # number of WritebackDirty accesses(hits+misses) 41111201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 1538777 # number of WritebackDirty accesses(hits+misses) 41211201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 792205 # number of WritebackClean accesses(hits+misses) 41311201Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 792205 # number of WritebackClean accesses(hits+misses) 41410639Sgabeblack@google.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 1829 # number of UpgradeReq accesses(hits+misses) 41510639Sgabeblack@google.comsystem.cpu.l2cache.UpgradeReq_accesses::total 1829 # number of UpgradeReq accesses(hits+misses) 41610645Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::cpu.data 314421 # number of ReadExReq accesses(hits+misses) 41710645Snilay@cs.wisc.edusystem.cpu.l2cache.ReadExReq_accesses::total 314421 # number of ReadExReq accesses(hits+misses) 41810892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 792722 # number of ReadCleanReq accesses(hits+misses) 41910892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 792722 # number of ReadCleanReq accesses(hits+misses) 42010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6657 # number of ReadSharedReq accesses(hits+misses) 42110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2901 # number of ReadSharedReq accesses(hits+misses) 42210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307362 # number of ReadSharedReq accesses(hits+misses) 42310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1316920 # number of ReadSharedReq accesses(hits+misses) 42410645Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 6657 # number of demand (read+write) accesses 42510639Sgabeblack@google.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 2901 # number of demand (read+write) accesses 42610645Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.inst 792722 # number of demand (read+write) accesses 42710645Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.data 1621783 # number of demand (read+write) accesses 42810645Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::total 2424063 # number of demand (read+write) accesses 42910645Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 6657 # number of overall (read+write) accesses 43010639Sgabeblack@google.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 2901 # number of overall (read+write) accesses 43110645Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.inst 792722 # number of overall (read+write) accesses 43210645Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.data 1621783 # number of overall (read+write) accesses 43310645Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::total 2424063 # number of overall (read+write) accesses 43410827Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988518 # miss rate for UpgradeReq accesses 43510827Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.988518 # miss rate for UpgradeReq accesses 43611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428238 # miss rate for ReadExReq accesses 43711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.428238 # miss rate for ReadExReq accesses 43811201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016694 # miss rate for ReadCleanReq accesses 43911201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016694 # miss rate for ReadCleanReq accesses 44010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000150 # miss rate for ReadSharedReq accesses 44110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001724 # miss rate for ReadSharedReq accesses 44211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024602 # miss rate for ReadSharedReq accesses 44311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024428 # miss rate for ReadSharedReq accesses 44410639Sgabeblack@google.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses 44510639Sgabeblack@google.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001724 # miss rate for demand accesses 44611201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.016694 # miss rate for demand accesses 44711201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.102857 # miss rate for demand accesses 44811201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.074277 # miss rate for demand accesses 44910639Sgabeblack@google.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000150 # miss rate for overall accesses 45010639Sgabeblack@google.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001724 # miss rate for overall accesses 45111201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.016694 # miss rate for overall accesses 45211201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.102857 # miss rate for overall accesses 45311201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.074277 # miss rate for overall accesses 4549289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4559289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4569289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 4579289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 4589289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4599289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4609289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 4619289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 46211201Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 98177 # number of writebacks 46311201Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 98177 # number of writebacks 4649289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 46511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 4856313 # Total number of requests made to the snoop filter. 46611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2425286 # Number of requests hitting in the snoop filter with a single holder of the requested data. 46711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 46811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter. 46911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 47011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 47110892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution 47210645Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadResp 15971490 # Transaction distribution 47310639Sgabeblack@google.comsystem.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution 47410639Sgabeblack@google.comsystem.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution 47511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 1538777 # Transaction distribution 47611201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 792205 # Transaction distribution 47711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 88200 # Transaction distribution 47810639Sgabeblack@google.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2281 # Transaction distribution 47910639Sgabeblack@google.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2281 # Transaction distribution 48010645Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExReq 314426 # Transaction distribution 48110645Snilay@cs.wisc.edusystem.cpu.toL2Bus.trans_dist::ReadExResp 314426 # Transaction distribution 48210892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 792735 # Transaction distribution 48310892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1321418 # Transaction distribution 48411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2377675 # Packet count per connected master and slave (bytes) 48511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613331 # Packet count per connected master and slave (bytes) 48611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 10293 # Packet count per connected master and slave (bytes) 48711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 22163 # Packet count per connected master and slave (bytes) 48811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 35023462 # Packet count per connected master and slave (bytes) 48911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101436160 # Cumulative packet size per connected master and slave (bytes) 49010892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227550265 # Cumulative packet size per connected master and slave (bytes) 49110639Sgabeblack@google.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes) 49210645Snilay@cs.wisc.edusystem.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes) 49311201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 330036665 # Cumulative packet size per connected master and slave (bytes) 49411201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 203470 # Total snoops (count) 49511201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 18930684 # Request fanout histogram 49611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram 49711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram 49810540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 49911201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 18911125 99.90% 99.90% # Request fanout histogram 50011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram 50111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram 50211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram 50311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 50410540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 50511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 50611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 50711201Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 18930684 # Request fanout histogram 50810639Sgabeblack@google.comsystem.iobus.trans_dist::ReadReq 10012057 # Transaction distribution 50910639Sgabeblack@google.comsystem.iobus.trans_dist::ReadResp 10012057 # Transaction distribution 51010639Sgabeblack@google.comsystem.iobus.trans_dist::WriteReq 57724 # Transaction distribution 51110892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 57724 # Transaction distribution 51210540Sgabeblack@google.comsystem.iobus.trans_dist::MessageReq 1696 # Transaction distribution 51310540Sgabeblack@google.comsystem.iobus.trans_dist::MessageResp 1696 # Transaction distribution 51410540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 51510540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 51610540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 51710540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 51810540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 51910540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 52010540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 52110540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 52210540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes) 52310540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) 52410549Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 52510540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 52610639Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27940 # Packet count per connected master and slave (bytes) 52710540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 52810540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 52910540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 53010540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 53110540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 53210639Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::total 20044316 # Packet count per connected master and slave (bytes) 53310639Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes) 53410639Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes) 53510540Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes) 53610540Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes) 53710639Sgabeblack@google.comsystem.iobus.pkt_count::total 20142954 # Packet count per connected master and slave (bytes) 53810540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 53910540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 54010540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 54110540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 54210540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 54310540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 54410540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 54510540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 54610540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes) 54710540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) 54810549Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 54910540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 55010639Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13970 # Cumulative packet size per connected master and slave (bytes) 55110540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 55210540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 55310540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 55410540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 55510540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 55610639Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::total 10028276 # Cumulative packet size per connected master and slave (bytes) 55710639Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes) 55810639Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes) 55910540Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) 56010540Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) 56110639Sgabeblack@google.comsystem.iobus.pkt_size::total 13062828 # Cumulative packet size per connected master and slave (bytes) 56210639Sgabeblack@google.comsystem.iocache.tags.replacements 47568 # number of replacements 56310639Sgabeblack@google.comsystem.iocache.tags.tagsinuse 0.042441 # Cycle average of tags in use 56410540Sgabeblack@google.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 56510639Sgabeblack@google.comsystem.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks. 56610540Sgabeblack@google.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 56710645Snilay@cs.wisc.edusystem.iocache.tags.warmup_cycle 4994875253009 # Cycle when the warmup percentage was hit. 56810639Sgabeblack@google.comsystem.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor 56910540Sgabeblack@google.comsystem.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 57010540Sgabeblack@google.comsystem.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 57110540Sgabeblack@google.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 57210540Sgabeblack@google.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 57310540Sgabeblack@google.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 57410639Sgabeblack@google.comsystem.iocache.tags.tag_accesses 428607 # Number of tag accesses 57510639Sgabeblack@google.comsystem.iocache.tags.data_accesses 428607 # Number of data accesses 57610639Sgabeblack@google.comsystem.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses 57710639Sgabeblack@google.comsystem.iocache.ReadReq_misses::total 903 # number of ReadReq misses 57810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 57910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses 58010639Sgabeblack@google.comsystem.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses 58110639Sgabeblack@google.comsystem.iocache.demand_misses::total 903 # number of demand (read+write) misses 58210639Sgabeblack@google.comsystem.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses 58310639Sgabeblack@google.comsystem.iocache.overall_misses::total 903 # number of overall misses 58410639Sgabeblack@google.comsystem.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) 58510639Sgabeblack@google.comsystem.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) 58610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 58710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) 58810639Sgabeblack@google.comsystem.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses 58910639Sgabeblack@google.comsystem.iocache.demand_accesses::total 903 # number of demand (read+write) accesses 59010639Sgabeblack@google.comsystem.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses 59110639Sgabeblack@google.comsystem.iocache.overall_accesses::total 903 # number of overall (read+write) accesses 59210540Sgabeblack@google.comsystem.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 59310540Sgabeblack@google.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 59410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 59510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 59610540Sgabeblack@google.comsystem.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 59710540Sgabeblack@google.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 59810540Sgabeblack@google.comsystem.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 59910540Sgabeblack@google.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 60010540Sgabeblack@google.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 60110540Sgabeblack@google.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 60210540Sgabeblack@google.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 60310540Sgabeblack@google.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 60410540Sgabeblack@google.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 60510540Sgabeblack@google.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 60610585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 60710540Sgabeblack@google.comsystem.iocache.cache_copies 0 # number of cache copies performed 60810585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 46667 # number of writebacks 60910585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 46667 # number of writebacks 61010540Sgabeblack@google.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 61110892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 13857337 # Transaction distribution 61211201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 13903644 # Transaction distribution 61310639Sgabeblack@google.comsystem.membus.trans_dist::WriteReq 13943 # Transaction distribution 61410639Sgabeblack@google.comsystem.membus.trans_dist::WriteResp 13943 # Transaction distribution 61511201Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 144844 # Transaction distribution 61611201Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 8271 # Transaction distribution 61711201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 2561 # Transaction distribution 61811201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 2109 # Transaction distribution 61911201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 134351 # Transaction distribution 62011201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 134346 # Transaction distribution 62111201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 46307 # Transaction distribution 62210540Sgabeblack@google.comsystem.membus.trans_dist::MessageReq 1696 # Transaction distribution 62310540Sgabeblack@google.comsystem.membus.trans_dist::MessageResp 1696 # Transaction distribution 62410892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 46720 # Transaction distribution 62510892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 46720 # Transaction distribution 62610540Sgabeblack@google.comsystem.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) 62710540Sgabeblack@google.comsystem.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) 62810639Sgabeblack@google.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes) 62910540Sgabeblack@google.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) 63011201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 470253 # Packet count per connected master and slave (bytes) 63111201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 28212813 # Packet count per connected master and slave (bytes) 63211138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142283 # Packet count per connected master and slave (bytes) 63311138Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 142283 # Packet count per connected master and slave (bytes) 63411201Sandreas.hansson@arm.comsystem.membus.pkt_count::total 28358488 # Packet count per connected master and slave (bytes) 63510540Sgabeblack@google.comsystem.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) 63610540Sgabeblack@google.comsystem.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) 63710639Sgabeblack@google.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes) 63810540Sgabeblack@google.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) 63911201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787328 # Cumulative packet size per connected master and slave (bytes) 64011201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 43212089 # Cumulative packet size per connected master and slave (bytes) 64110892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 # Cumulative packet size per connected master and slave (bytes) 64210892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes) 64311201Sandreas.hansson@arm.comsystem.membus.pkt_size::total 46263353 # Cumulative packet size per connected master and slave (bytes) 64410540Sgabeblack@google.comsystem.membus.snoops 0 # Total snoops (count) 64511201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 14256561 # Request fanout histogram 64610827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1.000119 # Request fanout histogram 64710892Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.010906 # Request fanout histogram 64810540Sgabeblack@google.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 64910540Sgabeblack@google.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 65011201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 14254865 99.99% 99.99% # Request fanout histogram 65110827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram 65210540Sgabeblack@google.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 65310540Sgabeblack@google.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 65410827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 2 # Request fanout histogram 65511201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 14256561 # Request fanout histogram 65610540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 65710540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 65810540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 65910540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 66010540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 66110540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 66210540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 66310540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 66410540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 66510540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 66610540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 66710540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 6687927SN/A 6697927SN/A---------- End Simulation Statistics ---------- 670