xref: /gem5/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  5.112152                       # Number of seconds simulated
sim_ticks                                5112152301500                       # Number of ticks simulated
final_tick                               5112152301500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1219492                       # Simulator instruction rate (inst/s)
host_op_rate                                  2496566                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            31160731508                       # Simulator tick rate (ticks/s)
host_mem_usage                                 598628                       # Number of bytes of host memory used
host_seconds                                   164.06                       # Real time elapsed on the host
sim_insts                                   200066731                       # Number of instructions simulated
sim_ops                                     409580371                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker           64                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker          320                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst            854656                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          10616192                       # Number of bytes read from this memory
system.physmem.bytes_read::pc.south_bridge.ide        28352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11499584                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       854656                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          854656                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      9265728                       # Number of bytes written to this memory
system.physmem.bytes_written::total           9265728                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker            1                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker            5                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst              13354                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             165878                       # Number of read requests responded to by this memory
system.physmem.num_reads::pc.south_bridge.ide          443                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                179681                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          144777                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               144777                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker             13                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker             63                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               167181                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              2076658                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::pc.south_bridge.ide         5546                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 2249460                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          167181                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             167181                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1812491                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1812491                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1812491                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker            13                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker            63                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              167181                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             2076658                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::pc.south_bridge.ide         5546                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                4061951                       # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.apic_clk_domain.clock                 8000                       # Clock period in ticks
system.cpu.numCycles                      10224308568                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   200066731                       # Number of instructions committed
system.cpu.committedOps                     409580371                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             374583495                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
system.cpu.num_func_calls                     2308877                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts     40001070                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    374583495                       # number of integer instructions
system.cpu.num_fp_insts                            48                       # number of float instructions
system.cpu.num_int_register_reads           682689563                       # number of times the integer registers were read
system.cpu.num_int_register_writes          323557658                       # number of times the integer registers were written
system.cpu.num_fp_register_reads                   48                       # number of times the floating registers were read
system.cpu.num_fp_register_writes                   0                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            233837318                       # number of times the CC registers were read
system.cpu.num_cc_register_writes           157316420                       # number of times the CC registers were written
system.cpu.num_mem_refs                      35667022                       # number of memory refs
system.cpu.num_load_insts                    27243255                       # Number of load instructions
system.cpu.num_store_insts                    8423767                       # Number of store instructions
system.cpu.num_idle_cycles               9770324721.656570                       # Number of idle cycles
system.cpu.num_busy_cycles               453983846.343430                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.044402                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.955598                       # Percentage of idle cycles
system.cpu.Branches                          43152159                       # Number of branches fetched
system.cpu.op_class::No_OpClass                172754      0.04%      0.04% # Class of executed instruction
system.cpu.op_class::IntAlu                 373476545     91.18%     91.23% # Class of executed instruction
system.cpu.op_class::IntMult                   144577      0.04%     91.26% # Class of executed instruction
system.cpu.op_class::IntDiv                    123078      0.03%     91.29% # Class of executed instruction
system.cpu.op_class::FloatAdd                       0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::FloatCmp                       0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::FloatCvt                      16      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     91.29% # Class of executed instruction
system.cpu.op_class::MemRead                 27240665      6.65%     97.94% # Class of executed instruction
system.cpu.op_class::MemWrite                 8423767      2.06%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                  409581402                       # Class of executed instruction
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
system.cpu.dcache.tags.replacements           1621902                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.999425                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            20181182                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           1622414                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             12.438984                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle           7549500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.999425                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999999                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999999                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0          282                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          202                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           28                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          88836888                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         88836888                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     12023339                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        12023339                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data      8096662                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total        8096662                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data        58900                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total         58900                       # number of SoftPFReq hits
system.cpu.dcache.demand_hits::cpu.data      20120001                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         20120001                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     20178901                       # number of overall hits
system.cpu.dcache.overall_hits::total        20178901                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       905249                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        905249                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       316707                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       316707                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data       402757                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total       402757                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data      1221956                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        1221956                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      1624713                       # number of overall misses
system.cpu.dcache.overall_misses::total       1624713                       # number of overall misses
system.cpu.dcache.ReadReq_accesses::cpu.data     12928588                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     12928588                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data      8413369                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total      8413369                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data       461657                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total       461657                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     21341957                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     21341957                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     21803614                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     21803614                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.070019                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.070019                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037643                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.037643                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.872416                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.872416                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.057256                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.057256                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.074516                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.074516                       # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      1535783                       # number of writebacks
system.cpu.dcache.writebacks::total           1535783                       # number of writebacks
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements         7749                       # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse     5.013997                       # Cycle average of tags in use
system.cpu.dtb_walker_cache.tags.total_refs        12940                       # Total number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.sampled_refs         7763                       # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.tags.avg_refs     1.666881                       # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.tags.warmup_cycle 5100454141000                       # Cycle when the warmup percentage was hit.
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker     5.013997                       # Average occupied blocks per requestor
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker     0.313375                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_percent::total     0.313375                       # Average percentage of cache occupancy
system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024           14                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0            5                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1            5                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024     0.875000                       # Percentage of cache occupancy per task id
system.cpu.dtb_walker_cache.tags.tag_accesses        52753                       # Number of tag accesses
system.cpu.dtb_walker_cache.tags.data_accesses        52753                       # Number of data accesses
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12941                       # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total        12941                       # number of ReadReq hits
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12941                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total        12941                       # number of demand (read+write) hits
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12941                       # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total        12941                       # number of overall hits
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8957                       # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total         8957                       # number of ReadReq misses
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8957                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total         8957                       # number of demand (read+write) misses
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8957                       # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total         8957                       # number of overall misses
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21898                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total        21898                       # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21898                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total        21898                       # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21898                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total        21898                       # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.409033                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total     0.409033                       # miss rate for ReadReq accesses
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.409033                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.demand_miss_rate::total     0.409033                       # miss rate for demand accesses
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.409033                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.overall_miss_rate::total     0.409033                       # miss rate for overall accesses
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.dtb_walker_cache.writebacks::writebacks         2453                       # number of writebacks
system.cpu.dtb_walker_cache.writebacks::total         2453                       # number of writebacks
system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements            792216                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.662956                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           243675150                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            792728                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs            307.388095                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle      148913118500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.662956                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997389                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997389                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           90                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          130                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          291                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         245260620                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        245260620                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    243675150                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       243675150                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     243675150                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        243675150                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    243675150                       # number of overall hits
system.cpu.icache.overall_hits::total       243675150                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst       792735                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        792735                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst       792735                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         792735                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst       792735                       # number of overall misses
system.cpu.icache.overall_misses::total        792735                       # number of overall misses
system.cpu.icache.ReadReq_accesses::cpu.inst    244467885                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    244467885                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    244467885                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    244467885                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    244467885                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    244467885                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003243                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.003243                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.003243                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.003243                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.003243                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.003243                       # miss rate for overall accesses
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.itb_walker_cache.tags.replacements         3586                       # number of replacements
system.cpu.itb_walker_cache.tags.tagsinuse     3.026546                       # Cycle average of tags in use
system.cpu.itb_walker_cache.tags.total_refs         7763                       # Total number of references to valid blocks.
system.cpu.itb_walker_cache.tags.sampled_refs         3597                       # Sample count of references to valid blocks.
system.cpu.itb_walker_cache.tags.avg_refs     2.158187                       # Average number of references to valid blocks.
system.cpu.itb_walker_cache.tags.warmup_cycle 5102144896000                       # Cycle when the warmup percentage was hit.
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker     3.026546                       # Average occupied blocks per requestor
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker     0.189159                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_percent::total     0.189159                       # Average percentage of cache occupancy
system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024           11                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0            6                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024     0.687500                       # Percentage of cache occupancy per task id
system.cpu.itb_walker_cache.tags.tag_accesses        28899                       # Number of tag accesses
system.cpu.itb_walker_cache.tags.data_accesses        28899                       # Number of data accesses
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7765                       # number of ReadReq hits
system.cpu.itb_walker_cache.ReadReq_hits::total         7765                       # number of ReadReq hits
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7767                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.demand_hits::total         7767                       # number of demand (read+write) hits
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7767                       # number of overall hits
system.cpu.itb_walker_cache.overall_hits::total         7767                       # number of overall hits
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4455                       # number of ReadReq misses
system.cpu.itb_walker_cache.ReadReq_misses::total         4455                       # number of ReadReq misses
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4455                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.demand_misses::total         4455                       # number of demand (read+write) misses
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4455                       # number of overall misses
system.cpu.itb_walker_cache.overall_misses::total         4455                       # number of overall misses
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12220                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.ReadReq_accesses::total        12220                       # number of ReadReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12222                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.demand_accesses::total        12222                       # number of demand (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12222                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total        12222                       # number of overall (read+write) accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.364566                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.ReadReq_miss_rate::total     0.364566                       # miss rate for ReadReq accesses
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.364507                       # miss rate for demand accesses
system.cpu.itb_walker_cache.demand_miss_rate::total     0.364507                       # miss rate for demand accesses
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.364507                       # miss rate for overall accesses
system.cpu.itb_walker_cache.overall_miss_rate::total     0.364507                       # miss rate for overall accesses
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_targets            0                       # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
system.cpu.itb_walker_cache.writebacks::writebacks          545                       # number of writebacks
system.cpu.itb_walker_cache.writebacks::total          545                       # number of writebacks
system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements           106219                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        64823.931305                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            3459867                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           170177                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            20.330991                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 51929.109466                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     0.002478                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.132289                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  2455.813677                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 10438.873394                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.792375                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000000                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000002                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.037473                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.159285                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.989135                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        63958                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           57                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          233                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3349                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3        20908                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        39411                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.975922                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         32212786                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        32212786                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         6656                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         2896                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst       779367                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data      1275199                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        2064118                       # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks      1538781                       # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total      1538781                       # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data           21                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total           21                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data       179771                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total       179771                       # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker         6656                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker         2896                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst       779367                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      1454970                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total         2243889                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker         6656                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker         2896                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst       779367                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      1454970                       # number of overall hits
system.cpu.l2cache.overall_hits::total        2243889                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker            1                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            5                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst        13355                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data        32163                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total        45524                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         1808                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         1808                       # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       134650                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       134650                       # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker            1                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker            5                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        13355                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       166813                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        180174                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker            1                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker            5                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        13355                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       166813                       # number of overall misses
system.cpu.l2cache.overall_misses::total       180174                       # number of overall misses
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker         6657                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         2901                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst       792722                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data      1307362                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      2109642                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks      1538781                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total      1538781                       # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data         1829                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total         1829                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data       314421                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total       314421                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker         6657                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker         2901                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst       792722                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      1621783                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total      2424063                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker         6657                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker         2901                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst       792722                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      1621783                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total      2424063                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.000150                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.001724                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.016847                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.024601                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.021579                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.988518                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.988518                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.428247                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.428247                       # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.000150                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.001724                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.016847                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.102858                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.074327                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.000150                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.001724                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.016847                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.102858                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.074327                       # miss rate for overall accesses
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks        98110                       # number of writebacks
system.cpu.l2cache.writebacks::total            98110                       # number of writebacks
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq       15971490                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      15971490                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         13943                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        13943                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback      1538781                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq         2281                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp         2281                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq       314426                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp       314426                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      1585470                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     32527769                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side         9455                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side        20367                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          34143061                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     50735040                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side    227550521                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       320000                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side       730240                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total          279335801                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       49698                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     17890240                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        3.002757                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.052432                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3           17840921     99.72%     99.72% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4              49319      0.28%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       17890240                       # Request fanout histogram
system.iobus.trans_dist::ReadReq             10012057                       # Transaction distribution
system.iobus.trans_dist::ReadResp            10012057                       # Transaction distribution
system.iobus.trans_dist::WriteReq               57724                       # Transaction distribution
system.iobus.trans_dist::WriteResp              11004                       # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.iobus.trans_dist::MessageReq              1696                       # Transaction distribution
system.iobus.trans_dist::MessageResp             1696                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio           44                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio            6                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio        11180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf          180                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio         1364                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio           86                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio           54                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio           30                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio     19999988                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio         1098                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio          170                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio            2                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio        27940                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio           12                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio         2128                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total     20044316                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side        95246                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total        95246                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         3392                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total         3392                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                20142954                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio           22                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio            3                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio         6738                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf          221                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio          682                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio           43                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio           27                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio           15                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio      9999994                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio         2196                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio           85                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio            1                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio        13970                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio            6                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio            5                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio         4256                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total     10028276                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side      3027768                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total      3027768                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave         6784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total         6784                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                 13062828                       # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements                47568                       # number of replacements
system.iocache.tags.tagsinuse                0.042441                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                47584                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         4994875253009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::pc.south_bridge.ide     0.042441                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::pc.south_bridge.ide     0.002653                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.002653                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::2           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               428607                       # Number of tag accesses
system.iocache.tags.data_accesses              428607                       # Number of data accesses
system.iocache.ReadReq_misses::pc.south_bridge.ide          903                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              903                       # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total        46720                       # number of WriteInvalidateReq misses
system.iocache.demand_misses::pc.south_bridge.ide          903                       # number of demand (read+write) misses
system.iocache.demand_misses::total               903                       # number of demand (read+write) misses
system.iocache.overall_misses::pc.south_bridge.ide          903                       # number of overall misses
system.iocache.overall_misses::total              903                       # number of overall misses
system.iocache.ReadReq_accesses::pc.south_bridge.ide          903                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            903                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total        46720                       # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::pc.south_bridge.ide          903                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total             903                       # number of demand (read+write) accesses
system.iocache.overall_accesses::pc.south_bridge.ide          903                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total            903                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks           46667                       # number of writebacks
system.iocache.writebacks::total                46667                       # number of writebacks
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq            13903764                       # Transaction distribution
system.membus.trans_dist::ReadResp           13903764                       # Transaction distribution
system.membus.trans_dist::WriteReq              13943                       # Transaction distribution
system.membus.trans_dist::WriteResp             13943                       # Transaction distribution
system.membus.trans_dist::Writeback            144777                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq        46720                       # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp        46720                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             2546                       # Transaction distribution
system.membus.trans_dist::UpgradeResp            2094                       # Transaction distribution
system.membus.trans_dist::ReadExReq            134369                       # Transaction distribution
system.membus.trans_dist::ReadExResp           134364                       # Transaction distribution
system.membus.trans_dist::MessageReq             1696                       # Transaction distribution
system.membus.trans_dist::MessageResp            1696                       # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave         3392                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.apicbridge.master::total         3392                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave     20044316                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio      7698244                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       462531                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total     28205091                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       141913                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       141913                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total               28350396                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave         6784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total         6784                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave     10028276                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio     15396485                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     17791872                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total     43216633                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      6034560                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      6034560                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                49257977                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples          14247815                       # Request fanout histogram
system.membus.snoop_fanout::mean             1.000119                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.010910                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                14246119     99.99%     99.99% # Request fanout histogram
system.membus.snoop_fanout::2                    1696      0.01%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               2                       # Request fanout histogram
system.membus.snoop_fanout::total            14247815                       # Request fanout histogram
system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs           32                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages          693                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes      2985984                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs          812                       # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_bytes            0                       # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_read_txs            0                       # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages            1                       # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes         4096                       # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs            1                       # Number of DMA write transactions.

---------- End Simulation Statistics   ----------