stats.txt revision 10585
17927SN/A 27927SN/A---------- Begin Simulation Statistics ---------- 310585Sandreas.hansson@arm.comsim_seconds 5.112156 # Number of seconds simulated 410585Sandreas.hansson@arm.comsim_ticks 5112155738500 # Number of ticks simulated 510585Sandreas.hansson@arm.comfinal_tick 5112155738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67927SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710585Sandreas.hansson@arm.comhost_inst_rate 1511003 # Simulator instruction rate (inst/s) 810585Sandreas.hansson@arm.comhost_op_rate 3093560 # Simulator op (including micro ops) rate (op/s) 910585Sandreas.hansson@arm.comhost_tick_rate 38615908446 # Simulator tick rate (ticks/s) 1010585Sandreas.hansson@arm.comhost_mem_usage 595640 # Number of bytes of host memory used 1110585Sandreas.hansson@arm.comhost_seconds 132.38 # Real time elapsed on the host 1210585Sandreas.hansson@arm.comsim_insts 200033669 # Number of instructions simulated 1310585Sandreas.hansson@arm.comsim_ops 409539941 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 179079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 1810585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 852224 # Number of bytes read from this memory 1910585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 10636736 # Number of bytes read from this memory 2010540Sgabeblack@google.comsystem.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 2110585Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11517696 # Number of bytes read from this memory 2210585Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 852224 # Number of instructions bytes read from this memory 2310585Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 852224 # Number of instructions bytes read from this memory 2410585Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 9281152 # Number of bytes written to this memory 2510585Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 9281152 # Number of bytes written to this memory 269901Sandreas@sandberg.pp.sesystem.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 279079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 2810585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 13316 # Number of read requests responded to by this memory 2910585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 166199 # Number of read requests responded to by this memory 3010540Sgabeblack@google.comsystem.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 3110585Sandreas.hansson@arm.comsystem.physmem.num_reads::total 179964 # Number of read requests responded to by this memory 3210585Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 145018 # Number of write requests responded to by this memory 3310585Sandreas.hansson@arm.comsystem.physmem.num_writes::total 145018 # Number of write requests responded to by this memory 349901Sandreas@sandberg.pp.sesystem.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 359079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 3610585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 166705 # Total read bandwidth from this memory (bytes/s) 3710585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 2080675 # Total read bandwidth from this memory (bytes/s) 3810540Sgabeblack@google.comsystem.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) 3910585Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2253002 # Total read bandwidth from this memory (bytes/s) 4010585Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 166705 # Instruction read bandwidth from this memory (bytes/s) 4110585Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 166705 # Instruction read bandwidth from this memory (bytes/s) 4210585Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1815507 # Write bandwidth from this memory (bytes/s) 4310585Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1815507 # Write bandwidth from this memory (bytes/s) 4410585Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1815507 # Total bandwidth to/from this memory (bytes/s) 459901Sandreas@sandberg.pp.sesystem.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 469079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 4710585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 166705 # Total bandwidth to/from this memory (bytes/s) 4810585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 2080675 # Total bandwidth to/from this memory (bytes/s) 4910585Sandreas.hansson@arm.comsystem.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s) 5010585Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4068508 # Total bandwidth to/from this memory (bytes/s) 5110036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 5210036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 5310585Sandreas.hansson@arm.comsystem.cpu.numCycles 10224315447 # number of cpu cycles simulated 548613SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 558613SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 5610585Sandreas.hansson@arm.comsystem.cpu.committedInsts 200033669 # Number of instructions committed 5710585Sandreas.hansson@arm.comsystem.cpu.committedOps 409539941 # Number of ops (including micro ops) committed 5810585Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 374549395 # Number of integer alu accesses 598613SN/Asystem.cpu.num_fp_alu_accesses 0 # Number of float alu accesses 6010585Sandreas.hansson@arm.comsystem.cpu.num_func_calls 2308749 # number of times a function call or return occured 6110585Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 39994798 # number of instructions that are conditional controls 6210585Sandreas.hansson@arm.comsystem.cpu.num_int_insts 374549395 # number of integer instructions 638613SN/Asystem.cpu.num_fp_insts 0 # number of float instructions 6410585Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 682628451 # number of times the integer registers were read 6510585Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 323525110 # number of times the integer registers were written 668613SN/Asystem.cpu.num_fp_register_reads 0 # number of times the floating registers were read 678613SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 6810585Sandreas.hansson@arm.comsystem.cpu.num_cc_register_reads 233820400 # number of times the CC registers were read 6910585Sandreas.hansson@arm.comsystem.cpu.num_cc_register_writes 157313425 # number of times the CC registers were written 7010585Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 35680406 # number of memory refs 7110585Sandreas.hansson@arm.comsystem.cpu.num_load_insts 27249300 # Number of load instructions 7210585Sandreas.hansson@arm.comsystem.cpu.num_store_insts 8431106 # Number of store instructions 7310585Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 9770368815.449127 # Number of idle cycles 7410585Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 453946631.550873 # Number of busy cycles 7510451Snilay@cs.wisc.edusystem.cpu.not_idle_fraction 0.044399 # Percentage of non-idle cycles 7610451Snilay@cs.wisc.edusystem.cpu.idle_fraction 0.955601 # Percentage of idle cycles 7710585Sandreas.hansson@arm.comsystem.cpu.Branches 43145649 # Number of branches fetched 7810585Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 175370 0.04% 0.04% # Class of executed instruction 7910585Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 373417675 91.18% 91.22% # Class of executed instruction 8010585Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 144551 0.04% 91.26% # Class of executed instruction 8110585Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 122974 0.03% 91.29% # Class of executed instruction 8210220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction 8310220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction 8410220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 91.29% # Class of executed instruction 8510220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction 8610220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction 8710220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction 8810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction 8910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction 9010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 91.29% # Class of executed instruction 9110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 91.29% # Class of executed instruction 9210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 91.29% # Class of executed instruction 9310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 91.29% # Class of executed instruction 9410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 91.29% # Class of executed instruction 9510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 91.29% # Class of executed instruction 9610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 91.29% # Class of executed instruction 9710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 91.29% # Class of executed instruction 9810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 91.29% # Class of executed instruction 9910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 91.29% # Class of executed instruction 10010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction 10110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction 10210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction 10310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction 10410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction 10510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction 10610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction 10710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction 10810585Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 27249300 6.65% 97.94% # Class of executed instruction 10910585Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 8431106 2.06% 100.00% # Class of executed instruction 11010220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 11110220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 11210585Sandreas.hansson@arm.comsystem.cpu.op_class::total 409540976 # Class of executed instruction 1138613SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 1148613SN/Asystem.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 11510585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1623460 # number of replacements 11610540Sgabeblack@google.comsystem.cpu.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use 11710585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 20193083 # Total number of references to valid blocks. 11810585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1623972 # Sample count of references to valid blocks. 11910585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 12.434379 # Average number of references to valid blocks. 12010540Sgabeblack@google.comsystem.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 12110540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.999462 # Average occupied blocks per requestor 12210540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 12310540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 12410540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 12510540Sgabeblack@google.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id 12610540Sgabeblack@google.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id 12710540Sgabeblack@google.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 12810540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 12910585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 88892257 # Number of tag accesses 13010585Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 88892257 # Number of data accesses 13110585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 12028370 # number of ReadReq hits 13210585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 12028370 # number of ReadReq hits 13310585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 8103548 # number of WriteReq hits 13410585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 8103548 # number of WriteReq hits 13510585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 58901 # number of SoftPFReq hits 13610585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 58901 # number of SoftPFReq hits 13710585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 20131918 # number of demand (read+write) hits 13810585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 20131918 # number of demand (read+write) hits 13910585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 20190819 # number of overall hits 14010585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 20190819 # number of overall hits 14110585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 906001 # number of ReadReq misses 14210585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 906001 # number of ReadReq misses 14310585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 317188 # number of WriteReq misses 14410585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 317188 # number of WriteReq misses 14510585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 403060 # number of SoftPFReq misses 14610585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 403060 # number of SoftPFReq misses 14710585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1223189 # number of demand (read+write) misses 14810585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 1223189 # number of demand (read+write) misses 14910585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1626249 # number of overall misses 15010585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 1626249 # number of overall misses 15110585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 12934371 # number of ReadReq accesses(hits+misses) 15210585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 12934371 # number of ReadReq accesses(hits+misses) 15310585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 8420736 # number of WriteReq accesses(hits+misses) 15410585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 8420736 # number of WriteReq accesses(hits+misses) 15510540Sgabeblack@google.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 461961 # number of SoftPFReq accesses(hits+misses) 15610540Sgabeblack@google.comsystem.cpu.dcache.SoftPFReq_accesses::total 461961 # number of SoftPFReq accesses(hits+misses) 15710585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 21355107 # number of demand (read+write) accesses 15810585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 21355107 # number of demand (read+write) accesses 15910585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 21817068 # number of overall (read+write) accesses 16010585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 21817068 # number of overall (read+write) accesses 16110585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070046 # miss rate for ReadReq accesses 16210585Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.070046 # miss rate for ReadReq accesses 16310585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037667 # miss rate for WriteReq accesses 16410585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.037667 # miss rate for WriteReq accesses 16510585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872498 # miss rate for SoftPFReq accesses 16610585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.872498 # miss rate for SoftPFReq accesses 16710585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.057279 # miss rate for demand accesses 16810585Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.057279 # miss rate for demand accesses 16910585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.074540 # miss rate for overall accesses 17010585Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.074540 # miss rate for overall accesses 17110540Sgabeblack@google.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 17210540Sgabeblack@google.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 17310540Sgabeblack@google.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 17410540Sgabeblack@google.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 17510540Sgabeblack@google.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 17610540Sgabeblack@google.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 17710540Sgabeblack@google.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 17810540Sgabeblack@google.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 17910585Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 1536867 # number of writebacks 18010585Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 1536867 # number of writebacks 18110540Sgabeblack@google.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 18210540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.replacements 8174 # number of replacements 18310585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.tagsinuse 5.013943 # Cycle average of tags in use 18410585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.total_refs 12520 # Total number of references to valid blocks. 18510540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.sampled_refs 8188 # Sample count of references to valid blocks. 18610585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.avg_refs 1.529067 # Average number of references to valid blocks. 18710585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.warmup_cycle 5101318572500 # Cycle when the warmup percentage was hit. 18810585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.013943 # Average occupied blocks per requestor 18910585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313371 # Average percentage of cache occupancy 19010585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_percent::total 0.313371 # Average percentage of cache occupancy 19110540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id 19210540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 19310540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 19410540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 19510540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id 19610585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.tag_accesses 53161 # Number of tag accesses 19710585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.data_accesses 53161 # Number of data accesses 19810585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12521 # number of ReadReq hits 19910585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_hits::total 12521 # number of ReadReq hits 20010585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12521 # number of demand (read+write) hits 20110585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::total 12521 # number of demand (read+write) hits 20210585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12521 # number of overall hits 20310585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::total 12521 # number of overall hits 20410540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 9373 # number of ReadReq misses 20510540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.ReadReq_misses::total 9373 # number of ReadReq misses 20610540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 9373 # number of demand (read+write) misses 20710540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.demand_misses::total 9373 # number of demand (read+write) misses 20810540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 9373 # number of overall misses 20910540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.overall_misses::total 9373 # number of overall misses 21010585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses) 21110585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses) 21210585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses 21310585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses 21410585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses 21510585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses 21610585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.428108 # miss rate for ReadReq accesses 21710585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.428108 # miss rate for ReadReq accesses 21810585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.428108 # miss rate for demand accesses 21910585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::total 0.428108 # miss rate for demand accesses 22010585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.428108 # miss rate for overall accesses 22110585Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::total 0.428108 # miss rate for overall accesses 22210540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 22310540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 22410540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 22510540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 22610540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 22710540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 22810540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 22910540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 23010540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.writebacks::writebacks 2794 # number of writebacks 23110540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.writebacks::total 2794 # number of writebacks 23210540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 23310585Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 791846 # number of replacements 23410451Snilay@cs.wisc.edusystem.cpu.icache.tags.tagsinuse 510.663108 # Cycle average of tags in use 23510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 243645674 # Total number of references to valid blocks. 23610585Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 792358 # Sample count of references to valid blocks. 23710585Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 307.494433 # Average number of references to valid blocks. 23810451Snilay@cs.wisc.edusystem.cpu.icache.tags.warmup_cycle 148876575500 # Cycle when the warmup percentage was hit. 23910451Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_blocks::cpu.inst 510.663108 # Average occupied blocks per requestor 24010451Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy 24110451Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy 24210036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 24310036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 24410036SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id 24510409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id 24610409Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 24710036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 24810585Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 245230404 # Number of tag accesses 24910585Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 245230404 # Number of data accesses 25010585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 243645674 # number of ReadReq hits 25110585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 243645674 # number of ReadReq hits 25210585Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 243645674 # number of demand (read+write) hits 25310585Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 243645674 # number of demand (read+write) hits 25410585Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 243645674 # number of overall hits 25510585Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 243645674 # number of overall hits 25610585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 792365 # number of ReadReq misses 25710585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 792365 # number of ReadReq misses 25810585Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 792365 # number of demand (read+write) misses 25910585Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 792365 # number of demand (read+write) misses 26010585Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 792365 # number of overall misses 26110585Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 792365 # number of overall misses 26210585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 244438039 # number of ReadReq accesses(hits+misses) 26310585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 244438039 # number of ReadReq accesses(hits+misses) 26410585Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 244438039 # number of demand (read+write) accesses 26510585Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 244438039 # number of demand (read+write) accesses 26610585Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 244438039 # number of overall (read+write) accesses 26710585Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 244438039 # number of overall (read+write) accesses 26810451Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003242 # miss rate for ReadReq accesses 26910451Snilay@cs.wisc.edusystem.cpu.icache.ReadReq_miss_rate::total 0.003242 # miss rate for ReadReq accesses 27010451Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::cpu.inst 0.003242 # miss rate for demand accesses 27110451Snilay@cs.wisc.edusystem.cpu.icache.demand_miss_rate::total 0.003242 # miss rate for demand accesses 27210451Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::cpu.inst 0.003242 # miss rate for overall accesses 27310451Snilay@cs.wisc.edusystem.cpu.icache.overall_miss_rate::total 0.003242 # miss rate for overall accesses 2748613SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2758613SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2768613SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2778613SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 2788983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2798983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2808613SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 2818613SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 2828613SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 28310409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.replacements 3702 # number of replacements 28410585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.tagsinuse 3.026443 # Cycle average of tags in use 28510409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.total_refs 7640 # Total number of references to valid blocks. 28610409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.sampled_refs 3715 # Sample count of references to valid blocks. 28710409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.avg_refs 2.056528 # Average number of references to valid blocks. 28810585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.warmup_cycle 5102148365500 # Cycle when the warmup percentage was hit. 28910585Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026443 # Average occupied blocks per requestor 29010409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189153 # Average percentage of cache occupancy 29110409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_percent::total 0.189153 # Average percentage of cache occupancy 29210409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id 29310036SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 29410409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 29510409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 29610409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 29710409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id 29810409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.tag_accesses 29024 # Number of tag accesses 29910409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.data_accesses 29024 # Number of data accesses 30010409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7640 # number of ReadReq hits 30110409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_hits::total 7640 # number of ReadReq hits 3028835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 3038613SN/Asystem.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 30410409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7642 # number of demand (read+write) hits 30510409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_hits::total 7642 # number of demand (read+write) hits 30610409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7642 # number of overall hits 30710409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_hits::total 7642 # number of overall hits 30810409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4580 # number of ReadReq misses 30910409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_misses::total 4580 # number of ReadReq misses 31010409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4580 # number of demand (read+write) misses 31110409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_misses::total 4580 # number of demand (read+write) misses 31210409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4580 # number of overall misses 31310409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_misses::total 4580 # number of overall misses 31410409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses) 31510409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses) 3168835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 3178613SN/Asystem.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 31810409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses 31910409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses 32010409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses 32110409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses 32210409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.374795 # miss rate for ReadReq accesses 32310409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.374795 # miss rate for ReadReq accesses 32410409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.374734 # miss rate for demand accesses 32510409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_miss_rate::total 0.374734 # miss rate for demand accesses 32610409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.374734 # miss rate for overall accesses 32710409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_miss_rate::total 0.374734 # miss rate for overall accesses 3288613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3298613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3308613SN/Asystem.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 3318613SN/Asystem.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 3328983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3338983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3348613SN/Asystem.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 3358613SN/Asystem.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 33610409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.writebacks::writebacks 802 # number of writebacks 33710409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.writebacks::total 802 # number of writebacks 3388613SN/Asystem.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 33910585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 106199 # number of replacements 34010585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 64825.456332 # Cycle average of tags in use 34110585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 3461789 # Total number of references to valid blocks. 34210585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 170310 # Sample count of references to valid blocks. 34310585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 20.326399 # Average number of references to valid blocks. 3449838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 34510585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 51911.006068 # Average occupied blocks per requestor 3469901Sandreas@sandberg.pp.sesystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002479 # Average occupied blocks per requestor 34710585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.132276 # Average occupied blocks per requestor 34810585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2490.288805 # Average occupied blocks per requestor 34910585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 10424.026704 # Average occupied blocks per requestor 35010451Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::writebacks 0.792099 # Average percentage of cache occupancy 3519797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 3529797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 35310451Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.037999 # Average percentage of cache occupancy 35410451Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::cpu.data 0.159058 # Average percentage of cache occupancy 35510451Snilay@cs.wisc.edusystem.cpu.l2cache.tags.occ_percent::total 0.989158 # Average percentage of cache occupancy 35610409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 64111 # Occupied blocks per task id 35710409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 35810409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id 35910409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3498 # Occupied blocks per task id 36010585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 20721 # Occupied blocks per task id 36110585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 39577 # Occupied blocks per task id 36210409Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.978256 # Percentage of cache occupancy per task id 36310585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 32245523 # Number of tag accesses 36410585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 32245523 # Number of data accesses 36510451Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7331 # number of ReadReq hits 36610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3337 # number of ReadReq hits 36710585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 779035 # number of ReadReq hits 36810585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 1276188 # number of ReadReq hits 36910585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 2065891 # number of ReadReq hits 37010585Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 1540463 # number of Writeback hits 37110585Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 1540463 # number of Writeback hits 37210409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits 37310409Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits 37410585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 180020 # number of ReadExReq hits 37510585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 180020 # number of ReadExReq hits 37610451Snilay@cs.wisc.edusystem.cpu.l2cache.demand_hits::cpu.dtb.walker 7331 # number of demand (read+write) hits 37710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 3337 # number of demand (read+write) hits 37810585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 779035 # number of demand (read+write) hits 37910585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1456208 # number of demand (read+write) hits 38010585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2245911 # number of demand (read+write) hits 38110451Snilay@cs.wisc.edusystem.cpu.l2cache.overall_hits::cpu.dtb.walker 7331 # number of overall hits 38210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 3337 # number of overall hits 38310585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 779035 # number of overall hits 38410585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1456208 # number of overall hits 38510585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2245911 # number of overall hits 3869901Sandreas@sandberg.pp.sesystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses 3879289Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 38810451Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.inst 13317 # number of ReadReq misses 38910451Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::cpu.data 32232 # number of ReadReq misses 39010451Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_misses::total 45555 # number of ReadReq misses 39110451Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1813 # number of UpgradeReq misses 39210451Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_misses::total 1813 # number of UpgradeReq misses 39310585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 134899 # number of ReadExReq misses 39410585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 134899 # number of ReadExReq misses 3959901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 3969289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 39710451Snilay@cs.wisc.edusystem.cpu.l2cache.demand_misses::cpu.inst 13317 # number of demand (read+write) misses 39810585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 167131 # number of demand (read+write) misses 39910585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 180454 # number of demand (read+write) misses 4009901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 4019289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 40210451Snilay@cs.wisc.edusystem.cpu.l2cache.overall_misses::cpu.inst 13317 # number of overall misses 40310585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 167131 # number of overall misses 40410585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 180454 # number of overall misses 40510451Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7332 # number of ReadReq accesses(hits+misses) 40610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3342 # number of ReadReq accesses(hits+misses) 40710585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 792352 # number of ReadReq accesses(hits+misses) 40810585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1308420 # number of ReadReq accesses(hits+misses) 40910585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2111446 # number of ReadReq accesses(hits+misses) 41010585Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 1540463 # number of Writeback accesses(hits+misses) 41110585Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 1540463 # number of Writeback accesses(hits+misses) 41210451Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 1835 # number of UpgradeReq accesses(hits+misses) 41310451Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_accesses::total 1835 # number of UpgradeReq accesses(hits+misses) 41410585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 314919 # number of ReadExReq accesses(hits+misses) 41510585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 314919 # number of ReadExReq accesses(hits+misses) 41610451Snilay@cs.wisc.edusystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 7332 # number of demand (read+write) accesses 41710409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 3342 # number of demand (read+write) accesses 41810585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 792352 # number of demand (read+write) accesses 41910585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1623339 # number of demand (read+write) accesses 42010585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2426365 # number of demand (read+write) accesses 42110451Snilay@cs.wisc.edusystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 7332 # number of overall (read+write) accesses 42210409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 3342 # number of overall (read+write) accesses 42310585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 792352 # number of overall (read+write) accesses 42410585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1623339 # number of overall (read+write) accesses 42510585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2426365 # number of overall (read+write) accesses 42610409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000136 # miss rate for ReadReq accesses 42710409Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001496 # miss rate for ReadReq accesses 42810585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016807 # miss rate for ReadReq accesses 42910451Snilay@cs.wisc.edusystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024634 # miss rate for ReadReq accesses 43010585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.021575 # miss rate for ReadReq accesses 43110451Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988011 # miss rate for UpgradeReq accesses 43210451Snilay@cs.wisc.edusystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.988011 # miss rate for UpgradeReq accesses 43310585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428361 # miss rate for ReadExReq accesses 43410585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.428361 # miss rate for ReadExReq accesses 43510409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000136 # miss rate for demand accesses 43610409Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001496 # miss rate for demand accesses 43710585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.016807 # miss rate for demand accesses 43810585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.102955 # miss rate for demand accesses 43910585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.074372 # miss rate for demand accesses 44010409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000136 # miss rate for overall accesses 44110409Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001496 # miss rate for overall accesses 44210585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.016807 # miss rate for overall accesses 44310585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.102955 # miss rate for overall accesses 44410585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.074372 # miss rate for overall accesses 4459289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4469289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4479289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 4489289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 4499289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4509289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4519289Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 4529289Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 45310585Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 98351 # number of writebacks 45410585Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 98351 # number of writebacks 4559289Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 45610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 15972684 # Transaction distribution 45710585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 15972684 # Transaction distribution 45810540Sgabeblack@google.comsystem.cpu.toL2Bus.trans_dist::WriteReq 13911 # Transaction distribution 45910540Sgabeblack@google.comsystem.cpu.toL2Bus.trans_dist::WriteResp 13911 # Transaction distribution 46010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 1540463 # Transaction distribution 46110540Sgabeblack@google.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2264 # Transaction distribution 46210540Sgabeblack@google.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2264 # Transaction distribution 46310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 314924 # Transaction distribution 46410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 314924 # Transaction distribution 46510585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1584730 # Packet count per connected master and slave (bytes) 46610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32531797 # Packet count per connected master and slave (bytes) 46710540Sgabeblack@google.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9962 # Packet count per connected master and slave (bytes) 46810540Sgabeblack@google.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 21540 # Packet count per connected master and slave (bytes) 46910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 34148029 # Packet count per connected master and slave (bytes) 47010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50711360 # Cumulative packet size per connected master and slave (bytes) 47110585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227719225 # Cumulative packet size per connected master and slave (bytes) 47210540Sgabeblack@google.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 344448 # Cumulative packet size per connected master and slave (bytes) 47310540Sgabeblack@google.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 778688 # Cumulative packet size per connected master and slave (bytes) 47410585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 279553721 # Cumulative packet size per connected master and slave (bytes) 47510540Sgabeblack@google.comsystem.cpu.toL2Bus.snoops 48008 # Total snoops (count) 47610585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 4020658 # Request fanout histogram 47710540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::mean 3.011846 # Request fanout histogram 47810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.108192 # Request fanout histogram 47910540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 48010540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 48110540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 48210540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 48310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 3973030 98.82% 98.82% # Request fanout histogram 48410540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::4 47628 1.18% 100.00% # Request fanout histogram 48510540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48610540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 48710540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 48810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 4020658 # Request fanout histogram 48910540Sgabeblack@google.comsystem.iobus.trans_dist::ReadReq 10012030 # Transaction distribution 49010540Sgabeblack@google.comsystem.iobus.trans_dist::ReadResp 10012030 # Transaction distribution 49110540Sgabeblack@google.comsystem.iobus.trans_dist::WriteReq 57692 # Transaction distribution 49210540Sgabeblack@google.comsystem.iobus.trans_dist::WriteResp 10972 # Transaction distribution 49310540Sgabeblack@google.comsystem.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 49410540Sgabeblack@google.comsystem.iobus.trans_dist::MessageReq 1696 # Transaction distribution 49510540Sgabeblack@google.comsystem.iobus.trans_dist::MessageResp 1696 # Transaction distribution 49610540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 49710540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 49810540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 49910540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 50010540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 50110540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 50210540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 50310540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 50410540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes) 50510540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) 50610549Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 50710540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 50810540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27812 # Packet count per connected master and slave (bytes) 50910540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 51010540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 51110540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 51210540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 51310540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 51410540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::total 20044188 # Packet count per connected master and slave (bytes) 51510540Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95256 # Packet count per connected master and slave (bytes) 51610540Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95256 # Packet count per connected master and slave (bytes) 51710540Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes) 51810540Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes) 51910540Sgabeblack@google.comsystem.iobus.pkt_count::total 20142836 # Packet count per connected master and slave (bytes) 52010540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 52110540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 52210540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 52310540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 52410540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 52510540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 52610540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 52710540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 52810540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes) 52910540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) 53010549Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 53110540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 53210540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13906 # Cumulative packet size per connected master and slave (bytes) 53310540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 53410540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 53510540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 53610540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 53710540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 53810540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::total 10028212 # Cumulative packet size per connected master and slave (bytes) 53910540Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027808 # Cumulative packet size per connected master and slave (bytes) 54010540Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027808 # Cumulative packet size per connected master and slave (bytes) 54110540Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) 54210540Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) 54310540Sgabeblack@google.comsystem.iobus.pkt_size::total 13062804 # Cumulative packet size per connected master and slave (bytes) 54410540Sgabeblack@google.comsystem.iocache.tags.replacements 47573 # number of replacements 54510585Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.042450 # Cycle average of tags in use 54610540Sgabeblack@google.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 54710540Sgabeblack@google.comsystem.iocache.tags.sampled_refs 47589 # Sample count of references to valid blocks. 54810540Sgabeblack@google.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 54910540Sgabeblack@google.comsystem.iocache.tags.warmup_cycle 4994875221009 # Cycle when the warmup percentage was hit. 55010585Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042450 # Average occupied blocks per requestor 55110540Sgabeblack@google.comsystem.iocache.tags.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy 55210540Sgabeblack@google.comsystem.iocache.tags.occ_percent::total 0.002653 # Average percentage of cache occupancy 55310540Sgabeblack@google.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 55410540Sgabeblack@google.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 55510540Sgabeblack@google.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 55610540Sgabeblack@google.comsystem.iocache.tags.tag_accesses 428652 # Number of tag accesses 55710540Sgabeblack@google.comsystem.iocache.tags.data_accesses 428652 # Number of data accesses 55810540Sgabeblack@google.comsystem.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses 55910540Sgabeblack@google.comsystem.iocache.ReadReq_misses::total 908 # number of ReadReq misses 56010585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses 56110585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses 56210540Sgabeblack@google.comsystem.iocache.demand_misses::pc.south_bridge.ide 908 # number of demand (read+write) misses 56310540Sgabeblack@google.comsystem.iocache.demand_misses::total 908 # number of demand (read+write) misses 56410540Sgabeblack@google.comsystem.iocache.overall_misses::pc.south_bridge.ide 908 # number of overall misses 56510540Sgabeblack@google.comsystem.iocache.overall_misses::total 908 # number of overall misses 56610540Sgabeblack@google.comsystem.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) 56710540Sgabeblack@google.comsystem.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) 56810540Sgabeblack@google.comsystem.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 56910540Sgabeblack@google.comsystem.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 57010540Sgabeblack@google.comsystem.iocache.demand_accesses::pc.south_bridge.ide 908 # number of demand (read+write) accesses 57110540Sgabeblack@google.comsystem.iocache.demand_accesses::total 908 # number of demand (read+write) accesses 57210540Sgabeblack@google.comsystem.iocache.overall_accesses::pc.south_bridge.ide 908 # number of overall (read+write) accesses 57310540Sgabeblack@google.comsystem.iocache.overall_accesses::total 908 # number of overall (read+write) accesses 57410540Sgabeblack@google.comsystem.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 57510540Sgabeblack@google.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 57610585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses 57710585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 57810540Sgabeblack@google.comsystem.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 57910540Sgabeblack@google.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 58010540Sgabeblack@google.comsystem.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 58110540Sgabeblack@google.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 58210540Sgabeblack@google.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58310540Sgabeblack@google.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58410540Sgabeblack@google.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 58510540Sgabeblack@google.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 58610540Sgabeblack@google.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 58710540Sgabeblack@google.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 58810585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 58910540Sgabeblack@google.comsystem.iocache.cache_copies 0 # number of cache copies performed 59010585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 46667 # number of writebacks 59110585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 46667 # number of writebacks 59210540Sgabeblack@google.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 59310540Sgabeblack@google.comsystem.membus.trans_dist::ReadReq 13903768 # Transaction distribution 59410540Sgabeblack@google.comsystem.membus.trans_dist::ReadResp 13903768 # Transaction distribution 59510540Sgabeblack@google.comsystem.membus.trans_dist::WriteReq 13911 # Transaction distribution 59610540Sgabeblack@google.comsystem.membus.trans_dist::WriteResp 13911 # Transaction distribution 59710585Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 145018 # Transaction distribution 59810540Sgabeblack@google.comsystem.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 59910540Sgabeblack@google.comsystem.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 60010540Sgabeblack@google.comsystem.membus.trans_dist::UpgradeReq 2525 # Transaction distribution 60110540Sgabeblack@google.comsystem.membus.trans_dist::UpgradeResp 2096 # Transaction distribution 60210585Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 134621 # Transaction distribution 60310585Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 134616 # Transaction distribution 60410540Sgabeblack@google.comsystem.membus.trans_dist::MessageReq 1696 # Transaction distribution 60510540Sgabeblack@google.comsystem.membus.trans_dist::MessageResp 1696 # Transaction distribution 60610540Sgabeblack@google.comsystem.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) 60710540Sgabeblack@google.comsystem.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) 60810540Sgabeblack@google.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044188 # Packet count per connected master and slave (bytes) 60910540Sgabeblack@google.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) 61010585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 463319 # Packet count per connected master and slave (bytes) 61110585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205751 # Packet count per connected master and slave (bytes) 61210585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141923 # Packet count per connected master and slave (bytes) 61310585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 141923 # Packet count per connected master and slave (bytes) 61410585Sandreas.hansson@arm.comsystem.membus.pkt_count::total 28351066 # Packet count per connected master and slave (bytes) 61510540Sgabeblack@google.comsystem.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) 61610540Sgabeblack@google.comsystem.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) 61710540Sgabeblack@google.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028212 # Cumulative packet size per connected master and slave (bytes) 61810540Sgabeblack@google.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) 61910585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825408 # Cumulative packet size per connected master and slave (bytes) 62010585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 43250105 # Cumulative packet size per connected master and slave (bytes) 62110585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6034880 # Cumulative packet size per connected master and slave (bytes) 62210585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 6034880 # Cumulative packet size per connected master and slave (bytes) 62310585Sandreas.hansson@arm.comsystem.membus.pkt_size::total 49291769 # Cumulative packet size per connected master and slave (bytes) 62410540Sgabeblack@google.comsystem.membus.snoops 0 # Total snoops (count) 62510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 375347 # Request fanout histogram 62610540Sgabeblack@google.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 62710540Sgabeblack@google.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 62810540Sgabeblack@google.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 62910540Sgabeblack@google.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 63010585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 375347 100.00% 100.00% # Request fanout histogram 63110540Sgabeblack@google.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 63210540Sgabeblack@google.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63310540Sgabeblack@google.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 63410540Sgabeblack@google.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 63510585Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 375347 # Request fanout histogram 63610540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 63710540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 63810540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 63910540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 64010540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 64110540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 64210540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 64310540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 64410540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 64510540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 64610540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 64710540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 6487927SN/A 6497927SN/A---------- End Simulation Statistics ---------- 650