17927SN/A 27927SN/A---------- Begin Simulation Statistics ---------- 310639Sgabeblack@google.comsim_seconds 5.112152 # Number of seconds simulated 411336Sandreas.hansson@arm.comsim_ticks 5112151729000 # Number of ticks simulated 511336Sandreas.hansson@arm.comfinal_tick 5112151729000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67927SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711502SCurtis.Dunham@arm.comhost_inst_rate 1314225 # Simulator instruction rate (inst/s) 811502SCurtis.Dunham@arm.comhost_op_rate 2690507 # Simulator op (including micro ops) rate (op/s) 911502SCurtis.Dunham@arm.comhost_tick_rate 33581335470 # Simulator tick rate (ticks/s) 1011502SCurtis.Dunham@arm.comhost_mem_usage 609616 # Number of bytes of host memory used 1111502SCurtis.Dunham@arm.comhost_seconds 152.23 # Real time elapsed on the host 1211336Sandreas.hansson@arm.comsim_insts 200067055 # Number of instructions simulated 1311336Sandreas.hansson@arm.comsim_ops 409581065 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 169901Sandreas@sandberg.pp.sesystem.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory 179079SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 1811201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 846912 # Number of bytes read from this memory 1911201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 10615104 # Number of bytes read from this memory 2010540Sgabeblack@google.comsystem.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11490752 # Number of bytes read from this memory 2211201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 846912 # Number of instructions bytes read from this memory 2311201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 846912 # Number of instructions bytes read from this memory 2411336Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 9269888 # Number of bytes written to this memory 2511336Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 9269888 # Number of bytes written to this memory 269901Sandreas@sandberg.pp.sesystem.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory 279079SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 2811201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 13233 # Number of read requests responded to by this memory 2911201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 165861 # Number of read requests responded to by this memory 3010540Sgabeblack@google.comsystem.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 3111201Sandreas.hansson@arm.comsystem.physmem.num_reads::total 179543 # Number of read requests responded to by this memory 3211336Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 144842 # Number of write requests responded to by this memory 3311336Sandreas.hansson@arm.comsystem.physmem.num_writes::total 144842 # Number of write requests responded to by this memory 349901Sandreas@sandberg.pp.sesystem.physmem.bw_read::cpu.dtb.walker 13 # Total read bandwidth from this memory (bytes/s) 359079SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s) 3611201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 165666 # Total read bandwidth from this memory (bytes/s) 3711201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 2076445 # Total read bandwidth from this memory (bytes/s) 3810540Sgabeblack@google.comsystem.physmem.bw_read::pc.south_bridge.ide 5546 # Total read bandwidth from this memory (bytes/s) 3911201Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2247733 # Total read bandwidth from this memory (bytes/s) 4011201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 165666 # Instruction read bandwidth from this memory (bytes/s) 4111201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 165666 # Instruction read bandwidth from this memory (bytes/s) 4211336Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1813305 # Write bandwidth from this memory (bytes/s) 4311336Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1813305 # Write bandwidth from this memory (bytes/s) 4411336Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1813305 # Total bandwidth to/from this memory (bytes/s) 459901Sandreas@sandberg.pp.sesystem.physmem.bw_total::cpu.dtb.walker 13 # Total bandwidth to/from this memory (bytes/s) 469079SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s) 4711201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 165666 # Total bandwidth to/from this memory (bytes/s) 4811201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 2076445 # Total bandwidth to/from this memory (bytes/s) 4910585Sandreas.hansson@arm.comsystem.physmem.bw_total::pc.south_bridge.ide 5546 # Total bandwidth to/from this memory (bytes/s) 5011336Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4061038 # Total bandwidth to/from this memory (bytes/s) 5110036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 5210036SAli.Saidi@ARM.comsystem.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 5311336Sandreas.hansson@arm.comsystem.cpu.numCycles 10224307424 # number of cpu cycles simulated 548613SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 558613SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 5611201Sandreas.hansson@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 5711201Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 5811336Sandreas.hansson@arm.comsystem.cpu.committedInsts 200067055 # Number of instructions committed 5911336Sandreas.hansson@arm.comsystem.cpu.committedOps 409581065 # Number of ops (including micro ops) committed 6011336Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 374584177 # Number of integer alu accesses 6110645Snilay@cs.wisc.edusystem.cpu.num_fp_alu_accesses 48 # Number of float alu accesses 6211336Sandreas.hansson@arm.comsystem.cpu.num_func_calls 2308905 # number of times a function call or return occured 6311336Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 40001120 # number of instructions that are conditional controls 6411336Sandreas.hansson@arm.comsystem.cpu.num_int_insts 374584177 # number of integer instructions 6510645Snilay@cs.wisc.edusystem.cpu.num_fp_insts 48 # number of float instructions 6611336Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 682690924 # number of times the integer registers were read 6711336Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 323558192 # number of times the integer registers were written 6810645Snilay@cs.wisc.edusystem.cpu.num_fp_register_reads 48 # number of times the floating registers were read 698613SN/Asystem.cpu.num_fp_register_writes 0 # number of times the floating registers were written 7011336Sandreas.hansson@arm.comsystem.cpu.num_cc_register_reads 233837631 # number of times the CC registers were read 7111336Sandreas.hansson@arm.comsystem.cpu.num_cc_register_writes 157316591 # number of times the CC registers were written 7211336Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 35667176 # number of memory refs 7311336Sandreas.hansson@arm.comsystem.cpu.num_load_insts 27243343 # Number of load instructions 7411336Sandreas.hansson@arm.comsystem.cpu.num_store_insts 8423833 # Number of store instructions 7511336Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 9770322790.617842 # Number of idle cycles 7611336Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 453984633.382158 # Number of busy cycles 7710639Sgabeblack@google.comsystem.cpu.not_idle_fraction 0.044402 # Percentage of non-idle cycles 7810639Sgabeblack@google.comsystem.cpu.idle_fraction 0.955598 # Percentage of idle cycles 7911336Sandreas.hansson@arm.comsystem.cpu.Branches 43152262 # Number of branches fetched 8011336Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 172765 0.04% 0.04% # Class of executed instruction 8111336Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 373477070 91.18% 91.23% # Class of executed instruction 8211336Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 144574 0.04% 91.26% # Class of executed instruction 8311336Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 123086 0.03% 91.29% # Class of executed instruction 8410220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 91.29% # Class of executed instruction 8510220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 91.29% # Class of executed instruction 8610645Snilay@cs.wisc.edusystem.cpu.op_class::FloatCvt 16 0.00% 91.29% # Class of executed instruction 8710220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 91.29% # Class of executed instruction 8810220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 91.29% # Class of executed instruction 8910220Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 91.29% # Class of executed instruction 9010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 91.29% # Class of executed instruction 9110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 91.29% # Class of executed instruction 9210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 91.29% # Class of executed instruction 9310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 91.29% # Class of executed instruction 9410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 91.29% # Class of executed instruction 9510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 91.29% # Class of executed instruction 9610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 91.29% # Class of executed instruction 9710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 91.29% # Class of executed instruction 9810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 91.29% # Class of executed instruction 9910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 91.29% # Class of executed instruction 10010220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 91.29% # Class of executed instruction 10110220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 91.29% # Class of executed instruction 10210220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 91.29% # Class of executed instruction 10310220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 91.29% # Class of executed instruction 10410220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 91.29% # Class of executed instruction 10510220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 91.29% # Class of executed instruction 10610220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 0 0.00% 91.29% # Class of executed instruction 10710220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 91.29% # Class of executed instruction 10810220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 91.29% # Class of executed instruction 10910220Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 91.29% # Class of executed instruction 11011336Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 27240752 6.65% 97.94% # Class of executed instruction 11111336Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 8423833 2.06% 100.00% # Class of executed instruction 11210220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 11310220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 11411336Sandreas.hansson@arm.comsystem.cpu.op_class::total 409582096 # Class of executed instruction 11511336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1621909 # number of replacements 11610639Sgabeblack@google.comsystem.cpu.dcache.tags.tagsinuse 511.999425 # Cycle average of tags in use 11711336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 20181333 # Total number of references to valid blocks. 11811336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1622421 # Sample count of references to valid blocks. 11911336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 12.439024 # Average number of references to valid blocks. 12010540Sgabeblack@google.comsystem.cpu.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. 12110639Sgabeblack@google.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.999425 # Average occupied blocks per requestor 12210540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy 12310540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy 12410540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 12510639Sgabeblack@google.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id 12610639Sgabeblack@google.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id 12710540Sgabeblack@google.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 12810540Sgabeblack@google.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 12911336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 88837527 # Number of tag accesses 13011336Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 88837527 # Number of data accesses 13111336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 12023410 # number of ReadReq hits 13211336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 12023410 # number of ReadReq hits 13311336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 8096819 # number of WriteReq hits 13411336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 8096819 # number of WriteReq hits 13511336Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 58904 # number of SoftPFReq hits 13611336Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 58904 # number of SoftPFReq hits 13711336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 20120229 # number of demand (read+write) hits 13811336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 20120229 # number of demand (read+write) hits 13911336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 20179133 # number of overall hits 14011336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 20179133 # number of overall hits 14111336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 905268 # number of ReadReq misses 14211336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 905268 # number of ReadReq misses 14311336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 316618 # number of WriteReq misses 14411336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 316618 # number of WriteReq misses 14511336Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 402753 # number of SoftPFReq misses 14611336Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 402753 # number of SoftPFReq misses 14711336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1221886 # number of demand (read+write) misses 14811336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 1221886 # number of demand (read+write) misses 14911336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1624639 # number of overall misses 15011336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 1624639 # number of overall misses 15111336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 12928678 # number of ReadReq accesses(hits+misses) 15211336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 12928678 # number of ReadReq accesses(hits+misses) 15311336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 8413437 # number of WriteReq accesses(hits+misses) 15411336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 8413437 # number of WriteReq accesses(hits+misses) 15510639Sgabeblack@google.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 461657 # number of SoftPFReq accesses(hits+misses) 15610639Sgabeblack@google.comsystem.cpu.dcache.SoftPFReq_accesses::total 461657 # number of SoftPFReq accesses(hits+misses) 15711336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 21342115 # number of demand (read+write) accesses 15811336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 21342115 # number of demand (read+write) accesses 15911336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 21803772 # number of overall (read+write) accesses 16011336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 21803772 # number of overall (read+write) accesses 16111336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070020 # miss rate for ReadReq accesses 16211336Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.070020 # miss rate for ReadReq accesses 16311336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037632 # miss rate for WriteReq accesses 16411336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.037632 # miss rate for WriteReq accesses 16511336Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872407 # miss rate for SoftPFReq accesses 16611336Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.872407 # miss rate for SoftPFReq accesses 16711336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.057252 # miss rate for demand accesses 16811336Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.057252 # miss rate for demand accesses 16911336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.074512 # miss rate for overall accesses 17011336Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.074512 # miss rate for overall accesses 17110540Sgabeblack@google.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 17210540Sgabeblack@google.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 17310540Sgabeblack@google.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 17410540Sgabeblack@google.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 17510540Sgabeblack@google.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 17610540Sgabeblack@google.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 17711336Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 1535790 # number of writebacks 17811336Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 1535790 # number of writebacks 17910645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.replacements 7749 # number of replacements 18011336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.tagsinuse 5.014001 # Cycle average of tags in use 18111336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.total_refs 12936 # Total number of references to valid blocks. 18210645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.sampled_refs 7763 # Sample count of references to valid blocks. 18311336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.avg_refs 1.666366 # Average number of references to valid blocks. 18411336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.warmup_cycle 5100450626500 # Cycle when the warmup percentage was hit. 18511336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.014001 # Average occupied blocks per requestor 18610645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.313375 # Average percentage of cache occupancy 18710645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.tags.occ_percent::total 0.313375 # Average percentage of cache occupancy 18810540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id 18910639Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id 19010540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 19110639Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 19210540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id 19311336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.tag_accesses 52745 # Number of tag accesses 19411336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.tags.data_accesses 52745 # Number of data accesses 19511336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12937 # number of ReadReq hits 19611336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_hits::total 12937 # number of ReadReq hits 19711336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12937 # number of demand (read+write) hits 19811336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_hits::total 12937 # number of demand (read+write) hits 19911336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12937 # number of overall hits 20011336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_hits::total 12937 # number of overall hits 20110645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8957 # number of ReadReq misses 20210645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.ReadReq_misses::total 8957 # number of ReadReq misses 20310645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8957 # number of demand (read+write) misses 20410645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.demand_misses::total 8957 # number of demand (read+write) misses 20510645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8957 # number of overall misses 20610645Snilay@cs.wisc.edusystem.cpu.dtb_walker_cache.overall_misses::total 8957 # number of overall misses 20711336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21894 # number of ReadReq accesses(hits+misses) 20811336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_accesses::total 21894 # number of ReadReq accesses(hits+misses) 20911336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21894 # number of demand (read+write) accesses 21011336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_accesses::total 21894 # number of demand (read+write) accesses 21111336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21894 # number of overall (read+write) accesses 21211336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_accesses::total 21894 # number of overall (read+write) accesses 21311336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409108 # miss rate for ReadReq accesses 21411336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.409108 # miss rate for ReadReq accesses 21511336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409108 # miss rate for demand accesses 21611336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.demand_miss_rate::total 0.409108 # miss rate for demand accesses 21711336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409108 # miss rate for overall accesses 21811336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.overall_miss_rate::total 0.409108 # miss rate for overall accesses 21910540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 22010540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 22110540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 22210540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 22310540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 22410540Sgabeblack@google.comsystem.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 22511336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.writebacks::writebacks 2897 # number of writebacks 22611336Sandreas.hansson@arm.comsystem.cpu.dtb_walker_cache.writebacks::total 2897 # number of writebacks 22711336Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 792340 # number of replacements 22810645Snilay@cs.wisc.edusystem.cpu.icache.tags.tagsinuse 510.662956 # Cycle average of tags in use 22911336Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 243675443 # Total number of references to valid blocks. 23011336Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 792852 # Sample count of references to valid blocks. 23111336Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 307.340390 # Average number of references to valid blocks. 23210645Snilay@cs.wisc.edusystem.cpu.icache.tags.warmup_cycle 148913118500 # Cycle when the warmup percentage was hit. 23310645Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_blocks::cpu.inst 510.662956 # Average occupied blocks per requestor 23410451Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::cpu.inst 0.997389 # Average percentage of cache occupancy 23510451Snilay@cs.wisc.edusystem.cpu.icache.tags.occ_percent::total 0.997389 # Average percentage of cache occupancy 23610036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 23710639Sgabeblack@google.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id 23810639Sgabeblack@google.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id 23910639Sgabeblack@google.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id 24010639Sgabeblack@google.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 24110036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 24211336Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 245261161 # Number of tag accesses 24311336Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 245261161 # Number of data accesses 24411336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 243675443 # number of ReadReq hits 24511336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 243675443 # number of ReadReq hits 24611336Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 243675443 # number of demand (read+write) hits 24711336Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 243675443 # number of demand (read+write) hits 24811336Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 243675443 # number of overall hits 24911336Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 243675443 # number of overall hits 25011336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 792859 # number of ReadReq misses 25111336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 792859 # number of ReadReq misses 25211336Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 792859 # number of demand (read+write) misses 25311336Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 792859 # number of demand (read+write) misses 25411336Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 792859 # number of overall misses 25511336Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 792859 # number of overall misses 25611336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 244468302 # number of ReadReq accesses(hits+misses) 25711336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 244468302 # number of ReadReq accesses(hits+misses) 25811336Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 244468302 # number of demand (read+write) accesses 25911336Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 244468302 # number of demand (read+write) accesses 26011336Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 244468302 # number of overall (read+write) accesses 26111336Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 244468302 # number of overall (read+write) accesses 26210639Sgabeblack@google.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003243 # miss rate for ReadReq accesses 26310639Sgabeblack@google.comsystem.cpu.icache.ReadReq_miss_rate::total 0.003243 # miss rate for ReadReq accesses 26410639Sgabeblack@google.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.003243 # miss rate for demand accesses 26510639Sgabeblack@google.comsystem.cpu.icache.demand_miss_rate::total 0.003243 # miss rate for demand accesses 26610639Sgabeblack@google.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.003243 # miss rate for overall accesses 26710639Sgabeblack@google.comsystem.cpu.icache.overall_miss_rate::total 0.003243 # miss rate for overall accesses 2688613SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2698613SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2708613SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 2718613SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 2728983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2738983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 27411336Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 792340 # number of writebacks 27511336Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 792340 # number of writebacks 27610639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.replacements 3586 # number of replacements 27711336Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.tagsinuse 3.026555 # Cycle average of tags in use 27810639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.total_refs 7763 # Total number of references to valid blocks. 27910639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.sampled_refs 3597 # Sample count of references to valid blocks. 28010639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.avg_refs 2.158187 # Average number of references to valid blocks. 28111336Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.warmup_cycle 5102137159500 # Cycle when the warmup percentage was hit. 28211336Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.026555 # Average occupied blocks per requestor 28311336Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.189160 # Average percentage of cache occupancy 28411336Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.occ_percent::total 0.189160 # Average percentage of cache occupancy 28510639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id 28610639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 28710639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 28810409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 28910639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id 29010639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.tag_accesses 28899 # Number of tag accesses 29110639Sgabeblack@google.comsystem.cpu.itb_walker_cache.tags.data_accesses 28899 # Number of data accesses 29210639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7765 # number of ReadReq hits 29310639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_hits::total 7765 # number of ReadReq hits 2948835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 2958613SN/Asystem.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 29610639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7767 # number of demand (read+write) hits 29710639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_hits::total 7767 # number of demand (read+write) hits 29810639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7767 # number of overall hits 29910639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_hits::total 7767 # number of overall hits 30010639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4455 # number of ReadReq misses 30110639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_misses::total 4455 # number of ReadReq misses 30210639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4455 # number of demand (read+write) misses 30310639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_misses::total 4455 # number of demand (read+write) misses 30410639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4455 # number of overall misses 30510639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_misses::total 4455 # number of overall misses 30610409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12220 # number of ReadReq accesses(hits+misses) 30710409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.ReadReq_accesses::total 12220 # number of ReadReq accesses(hits+misses) 3088835SAli.Saidi@ARM.comsystem.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 3098613SN/Asystem.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 31010409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12222 # number of demand (read+write) accesses 31110409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.demand_accesses::total 12222 # number of demand (read+write) accesses 31210409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12222 # number of overall (read+write) accesses 31310409Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.overall_accesses::total 12222 # number of overall (read+write) accesses 31410639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.364566 # miss rate for ReadReq accesses 31510639Sgabeblack@google.comsystem.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.364566 # miss rate for ReadReq accesses 31610639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.364507 # miss rate for demand accesses 31710639Sgabeblack@google.comsystem.cpu.itb_walker_cache.demand_miss_rate::total 0.364507 # miss rate for demand accesses 31810639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.364507 # miss rate for overall accesses 31910639Sgabeblack@google.comsystem.cpu.itb_walker_cache.overall_miss_rate::total 0.364507 # miss rate for overall accesses 3208613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3218613SN/Asystem.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3228613SN/Asystem.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 3238613SN/Asystem.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 3248983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3258983Snate@binkert.orgsystem.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 32611336Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.writebacks::writebacks 700 # number of writebacks 32711336Sandreas.hansson@arm.comsystem.cpu.itb_walker_cache.writebacks::total 700 # number of writebacks 32811336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 106202 # number of replacements 32911336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 64823.935074 # Cycle average of tags in use 33011336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 4340729 # Total number of references to valid blocks. 33111201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 170162 # Sample count of references to valid blocks. 33211336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 25.509391 # Average number of references to valid blocks. 3339838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 33411336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 51928.967732 # Average occupied blocks per requestor 33510639Sgabeblack@google.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.002478 # Average occupied blocks per requestor 33611336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135114 # Average occupied blocks per requestor 33711336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 2458.317021 # Average occupied blocks per requestor 33811336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 10436.512729 # Average occupied blocks per requestor 33911201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.792373 # Average percentage of cache occupancy 3409797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy 3419797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 34211201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.037511 # Average percentage of cache occupancy 34311201Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.159249 # Average percentage of cache occupancy 34410639Sgabeblack@google.comsystem.cpu.l2cache.tags.occ_percent::total 0.989135 # Average percentage of cache occupancy 34511336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 63960 # Occupied blocks per task id 34610639Sgabeblack@google.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 34710639Sgabeblack@google.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id 34811336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3348 # Occupied blocks per task id 34911336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 20880 # Occupied blocks per task id 35011336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 39442 # Occupied blocks per task id 35111336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.975952 # Percentage of cache occupancy per task id 35211336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 39254568 # Number of tag accesses 35311336Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 39254568 # Number of data accesses 35411336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 1539387 # number of WritebackDirty hits 35511336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 1539387 # number of WritebackDirty hits 35611336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 792329 # number of WritebackClean hits 35711336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 792329 # number of WritebackClean hits 35811336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 312 # number of UpgradeReq hits 35911336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 312 # number of UpgradeReq hits 36011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 179766 # number of ReadExReq hits 36111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 179766 # number of ReadExReq hits 36211336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 779612 # number of ReadCleanReq hits 36311336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 779612 # number of ReadCleanReq hits 36411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.dtb.walker 6533 # number of ReadSharedReq hits 36511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.itb.walker 2871 # number of ReadSharedReq hits 36611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 1275070 # number of ReadSharedReq hits 36711336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 1284474 # number of ReadSharedReq hits 36811336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 6533 # number of demand (read+write) hits 36911336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 2871 # number of demand (read+write) hits 37011336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 779612 # number of demand (read+write) hits 37111336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1454836 # number of demand (read+write) hits 37211336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2243852 # number of demand (read+write) hits 37311336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 6533 # number of overall hits 37411336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 2871 # number of overall hits 37511336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 779612 # number of overall hits 37611336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1454836 # number of overall hits 37711336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2243852 # number of overall hits 37811336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 1349 # number of UpgradeReq misses 37911336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 1349 # number of UpgradeReq misses 38011201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 134647 # number of ReadExReq misses 38111201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 134647 # number of ReadExReq misses 38211201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13234 # number of ReadCleanReq misses 38311201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 13234 # number of ReadCleanReq misses 38410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.dtb.walker 1 # number of ReadSharedReq misses 38510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.itb.walker 5 # number of ReadSharedReq misses 38611201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 32164 # number of ReadSharedReq misses 38711201Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 32170 # number of ReadSharedReq misses 3889901Sandreas@sandberg.pp.sesystem.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses 3899289Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 39011201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 13234 # number of demand (read+write) misses 39111201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 166811 # number of demand (read+write) misses 39211201Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 180051 # number of demand (read+write) misses 3939901Sandreas@sandberg.pp.sesystem.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses 3949289Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 39511201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 13234 # number of overall misses 39611201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 166811 # number of overall misses 39711201Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 180051 # number of overall misses 39811336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 1539387 # number of WritebackDirty accesses(hits+misses) 39911336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 1539387 # number of WritebackDirty accesses(hits+misses) 40011336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 792329 # number of WritebackClean accesses(hits+misses) 40111336Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 792329 # number of WritebackClean accesses(hits+misses) 40211336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 1661 # number of UpgradeReq accesses(hits+misses) 40311336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 1661 # number of UpgradeReq accesses(hits+misses) 40411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 314413 # number of ReadExReq accesses(hits+misses) 40511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 314413 # number of ReadExReq accesses(hits+misses) 40611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 792846 # number of ReadCleanReq accesses(hits+misses) 40711336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 792846 # number of ReadCleanReq accesses(hits+misses) 40811336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.dtb.walker 6534 # number of ReadSharedReq accesses(hits+misses) 40911336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.itb.walker 2876 # number of ReadSharedReq accesses(hits+misses) 41011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1307234 # number of ReadSharedReq accesses(hits+misses) 41111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1316644 # number of ReadSharedReq accesses(hits+misses) 41211336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 6534 # number of demand (read+write) accesses 41311336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 2876 # number of demand (read+write) accesses 41411336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 792846 # number of demand (read+write) accesses 41511336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1621647 # number of demand (read+write) accesses 41611336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2423903 # number of demand (read+write) accesses 41711336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 6534 # number of overall (read+write) accesses 41811336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 2876 # number of overall (read+write) accesses 41911336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 792846 # number of overall (read+write) accesses 42011336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1621647 # number of overall (read+write) accesses 42111336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2423903 # number of overall (read+write) accesses 42211336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.812161 # miss rate for UpgradeReq accesses 42311336Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.812161 # miss rate for UpgradeReq accesses 42411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428249 # miss rate for ReadExReq accesses 42511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.428249 # miss rate for ReadExReq accesses 42611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.016692 # miss rate for ReadCleanReq accesses 42711336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.016692 # miss rate for ReadCleanReq accesses 42811336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.dtb.walker 0.000153 # miss rate for ReadSharedReq accesses 42911336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.itb.walker 0.001739 # miss rate for ReadSharedReq accesses 43011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.024605 # miss rate for ReadSharedReq accesses 43111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.024433 # miss rate for ReadSharedReq accesses 43211336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000153 # miss rate for demand accesses 43311336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001739 # miss rate for demand accesses 43411336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.016692 # miss rate for demand accesses 43511336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.102865 # miss rate for demand accesses 43611336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.074281 # miss rate for demand accesses 43711336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000153 # miss rate for overall accesses 43811336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001739 # miss rate for overall accesses 43911336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.016692 # miss rate for overall accesses 44011336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.102865 # miss rate for overall accesses 44111336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.074281 # miss rate for overall accesses 4429289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4439289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4449289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 4459289Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 4469289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4479289Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 44811336Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 98175 # number of writebacks 44911336Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 98175 # number of writebacks 45011336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 4856494 # Total number of requests made to the snoop filter. 45111336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2425336 # Number of requests hitting in the snoop filter with a single holder of the requested data. 45211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 11672 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 45311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 1230 # Total number of snoops made to the snoop filter. 45411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 1230 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 45511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 45610892Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 13857337 # Transaction distribution 45711336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 15971629 # Transaction distribution 45810639Sgabeblack@google.comsystem.cpu.toL2Bus.trans_dist::WriteReq 13943 # Transaction distribution 45910639Sgabeblack@google.comsystem.cpu.toL2Bus.trans_dist::WriteResp 13943 # Transaction distribution 46011336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 1539387 # Transaction distribution 46111336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 792340 # Transaction distribution 46211336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 93857 # Transaction distribution 46311336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2200 # Transaction distribution 46411336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2200 # Transaction distribution 46511336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 314418 # Transaction distribution 46611336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 314418 # Transaction distribution 46711336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 792859 # Transaction distribution 46811336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1321433 # Transaction distribution 46911336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2378058 # Packet count per connected master and slave (bytes) 47011336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32613747 # Packet count per connected master and slave (bytes) 47111336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 12496 # Packet count per connected master and slave (bytes) 47211336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 25663 # Packet count per connected master and slave (bytes) 47311336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 35029964 # Packet count per connected master and slave (bytes) 47411336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 101452736 # Cumulative packet size per connected master and slave (bytes) 47511336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 227551417 # Cumulative packet size per connected master and slave (bytes) 47611336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 329920 # Cumulative packet size per connected master and slave (bytes) 47711336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 758656 # Cumulative packet size per connected master and slave (bytes) 47811336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 330092729 # Cumulative packet size per connected master and slave (bytes) 47911336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 203468 # Total snoops (count) 48011336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 18930863 # Request fanout histogram 48111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.001304 # Request fanout histogram 48211138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.042949 # Request fanout histogram 48310540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 48411336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 18911304 99.90% 99.90% # Request fanout histogram 48511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 14428 0.08% 99.97% # Request fanout histogram 48611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 5131 0.03% 100.00% # Request fanout histogram 48711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 100.00% # Request fanout histogram 48811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram 48910540Sgabeblack@google.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 49011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 49111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 49211336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 18930863 # Request fanout histogram 49310639Sgabeblack@google.comsystem.iobus.trans_dist::ReadReq 10012057 # Transaction distribution 49410639Sgabeblack@google.comsystem.iobus.trans_dist::ReadResp 10012057 # Transaction distribution 49510639Sgabeblack@google.comsystem.iobus.trans_dist::WriteReq 57724 # Transaction distribution 49610892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 57724 # Transaction distribution 49710540Sgabeblack@google.comsystem.iobus.trans_dist::MessageReq 1696 # Transaction distribution 49810540Sgabeblack@google.comsystem.iobus.trans_dist::MessageResp 1696 # Transaction distribution 49910540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 50010540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 50110540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) 50210540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 50310540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) 50410540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 50510540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 50610540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 19999988 # Packet count per connected master and slave (bytes) 50710540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1098 # Packet count per connected master and slave (bytes) 50810549Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 50910540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 51010639Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27940 # Packet count per connected master and slave (bytes) 51110540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 51210540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 51310540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 51410540Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 51511245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.pc.pci_host.pio 2308 # Packet count per connected master and slave (bytes) 51610639Sgabeblack@google.comsystem.iobus.pkt_count_system.bridge.master::total 20044316 # Packet count per connected master and slave (bytes) 51710639Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes) 51810639Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes) 51910540Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3392 # Packet count per connected master and slave (bytes) 52010540Sgabeblack@google.comsystem.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3392 # Packet count per connected master and slave (bytes) 52110639Sgabeblack@google.comsystem.iobus.pkt_count::total 20142954 # Packet count per connected master and slave (bytes) 52210540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 52310540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 52410540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) 52510540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 52610540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) 52710540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 52810540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 52910540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 9999994 # Cumulative packet size per connected master and slave (bytes) 53010540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2196 # Cumulative packet size per connected master and slave (bytes) 53110549Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 53210540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 53310639Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13970 # Cumulative packet size per connected master and slave (bytes) 53410540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 53510540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 53610540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 53710540Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 53811245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.pc.pci_host.pio 4477 # Cumulative packet size per connected master and slave (bytes) 53910639Sgabeblack@google.comsystem.iobus.pkt_size_system.bridge.master::total 10028276 # Cumulative packet size per connected master and slave (bytes) 54010639Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes) 54110639Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes) 54210540Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6784 # Cumulative packet size per connected master and slave (bytes) 54310540Sgabeblack@google.comsystem.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6784 # Cumulative packet size per connected master and slave (bytes) 54410639Sgabeblack@google.comsystem.iobus.pkt_size::total 13062828 # Cumulative packet size per connected master and slave (bytes) 54510639Sgabeblack@google.comsystem.iocache.tags.replacements 47568 # number of replacements 54611336Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.042439 # Cycle average of tags in use 54710540Sgabeblack@google.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 54810639Sgabeblack@google.comsystem.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks. 54910540Sgabeblack@google.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 55010645Snilay@cs.wisc.edusystem.iocache.tags.warmup_cycle 4994875253009 # Cycle when the warmup percentage was hit. 55111336Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::pc.south_bridge.ide 0.042439 # Average occupied blocks per requestor 55211336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::pc.south_bridge.ide 0.002652 # Average percentage of cache occupancy 55311336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.002652 # Average percentage of cache occupancy 55410540Sgabeblack@google.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 55510540Sgabeblack@google.comsystem.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 55610540Sgabeblack@google.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 55710639Sgabeblack@google.comsystem.iocache.tags.tag_accesses 428607 # Number of tag accesses 55810639Sgabeblack@google.comsystem.iocache.tags.data_accesses 428607 # Number of data accesses 55910639Sgabeblack@google.comsystem.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses 56010639Sgabeblack@google.comsystem.iocache.ReadReq_misses::total 903 # number of ReadReq misses 56110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::pc.south_bridge.ide 46720 # number of WriteLineReq misses 56210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 46720 # number of WriteLineReq misses 56311456Sandreas.hansson@arm.comsystem.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses 56411456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 47623 # number of demand (read+write) misses 56511456Sandreas.hansson@arm.comsystem.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses 56611456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 47623 # number of overall misses 56710639Sgabeblack@google.comsystem.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) 56810639Sgabeblack@google.comsystem.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) 56910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::pc.south_bridge.ide 46720 # number of WriteLineReq accesses(hits+misses) 57010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 46720 # number of WriteLineReq accesses(hits+misses) 57111456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses 57211456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses 57311456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses 57411456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses 57510540Sgabeblack@google.comsystem.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 57610540Sgabeblack@google.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 57710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteLineReq accesses 57810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 57910540Sgabeblack@google.comsystem.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 58010540Sgabeblack@google.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 58110540Sgabeblack@google.comsystem.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 58210540Sgabeblack@google.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 58310540Sgabeblack@google.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58410540Sgabeblack@google.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58510540Sgabeblack@google.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 58610540Sgabeblack@google.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 58710540Sgabeblack@google.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 58810540Sgabeblack@google.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 58910585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 46667 # number of writebacks 59010585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 46667 # number of writebacks 59110892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 13857337 # Transaction distribution 59211201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 13903644 # Transaction distribution 59310639Sgabeblack@google.comsystem.membus.trans_dist::WriteReq 13943 # Transaction distribution 59410639Sgabeblack@google.comsystem.membus.trans_dist::WriteResp 13943 # Transaction distribution 59511336Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 144842 # Transaction distribution 59611336Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 8802 # Transaction distribution 59711336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 2189 # Transaction distribution 59811336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 1650 # Transaction distribution 59911336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 134346 # Transaction distribution 60011201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 134346 # Transaction distribution 60111201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 46307 # Transaction distribution 60210540Sgabeblack@google.comsystem.membus.trans_dist::MessageReq 1696 # Transaction distribution 60310540Sgabeblack@google.comsystem.membus.trans_dist::MessageResp 1696 # Transaction distribution 60410892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 46720 # Transaction distribution 60510892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 46720 # Transaction distribution 60610540Sgabeblack@google.comsystem.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3392 # Packet count per connected master and slave (bytes) 60710540Sgabeblack@google.comsystem.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes) 60810639Sgabeblack@google.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes) 60910540Sgabeblack@google.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes) 61011336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 469415 # Packet count per connected master and slave (bytes) 61111336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 28211975 # Packet count per connected master and slave (bytes) 61211336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 142814 # Packet count per connected master and slave (bytes) 61311336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 142814 # Packet count per connected master and slave (bytes) 61411336Sandreas.hansson@arm.comsystem.membus.pkt_count::total 28358181 # Packet count per connected master and slave (bytes) 61510540Sgabeblack@google.comsystem.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes) 61610540Sgabeblack@google.comsystem.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes) 61710639Sgabeblack@google.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes) 61810540Sgabeblack@google.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 15396485 # Cumulative packet size per connected master and slave (bytes) 61911336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17787200 # Cumulative packet size per connected master and slave (bytes) 62011336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 43211961 # Cumulative packet size per connected master and slave (bytes) 62110892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3044480 # Cumulative packet size per connected master and slave (bytes) 62210892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 3044480 # Cumulative packet size per connected master and slave (bytes) 62311336Sandreas.hansson@arm.comsystem.membus.pkt_size::total 46263225 # Cumulative packet size per connected master and slave (bytes) 62410540Sgabeblack@google.comsystem.membus.snoops 0 # Total snoops (count) 62511336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 14256182 # Request fanout histogram 62610827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1.000119 # Request fanout histogram 62711336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.010907 # Request fanout histogram 62810540Sgabeblack@google.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 62910540Sgabeblack@google.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 63011336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 14254486 99.99% 99.99% # Request fanout histogram 63110827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram 63210540Sgabeblack@google.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63310540Sgabeblack@google.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 63410827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 2 # Request fanout histogram 63511336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 14256182 # Request fanout histogram 63610540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 63710540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 63810540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 63910540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 64010540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 64110540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 64210540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 64310540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 64410540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 64510540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 64610540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 64710540Sgabeblack@google.comsystem.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 6487927SN/A 6497927SN/A---------- End Simulation Statistics ---------- 650