stats.txt revision 10535:4ccec5baf82c
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.902619 # Number of seconds simulated 4sim_ticks 2902619131000 # Number of ticks simulated 5final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 783857 # Simulator instruction rate (inst/s) 8host_op_rate 945096 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 20223090080 # Simulator tick rate (ticks/s) 10host_mem_usage 560080 # Number of bytes of host memory used 11host_seconds 143.53 # Real time elapsed on the host 12sim_insts 112507011 # Number of instructions simulated 13sim_ops 135649580 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1190564 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1190564 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 5259520 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 27system.physmem.bytes_written::total 7595380 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 27056 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 141197 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 168277 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 82180 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 36system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 37system.physmem.num_writes::total 122785 # Number of write requests responded to by this memory 38system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.inst 410169 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu.data 3101807 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::total 3512505 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::cpu.inst 410169 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_inst_read::total 410169 # Instruction read bandwidth from this memory (bytes/s) 46system.physmem.bw_write::writebacks 1811991 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s) 49system.physmem.bw_write::total 2616733 # Write bandwidth from this memory (bytes/s) 50system.physmem.bw_total::writebacks 1811991 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu.inst 410169 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu.data 3107844 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::total 6129238 # Total bandwidth to/from this memory (bytes/s) 57system.physmem.readReqs 168277 # Number of read requests accepted 58system.physmem.writeReqs 122785 # Number of write requests accepted 59system.physmem.readBursts 168277 # Number of DRAM read bursts, including those serviced by the write queue 60system.physmem.writeBursts 122785 # Number of DRAM write bursts, including those merged in the write queue 61system.physmem.bytesReadDRAM 10758080 # Total number of bytes read from DRAM 62system.physmem.bytesReadWrQ 11648 # Total number of bytes read from write queue 63system.physmem.bytesWritten 7609472 # Total number of bytes written to DRAM 64system.physmem.bytesReadSys 10195464 # Total read bytes from the system interface side 65system.physmem.bytesWrittenSys 7595380 # Total written bytes from the system interface side 66system.physmem.servicedByWrQ 182 # Number of DRAM read bursts serviced by the write queue 67system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one 68system.physmem.neitherReadNorWriteReqs 4505 # Number of requests that are neither read nor write 69system.physmem.perBankRdBursts::0 9709 # Per bank write bursts 70system.physmem.perBankRdBursts::1 9253 # Per bank write bursts 71system.physmem.perBankRdBursts::2 10215 # Per bank write bursts 72system.physmem.perBankRdBursts::3 10266 # Per bank write bursts 73system.physmem.perBankRdBursts::4 18988 # Per bank write bursts 74system.physmem.perBankRdBursts::5 10225 # Per bank write bursts 75system.physmem.perBankRdBursts::6 10580 # Per bank write bursts 76system.physmem.perBankRdBursts::7 10353 # Per bank write bursts 77system.physmem.perBankRdBursts::8 9698 # Per bank write bursts 78system.physmem.perBankRdBursts::9 9938 # Per bank write bursts 79system.physmem.perBankRdBursts::10 9924 # Per bank write bursts 80system.physmem.perBankRdBursts::11 8855 # Per bank write bursts 81system.physmem.perBankRdBursts::12 9985 # Per bank write bursts 82system.physmem.perBankRdBursts::13 10410 # Per bank write bursts 83system.physmem.perBankRdBursts::14 9933 # Per bank write bursts 84system.physmem.perBankRdBursts::15 9763 # Per bank write bursts 85system.physmem.perBankWrBursts::0 7210 # Per bank write bursts 86system.physmem.perBankWrBursts::1 6831 # Per bank write bursts 87system.physmem.perBankWrBursts::2 8029 # Per bank write bursts 88system.physmem.perBankWrBursts::3 7890 # Per bank write bursts 89system.physmem.perBankWrBursts::4 7400 # Per bank write bursts 90system.physmem.perBankWrBursts::5 7418 # Per bank write bursts 91system.physmem.perBankWrBursts::6 7750 # Per bank write bursts 92system.physmem.perBankWrBursts::7 7625 # Per bank write bursts 93system.physmem.perBankWrBursts::8 7363 # Per bank write bursts 94system.physmem.perBankWrBursts::9 7566 # Per bank write bursts 95system.physmem.perBankWrBursts::10 7503 # Per bank write bursts 96system.physmem.perBankWrBursts::11 6751 # Per bank write bursts 97system.physmem.perBankWrBursts::12 7436 # Per bank write bursts 98system.physmem.perBankWrBursts::13 7741 # Per bank write bursts 99system.physmem.perBankWrBursts::14 7284 # Per bank write bursts 100system.physmem.perBankWrBursts::15 7101 # Per bank write bursts 101system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 102system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 103system.physmem.totGap 2902618754500 # Total gap between requests 104system.physmem.readPktSize::0 0 # Read request sizes (log2) 105system.physmem.readPktSize::1 0 # Read request sizes (log2) 106system.physmem.readPktSize::2 9558 # Read request sizes (log2) 107system.physmem.readPktSize::3 14 # Read request sizes (log2) 108system.physmem.readPktSize::4 0 # Read request sizes (log2) 109system.physmem.readPktSize::5 0 # Read request sizes (log2) 110system.physmem.readPktSize::6 158705 # Read request sizes (log2) 111system.physmem.writePktSize::0 0 # Write request sizes (log2) 112system.physmem.writePktSize::1 0 # Write request sizes (log2) 113system.physmem.writePktSize::2 4381 # Write request sizes (log2) 114system.physmem.writePktSize::3 0 # Write request sizes (log2) 115system.physmem.writePktSize::4 0 # Write request sizes (log2) 116system.physmem.writePktSize::5 0 # Write request sizes (log2) 117system.physmem.writePktSize::6 118404 # Write request sizes (log2) 118system.physmem.rdQLenPdf::0 167256 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::1 571 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::2 256 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 150system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::15 2070 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::16 2628 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::17 6016 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::18 6156 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::19 6193 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::20 6817 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::21 7034 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::22 7564 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::23 8052 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::24 8864 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::25 8233 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::26 7730 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::27 7142 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::28 6957 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::29 6255 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::30 6112 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::31 6123 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::32 6074 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::33 239 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::34 234 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::35 217 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::36 180 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::38 128 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::39 123 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::40 108 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::41 113 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::43 118 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::44 135 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::45 142 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::46 124 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::48 100 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::49 87 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::50 70 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::51 57 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::57 38 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::58 25 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::59 18 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see 214system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::gmean 183.640199 # Bytes accessed per row activation 217system.physmem.bytesPerActivate::stdev 334.584074 # Bytes accessed per row activation 218system.physmem.bytesPerActivate::0-127 21469 36.67% 36.67% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::128-255 14640 25.00% 61.67% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::256-383 5516 9.42% 71.09% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::384-511 3473 5.93% 77.02% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::512-639 2278 3.89% 80.91% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::768-895 999 1.71% 85.31% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.12% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::1024-1151 7539 12.88% 100.00% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation 228system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::0-2047 5861 99.97% 99.97% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::total 5863 # Reads before turning the bus around for writes 235system.physmem.wrPerTurnAround::samples 5863 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::mean 20.279379 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::gmean 18.638132 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::stdev 12.466375 # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::16-19 5064 86.37% 86.37% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::20-23 42 0.72% 87.09% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::24-27 33 0.56% 87.65% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::28-31 216 3.68% 91.34% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::32-35 215 3.67% 95.00% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::36-39 12 0.20% 95.21% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::40-43 16 0.27% 95.48% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::44-47 7 0.12% 95.60% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::48-51 25 0.43% 96.03% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::52-55 3 0.05% 96.08% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::56-59 6 0.10% 96.18% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::60-63 4 0.07% 96.25% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::64-67 164 2.80% 99.04% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::68-71 4 0.07% 99.11% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::72-75 3 0.05% 99.16% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::76-79 2 0.03% 99.20% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::80-83 13 0.22% 99.42% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::88-91 2 0.03% 99.45% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::92-95 1 0.02% 99.47% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::96-99 5 0.09% 99.56% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::100-103 1 0.02% 99.57% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::104-107 3 0.05% 99.62% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::108-111 3 0.05% 99.68% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::112-115 2 0.03% 99.71% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::116-119 2 0.03% 99.74% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::124-127 1 0.02% 99.76% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::128-131 8 0.14% 99.90% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::132-135 3 0.05% 99.95% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads 271system.physmem.totQLat 1491102500 # Total ticks spent queuing 272system.physmem.totMemAccLat 4642883750 # Total ticks spent from burst creation until serviced by the DRAM 273system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers 274system.physmem.avgQLat 8870.59 # Average queueing delay per DRAM burst 275system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 276system.physmem.avgMemAccLat 27620.59 # Average memory access latency per DRAM burst 277system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s 278system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s 279system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s 280system.physmem.avgWrBWSys 2.62 # Average system write bandwidth in MiByte/s 281system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 282system.physmem.busUtil 0.05 # Data bus utilization in percentage 283system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 284system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 285system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 286system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing 287system.physmem.readRowHits 138436 # Number of row buffer hits during reads 288system.physmem.writeRowHits 90002 # Number of row buffer hits during writes 289system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads 290system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes 291system.physmem.avgGap 9972510.17 # Average gap between requests 292system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined 293system.physmem.memoryStateTime::IDLE 2755210874500 # Time in different power states 294system.physmem.memoryStateTime::REF 96924620000 # Time in different power states 295system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 296system.physmem.memoryStateTime::ACT 50483546000 # Time in different power states 297system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 298system.physmem.actEnergy::0 226731960 # Energy for activate commands per rank (pJ) 299system.physmem.actEnergy::1 215936280 # Energy for activate commands per rank (pJ) 300system.physmem.preEnergy::0 123712875 # Energy for precharge commands per rank (pJ) 301system.physmem.preEnergy::1 117822375 # Energy for precharge commands per rank (pJ) 302system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ) 303system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ) 304system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ) 305system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ) 306system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ) 307system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ) 308system.physmem.actBackEnergy::0 86730297120 # Energy for active background per rank (pJ) 309system.physmem.actBackEnergy::1 85558991580 # Energy for active background per rank (pJ) 310system.physmem.preBackEnergy::0 1665488607000 # Energy for precharge background per rank (pJ) 311system.physmem.preBackEnergy::1 1666516068000 # Energy for precharge background per rank (pJ) 312system.physmem.totalEnergy::0 1943242491315 # Total energy per rank (pJ) 313system.physmem.totalEnergy::1 1942986381555 # Total energy per rank (pJ) 314system.physmem.averagePower::0 669.480387 # Core power per rank (mW) 315system.physmem.averagePower::1 669.392153 # Core power per rank (mW) 316system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 317system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 318system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 319system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 320system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 321system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 322system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 323system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 324system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 325system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 326system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 327system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 328system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 329system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 330system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 331system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 332system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 333system.cf0.dma_write_txs 631 # Number of DMA write transactions. 334system.cpu_clk_domain.clock 500 # Clock period in ticks 335system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 336system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 337system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 338system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 339system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 340system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 341system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 342system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 343system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 344system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 345system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 346system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 347system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 348system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 349system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 350system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 351system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 352system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 353system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 354system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 355system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 356system.cpu.dtb.inst_hits 0 # ITB inst hits 357system.cpu.dtb.inst_misses 0 # ITB inst misses 358system.cpu.dtb.read_hits 24532671 # DTB read hits 359system.cpu.dtb.read_misses 8148 # DTB read misses 360system.cpu.dtb.write_hits 19614515 # DTB write hits 361system.cpu.dtb.write_misses 1410 # DTB write misses 362system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 363system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 364system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 365system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 366system.cpu.dtb.flush_entries 4272 # Number of entries that have been flushed from TLB 367system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 368system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch 369system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 370system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 371system.cpu.dtb.read_accesses 24540819 # DTB read accesses 372system.cpu.dtb.write_accesses 19615925 # DTB write accesses 373system.cpu.dtb.inst_accesses 0 # ITB inst accesses 374system.cpu.dtb.hits 44147186 # DTB hits 375system.cpu.dtb.misses 9558 # DTB misses 376system.cpu.dtb.accesses 44156744 # DTB accesses 377system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 378system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 379system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 380system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 381system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 382system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 383system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 384system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 385system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 386system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 387system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 388system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 389system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 390system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 391system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 392system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 393system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 394system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 395system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 396system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 397system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 398system.cpu.itb.inst_hits 115605918 # ITB inst hits 399system.cpu.itb.inst_misses 4762 # ITB inst misses 400system.cpu.itb.read_hits 0 # DTB read hits 401system.cpu.itb.read_misses 0 # DTB read misses 402system.cpu.itb.write_hits 0 # DTB write hits 403system.cpu.itb.write_misses 0 # DTB write misses 404system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 405system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 406system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 407system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 408system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 409system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 410system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 411system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 412system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 413system.cpu.itb.read_accesses 0 # DTB read accesses 414system.cpu.itb.write_accesses 0 # DTB write accesses 415system.cpu.itb.inst_accesses 115610680 # ITB inst accesses 416system.cpu.itb.hits 115605918 # DTB hits 417system.cpu.itb.misses 4762 # DTB misses 418system.cpu.itb.accesses 115610680 # DTB accesses 419system.cpu.numCycles 5805238262 # number of cpu cycles simulated 420system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 421system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 422system.cpu.committedInsts 112507011 # Number of instructions committed 423system.cpu.committedOps 135649580 # Number of ops (including micro ops) committed 424system.cpu.num_int_alu_accesses 119948946 # Number of integer alu accesses 425system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses 426system.cpu.num_func_calls 9898964 # number of times a function call or return occured 427system.cpu.num_conditional_control_insts 15236406 # number of instructions that are conditional controls 428system.cpu.num_int_insts 119948946 # number of integer instructions 429system.cpu.num_fp_insts 11161 # number of float instructions 430system.cpu.num_int_register_reads 218165471 # number of times the integer registers were read 431system.cpu.num_int_register_writes 82686622 # number of times the integer registers were written 432system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read 433system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 434system.cpu.num_cc_register_reads 489970666 # number of times the CC registers were read 435system.cpu.num_cc_register_writes 51914345 # number of times the CC registers were written 436system.cpu.num_mem_refs 45428250 # number of memory refs 437system.cpu.num_load_insts 24855398 # Number of load instructions 438system.cpu.num_store_insts 20572852 # Number of store instructions 439system.cpu.num_idle_cycles 5386458042.024144 # Number of idle cycles 440system.cpu.num_busy_cycles 418780219.975856 # Number of busy cycles 441system.cpu.not_idle_fraction 0.072138 # Percentage of non-idle cycles 442system.cpu.idle_fraction 0.927862 # Percentage of idle cycles 443system.cpu.Branches 25929462 # Number of branches fetched 444system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 445system.cpu.op_class::IntAlu 93218062 67.17% 67.18% # Class of executed instruction 446system.cpu.op_class::IntMult 114523 0.08% 67.26% # Class of executed instruction 447system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction 448system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction 449system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction 450system.cpu.op_class::FloatCvt 0 0.00% 67.26% # Class of executed instruction 451system.cpu.op_class::FloatMult 0 0.00% 67.26% # Class of executed instruction 452system.cpu.op_class::FloatDiv 0 0.00% 67.26% # Class of executed instruction 453system.cpu.op_class::FloatSqrt 0 0.00% 67.26% # Class of executed instruction 454system.cpu.op_class::SimdAdd 0 0.00% 67.26% # Class of executed instruction 455system.cpu.op_class::SimdAddAcc 0 0.00% 67.26% # Class of executed instruction 456system.cpu.op_class::SimdAlu 0 0.00% 67.26% # Class of executed instruction 457system.cpu.op_class::SimdCmp 0 0.00% 67.26% # Class of executed instruction 458system.cpu.op_class::SimdCvt 0 0.00% 67.26% # Class of executed instruction 459system.cpu.op_class::SimdMisc 0 0.00% 67.26% # Class of executed instruction 460system.cpu.op_class::SimdMult 0 0.00% 67.26% # Class of executed instruction 461system.cpu.op_class::SimdMultAcc 0 0.00% 67.26% # Class of executed instruction 462system.cpu.op_class::SimdShift 0 0.00% 67.26% # Class of executed instruction 463system.cpu.op_class::SimdShiftAcc 0 0.00% 67.26% # Class of executed instruction 464system.cpu.op_class::SimdSqrt 0 0.00% 67.26% # Class of executed instruction 465system.cpu.op_class::SimdFloatAdd 0 0.00% 67.26% # Class of executed instruction 466system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Class of executed instruction 467system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction 468system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction 469system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction 470system.cpu.op_class::SimdFloatMisc 8475 0.01% 67.26% # Class of executed instruction 471system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction 472system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction 473system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction 474system.cpu.op_class::MemRead 24855398 17.91% 85.18% # Class of executed instruction 475system.cpu.op_class::MemWrite 20572852 14.82% 100.00% # Class of executed instruction 476system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 477system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 478system.cpu.op_class::total 138771647 # Class of executed instruction 479system.cpu.kern.inst.arm 0 # number of arm instructions executed 480system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed 481system.cpu.dcache.tags.replacements 822746 # number of replacements 482system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use 483system.cpu.dcache.tags.total_refs 43252602 # Total number of references to valid blocks. 484system.cpu.dcache.tags.sampled_refs 823258 # Sample count of references to valid blocks. 485system.cpu.dcache.tags.avg_refs 52.538332 # Average number of references to valid blocks. 486system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. 487system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor 488system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy 489system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy 490system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 491system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id 492system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id 493system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id 494system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id 495system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 496system.cpu.dcache.tags.tag_accesses 177194888 # Number of tag accesses 497system.cpu.dcache.tags.data_accesses 177194888 # Number of data accesses 498system.cpu.dcache.ReadReq_hits::cpu.data 23122389 # number of ReadReq hits 499system.cpu.dcache.ReadReq_hits::total 23122389 # number of ReadReq hits 500system.cpu.dcache.WriteReq_hits::cpu.data 18831358 # number of WriteReq hits 501system.cpu.dcache.WriteReq_hits::total 18831358 # number of WriteReq hits 502system.cpu.dcache.SoftPFReq_hits::cpu.data 392121 # number of SoftPFReq hits 503system.cpu.dcache.SoftPFReq_hits::total 392121 # number of SoftPFReq hits 504system.cpu.dcache.LoadLockedReq_hits::cpu.data 443546 # number of LoadLockedReq hits 505system.cpu.dcache.LoadLockedReq_hits::total 443546 # number of LoadLockedReq hits 506system.cpu.dcache.StoreCondReq_hits::cpu.data 460444 # number of StoreCondReq hits 507system.cpu.dcache.StoreCondReq_hits::total 460444 # number of StoreCondReq hits 508system.cpu.dcache.demand_hits::cpu.data 41953747 # number of demand (read+write) hits 509system.cpu.dcache.demand_hits::total 41953747 # number of demand (read+write) hits 510system.cpu.dcache.overall_hits::cpu.data 42345868 # number of overall hits 511system.cpu.dcache.overall_hits::total 42345868 # number of overall hits 512system.cpu.dcache.ReadReq_misses::cpu.data 402166 # number of ReadReq misses 513system.cpu.dcache.ReadReq_misses::total 402166 # number of ReadReq misses 514system.cpu.dcache.WriteReq_misses::cpu.data 299026 # number of WriteReq misses 515system.cpu.dcache.WriteReq_misses::total 299026 # number of WriteReq misses 516system.cpu.dcache.SoftPFReq_misses::cpu.data 119155 # number of SoftPFReq misses 517system.cpu.dcache.SoftPFReq_misses::total 119155 # number of SoftPFReq misses 518system.cpu.dcache.LoadLockedReq_misses::cpu.data 22691 # number of LoadLockedReq misses 519system.cpu.dcache.LoadLockedReq_misses::total 22691 # number of LoadLockedReq misses 520system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 521system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 522system.cpu.dcache.demand_misses::cpu.data 701192 # number of demand (read+write) misses 523system.cpu.dcache.demand_misses::total 701192 # number of demand (read+write) misses 524system.cpu.dcache.overall_misses::cpu.data 820347 # number of overall misses 525system.cpu.dcache.overall_misses::total 820347 # number of overall misses 526system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900442000 # number of ReadReq miss cycles 527system.cpu.dcache.ReadReq_miss_latency::total 5900442000 # number of ReadReq miss cycles 528system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658351003 # number of WriteReq miss cycles 529system.cpu.dcache.WriteReq_miss_latency::total 11658351003 # number of WriteReq miss cycles 530system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles 531system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles 532system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles 533system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles 534system.cpu.dcache.demand_miss_latency::cpu.data 17558793003 # number of demand (read+write) miss cycles 535system.cpu.dcache.demand_miss_latency::total 17558793003 # number of demand (read+write) miss cycles 536system.cpu.dcache.overall_miss_latency::cpu.data 17558793003 # number of overall miss cycles 537system.cpu.dcache.overall_miss_latency::total 17558793003 # number of overall miss cycles 538system.cpu.dcache.ReadReq_accesses::cpu.data 23524555 # number of ReadReq accesses(hits+misses) 539system.cpu.dcache.ReadReq_accesses::total 23524555 # number of ReadReq accesses(hits+misses) 540system.cpu.dcache.WriteReq_accesses::cpu.data 19130384 # number of WriteReq accesses(hits+misses) 541system.cpu.dcache.WriteReq_accesses::total 19130384 # number of WriteReq accesses(hits+misses) 542system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses) 543system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses) 544system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses) 545system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses) 546system.cpu.dcache.StoreCondReq_accesses::cpu.data 460446 # number of StoreCondReq accesses(hits+misses) 547system.cpu.dcache.StoreCondReq_accesses::total 460446 # number of StoreCondReq accesses(hits+misses) 548system.cpu.dcache.demand_accesses::cpu.data 42654939 # number of demand (read+write) accesses 549system.cpu.dcache.demand_accesses::total 42654939 # number of demand (read+write) accesses 550system.cpu.dcache.overall_accesses::cpu.data 43166215 # number of overall (read+write) accesses 551system.cpu.dcache.overall_accesses::total 43166215 # number of overall (read+write) accesses 552system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017096 # miss rate for ReadReq accesses 553system.cpu.dcache.ReadReq_miss_rate::total 0.017096 # miss rate for ReadReq accesses 554system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses 555system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses 556system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233054 # miss rate for SoftPFReq accesses 557system.cpu.dcache.SoftPFReq_miss_rate::total 0.233054 # miss rate for SoftPFReq accesses 558system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048668 # miss rate for LoadLockedReq accesses 559system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048668 # miss rate for LoadLockedReq accesses 560system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 561system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 562system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses 563system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses 564system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses 565system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses 566system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14671.657972 # average ReadReq miss latency 567system.cpu.dcache.ReadReq_avg_miss_latency::total 14671.657972 # average ReadReq miss latency 568system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38987.750239 # average WriteReq miss latency 569system.cpu.dcache.WriteReq_avg_miss_latency::total 38987.750239 # average WriteReq miss latency 570system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency 571system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency 572system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency 573system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency 574system.cpu.dcache.demand_avg_miss_latency::cpu.data 25041.348166 # average overall miss latency 575system.cpu.dcache.demand_avg_miss_latency::total 25041.348166 # average overall miss latency 576system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.104608 # average overall miss latency 577system.cpu.dcache.overall_avg_miss_latency::total 21404.104608 # average overall miss latency 578system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked 579system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 580system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked 581system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 582system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked 583system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 584system.cpu.dcache.fast_writes 0 # number of fast writes performed 585system.cpu.dcache.cache_copies 0 # number of cache copies performed 586system.cpu.dcache.writebacks::writebacks 686230 # number of writebacks 587system.cpu.dcache.writebacks::total 686230 # number of writebacks 588system.cpu.dcache.ReadReq_mshr_hits::cpu.data 627 # number of ReadReq MSHR hits 589system.cpu.dcache.ReadReq_mshr_hits::total 627 # number of ReadReq MSHR hits 590system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14222 # number of LoadLockedReq MSHR hits 591system.cpu.dcache.LoadLockedReq_mshr_hits::total 14222 # number of LoadLockedReq MSHR hits 592system.cpu.dcache.demand_mshr_hits::cpu.data 627 # number of demand (read+write) MSHR hits 593system.cpu.dcache.demand_mshr_hits::total 627 # number of demand (read+write) MSHR hits 594system.cpu.dcache.overall_mshr_hits::cpu.data 627 # number of overall MSHR hits 595system.cpu.dcache.overall_mshr_hits::total 627 # number of overall MSHR hits 596system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401539 # number of ReadReq MSHR misses 597system.cpu.dcache.ReadReq_mshr_misses::total 401539 # number of ReadReq MSHR misses 598system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299026 # number of WriteReq MSHR misses 599system.cpu.dcache.WriteReq_mshr_misses::total 299026 # number of WriteReq MSHR misses 600system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses 601system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses 602system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses 603system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses 604system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 605system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 606system.cpu.dcache.demand_mshr_misses::cpu.data 700565 # number of demand (read+write) MSHR misses 607system.cpu.dcache.demand_mshr_misses::total 700565 # number of demand (read+write) MSHR misses 608system.cpu.dcache.overall_mshr_misses::cpu.data 817569 # number of overall MSHR misses 609system.cpu.dcache.overall_mshr_misses::total 817569 # number of overall MSHR misses 610system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083326500 # number of ReadReq MSHR miss cycles 611system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083326500 # number of ReadReq MSHR miss cycles 612system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002800997 # number of WriteReq MSHR miss cycles 613system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002800997 # number of WriteReq MSHR miss cycles 614system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles 615system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles 616system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles 617system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles 618system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles 619system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles 620system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086127497 # number of demand (read+write) MSHR miss cycles 621system.cpu.dcache.demand_mshr_miss_latency::total 16086127497 # number of demand (read+write) MSHR miss cycles 622system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497317497 # number of overall MSHR miss cycles 623system.cpu.dcache.overall_mshr_miss_latency::total 17497317497 # number of overall MSHR miss cycles 624system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles 625system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles 626system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles 627system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles 628system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles 629system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles 630system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses 631system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses 632system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses 633system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses 634system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses 635system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses 636system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses 637system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses 638system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses 639system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses 640system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses 641system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses 642system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses 643system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses 644system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12659.608407 # average ReadReq mshr miss latency 645system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12659.608407 # average ReadReq mshr miss latency 646system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.465936 # average WriteReq mshr miss latency 647system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.465936 # average WriteReq mshr miss latency 648system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency 649system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency 650system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency 651system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency 652system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency 653system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency 654system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22961.648808 # average overall mshr miss latency 655system.cpu.dcache.demand_avg_mshr_miss_latency::total 22961.648808 # average overall mshr miss latency 656system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21401.640103 # average overall mshr miss latency 657system.cpu.dcache.overall_avg_mshr_miss_latency::total 21401.640103 # average overall mshr miss latency 658system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 659system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 660system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 661system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 662system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 663system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 664system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 665system.cpu.icache.tags.replacements 1699818 # number of replacements 666system.cpu.icache.tags.tagsinuse 510.781939 # Cycle average of tags in use 667system.cpu.icache.tags.total_refs 113905582 # Total number of references to valid blocks. 668system.cpu.icache.tags.sampled_refs 1700330 # Sample count of references to valid blocks. 669system.cpu.icache.tags.avg_refs 66.990280 # Average number of references to valid blocks. 670system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. 671system.cpu.icache.tags.occ_blocks::cpu.inst 510.781939 # Average occupied blocks per requestor 672system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy 673system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy 674system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 675system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 676system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id 677system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id 678system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 679system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 680system.cpu.icache.tags.tag_accesses 117306254 # Number of tag accesses 681system.cpu.icache.tags.data_accesses 117306254 # Number of data accesses 682system.cpu.icache.ReadReq_hits::cpu.inst 113905582 # number of ReadReq hits 683system.cpu.icache.ReadReq_hits::total 113905582 # number of ReadReq hits 684system.cpu.icache.demand_hits::cpu.inst 113905582 # number of demand (read+write) hits 685system.cpu.icache.demand_hits::total 113905582 # number of demand (read+write) hits 686system.cpu.icache.overall_hits::cpu.inst 113905582 # number of overall hits 687system.cpu.icache.overall_hits::total 113905582 # number of overall hits 688system.cpu.icache.ReadReq_misses::cpu.inst 1700336 # number of ReadReq misses 689system.cpu.icache.ReadReq_misses::total 1700336 # number of ReadReq misses 690system.cpu.icache.demand_misses::cpu.inst 1700336 # number of demand (read+write) misses 691system.cpu.icache.demand_misses::total 1700336 # number of demand (read+write) misses 692system.cpu.icache.overall_misses::cpu.inst 1700336 # number of overall misses 693system.cpu.icache.overall_misses::total 1700336 # number of overall misses 694system.cpu.icache.ReadReq_miss_latency::cpu.inst 23242723500 # number of ReadReq miss cycles 695system.cpu.icache.ReadReq_miss_latency::total 23242723500 # number of ReadReq miss cycles 696system.cpu.icache.demand_miss_latency::cpu.inst 23242723500 # number of demand (read+write) miss cycles 697system.cpu.icache.demand_miss_latency::total 23242723500 # number of demand (read+write) miss cycles 698system.cpu.icache.overall_miss_latency::cpu.inst 23242723500 # number of overall miss cycles 699system.cpu.icache.overall_miss_latency::total 23242723500 # number of overall miss cycles 700system.cpu.icache.ReadReq_accesses::cpu.inst 115605918 # number of ReadReq accesses(hits+misses) 701system.cpu.icache.ReadReq_accesses::total 115605918 # number of ReadReq accesses(hits+misses) 702system.cpu.icache.demand_accesses::cpu.inst 115605918 # number of demand (read+write) accesses 703system.cpu.icache.demand_accesses::total 115605918 # number of demand (read+write) accesses 704system.cpu.icache.overall_accesses::cpu.inst 115605918 # number of overall (read+write) accesses 705system.cpu.icache.overall_accesses::total 115605918 # number of overall (read+write) accesses 706system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014708 # miss rate for ReadReq accesses 707system.cpu.icache.ReadReq_miss_rate::total 0.014708 # miss rate for ReadReq accesses 708system.cpu.icache.demand_miss_rate::cpu.inst 0.014708 # miss rate for demand accesses 709system.cpu.icache.demand_miss_rate::total 0.014708 # miss rate for demand accesses 710system.cpu.icache.overall_miss_rate::cpu.inst 0.014708 # miss rate for overall accesses 711system.cpu.icache.overall_miss_rate::total 0.014708 # miss rate for overall accesses 712system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.488560 # average ReadReq miss latency 713system.cpu.icache.ReadReq_avg_miss_latency::total 13669.488560 # average ReadReq miss latency 714system.cpu.icache.demand_avg_miss_latency::cpu.inst 13669.488560 # average overall miss latency 715system.cpu.icache.demand_avg_miss_latency::total 13669.488560 # average overall miss latency 716system.cpu.icache.overall_avg_miss_latency::cpu.inst 13669.488560 # average overall miss latency 717system.cpu.icache.overall_avg_miss_latency::total 13669.488560 # average overall miss latency 718system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 719system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 720system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 721system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 722system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 723system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 724system.cpu.icache.fast_writes 0 # number of fast writes performed 725system.cpu.icache.cache_copies 0 # number of cache copies performed 726system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700336 # number of ReadReq MSHR misses 727system.cpu.icache.ReadReq_mshr_misses::total 1700336 # number of ReadReq MSHR misses 728system.cpu.icache.demand_mshr_misses::cpu.inst 1700336 # number of demand (read+write) MSHR misses 729system.cpu.icache.demand_mshr_misses::total 1700336 # number of demand (read+write) MSHR misses 730system.cpu.icache.overall_mshr_misses::cpu.inst 1700336 # number of overall MSHR misses 731system.cpu.icache.overall_mshr_misses::total 1700336 # number of overall MSHR misses 732system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19835501500 # number of ReadReq MSHR miss cycles 733system.cpu.icache.ReadReq_mshr_miss_latency::total 19835501500 # number of ReadReq MSHR miss cycles 734system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19835501500 # number of demand (read+write) MSHR miss cycles 735system.cpu.icache.demand_mshr_miss_latency::total 19835501500 # number of demand (read+write) MSHR miss cycles 736system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19835501500 # number of overall MSHR miss cycles 737system.cpu.icache.overall_mshr_miss_latency::total 19835501500 # number of overall MSHR miss cycles 738system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles 739system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles 740system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles 741system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles 742system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for ReadReq accesses 743system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014708 # mshr miss rate for ReadReq accesses 744system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for demand accesses 745system.cpu.icache.demand_mshr_miss_rate::total 0.014708 # mshr miss rate for demand accesses 746system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014708 # mshr miss rate for overall accesses 747system.cpu.icache.overall_mshr_miss_rate::total 0.014708 # mshr miss rate for overall accesses 748system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.636380 # average ReadReq mshr miss latency 749system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.636380 # average ReadReq mshr miss latency 750system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11665.636380 # average overall mshr miss latency 751system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.636380 # average overall mshr miss latency 752system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11665.636380 # average overall mshr miss latency 753system.cpu.icache.overall_avg_mshr_miss_latency::total 11665.636380 # average overall mshr miss latency 754system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 755system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 756system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 757system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 758system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 759system.cpu.l2cache.tags.replacements 88869 # number of replacements 760system.cpu.l2cache.tags.tagsinuse 64932.369335 # Cycle average of tags in use 761system.cpu.l2cache.tags.total_refs 2760844 # Total number of references to valid blocks. 762system.cpu.l2cache.tags.sampled_refs 154135 # Sample count of references to valid blocks. 763system.cpu.l2cache.tags.avg_refs 17.911856 # Average number of references to valid blocks. 764system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 765system.cpu.l2cache.tags.occ_blocks::writebacks 50673.822123 # Average occupied blocks per requestor 766system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.809354 # Average occupied blocks per requestor 767system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012212 # Average occupied blocks per requestor 768system.cpu.l2cache.tags.occ_blocks::cpu.inst 9580.724050 # Average occupied blocks per requestor 769system.cpu.l2cache.tags.occ_blocks::cpu.data 4674.001596 # Average occupied blocks per requestor 770system.cpu.l2cache.tags.occ_percent::writebacks 0.773221 # Average percentage of cache occupancy 771system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy 772system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 773system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146190 # Average percentage of cache occupancy 774system.cpu.l2cache.tags.occ_percent::cpu.data 0.071320 # Average percentage of cache occupancy 775system.cpu.l2cache.tags.occ_percent::total 0.990789 # Average percentage of cache occupancy 776system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 777system.cpu.l2cache.tags.occ_task_id_blocks::1024 65261 # Occupied blocks per task id 778system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 779system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 780system.cpu.l2cache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id 781system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2131 # Occupied blocks per task id 782system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6951 # Occupied blocks per task id 783system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56138 # Occupied blocks per task id 784system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 785system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995804 # Percentage of cache occupancy per task id 786system.cpu.l2cache.tags.tag_accesses 26241950 # Number of tag accesses 787system.cpu.l2cache.tags.data_accesses 26241950 # Number of data accesses 788system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7097 # number of ReadReq hits 789system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3700 # number of ReadReq hits 790system.cpu.l2cache.ReadReq_hits::cpu.inst 1682273 # number of ReadReq hits 791system.cpu.l2cache.ReadReq_hits::cpu.data 514821 # number of ReadReq hits 792system.cpu.l2cache.ReadReq_hits::total 2207891 # number of ReadReq hits 793system.cpu.l2cache.Writeback_hits::writebacks 686230 # number of Writeback hits 794system.cpu.l2cache.Writeback_hits::total 686230 # number of Writeback hits 795system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits 796system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits 797system.cpu.l2cache.ReadExReq_hits::cpu.data 166049 # number of ReadExReq hits 798system.cpu.l2cache.ReadExReq_hits::total 166049 # number of ReadExReq hits 799system.cpu.l2cache.demand_hits::cpu.dtb.walker 7097 # number of demand (read+write) hits 800system.cpu.l2cache.demand_hits::cpu.itb.walker 3700 # number of demand (read+write) hits 801system.cpu.l2cache.demand_hits::cpu.inst 1682273 # number of demand (read+write) hits 802system.cpu.l2cache.demand_hits::cpu.data 680870 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::total 2373940 # number of demand (read+write) hits 804system.cpu.l2cache.overall_hits::cpu.dtb.walker 7097 # number of overall hits 805system.cpu.l2cache.overall_hits::cpu.itb.walker 3700 # number of overall hits 806system.cpu.l2cache.overall_hits::cpu.inst 1682273 # number of overall hits 807system.cpu.l2cache.overall_hits::cpu.data 680870 # number of overall hits 808system.cpu.l2cache.overall_hits::total 2373940 # number of overall hits 809system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 810system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 811system.cpu.l2cache.ReadReq_misses::cpu.inst 18039 # number of ReadReq misses 812system.cpu.l2cache.ReadReq_misses::cpu.data 12191 # number of ReadReq misses 813system.cpu.l2cache.ReadReq_misses::total 30239 # number of ReadReq misses 814system.cpu.l2cache.UpgradeReq_misses::cpu.data 2719 # number of UpgradeReq misses 815system.cpu.l2cache.UpgradeReq_misses::total 2719 # number of UpgradeReq misses 816system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 817system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 818system.cpu.l2cache.ReadExReq_misses::cpu.data 130235 # number of ReadExReq misses 819system.cpu.l2cache.ReadExReq_misses::total 130235 # number of ReadExReq misses 820system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 821system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 822system.cpu.l2cache.demand_misses::cpu.inst 18039 # number of demand (read+write) misses 823system.cpu.l2cache.demand_misses::cpu.data 142426 # number of demand (read+write) misses 824system.cpu.l2cache.demand_misses::total 160474 # number of demand (read+write) misses 825system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 826system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 827system.cpu.l2cache.overall_misses::cpu.inst 18039 # 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number of overall (read+write) accesses 871system.cpu.l2cache.overall_accesses::cpu.inst 1700312 # number of overall (read+write) accesses 872system.cpu.l2cache.overall_accesses::cpu.data 823296 # number of overall (read+write) accesses 873system.cpu.l2cache.overall_accesses::total 2534414 # number of overall (read+write) accesses 874system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000985 # miss rate for ReadReq accesses 875system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000540 # miss rate for ReadReq accesses 876system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010609 # miss rate for ReadReq accesses 877system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023132 # miss rate for ReadReq accesses 878system.cpu.l2cache.ReadReq_miss_rate::total 0.013511 # miss rate for ReadReq accesses 879system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991612 # miss rate for UpgradeReq accesses 880system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991612 # miss rate for UpgradeReq accesses 881system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 882system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 883system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.439561 # miss rate for ReadExReq accesses 884system.cpu.l2cache.ReadExReq_miss_rate::total 0.439561 # miss rate for ReadExReq accesses 885system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000985 # miss rate for demand accesses 886system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000540 # miss rate for demand accesses 887system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010609 # miss rate for demand accesses 888system.cpu.l2cache.demand_miss_rate::cpu.data 0.172995 # miss rate for demand accesses 889system.cpu.l2cache.demand_miss_rate::total 0.063318 # miss rate for demand accesses 890system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000985 # miss rate for overall accesses 891system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000540 # miss rate for overall accesses 892system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010609 # miss rate for overall accesses 893system.cpu.l2cache.overall_miss_rate::cpu.data 0.172995 # miss rate for overall accesses 894system.cpu.l2cache.overall_miss_rate::total 0.063318 # miss rate for overall accesses 895system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 81107.142857 # average ReadReq miss latency 896system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency 897system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72753.062808 # average ReadReq miss latency 898system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75327.967353 # average ReadReq miss latency 899system.cpu.l2cache.ReadReq_avg_miss_latency::total 73793.214061 # average ReadReq miss latency 900system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 172.114748 # average UpgradeReq miss latency 901system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 172.114748 # average UpgradeReq miss latency 902system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 23499 # average SCUpgradeReq miss latency 903system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 23499 # average SCUpgradeReq miss latency 904system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68972.574316 # average ReadExReq miss latency 905system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68972.574316 # average ReadExReq miss latency 906system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency 907system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 908system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72753.062808 # average overall miss latency 909system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69516.566259 # average overall miss latency 910system.cpu.l2cache.demand_avg_miss_latency::total 69880.954024 # average overall miss latency 911system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 81107.142857 # average overall miss latency 912system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency 913system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72753.062808 # average overall miss latency 914system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69516.566259 # average overall miss latency 915system.cpu.l2cache.overall_avg_miss_latency::total 69880.954024 # average overall miss latency 916system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 917system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 918system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 919system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 920system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 921system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 922system.cpu.l2cache.fast_writes 0 # number of fast writes performed 923system.cpu.l2cache.cache_copies 0 # number of cache copies performed 924system.cpu.l2cache.writebacks::writebacks 82180 # number of writebacks 925system.cpu.l2cache.writebacks::total 82180 # number of writebacks 926system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses 927system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses 928system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18039 # number of ReadReq MSHR misses 929system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12191 # number of ReadReq MSHR misses 930system.cpu.l2cache.ReadReq_mshr_misses::total 30239 # number of ReadReq MSHR misses 931system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2719 # number of UpgradeReq MSHR misses 932system.cpu.l2cache.UpgradeReq_mshr_misses::total 2719 # number of UpgradeReq MSHR misses 933system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 934system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 935system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130235 # number of ReadExReq MSHR misses 936system.cpu.l2cache.ReadExReq_mshr_misses::total 130235 # number of ReadExReq MSHR misses 937system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses 938system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses 939system.cpu.l2cache.demand_mshr_misses::cpu.inst 18039 # number of demand (read+write) MSHR misses 940system.cpu.l2cache.demand_mshr_misses::cpu.data 142426 # number of demand (read+write) MSHR misses 941system.cpu.l2cache.demand_mshr_misses::total 160474 # number of demand (read+write) MSHR misses 942system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses 943system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses 944system.cpu.l2cache.overall_mshr_misses::cpu.inst 18039 # number of overall MSHR misses 945system.cpu.l2cache.overall_mshr_misses::cpu.data 142426 # number of overall MSHR misses 946system.cpu.l2cache.overall_mshr_misses::total 160474 # number of overall MSHR misses 947system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 480750 # number of ReadReq MSHR miss cycles 948system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles 949system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1086559000 # number of ReadReq MSHR miss cycles 950system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 766168250 # number of ReadReq MSHR miss cycles 951system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1853333000 # number of ReadReq MSHR miss cycles 952system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27220719 # number of UpgradeReq MSHR miss cycles 953system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27220719 # number of UpgradeReq MSHR miss cycles 954system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 20002 # number of SCUpgradeReq MSHR miss cycles 955system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles 956system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7352907784 # number of ReadExReq MSHR miss cycles 957system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7352907784 # number of ReadExReq MSHR miss cycles 958system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 480750 # number of demand (read+write) MSHR miss cycles 959system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles 960system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1086559000 # number of demand (read+write) MSHR miss cycles 961system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8119076034 # number of demand (read+write) MSHR miss cycles 962system.cpu.l2cache.demand_mshr_miss_latency::total 9206240784 # number of demand (read+write) MSHR miss cycles 963system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 480750 # number of overall MSHR miss cycles 964system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles 965system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1086559000 # number of overall MSHR miss cycles 966system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8119076034 # number of overall MSHR miss cycles 967system.cpu.l2cache.overall_mshr_miss_latency::total 9206240784 # number of overall MSHR miss cycles 968system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles 969system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385932000 # number of ReadReq MSHR uncacheable cycles 970system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860147000 # number of ReadReq MSHR uncacheable cycles 971system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098166000 # number of WriteReq MSHR uncacheable cycles 972system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098166000 # number of WriteReq MSHR uncacheable cycles 973system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles 974system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484098000 # number of overall MSHR uncacheable cycles 975system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958313000 # number of overall MSHR uncacheable cycles 976system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for ReadReq accesses 977system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for ReadReq accesses 978system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for ReadReq accesses 979system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023132 # mshr miss rate for ReadReq accesses 980system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013511 # mshr miss rate for ReadReq accesses 981system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991612 # mshr miss rate for UpgradeReq accesses 982system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991612 # mshr miss rate for UpgradeReq accesses 983system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 984system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 985system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439561 # mshr miss rate for ReadExReq accesses 986system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439561 # mshr miss rate for ReadExReq accesses 987system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for demand accesses 988system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for demand accesses 989system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for demand accesses 990system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172995 # mshr miss rate for demand accesses 991system.cpu.l2cache.demand_mshr_miss_rate::total 0.063318 # mshr miss rate for demand accesses 992system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000985 # mshr miss rate for overall accesses 993system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000540 # mshr miss rate for overall accesses 994system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010609 # mshr miss rate for overall accesses 995system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172995 # mshr miss rate for overall accesses 996system.cpu.l2cache.overall_mshr_miss_rate::total 0.063318 # mshr miss rate for overall accesses 997system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average ReadReq mshr miss latency 998system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency 999system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60233.882144 # average ReadReq mshr miss latency 1000system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62847.038799 # average ReadReq mshr miss latency 1001system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61289.493700 # average ReadReq mshr miss latency 1002system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10011.297904 # average UpgradeReq mshr miss latency 1003system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10011.297904 # average UpgradeReq mshr miss latency 1004system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency 1005system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency 1006system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56458.769025 # average ReadExReq mshr miss latency 1007system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56458.769025 # average ReadExReq mshr miss latency 1008system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency 1009system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1010system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency 1011system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency 1012system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency 1013system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 68678.571429 # average overall mshr miss latency 1014system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency 1015system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60233.882144 # average overall mshr miss latency 1016system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57005.575064 # average overall mshr miss latency 1017system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57369.049092 # average overall mshr miss latency 1018system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency 1019system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1020system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1021system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1022system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1023system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency 1024system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1025system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1026system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1027system.cpu.toL2Bus.trans_dist::ReadReq 2294825 # Transaction distribution 1028system.cpu.toL2Bus.trans_dist::ReadResp 2294810 # Transaction distribution 1029system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution 1030system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution 1031system.cpu.toL2Bus.trans_dist::Writeback 686230 # Transaction distribution 1032system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution 1033system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution 1034system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1035system.cpu.toL2Bus.trans_dist::UpgradeResp 2744 # Transaction distribution 1036system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution 1037system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution 1038system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes) 1039system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456073 # Packet count per connected master and slave (bytes) 1040system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes) 1041system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes) 1042system.cpu.toL2Bus.pkt_count::total 5912638 # Packet count per connected master and slave (bytes) 1043system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes) 1044system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96806921 # Cumulative packet size per connected master and slave (bytes) 1045system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes) 1046system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes) 1047system.cpu.toL2Bus.pkt_size::total 205706201 # Cumulative packet size per connected master and slave (bytes) 1048system.cpu.toL2Bus.snoops 52963 # Total snoops (count) 1049system.cpu.toL2Bus.snoop_fanout::samples 3276132 # Request fanout histogram 1050system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram 1051system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram 1052system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1053system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1054system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1055system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1056system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1057system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1058system.cpu.toL2Bus.snoop_fanout::5 3239673 98.89% 98.89% # Request fanout histogram 1059system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram 1060system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1061system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1062system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1063system.cpu.toL2Bus.snoop_fanout::total 3276132 # Request fanout histogram 1064system.cpu.toL2Bus.reqLayer0.occupancy 2353772500 # Layer occupancy (ticks) 1065system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1066system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) 1067system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1068system.cpu.toL2Bus.respLayer0.occupancy 2564911000 # Layer occupancy (ticks) 1069system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1070system.cpu.toL2Bus.respLayer1.occupancy 1311851755 # Layer occupancy (ticks) 1071system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1072system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) 1073system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1074system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks) 1075system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1076system.iobus.trans_dist::ReadReq 30195 # Transaction distribution 1077system.iobus.trans_dist::ReadResp 30195 # Transaction distribution 1078system.iobus.trans_dist::WriteReq 59038 # Transaction distribution 1079system.iobus.trans_dist::WriteResp 59038 # Transaction distribution 1080system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) 1081system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 1082system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1083system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1084system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 1085system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 1086system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1087system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1088system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1089system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1090system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1091system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1092system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1093system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1094system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1095system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1096system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1097system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1098system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1099system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1100system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1101system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) 1102system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) 1103system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) 1104system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) 1105system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) 1106system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 1107system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1108system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1109system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 1110system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 1111system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1112system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1113system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1114system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1115system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1116system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1117system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1118system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1119system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1120system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1121system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1122system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1123system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1124system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1125system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1126system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) 1127system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) 1128system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) 1129system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) 1130system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) 1131system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1132system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) 1133system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1134system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) 1135system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1136system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) 1137system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1138system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) 1139system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1140system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) 1141system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1142system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) 1143system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1144system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1145system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1146system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1147system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1148system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1149system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1150system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) 1151system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1152system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1153system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1154system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) 1155system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1156system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) 1157system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1158system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) 1159system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1160system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) 1161system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 1162system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) 1163system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1164system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) 1165system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1166system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) 1167system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1168system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) 1169system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1170system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) 1171system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1172system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1173system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1174system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) 1175system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1176system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks) 1177system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1178system.iocache.tags.replacements 36424 # number of replacements 1179system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use 1180system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1181system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. 1182system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1183system.iocache.tags.warmup_cycle 298397241000 # Cycle when the warmup percentage was hit. 1184system.iocache.tags.occ_blocks::realview.ide 1.133398 # Average occupied blocks per requestor 1185system.iocache.tags.occ_percent::realview.ide 0.070837 # Average percentage of cache occupancy 1186system.iocache.tags.occ_percent::total 0.070837 # Average percentage of cache occupancy 1187system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1188system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1189system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1190system.iocache.tags.tag_accesses 328122 # Number of tag accesses 1191system.iocache.tags.data_accesses 328122 # Number of data accesses 1192system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 1193system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 1194system.iocache.ReadReq_misses::realview.ide 234 # number of ReadReq misses 1195system.iocache.ReadReq_misses::total 234 # number of ReadReq misses 1196system.iocache.demand_misses::realview.ide 234 # number of demand (read+write) misses 1197system.iocache.demand_misses::total 234 # number of demand (read+write) misses 1198system.iocache.overall_misses::realview.ide 234 # number of overall misses 1199system.iocache.overall_misses::total 234 # number of overall misses 1200system.iocache.ReadReq_miss_latency::realview.ide 28038377 # number of ReadReq miss cycles 1201system.iocache.ReadReq_miss_latency::total 28038377 # number of ReadReq miss cycles 1202system.iocache.demand_miss_latency::realview.ide 28038377 # number of demand (read+write) miss cycles 1203system.iocache.demand_miss_latency::total 28038377 # number of demand (read+write) miss cycles 1204system.iocache.overall_miss_latency::realview.ide 28038377 # number of overall miss cycles 1205system.iocache.overall_miss_latency::total 28038377 # number of overall miss cycles 1206system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) 1207system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) 1208system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 1209system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 1210system.iocache.demand_accesses::realview.ide 234 # number of demand (read+write) accesses 1211system.iocache.demand_accesses::total 234 # number of demand (read+write) accesses 1212system.iocache.overall_accesses::realview.ide 234 # number of overall (read+write) accesses 1213system.iocache.overall_accesses::total 234 # number of overall (read+write) accesses 1214system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1215system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1216system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1217system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1218system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1219system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1220system.iocache.ReadReq_avg_miss_latency::realview.ide 119822.123932 # average ReadReq miss latency 1221system.iocache.ReadReq_avg_miss_latency::total 119822.123932 # average ReadReq miss latency 1222system.iocache.demand_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency 1223system.iocache.demand_avg_miss_latency::total 119822.123932 # average overall miss latency 1224system.iocache.overall_avg_miss_latency::realview.ide 119822.123932 # average overall miss latency 1225system.iocache.overall_avg_miss_latency::total 119822.123932 # average overall miss latency 1226system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1227system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1228system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1229system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1230system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1231system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1232system.iocache.fast_writes 36224 # number of fast writes performed 1233system.iocache.cache_copies 0 # number of cache copies performed 1234system.iocache.ReadReq_mshr_misses::realview.ide 234 # number of ReadReq MSHR misses 1235system.iocache.ReadReq_mshr_misses::total 234 # number of ReadReq MSHR misses 1236system.iocache.demand_mshr_misses::realview.ide 234 # number of demand (read+write) MSHR misses 1237system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses 1238system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses 1239system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses 1240system.iocache.ReadReq_mshr_miss_latency::realview.ide 15869377 # number of ReadReq MSHR miss cycles 1241system.iocache.ReadReq_mshr_miss_latency::total 15869377 # number of ReadReq MSHR miss cycles 1242system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2206856981 # number of WriteInvalidateReq MSHR miss cycles 1243system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2206856981 # number of WriteInvalidateReq MSHR miss cycles 1244system.iocache.demand_mshr_miss_latency::realview.ide 15869377 # number of demand (read+write) MSHR miss cycles 1245system.iocache.demand_mshr_miss_latency::total 15869377 # number of demand (read+write) MSHR miss cycles 1246system.iocache.overall_mshr_miss_latency::realview.ide 15869377 # number of overall MSHR miss cycles 1247system.iocache.overall_mshr_miss_latency::total 15869377 # number of overall MSHR miss cycles 1248system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1249system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1250system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1251system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1252system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1253system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1254system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67817.850427 # average ReadReq mshr miss latency 1255system.iocache.ReadReq_avg_mshr_miss_latency::total 67817.850427 # average ReadReq mshr miss latency 1256system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency 1257system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency 1258system.iocache.demand_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency 1259system.iocache.demand_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency 1260system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency 1261system.iocache.overall_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency 1262system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1263system.membus.trans_dist::ReadReq 70649 # Transaction distribution 1264system.membus.trans_dist::ReadResp 70649 # Transaction distribution 1265system.membus.trans_dist::WriteReq 27618 # Transaction distribution 1266system.membus.trans_dist::WriteResp 27618 # Transaction distribution 1267system.membus.trans_dist::Writeback 82180 # Transaction distribution 1268system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 1269system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 1270system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution 1271system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1272system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution 1273system.membus.trans_dist::ReadExReq 128451 # Transaction distribution 1274system.membus.trans_dist::ReadExResp 128451 # Transaction distribution 1275system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) 1276system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 1277system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) 1278system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes) 1279system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes) 1280system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) 1281system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) 1282system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes) 1283system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) 1284system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 1285system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) 1286system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes) 1287system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes) 1288system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) 1289system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) 1290system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes) 1291system.membus.snoops 219 # Total snoops (count) 1292system.membus.snoop_fanout::samples 281834 # Request fanout histogram 1293system.membus.snoop_fanout::mean 1 # Request fanout histogram 1294system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1295system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1296system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1297system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram 1298system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1299system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1300system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1301system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1302system.membus.snoop_fanout::total 281834 # Request fanout histogram 1303system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks) 1304system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1305system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) 1306system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1307system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks) 1308system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1309system.membus.reqLayer5.occupancy 1264017500 # Layer occupancy (ticks) 1310system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1311system.membus.respLayer2.occupancy 1594856995 # Layer occupancy (ticks) 1312system.membus.respLayer2.utilization 0.1 # Layer utilization (%) 1313system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks) 1314system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1315system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1316system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1317system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1318system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1319system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1320system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1321system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1322system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1323system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1324system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1325system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1326system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1327system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1328system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1329system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1330system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1331system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1332system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1333system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1334system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1335system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1336system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1337system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1338system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1339system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1340system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1341system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1342system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1343system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1344system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1345system.realview.ethernet.droppedPackets 0 # number of packets dropped 1346 1347---------- End Simulation Statistics ---------- 1348