stats.txt revision 9620:89aa34e10625
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.183438 # Number of seconds simulated 4sim_ticks 1183437503500 # Number of ticks simulated 5final_tick 1183437503500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 462248 # Simulator instruction rate (inst/s) 8host_op_rate 589061 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 8900686287 # Simulator tick rate (ticks/s) 10host_mem_usage 440324 # Number of bytes of host memory used 11host_seconds 132.96 # Real time elapsed on the host 12sim_insts 61460532 # Number of instructions simulated 13sim_ops 78321652 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 393828 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 4708980 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 4819184 # Number of bytes read from this memory 22system.physmem.bytes_read::total 62150116 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 393828 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 716992 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4119552 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7146896 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 12372 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 73650 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 75326 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 6654550 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 64368 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 821204 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43859107 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 332783 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 3979069 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 273072 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 4072191 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 52516602 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 332783 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 273072 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 605855 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 3481005 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 14365 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 2543729 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 6039099 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 3481005 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43859107 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 332783 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 3993434 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 273072 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 6615920 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 58555700 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.readReqs 6654550 # Total number of read requests seen 70system.physmem.writeReqs 821204 # Total number of write requests seen 71system.physmem.cpureqs 235817 # Reqs generatd by CPU via cache - shady 72system.physmem.bytesRead 425891200 # Total number of bytes read from memory 73system.physmem.bytesWritten 52557056 # Total number of bytes written to memory 74system.physmem.bytesConsumedRd 62150116 # bytesRead derated as per pkt->getSize() 75system.physmem.bytesConsumedWr 7146896 # bytesWritten derated as per pkt->getSize() 76system.physmem.servicedByWrQ 97 # Number of read reqs serviced by write Q 77system.physmem.neitherReadNorWrite 11788 # Reqs where no action is needed 78system.physmem.perBankRdReqs::0 422295 # Track reads on a per bank basis 79system.physmem.perBankRdReqs::1 415695 # Track reads on a per bank basis 80system.physmem.perBankRdReqs::2 415259 # Track reads on a per bank basis 81system.physmem.perBankRdReqs::3 415928 # Track reads on a per bank basis 82system.physmem.perBankRdReqs::4 415873 # Track reads on a per bank basis 83system.physmem.perBankRdReqs::5 415149 # Track reads on a per bank basis 84system.physmem.perBankRdReqs::6 415167 # Track reads on a per bank basis 85system.physmem.perBankRdReqs::7 415977 # Track reads on a per bank basis 86system.physmem.perBankRdReqs::8 415766 # Track reads on a per bank basis 87system.physmem.perBankRdReqs::9 415145 # Track reads on a per bank basis 88system.physmem.perBankRdReqs::10 415183 # Track reads on a per bank basis 89system.physmem.perBankRdReqs::11 415709 # Track reads on a per bank basis 90system.physmem.perBankRdReqs::12 415657 # Track reads on a per bank basis 91system.physmem.perBankRdReqs::13 415044 # Track reads on a per bank basis 92system.physmem.perBankRdReqs::14 414930 # Track reads on a per bank basis 93system.physmem.perBankRdReqs::15 415676 # Track reads on a per bank basis 94system.physmem.perBankWrReqs::0 51328 # Track writes on a per bank basis 95system.physmem.perBankWrReqs::1 51156 # Track writes on a per bank basis 96system.physmem.perBankWrReqs::2 50890 # Track writes on a per bank basis 97system.physmem.perBankWrReqs::3 51482 # Track writes on a per bank basis 98system.physmem.perBankWrReqs::4 51387 # Track writes on a per bank basis 99system.physmem.perBankWrReqs::5 50754 # Track writes on a per bank basis 100system.physmem.perBankWrReqs::6 50751 # Track writes on a per bank basis 101system.physmem.perBankWrReqs::7 51440 # Track writes on a per bank basis 102system.physmem.perBankWrReqs::8 51875 # Track writes on a per bank basis 103system.physmem.perBankWrReqs::9 51227 # Track writes on a per bank basis 104system.physmem.perBankWrReqs::10 51302 # Track writes on a per bank basis 105system.physmem.perBankWrReqs::11 51806 # Track writes on a per bank basis 106system.physmem.perBankWrReqs::12 51729 # Track writes on a per bank basis 107system.physmem.perBankWrReqs::13 51213 # Track writes on a per bank basis 108system.physmem.perBankWrReqs::14 51075 # Track writes on a per bank basis 109system.physmem.perBankWrReqs::15 51789 # Track writes on a per bank basis 110system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 111system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 112system.physmem.totGap 1183433014000 # Total gap between requests 113system.physmem.readPktSize::0 0 # Categorize read packet sizes 114system.physmem.readPktSize::1 0 # Categorize read packet sizes 115system.physmem.readPktSize::2 6825 # Categorize read packet sizes 116system.physmem.readPktSize::3 6488064 # Categorize read packet sizes 117system.physmem.readPktSize::4 0 # Categorize read packet sizes 118system.physmem.readPktSize::5 0 # Categorize read packet sizes 119system.physmem.readPktSize::6 159661 # Categorize read packet sizes 120system.physmem.writePktSize::0 0 # Categorize write packet sizes 121system.physmem.writePktSize::1 0 # Categorize write packet sizes 122system.physmem.writePktSize::2 756836 # Categorize write packet sizes 123system.physmem.writePktSize::3 0 # Categorize write packet sizes 124system.physmem.writePktSize::4 0 # Categorize write packet sizes 125system.physmem.writePktSize::5 0 # Categorize write packet sizes 126system.physmem.writePktSize::6 64368 # Categorize write packet sizes 127system.physmem.rdQLenPdf::0 571102 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::1 408461 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::2 415701 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::3 1537889 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::4 1165282 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::5 1169319 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::6 1141412 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::7 29559 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::8 27546 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::9 48416 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::10 68998 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::11 48154 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::12 5894 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::13 5718 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::14 5549 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::15 5372 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::16 81 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 159system.physmem.wrQLenPdf::0 35455 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::1 35679 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::2 35685 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::3 35691 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::4 35695 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::5 35695 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::7 35705 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::8 35705 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::9 35705 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::10 35705 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::11 35705 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::12 35704 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::13 35704 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::14 35704 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::15 35704 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::16 35704 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::17 35704 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::18 35704 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::19 35704 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::20 35704 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::21 35704 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::22 35704 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::23 250 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::24 26 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::25 20 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::26 14 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::28 10 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 191system.physmem.totQLat 147040385750 # Total cycles spent in queuing delays 192system.physmem.totMemAccLat 189361608250 # Sum of mem lat for all requests 193system.physmem.totBusLat 33272265000 # Total cycles spent in databus access 194system.physmem.totBankLat 9048957500 # Total cycles spent in bank access 195system.physmem.avgQLat 22096.54 # Average queueing delay per request 196system.physmem.avgBankLat 1359.83 # Average bank access latency per request 197system.physmem.avgBusLat 5000.00 # Average bus latency per request 198system.physmem.avgMemAccLat 28456.37 # Average memory access latency 199system.physmem.avgRdBW 359.88 # Average achieved read bandwidth in MB/s 200system.physmem.avgWrBW 44.41 # Average achieved write bandwidth in MB/s 201system.physmem.avgConsumedRdBW 52.52 # Average consumed read bandwidth in MB/s 202system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s 203system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 204system.physmem.busUtil 3.16 # Data bus utilization in percentage 205system.physmem.avgRdQLen 0.16 # Average read queue length over time 206system.physmem.avgWrQLen 11.75 # Average write queue length over time 207system.physmem.readRowHits 6612404 # Number of row buffer hits during reads 208system.physmem.writeRowHits 800418 # Number of row buffer hits during writes 209system.physmem.readRowHitRate 99.37 # Row buffer hit rate for reads 210system.physmem.writeRowHitRate 97.47 # Row buffer hit rate for writes 211system.physmem.avgGap 158302.83 # Average gap between requests 212system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 213system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 214system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 215system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 216system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 217system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 218system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 219system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 220system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 221system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 222system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) 223system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 224system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 225system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) 226system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 227system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 228system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) 229system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) 230system.l2c.replacements 69541 # number of replacements 231system.l2c.tagsinuse 53035.489918 # Cycle average of tags in use 232system.l2c.total_refs 1672596 # Total number of references to valid blocks. 233system.l2c.sampled_refs 134740 # Sample count of references to valid blocks. 234system.l2c.avg_refs 12.413507 # Average number of references to valid blocks. 235system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 236system.l2c.occ_blocks::writebacks 40180.165903 # Average occupied blocks per requestor 237system.l2c.occ_blocks::cpu0.dtb.walker 0.000406 # Average occupied blocks per requestor 238system.l2c.occ_blocks::cpu0.itb.walker 0.001420 # Average occupied blocks per requestor 239system.l2c.occ_blocks::cpu0.inst 3726.817906 # Average occupied blocks per requestor 240system.l2c.occ_blocks::cpu0.data 4242.402809 # Average occupied blocks per requestor 241system.l2c.occ_blocks::cpu1.dtb.walker 2.742182 # Average occupied blocks per requestor 242system.l2c.occ_blocks::cpu1.inst 2823.857423 # Average occupied blocks per requestor 243system.l2c.occ_blocks::cpu1.data 2059.501869 # Average occupied blocks per requestor 244system.l2c.occ_percent::writebacks 0.613101 # Average percentage of cache occupancy 245system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 246system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 247system.l2c.occ_percent::cpu0.inst 0.056867 # Average percentage of cache occupancy 248system.l2c.occ_percent::cpu0.data 0.064734 # Average percentage of cache occupancy 249system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy 250system.l2c.occ_percent::cpu1.inst 0.043089 # Average percentage of cache occupancy 251system.l2c.occ_percent::cpu1.data 0.031426 # Average percentage of cache occupancy 252system.l2c.occ_percent::total 0.809257 # Average percentage of cache occupancy 253system.l2c.ReadReq_hits::cpu0.dtb.walker 3941 # number of ReadReq hits 254system.l2c.ReadReq_hits::cpu0.itb.walker 1769 # number of ReadReq hits 255system.l2c.ReadReq_hits::cpu0.inst 419774 # number of ReadReq hits 256system.l2c.ReadReq_hits::cpu0.data 205645 # number of ReadReq hits 257system.l2c.ReadReq_hits::cpu1.dtb.walker 5809 # number of ReadReq hits 258system.l2c.ReadReq_hits::cpu1.itb.walker 2015 # number of ReadReq hits 259system.l2c.ReadReq_hits::cpu1.inst 464124 # number of ReadReq hits 260system.l2c.ReadReq_hits::cpu1.data 143605 # number of ReadReq hits 261system.l2c.ReadReq_hits::total 1246682 # number of ReadReq hits 262system.l2c.Writeback_hits::writebacks 571448 # number of Writeback hits 263system.l2c.Writeback_hits::total 571448 # number of Writeback hits 264system.l2c.UpgradeReq_hits::cpu0.data 1206 # number of UpgradeReq hits 265system.l2c.UpgradeReq_hits::cpu1.data 615 # number of UpgradeReq hits 266system.l2c.UpgradeReq_hits::total 1821 # number of UpgradeReq hits 267system.l2c.SCUpgradeReq_hits::cpu0.data 214 # number of SCUpgradeReq hits 268system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits 269system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits 270system.l2c.ReadExReq_hits::cpu0.data 56897 # number of ReadExReq hits 271system.l2c.ReadExReq_hits::cpu1.data 52477 # number of ReadExReq hits 272system.l2c.ReadExReq_hits::total 109374 # number of ReadExReq hits 273system.l2c.demand_hits::cpu0.dtb.walker 3941 # number of demand (read+write) hits 274system.l2c.demand_hits::cpu0.itb.walker 1769 # number of demand (read+write) hits 275system.l2c.demand_hits::cpu0.inst 419774 # number of demand (read+write) hits 276system.l2c.demand_hits::cpu0.data 262542 # number of demand (read+write) hits 277system.l2c.demand_hits::cpu1.dtb.walker 5809 # number of demand (read+write) hits 278system.l2c.demand_hits::cpu1.itb.walker 2015 # number of demand (read+write) hits 279system.l2c.demand_hits::cpu1.inst 464124 # number of demand (read+write) hits 280system.l2c.demand_hits::cpu1.data 196082 # number of demand (read+write) hits 281system.l2c.demand_hits::total 1356056 # number of demand (read+write) hits 282system.l2c.overall_hits::cpu0.dtb.walker 3941 # number of overall hits 283system.l2c.overall_hits::cpu0.itb.walker 1769 # number of overall hits 284system.l2c.overall_hits::cpu0.inst 419774 # number of overall hits 285system.l2c.overall_hits::cpu0.data 262542 # number of overall hits 286system.l2c.overall_hits::cpu1.dtb.walker 5809 # number of overall hits 287system.l2c.overall_hits::cpu1.itb.walker 2015 # number of overall hits 288system.l2c.overall_hits::cpu1.inst 464124 # number of overall hits 289system.l2c.overall_hits::cpu1.data 196082 # number of overall hits 290system.l2c.overall_hits::total 1356056 # number of overall hits 291system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 292system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 293system.l2c.ReadReq_misses::cpu0.inst 5740 # number of ReadReq misses 294system.l2c.ReadReq_misses::cpu0.data 7867 # number of ReadReq misses 295system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses 296system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses 297system.l2c.ReadReq_misses::cpu1.data 3619 # number of ReadReq misses 298system.l2c.ReadReq_misses::total 22277 # number of ReadReq misses 299system.l2c.UpgradeReq_misses::cpu0.data 4714 # number of UpgradeReq misses 300system.l2c.UpgradeReq_misses::cpu1.data 3582 # number of UpgradeReq misses 301system.l2c.UpgradeReq_misses::total 8296 # number of UpgradeReq misses 302system.l2c.SCUpgradeReq_misses::cpu0.data 566 # number of SCUpgradeReq misses 303system.l2c.SCUpgradeReq_misses::cpu1.data 479 # number of SCUpgradeReq misses 304system.l2c.SCUpgradeReq_misses::total 1045 # number of SCUpgradeReq misses 305system.l2c.ReadExReq_misses::cpu0.data 67030 # number of ReadExReq misses 306system.l2c.ReadExReq_misses::cpu1.data 72802 # number of ReadExReq misses 307system.l2c.ReadExReq_misses::total 139832 # number of ReadExReq misses 308system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 309system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 310system.l2c.demand_misses::cpu0.inst 5740 # number of demand (read+write) misses 311system.l2c.demand_misses::cpu0.data 74897 # number of demand (read+write) misses 312system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses 313system.l2c.demand_misses::cpu1.inst 5044 # number of demand (read+write) misses 314system.l2c.demand_misses::cpu1.data 76421 # number of demand (read+write) misses 315system.l2c.demand_misses::total 162109 # number of demand (read+write) misses 316system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 317system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 318system.l2c.overall_misses::cpu0.inst 5740 # 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number of ReadReq MSHR uncacheable cycles 547system.l2c.ReadReq_mshr_uncacheable_latency::total 166993547320 # number of ReadReq MSHR uncacheable cycles 548system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000474745 # number of WriteReq MSHR uncacheable cycles 549system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8209478823 # number of WriteReq MSHR uncacheable cycles 550system.l2c.WriteReq_mshr_uncacheable_latency::total 9209953568 # number of WriteReq MSHR uncacheable cycles 551system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 209633632 # number of overall MSHR uncacheable cycles 552system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13455227070 # number of overall MSHR uncacheable cycles 553system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3167837 # number of overall MSHR uncacheable cycles 554system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162535472349 # number of overall MSHR uncacheable cycles 555system.l2c.overall_mshr_uncacheable_latency::total 176203500888 # number of overall MSHR uncacheable cycles 556system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000254 # mshr miss rate for ReadReq accesses 557system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001129 # mshr miss rate for ReadReq accesses 558system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013487 # mshr miss rate for ReadReq accesses 559system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036846 # mshr miss rate for ReadReq accesses 560system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for ReadReq accesses 561system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010751 # mshr miss rate for ReadReq accesses 562system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for ReadReq accesses 563system.l2c.ReadReq_mshr_miss_rate::total 0.017555 # mshr miss rate for ReadReq accesses 564system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.796284 # mshr miss rate for UpgradeReq accesses 565system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.853467 # mshr miss rate for UpgradeReq accesses 566system.l2c.UpgradeReq_mshr_miss_rate::total 0.820006 # mshr miss rate for UpgradeReq accesses 567system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.725641 # mshr miss rate for SCUpgradeReq accesses 568system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.821612 # mshr miss rate for SCUpgradeReq accesses 569system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.766691 # mshr miss rate for SCUpgradeReq accesses 570system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.540883 # mshr miss rate for ReadExReq accesses 571system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.581119 # mshr miss rate for ReadExReq accesses 572system.l2c.ReadExReq_mshr_miss_rate::total 0.561110 # mshr miss rate for ReadExReq accesses 573system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000254 # mshr miss rate for demand accesses 574system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001129 # mshr miss rate for demand accesses 575system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013487 # mshr miss rate for demand accesses 576system.l2c.demand_mshr_miss_rate::cpu0.data 0.221957 # mshr miss rate for demand accesses 577system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for demand accesses 578system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010751 # mshr miss rate for demand accesses 579system.l2c.demand_mshr_miss_rate::cpu1.data 0.280441 # mshr miss rate for demand accesses 580system.l2c.demand_mshr_miss_rate::total 0.106779 # mshr miss rate for demand accesses 581system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000254 # mshr miss rate for overall accesses 582system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001129 # mshr miss rate for overall accesses 583system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013487 # mshr miss rate for overall accesses 584system.l2c.overall_mshr_miss_rate::cpu0.data 0.221957 # mshr miss rate for overall accesses 585system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for overall accesses 586system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010751 # mshr miss rate for overall accesses 587system.l2c.overall_mshr_miss_rate::cpu1.data 0.280441 # mshr miss rate for overall accesses 588system.l2c.overall_mshr_miss_rate::total 0.106779 # mshr miss rate for overall accesses 589system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average ReadReq mshr miss latency 590system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average ReadReq mshr miss latency 591system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average ReadReq mshr miss latency 592system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40843.505784 # average ReadReq mshr miss latency 593system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average ReadReq mshr miss latency 594system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average ReadReq mshr miss latency 595system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 48989.739983 # average ReadReq mshr miss latency 596system.l2c.ReadReq_avg_mshr_miss_latency::total 42289.325058 # average ReadReq mshr miss latency 597system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10024.534578 # average UpgradeReq mshr miss latency 598system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10033.376047 # average UpgradeReq mshr miss latency 599system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10028.352097 # average UpgradeReq mshr miss latency 600system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10033.666078 # average SCUpgradeReq mshr miss latency 601system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.524008 # average SCUpgradeReq mshr miss latency 602system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.434450 # average SCUpgradeReq mshr miss latency 603system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 32591.685499 # average ReadExReq mshr miss latency 604system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34860.480797 # average ReadExReq mshr miss latency 605system.l2c.ReadExReq_avg_mshr_miss_latency::total 33772.908934 # average ReadExReq mshr miss latency 606system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency 607system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency 608system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average overall mshr miss latency 609system.l2c.demand_avg_mshr_miss_latency::cpu0.data 33458.436773 # average overall mshr miss latency 610system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency 611system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average overall mshr miss latency 612system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35529.587312 # average overall mshr miss latency 613system.l2c.demand_avg_mshr_miss_latency::total 34943.188535 # average overall mshr miss latency 614system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56251 # average overall mshr miss latency 615system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 28751 # average overall mshr miss latency 616system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40057.977522 # average overall mshr miss latency 617system.l2c.overall_avg_mshr_miss_latency::cpu0.data 33458.436773 # average overall mshr miss latency 618system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49376 # average overall mshr miss latency 619system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42272.657811 # average overall mshr miss latency 620system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35529.587312 # average overall mshr miss latency 621system.l2c.overall_avg_mshr_miss_latency::total 34943.188535 # average overall mshr miss latency 622system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 623system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 624system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 625system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 626system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 627system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 628system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 629system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 630system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 631system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 632system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 633system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 634system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 635system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 636system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 637system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 638system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 639system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 640system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 641system.cf0.dma_write_txs 0 # Number of DMA write transactions. 642system.cpu0.dtb.inst_hits 0 # ITB inst hits 643system.cpu0.dtb.inst_misses 0 # ITB inst misses 644system.cpu0.dtb.read_hits 7074446 # DTB read hits 645system.cpu0.dtb.read_misses 3765 # DTB read misses 646system.cpu0.dtb.write_hits 5659669 # DTB write hits 647system.cpu0.dtb.write_misses 803 # DTB write misses 648system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 649system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 650system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 651system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 652system.cpu0.dtb.flush_entries 1806 # Number of entries that have been flushed from TLB 653system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 654system.cpu0.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch 655system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 656system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 657system.cpu0.dtb.read_accesses 7078211 # DTB read accesses 658system.cpu0.dtb.write_accesses 5660472 # DTB write accesses 659system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 660system.cpu0.dtb.hits 12734115 # DTB hits 661system.cpu0.dtb.misses 4568 # DTB misses 662system.cpu0.dtb.accesses 12738683 # DTB accesses 663system.cpu0.itb.inst_hits 29576941 # ITB inst hits 664system.cpu0.itb.inst_misses 2205 # ITB inst misses 665system.cpu0.itb.read_hits 0 # DTB read hits 666system.cpu0.itb.read_misses 0 # DTB read misses 667system.cpu0.itb.write_hits 0 # DTB write hits 668system.cpu0.itb.write_misses 0 # DTB write misses 669system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 670system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 671system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 672system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 673system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 674system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 675system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 676system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 677system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 678system.cpu0.itb.read_accesses 0 # DTB read accesses 679system.cpu0.itb.write_accesses 0 # DTB write accesses 680system.cpu0.itb.inst_accesses 29579146 # ITB inst accesses 681system.cpu0.itb.hits 29576941 # DTB hits 682system.cpu0.itb.misses 2205 # DTB misses 683system.cpu0.itb.accesses 29579146 # DTB accesses 684system.cpu0.numCycles 2366875007 # number of cpu cycles simulated 685system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 686system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 687system.cpu0.committedInsts 28878978 # Number of instructions committed 688system.cpu0.committedOps 37226861 # Number of ops (including micro ops) committed 689system.cpu0.num_int_alu_accesses 33113061 # Number of integer alu accesses 690system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses 691system.cpu0.num_func_calls 1241874 # number of times a function call or return occured 692system.cpu0.num_conditional_control_insts 4373945 # number of instructions that are conditional controls 693system.cpu0.num_int_insts 33113061 # number of integer instructions 694system.cpu0.num_fp_insts 3860 # number of float instructions 695system.cpu0.num_int_register_reads 190134215 # number of times the integer registers were read 696system.cpu0.num_int_register_writes 36237784 # number of times the integer registers were written 697system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 698system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 699system.cpu0.num_mem_refs 13402466 # number of memory refs 700system.cpu0.num_load_insts 7412077 # Number of load instructions 701system.cpu0.num_store_insts 5990389 # Number of store instructions 702system.cpu0.num_idle_cycles 2224972760.370120 # Number of idle cycles 703system.cpu0.num_busy_cycles 141902246.629880 # Number of busy cycles 704system.cpu0.not_idle_fraction 0.059953 # Percentage of non-idle cycles 705system.cpu0.idle_fraction 0.940047 # Percentage of idle cycles 706system.cpu0.kern.inst.arm 0 # number of arm instructions executed 707system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed 708system.cpu0.icache.replacements 425548 # number of replacements 709system.cpu0.icache.tagsinuse 509.590371 # Cycle average of tags in use 710system.cpu0.icache.total_refs 29150863 # Total number of references to valid blocks. 711system.cpu0.icache.sampled_refs 426060 # Sample count of references to valid blocks. 712system.cpu0.icache.avg_refs 68.419619 # Average number of references to valid blocks. 713system.cpu0.icache.warmup_cycle 75070085000 # Cycle when the warmup percentage was hit. 714system.cpu0.icache.occ_blocks::cpu0.inst 509.590371 # Average occupied blocks per requestor 715system.cpu0.icache.occ_percent::cpu0.inst 0.995294 # Average percentage of cache occupancy 716system.cpu0.icache.occ_percent::total 0.995294 # Average percentage of cache occupancy 717system.cpu0.icache.ReadReq_hits::cpu0.inst 29150863 # number of ReadReq hits 718system.cpu0.icache.ReadReq_hits::total 29150863 # number of ReadReq hits 719system.cpu0.icache.demand_hits::cpu0.inst 29150863 # number of demand (read+write) hits 720system.cpu0.icache.demand_hits::total 29150863 # number of demand (read+write) hits 721system.cpu0.icache.overall_hits::cpu0.inst 29150863 # number of overall hits 722system.cpu0.icache.overall_hits::total 29150863 # number of overall hits 723system.cpu0.icache.ReadReq_misses::cpu0.inst 426061 # number of ReadReq misses 724system.cpu0.icache.ReadReq_misses::total 426061 # number of ReadReq misses 725system.cpu0.icache.demand_misses::cpu0.inst 426061 # number of demand (read+write) misses 726system.cpu0.icache.demand_misses::total 426061 # number of demand (read+write) misses 727system.cpu0.icache.overall_misses::cpu0.inst 426061 # number of overall misses 728system.cpu0.icache.overall_misses::total 426061 # number of overall misses 729system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5812849500 # number of ReadReq miss cycles 730system.cpu0.icache.ReadReq_miss_latency::total 5812849500 # number of ReadReq miss cycles 731system.cpu0.icache.demand_miss_latency::cpu0.inst 5812849500 # number of demand (read+write) miss cycles 732system.cpu0.icache.demand_miss_latency::total 5812849500 # number of demand (read+write) miss cycles 733system.cpu0.icache.overall_miss_latency::cpu0.inst 5812849500 # number of overall miss cycles 734system.cpu0.icache.overall_miss_latency::total 5812849500 # number of overall miss cycles 735system.cpu0.icache.ReadReq_accesses::cpu0.inst 29576924 # number of ReadReq accesses(hits+misses) 736system.cpu0.icache.ReadReq_accesses::total 29576924 # number of ReadReq accesses(hits+misses) 737system.cpu0.icache.demand_accesses::cpu0.inst 29576924 # number of demand (read+write) accesses 738system.cpu0.icache.demand_accesses::total 29576924 # number of demand (read+write) accesses 739system.cpu0.icache.overall_accesses::cpu0.inst 29576924 # number of overall (read+write) accesses 740system.cpu0.icache.overall_accesses::total 29576924 # number of overall (read+write) accesses 741system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses 742system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses 743system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses 744system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses 745system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses 746system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses 747system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13643.233011 # average ReadReq miss latency 748system.cpu0.icache.ReadReq_avg_miss_latency::total 13643.233011 # average ReadReq miss latency 749system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency 750system.cpu0.icache.demand_avg_miss_latency::total 13643.233011 # average overall miss latency 751system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13643.233011 # average overall miss latency 752system.cpu0.icache.overall_avg_miss_latency::total 13643.233011 # average overall miss latency 753system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 754system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 755system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 756system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 757system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 758system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 759system.cpu0.icache.fast_writes 0 # number of fast writes performed 760system.cpu0.icache.cache_copies 0 # number of cache copies performed 761system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 426061 # number of ReadReq MSHR misses 762system.cpu0.icache.ReadReq_mshr_misses::total 426061 # number of ReadReq MSHR misses 763system.cpu0.icache.demand_mshr_misses::cpu0.inst 426061 # number of demand (read+write) MSHR misses 764system.cpu0.icache.demand_mshr_misses::total 426061 # number of demand (read+write) MSHR misses 765system.cpu0.icache.overall_mshr_misses::cpu0.inst 426061 # number of overall MSHR misses 766system.cpu0.icache.overall_mshr_misses::total 426061 # number of overall MSHR misses 767system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4960727500 # number of ReadReq MSHR miss cycles 768system.cpu0.icache.ReadReq_mshr_miss_latency::total 4960727500 # number of ReadReq MSHR miss cycles 769system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4960727500 # number of demand (read+write) MSHR miss cycles 770system.cpu0.icache.demand_mshr_miss_latency::total 4960727500 # number of demand (read+write) MSHR miss cycles 771system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4960727500 # number of overall MSHR miss cycles 772system.cpu0.icache.overall_mshr_miss_latency::total 4960727500 # number of overall MSHR miss cycles 773system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 299599000 # number of ReadReq MSHR uncacheable cycles 774system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 299599000 # number of ReadReq MSHR uncacheable cycles 775system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 299599000 # number of overall MSHR uncacheable cycles 776system.cpu0.icache.overall_mshr_uncacheable_latency::total 299599000 # number of overall MSHR uncacheable cycles 777system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses 778system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses 779system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses 780system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses 781system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses 782system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses 783system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average ReadReq mshr miss latency 784system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11643.233011 # average ReadReq mshr miss latency 785system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average overall mshr miss latency 786system.cpu0.icache.demand_avg_mshr_miss_latency::total 11643.233011 # average overall mshr miss latency 787system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11643.233011 # average overall mshr miss latency 788system.cpu0.icache.overall_avg_mshr_miss_latency::total 11643.233011 # average overall mshr miss latency 789system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 790system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 791system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 792system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 793system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 794system.cpu0.dcache.replacements 330262 # number of replacements 795system.cpu0.dcache.tagsinuse 452.976504 # Cycle average of tags in use 796system.cpu0.dcache.total_refs 12279097 # Total number of references to valid blocks. 797system.cpu0.dcache.sampled_refs 330774 # Sample count of references to valid blocks. 798system.cpu0.dcache.avg_refs 37.122316 # Average number of references to valid blocks. 799system.cpu0.dcache.warmup_cycle 473556000 # Cycle when the warmup percentage was hit. 800system.cpu0.dcache.occ_blocks::cpu0.data 452.976504 # Average occupied blocks per requestor 801system.cpu0.dcache.occ_percent::cpu0.data 0.884720 # Average percentage of cache occupancy 802system.cpu0.dcache.occ_percent::total 0.884720 # Average percentage of cache occupancy 803system.cpu0.dcache.ReadReq_hits::cpu0.data 6604621 # number of ReadReq hits 804system.cpu0.dcache.ReadReq_hits::total 6604621 # number of ReadReq hits 805system.cpu0.dcache.WriteReq_hits::cpu0.data 5354486 # number of WriteReq hits 806system.cpu0.dcache.WriteReq_hits::total 5354486 # number of WriteReq hits 807system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147953 # number of LoadLockedReq hits 808system.cpu0.dcache.LoadLockedReq_hits::total 147953 # number of LoadLockedReq hits 809system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149702 # number of StoreCondReq hits 810system.cpu0.dcache.StoreCondReq_hits::total 149702 # number of StoreCondReq hits 811system.cpu0.dcache.demand_hits::cpu0.data 11959107 # number of demand (read+write) hits 812system.cpu0.dcache.demand_hits::total 11959107 # number of demand (read+write) hits 813system.cpu0.dcache.overall_hits::cpu0.data 11959107 # number of overall hits 814system.cpu0.dcache.overall_hits::total 11959107 # number of overall hits 815system.cpu0.dcache.ReadReq_misses::cpu0.data 227474 # number of ReadReq misses 816system.cpu0.dcache.ReadReq_misses::total 227474 # number of ReadReq misses 817system.cpu0.dcache.WriteReq_misses::cpu0.data 141720 # number of WriteReq misses 818system.cpu0.dcache.WriteReq_misses::total 141720 # number of WriteReq misses 819system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9335 # number of LoadLockedReq misses 820system.cpu0.dcache.LoadLockedReq_misses::total 9335 # number of LoadLockedReq misses 821system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7505 # number of StoreCondReq misses 822system.cpu0.dcache.StoreCondReq_misses::total 7505 # number of StoreCondReq misses 823system.cpu0.dcache.demand_misses::cpu0.data 369194 # number of demand (read+write) misses 824system.cpu0.dcache.demand_misses::total 369194 # number of demand (read+write) misses 825system.cpu0.dcache.overall_misses::cpu0.data 369194 # number of overall misses 826system.cpu0.dcache.overall_misses::total 369194 # number of overall misses 827system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3141338000 # number of ReadReq miss cycles 828system.cpu0.dcache.ReadReq_miss_latency::total 3141338000 # number of ReadReq miss cycles 829system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4161237500 # number of WriteReq miss cycles 830system.cpu0.dcache.WriteReq_miss_latency::total 4161237500 # number of WriteReq miss cycles 831system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88637000 # number of LoadLockedReq miss cycles 832system.cpu0.dcache.LoadLockedReq_miss_latency::total 88637000 # number of LoadLockedReq miss cycles 833system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44352500 # number of StoreCondReq miss cycles 834system.cpu0.dcache.StoreCondReq_miss_latency::total 44352500 # number of StoreCondReq miss cycles 835system.cpu0.dcache.demand_miss_latency::cpu0.data 7302575500 # number of demand (read+write) miss cycles 836system.cpu0.dcache.demand_miss_latency::total 7302575500 # number of demand (read+write) miss cycles 837system.cpu0.dcache.overall_miss_latency::cpu0.data 7302575500 # number of overall miss cycles 838system.cpu0.dcache.overall_miss_latency::total 7302575500 # number of overall miss cycles 839system.cpu0.dcache.ReadReq_accesses::cpu0.data 6832095 # number of ReadReq accesses(hits+misses) 840system.cpu0.dcache.ReadReq_accesses::total 6832095 # number of ReadReq accesses(hits+misses) 841system.cpu0.dcache.WriteReq_accesses::cpu0.data 5496206 # number of WriteReq accesses(hits+misses) 842system.cpu0.dcache.WriteReq_accesses::total 5496206 # number of WriteReq accesses(hits+misses) 843system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157288 # number of LoadLockedReq accesses(hits+misses) 844system.cpu0.dcache.LoadLockedReq_accesses::total 157288 # number of LoadLockedReq accesses(hits+misses) 845system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157207 # number of StoreCondReq accesses(hits+misses) 846system.cpu0.dcache.StoreCondReq_accesses::total 157207 # number of StoreCondReq accesses(hits+misses) 847system.cpu0.dcache.demand_accesses::cpu0.data 12328301 # number of demand (read+write) accesses 848system.cpu0.dcache.demand_accesses::total 12328301 # number of demand (read+write) accesses 849system.cpu0.dcache.overall_accesses::cpu0.data 12328301 # number of overall (read+write) accesses 850system.cpu0.dcache.overall_accesses::total 12328301 # number of overall (read+write) accesses 851system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033295 # miss rate for ReadReq accesses 852system.cpu0.dcache.ReadReq_miss_rate::total 0.033295 # miss rate for ReadReq accesses 853system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025785 # miss rate for WriteReq accesses 854system.cpu0.dcache.WriteReq_miss_rate::total 0.025785 # miss rate for WriteReq accesses 855system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059350 # miss rate for LoadLockedReq accesses 856system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059350 # miss rate for LoadLockedReq accesses 857system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047740 # miss rate for StoreCondReq accesses 858system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047740 # miss rate for StoreCondReq accesses 859system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029947 # miss rate for demand accesses 860system.cpu0.dcache.demand_miss_rate::total 0.029947 # miss rate for demand accesses 861system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029947 # miss rate for overall accesses 862system.cpu0.dcache.overall_miss_rate::total 0.029947 # miss rate for overall accesses 863system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13809.657367 # average ReadReq miss latency 864system.cpu0.dcache.ReadReq_avg_miss_latency::total 13809.657367 # average ReadReq miss latency 865system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29362.387101 # average WriteReq miss latency 866system.cpu0.dcache.WriteReq_avg_miss_latency::total 29362.387101 # average WriteReq miss latency 867system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9495.125870 # average LoadLockedReq miss latency 868system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9495.125870 # average LoadLockedReq miss latency 869system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5909.726849 # average StoreCondReq miss latency 870system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5909.726849 # average StoreCondReq miss latency 871system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19779.778382 # average overall miss latency 872system.cpu0.dcache.demand_avg_miss_latency::total 19779.778382 # average overall miss latency 873system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19779.778382 # average overall miss latency 874system.cpu0.dcache.overall_avg_miss_latency::total 19779.778382 # average overall miss latency 875system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 876system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 877system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 878system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 879system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 880system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 881system.cpu0.dcache.fast_writes 0 # number of fast writes performed 882system.cpu0.dcache.cache_copies 0 # number of cache copies performed 883system.cpu0.dcache.writebacks::writebacks 306255 # number of writebacks 884system.cpu0.dcache.writebacks::total 306255 # number of writebacks 885system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227474 # number of ReadReq MSHR misses 886system.cpu0.dcache.ReadReq_mshr_misses::total 227474 # number of ReadReq MSHR misses 887system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141720 # number of WriteReq MSHR misses 888system.cpu0.dcache.WriteReq_mshr_misses::total 141720 # number of WriteReq MSHR misses 889system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9335 # number of LoadLockedReq MSHR misses 890system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9335 # number of LoadLockedReq MSHR misses 891system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7498 # number of StoreCondReq MSHR misses 892system.cpu0.dcache.StoreCondReq_mshr_misses::total 7498 # number of StoreCondReq MSHR misses 893system.cpu0.dcache.demand_mshr_misses::cpu0.data 369194 # number of demand (read+write) MSHR misses 894system.cpu0.dcache.demand_mshr_misses::total 369194 # number of demand (read+write) MSHR misses 895system.cpu0.dcache.overall_mshr_misses::cpu0.data 369194 # number of overall MSHR misses 896system.cpu0.dcache.overall_mshr_misses::total 369194 # number of overall MSHR misses 897system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2686390000 # number of ReadReq MSHR miss cycles 898system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2686390000 # number of ReadReq MSHR miss cycles 899system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3877797500 # number of WriteReq MSHR miss cycles 900system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3877797500 # number of WriteReq MSHR miss cycles 901system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69967000 # number of LoadLockedReq MSHR miss cycles 902system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69967000 # number of LoadLockedReq MSHR miss cycles 903system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29358500 # number of StoreCondReq MSHR miss cycles 904system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29358500 # number of StoreCondReq MSHR miss cycles 905system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 906system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 907system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6564187500 # number of demand (read+write) MSHR miss cycles 908system.cpu0.dcache.demand_mshr_miss_latency::total 6564187500 # number of demand (read+write) MSHR miss cycles 909system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6564187500 # number of overall MSHR miss cycles 910system.cpu0.dcache.overall_mshr_miss_latency::total 6564187500 # number of overall MSHR miss cycles 911system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13562288000 # number of ReadReq MSHR uncacheable cycles 912system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13562288000 # number of ReadReq MSHR uncacheable cycles 913system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128633000 # number of WriteReq MSHR uncacheable cycles 914system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128633000 # number of WriteReq MSHR uncacheable cycles 915system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14690921000 # number of overall MSHR uncacheable cycles 916system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14690921000 # number of overall MSHR uncacheable cycles 917system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033295 # mshr miss rate for ReadReq accesses 918system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033295 # mshr miss rate for ReadReq accesses 919system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025785 # mshr miss rate for WriteReq accesses 920system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025785 # mshr miss rate for WriteReq accesses 921system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059350 # mshr miss rate for LoadLockedReq accesses 922system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059350 # mshr miss rate for LoadLockedReq accesses 923system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047695 # mshr miss rate for StoreCondReq accesses 924system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047695 # mshr miss rate for StoreCondReq accesses 925system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for demand accesses 926system.cpu0.dcache.demand_mshr_miss_rate::total 0.029947 # mshr miss rate for demand accesses 927system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029947 # mshr miss rate for overall accesses 928system.cpu0.dcache.overall_mshr_miss_rate::total 0.029947 # mshr miss rate for overall accesses 929system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11809.657367 # average ReadReq mshr miss latency 930system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11809.657367 # average ReadReq mshr miss latency 931system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27362.387101 # average WriteReq mshr miss latency 932system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27362.387101 # average WriteReq mshr miss latency 933system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7495.125870 # average LoadLockedReq mshr miss latency 934system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7495.125870 # average LoadLockedReq mshr miss latency 935system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3915.510803 # average StoreCondReq mshr miss latency 936system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3915.510803 # average StoreCondReq mshr miss latency 937system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 938system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 939system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency 940system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency 941system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17779.778382 # average overall mshr miss latency 942system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17779.778382 # average overall mshr miss latency 943system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 944system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 945system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 946system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 947system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 948system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 949system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 950system.cpu1.dtb.inst_hits 0 # ITB inst hits 951system.cpu1.dtb.inst_misses 0 # ITB inst misses 952system.cpu1.dtb.read_hits 8312224 # DTB read hits 953system.cpu1.dtb.read_misses 3649 # DTB read misses 954system.cpu1.dtb.write_hits 5828610 # DTB write hits 955system.cpu1.dtb.write_misses 1432 # DTB write misses 956system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 957system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 958system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 959system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 960system.cpu1.dtb.flush_entries 1964 # Number of entries that have been flushed from TLB 961system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 962system.cpu1.dtb.prefetch_faults 142 # Number of TLB faults due to prefetch 963system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 964system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 965system.cpu1.dtb.read_accesses 8315873 # DTB read accesses 966system.cpu1.dtb.write_accesses 5830042 # DTB write accesses 967system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 968system.cpu1.dtb.hits 14140834 # DTB hits 969system.cpu1.dtb.misses 5081 # DTB misses 970system.cpu1.dtb.accesses 14145915 # DTB accesses 971system.cpu1.itb.inst_hits 33192056 # ITB inst hits 972system.cpu1.itb.inst_misses 2171 # ITB inst misses 973system.cpu1.itb.read_hits 0 # DTB read hits 974system.cpu1.itb.read_misses 0 # DTB read misses 975system.cpu1.itb.write_hits 0 # DTB write hits 976system.cpu1.itb.write_misses 0 # DTB write misses 977system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 978system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 979system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 980system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 981system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 982system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 983system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 984system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 985system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 986system.cpu1.itb.read_accesses 0 # DTB read accesses 987system.cpu1.itb.write_accesses 0 # DTB write accesses 988system.cpu1.itb.inst_accesses 33194227 # ITB inst accesses 989system.cpu1.itb.hits 33192056 # DTB hits 990system.cpu1.itb.misses 2171 # DTB misses 991system.cpu1.itb.accesses 33194227 # DTB accesses 992system.cpu1.numCycles 2365415230 # number of cpu cycles simulated 993system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 994system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 995system.cpu1.committedInsts 32581554 # Number of instructions committed 996system.cpu1.committedOps 41094791 # Number of ops (including micro ops) committed 997system.cpu1.num_int_alu_accesses 37318858 # Number of integer alu accesses 998system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses 999system.cpu1.num_func_calls 962092 # number of times a function call or return occured 1000system.cpu1.num_conditional_control_insts 3732954 # number of instructions that are conditional controls 1001system.cpu1.num_int_insts 37318858 # number of integer instructions 1002system.cpu1.num_fp_insts 6793 # number of float instructions 1003system.cpu1.num_int_register_reads 213696952 # number of times the integer registers were read 1004system.cpu1.num_int_register_writes 39459665 # number of times the integer registers were written 1005system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1006system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 1007system.cpu1.num_mem_refs 14678596 # number of memory refs 1008system.cpu1.num_load_insts 8634126 # Number of load instructions 1009system.cpu1.num_store_insts 6044470 # Number of store instructions 1010system.cpu1.num_idle_cycles 1868274479.951726 # Number of idle cycles 1011system.cpu1.num_busy_cycles 497140750.048273 # Number of busy cycles 1012system.cpu1.not_idle_fraction 0.210171 # Percentage of non-idle cycles 1013system.cpu1.idle_fraction 0.789829 # Percentage of idle cycles 1014system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1015system.cpu1.kern.inst.quiesce 43886 # number of quiesce instructions executed 1016system.cpu1.icache.replacements 469169 # number of replacements 1017system.cpu1.icache.tagsinuse 478.729775 # Cycle average of tags in use 1018system.cpu1.icache.total_refs 32722371 # Total number of references to valid blocks. 1019system.cpu1.icache.sampled_refs 469681 # Sample count of references to valid blocks. 1020system.cpu1.icache.avg_refs 69.669352 # Average number of references to valid blocks. 1021system.cpu1.icache.warmup_cycle 92399174500 # Cycle when the warmup percentage was hit. 1022system.cpu1.icache.occ_blocks::cpu1.inst 478.729775 # Average occupied blocks per requestor 1023system.cpu1.icache.occ_percent::cpu1.inst 0.935019 # Average percentage of cache occupancy 1024system.cpu1.icache.occ_percent::total 0.935019 # Average percentage of cache occupancy 1025system.cpu1.icache.ReadReq_hits::cpu1.inst 32722371 # number of ReadReq hits 1026system.cpu1.icache.ReadReq_hits::total 32722371 # number of ReadReq hits 1027system.cpu1.icache.demand_hits::cpu1.inst 32722371 # number of demand (read+write) hits 1028system.cpu1.icache.demand_hits::total 32722371 # number of demand (read+write) hits 1029system.cpu1.icache.overall_hits::cpu1.inst 32722371 # number of overall hits 1030system.cpu1.icache.overall_hits::total 32722371 # number of overall hits 1031system.cpu1.icache.ReadReq_misses::cpu1.inst 469681 # number of ReadReq misses 1032system.cpu1.icache.ReadReq_misses::total 469681 # number of ReadReq misses 1033system.cpu1.icache.demand_misses::cpu1.inst 469681 # number of demand (read+write) misses 1034system.cpu1.icache.demand_misses::total 469681 # number of demand (read+write) misses 1035system.cpu1.icache.overall_misses::cpu1.inst 469681 # number of overall misses 1036system.cpu1.icache.overall_misses::total 469681 # number of overall misses 1037system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6362521500 # number of ReadReq miss cycles 1038system.cpu1.icache.ReadReq_miss_latency::total 6362521500 # number of ReadReq miss cycles 1039system.cpu1.icache.demand_miss_latency::cpu1.inst 6362521500 # number of demand (read+write) miss cycles 1040system.cpu1.icache.demand_miss_latency::total 6362521500 # number of demand (read+write) miss cycles 1041system.cpu1.icache.overall_miss_latency::cpu1.inst 6362521500 # number of overall miss cycles 1042system.cpu1.icache.overall_miss_latency::total 6362521500 # number of overall miss cycles 1043system.cpu1.icache.ReadReq_accesses::cpu1.inst 33192052 # number of ReadReq accesses(hits+misses) 1044system.cpu1.icache.ReadReq_accesses::total 33192052 # number of ReadReq accesses(hits+misses) 1045system.cpu1.icache.demand_accesses::cpu1.inst 33192052 # number of demand (read+write) accesses 1046system.cpu1.icache.demand_accesses::total 33192052 # number of demand (read+write) accesses 1047system.cpu1.icache.overall_accesses::cpu1.inst 33192052 # number of overall (read+write) accesses 1048system.cpu1.icache.overall_accesses::total 33192052 # number of overall (read+write) accesses 1049system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014150 # miss rate for ReadReq accesses 1050system.cpu1.icache.ReadReq_miss_rate::total 0.014150 # miss rate for ReadReq accesses 1051system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014150 # miss rate for demand accesses 1052system.cpu1.icache.demand_miss_rate::total 0.014150 # miss rate for demand accesses 1053system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014150 # miss rate for overall accesses 1054system.cpu1.icache.overall_miss_rate::total 0.014150 # miss rate for overall accesses 1055system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13546.474096 # average ReadReq miss latency 1056system.cpu1.icache.ReadReq_avg_miss_latency::total 13546.474096 # average ReadReq miss latency 1057system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13546.474096 # average overall miss latency 1058system.cpu1.icache.demand_avg_miss_latency::total 13546.474096 # average overall miss latency 1059system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13546.474096 # average overall miss latency 1060system.cpu1.icache.overall_avg_miss_latency::total 13546.474096 # average overall miss latency 1061system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1062system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1063system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1064system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1065system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1066system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1067system.cpu1.icache.fast_writes 0 # number of fast writes performed 1068system.cpu1.icache.cache_copies 0 # number of cache copies performed 1069system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469681 # number of ReadReq MSHR misses 1070system.cpu1.icache.ReadReq_mshr_misses::total 469681 # number of ReadReq MSHR misses 1071system.cpu1.icache.demand_mshr_misses::cpu1.inst 469681 # number of demand (read+write) MSHR misses 1072system.cpu1.icache.demand_mshr_misses::total 469681 # number of demand (read+write) MSHR misses 1073system.cpu1.icache.overall_mshr_misses::cpu1.inst 469681 # number of overall MSHR misses 1074system.cpu1.icache.overall_mshr_misses::total 469681 # number of overall MSHR misses 1075system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5423159500 # number of ReadReq MSHR miss cycles 1076system.cpu1.icache.ReadReq_mshr_miss_latency::total 5423159500 # number of ReadReq MSHR miss cycles 1077system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5423159500 # number of demand (read+write) MSHR miss cycles 1078system.cpu1.icache.demand_mshr_miss_latency::total 5423159500 # number of demand (read+write) MSHR miss cycles 1079system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5423159500 # number of overall MSHR miss cycles 1080system.cpu1.icache.overall_mshr_miss_latency::total 5423159500 # number of overall MSHR miss cycles 1081system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4481000 # number of ReadReq MSHR uncacheable cycles 1082system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4481000 # number of ReadReq MSHR uncacheable cycles 1083system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4481000 # number of overall MSHR uncacheable cycles 1084system.cpu1.icache.overall_mshr_uncacheable_latency::total 4481000 # number of overall MSHR uncacheable cycles 1085system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for ReadReq accesses 1086system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014150 # mshr miss rate for ReadReq accesses 1087system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for demand accesses 1088system.cpu1.icache.demand_mshr_miss_rate::total 0.014150 # mshr miss rate for demand accesses 1089system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014150 # mshr miss rate for overall accesses 1090system.cpu1.icache.overall_mshr_miss_rate::total 0.014150 # mshr miss rate for overall accesses 1091system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average ReadReq mshr miss latency 1092system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11546.474096 # average ReadReq mshr miss latency 1093system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average overall mshr miss latency 1094system.cpu1.icache.demand_avg_mshr_miss_latency::total 11546.474096 # average overall mshr miss latency 1095system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11546.474096 # average overall mshr miss latency 1096system.cpu1.icache.overall_avg_mshr_miss_latency::total 11546.474096 # average overall mshr miss latency 1097system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1098system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1099system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1100system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1101system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1102system.cpu1.dcache.replacements 292058 # number of replacements 1103system.cpu1.dcache.tagsinuse 471.819179 # Cycle average of tags in use 1104system.cpu1.dcache.total_refs 11963833 # Total number of references to valid blocks. 1105system.cpu1.dcache.sampled_refs 292409 # Sample count of references to valid blocks. 1106system.cpu1.dcache.avg_refs 40.914722 # Average number of references to valid blocks. 1107system.cpu1.dcache.warmup_cycle 83872114000 # Cycle when the warmup percentage was hit. 1108system.cpu1.dcache.occ_blocks::cpu1.data 471.819179 # Average occupied blocks per requestor 1109system.cpu1.dcache.occ_percent::cpu1.data 0.921522 # Average percentage of cache occupancy 1110system.cpu1.dcache.occ_percent::total 0.921522 # Average percentage of cache occupancy 1111system.cpu1.dcache.ReadReq_hits::cpu1.data 6947661 # number of ReadReq hits 1112system.cpu1.dcache.ReadReq_hits::total 6947661 # number of ReadReq hits 1113system.cpu1.dcache.WriteReq_hits::cpu1.data 4828322 # number of WriteReq hits 1114system.cpu1.dcache.WriteReq_hits::total 4828322 # number of WriteReq hits 1115system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81798 # number of LoadLockedReq hits 1116system.cpu1.dcache.LoadLockedReq_hits::total 81798 # number of LoadLockedReq hits 1117system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82734 # number of StoreCondReq hits 1118system.cpu1.dcache.StoreCondReq_hits::total 82734 # number of StoreCondReq hits 1119system.cpu1.dcache.demand_hits::cpu1.data 11775983 # number of demand (read+write) hits 1120system.cpu1.dcache.demand_hits::total 11775983 # number of demand (read+write) hits 1121system.cpu1.dcache.overall_hits::cpu1.data 11775983 # number of overall hits 1122system.cpu1.dcache.overall_hits::total 11775983 # number of overall hits 1123system.cpu1.dcache.ReadReq_misses::cpu1.data 170592 # number of ReadReq misses 1124system.cpu1.dcache.ReadReq_misses::total 170592 # number of ReadReq misses 1125system.cpu1.dcache.WriteReq_misses::cpu1.data 149961 # number of WriteReq misses 1126system.cpu1.dcache.WriteReq_misses::total 149961 # number of WriteReq misses 1127system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11053 # number of LoadLockedReq misses 1128system.cpu1.dcache.LoadLockedReq_misses::total 11053 # number of LoadLockedReq misses 1129system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10044 # number of StoreCondReq misses 1130system.cpu1.dcache.StoreCondReq_misses::total 10044 # number of StoreCondReq misses 1131system.cpu1.dcache.demand_misses::cpu1.data 320553 # number of demand (read+write) misses 1132system.cpu1.dcache.demand_misses::total 320553 # number of demand (read+write) misses 1133system.cpu1.dcache.overall_misses::cpu1.data 320553 # number of overall misses 1134system.cpu1.dcache.overall_misses::total 320553 # number of overall misses 1135system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2164105500 # number of ReadReq miss cycles 1136system.cpu1.dcache.ReadReq_miss_latency::total 2164105500 # number of ReadReq miss cycles 1137system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4535823500 # number of WriteReq miss cycles 1138system.cpu1.dcache.WriteReq_miss_latency::total 4535823500 # number of WriteReq miss cycles 1139system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92227500 # number of LoadLockedReq miss cycles 1140system.cpu1.dcache.LoadLockedReq_miss_latency::total 92227500 # number of LoadLockedReq miss cycles 1141system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51992500 # number of StoreCondReq miss cycles 1142system.cpu1.dcache.StoreCondReq_miss_latency::total 51992500 # number of StoreCondReq miss cycles 1143system.cpu1.dcache.demand_miss_latency::cpu1.data 6699929000 # number of demand (read+write) miss cycles 1144system.cpu1.dcache.demand_miss_latency::total 6699929000 # number of demand (read+write) miss cycles 1145system.cpu1.dcache.overall_miss_latency::cpu1.data 6699929000 # number of overall miss cycles 1146system.cpu1.dcache.overall_miss_latency::total 6699929000 # number of overall miss cycles 1147system.cpu1.dcache.ReadReq_accesses::cpu1.data 7118253 # number of ReadReq accesses(hits+misses) 1148system.cpu1.dcache.ReadReq_accesses::total 7118253 # number of ReadReq accesses(hits+misses) 1149system.cpu1.dcache.WriteReq_accesses::cpu1.data 4978283 # number of WriteReq accesses(hits+misses) 1150system.cpu1.dcache.WriteReq_accesses::total 4978283 # number of WriteReq accesses(hits+misses) 1151system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92851 # number of LoadLockedReq accesses(hits+misses) 1152system.cpu1.dcache.LoadLockedReq_accesses::total 92851 # number of LoadLockedReq accesses(hits+misses) 1153system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92778 # number of StoreCondReq accesses(hits+misses) 1154system.cpu1.dcache.StoreCondReq_accesses::total 92778 # number of StoreCondReq accesses(hits+misses) 1155system.cpu1.dcache.demand_accesses::cpu1.data 12096536 # number of demand (read+write) accesses 1156system.cpu1.dcache.demand_accesses::total 12096536 # number of demand (read+write) accesses 1157system.cpu1.dcache.overall_accesses::cpu1.data 12096536 # number of overall (read+write) accesses 1158system.cpu1.dcache.overall_accesses::total 12096536 # number of overall (read+write) accesses 1159system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023965 # miss rate for ReadReq accesses 1160system.cpu1.dcache.ReadReq_miss_rate::total 0.023965 # miss rate for ReadReq accesses 1161system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030123 # miss rate for WriteReq accesses 1162system.cpu1.dcache.WriteReq_miss_rate::total 0.030123 # miss rate for WriteReq accesses 1163system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119040 # miss rate for LoadLockedReq accesses 1164system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119040 # miss rate for LoadLockedReq accesses 1165system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108258 # miss rate for StoreCondReq accesses 1166system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108258 # miss rate for StoreCondReq accesses 1167system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026500 # miss rate for demand accesses 1168system.cpu1.dcache.demand_miss_rate::total 0.026500 # miss rate for demand accesses 1169system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026500 # miss rate for overall accesses 1170system.cpu1.dcache.overall_miss_rate::total 0.026500 # miss rate for overall accesses 1171system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12685.855726 # average ReadReq miss latency 1172system.cpu1.dcache.ReadReq_avg_miss_latency::total 12685.855726 # average ReadReq miss latency 1173system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30246.687472 # average WriteReq miss latency 1174system.cpu1.dcache.WriteReq_avg_miss_latency::total 30246.687472 # average WriteReq miss latency 1175system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8344.114720 # average LoadLockedReq miss latency 1176system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8344.114720 # average LoadLockedReq miss latency 1177system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5176.473517 # average StoreCondReq miss latency 1178system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5176.473517 # average StoreCondReq miss latency 1179system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20901.158311 # average overall miss latency 1180system.cpu1.dcache.demand_avg_miss_latency::total 20901.158311 # average overall miss latency 1181system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20901.158311 # average overall miss latency 1182system.cpu1.dcache.overall_avg_miss_latency::total 20901.158311 # average overall miss latency 1183system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1184system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1185system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1186system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1187system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1188system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1189system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1190system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1191system.cpu1.dcache.writebacks::writebacks 265193 # number of writebacks 1192system.cpu1.dcache.writebacks::total 265193 # number of writebacks 1193system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170592 # number of ReadReq MSHR misses 1194system.cpu1.dcache.ReadReq_mshr_misses::total 170592 # number of ReadReq MSHR misses 1195system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149961 # number of WriteReq MSHR misses 1196system.cpu1.dcache.WriteReq_mshr_misses::total 149961 # number of WriteReq MSHR misses 1197system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11053 # number of LoadLockedReq MSHR misses 1198system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11053 # number of LoadLockedReq MSHR misses 1199system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10042 # number of StoreCondReq MSHR misses 1200system.cpu1.dcache.StoreCondReq_mshr_misses::total 10042 # number of StoreCondReq MSHR misses 1201system.cpu1.dcache.demand_mshr_misses::cpu1.data 320553 # number of demand (read+write) MSHR misses 1202system.cpu1.dcache.demand_mshr_misses::total 320553 # number of demand (read+write) MSHR misses 1203system.cpu1.dcache.overall_mshr_misses::cpu1.data 320553 # number of overall MSHR misses 1204system.cpu1.dcache.overall_mshr_misses::total 320553 # number of overall MSHR misses 1205system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1822921500 # number of ReadReq MSHR miss cycles 1206system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1822921500 # number of ReadReq MSHR miss cycles 1207system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4235901500 # number of WriteReq MSHR miss cycles 1208system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4235901500 # number of WriteReq MSHR miss cycles 1209system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70121500 # number of LoadLockedReq MSHR miss cycles 1210system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70121500 # number of LoadLockedReq MSHR miss cycles 1211system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31910500 # number of StoreCondReq MSHR miss cycles 1212system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31910500 # number of StoreCondReq MSHR miss cycles 1213system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1214system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1215system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6058823000 # number of demand (read+write) MSHR miss cycles 1216system.cpu1.dcache.demand_mshr_miss_latency::total 6058823000 # number of demand (read+write) MSHR miss cycles 1217system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6058823000 # number of overall MSHR miss cycles 1218system.cpu1.dcache.overall_mshr_miss_latency::total 6058823000 # number of overall MSHR miss cycles 1219system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168642031500 # number of ReadReq MSHR uncacheable cycles 1220system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168642031500 # number of ReadReq MSHR uncacheable cycles 1221system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17668268500 # number of WriteReq MSHR uncacheable cycles 1222system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17668268500 # number of WriteReq MSHR uncacheable cycles 1223system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186310300000 # number of overall MSHR uncacheable cycles 1224system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186310300000 # number of overall MSHR uncacheable cycles 1225system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023965 # mshr miss rate for ReadReq accesses 1226system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023965 # mshr miss rate for ReadReq accesses 1227system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses 1228system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses 1229system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119040 # mshr miss rate for LoadLockedReq accesses 1230system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119040 # mshr miss rate for LoadLockedReq accesses 1231system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108237 # mshr miss rate for StoreCondReq accesses 1232system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108237 # mshr miss rate for StoreCondReq accesses 1233system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for demand accesses 1234system.cpu1.dcache.demand_mshr_miss_rate::total 0.026500 # mshr miss rate for demand accesses 1235system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026500 # mshr miss rate for overall accesses 1236system.cpu1.dcache.overall_mshr_miss_rate::total 0.026500 # mshr miss rate for overall accesses 1237system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10685.855726 # average ReadReq mshr miss latency 1238system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10685.855726 # average ReadReq mshr miss latency 1239system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28246.687472 # average WriteReq mshr miss latency 1240system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28246.687472 # average WriteReq mshr miss latency 1241system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6344.114720 # average LoadLockedReq mshr miss latency 1242system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6344.114720 # average LoadLockedReq mshr miss latency 1243system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3177.703645 # average StoreCondReq mshr miss latency 1244system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3177.703645 # average StoreCondReq mshr miss latency 1245system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1246system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1247system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency 1248system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency 1249system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18901.158311 # average overall mshr miss latency 1250system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18901.158311 # average overall mshr miss latency 1251system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1252system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1253system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1254system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1255system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1256system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1257system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1258system.iocache.replacements 0 # number of replacements 1259system.iocache.tagsinuse 0 # Cycle average of tags in use 1260system.iocache.total_refs 0 # Total number of references to valid blocks. 1261system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1262system.iocache.avg_refs nan # Average number of references to valid blocks. 1263system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1264system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1265system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1266system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1267system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1268system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1269system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1270system.iocache.fast_writes 0 # number of fast writes performed 1271system.iocache.cache_copies 0 # number of cache copies performed 1272system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 509664351240 # number of ReadReq MSHR uncacheable cycles 1273system.iocache.ReadReq_mshr_uncacheable_latency::total 509664351240 # number of ReadReq MSHR uncacheable cycles 1274system.iocache.overall_mshr_uncacheable_latency::realview.clcd 509664351240 # number of overall MSHR uncacheable cycles 1275system.iocache.overall_mshr_uncacheable_latency::total 509664351240 # number of overall MSHR uncacheable cycles 1276system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1277system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1278system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1279system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1280system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1281 1282---------- End Simulation Statistics ---------- 1283