stats.txt revision 9449:56610ab73040
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.182882 # Number of seconds simulated 4sim_ticks 1182882156500 # Number of ticks simulated 5final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 184229 # Simulator instruction rate (inst/s) 8host_op_rate 234741 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3546252898 # Simulator tick rate (ticks/s) 10host_mem_usage 402168 # Number of bytes of host memory used 11host_seconds 333.56 # Real time elapsed on the host 12sim_insts 61450993 # Number of instructions simulated 13sim_ops 78299715 # Number of ops (including micro ops) simulated 14system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 22system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 23system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) 30system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) 31system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory 33system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 34system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.inst 393572 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.data 4715764 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.data 4806320 # Number of bytes read from this memory 40system.physmem.bytes_read::total 62143780 # Number of bytes read from this memory 41system.physmem.bytes_inst_read::cpu0.inst 393572 # Number of instructions bytes read from this memory 42system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory 44system.physmem.bytes_written::writebacks 4114688 # Number of bytes written to this memory 45system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 46system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory 47system.physmem.bytes_written::total 7142032 # Number of bytes written to this memory 48system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory 49system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 50system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.inst 12368 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.data 73756 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.data 75125 # Number of read requests responded to by this memory 56system.physmem.num_reads::total 6654451 # Number of read requests responded to by this memory 57system.physmem.num_writes::writebacks 64292 # Number of write requests responded to by this memory 58system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 59system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory 60system.physmem.num_writes::total 821128 # Number of write requests responded to by this memory 61system.physmem.bw_read::realview.clcd 43879698 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::cpu0.inst 332723 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.data 3986673 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu1.inst 273201 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu1.data 4063228 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::total 52535901 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_inst_read::cpu0.inst 332723 # Instruction read bandwidth from this memory (bytes/s) 71system.physmem.bw_inst_read::cpu1.inst 273201 # Instruction read bandwidth from this memory (bytes/s) 72system.physmem.bw_inst_read::total 605923 # Instruction read bandwidth from this memory (bytes/s) 73system.physmem.bw_write::writebacks 3478527 # Write bandwidth from this memory (bytes/s) 74system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) 75system.physmem.bw_write::cpu1.data 2544923 # Write bandwidth from this memory (bytes/s) 76system.physmem.bw_write::total 6037822 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_total::writebacks 3478527 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::realview.clcd 43879698 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu0.inst 332723 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu0.data 4001044 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu1.inst 273201 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu1.data 6608151 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::total 58573723 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.readReqs 6654451 # Total number of read requests seen 88system.physmem.writeReqs 821128 # Total number of write requests seen 89system.physmem.cpureqs 272784 # Reqs generatd by CPU via cache - shady 90system.physmem.bytesRead 425884864 # Total number of bytes read from memory 91system.physmem.bytesWritten 52552192 # Total number of bytes written to memory 92system.physmem.bytesConsumedRd 62143780 # bytesRead derated as per pkt->getSize() 93system.physmem.bytesConsumedWr 7142032 # bytesWritten derated as per pkt->getSize() 94system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q 95system.physmem.neitherReadNorWrite 11751 # Reqs where no action is needed 96system.physmem.perBankRdReqs::0 415571 # Track reads on a per bank basis 97system.physmem.perBankRdReqs::1 415750 # Track reads on a per bank basis 98system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis 99system.physmem.perBankRdReqs::3 415468 # Track reads on a per bank basis 100system.physmem.perBankRdReqs::4 415552 # Track reads on a per bank basis 101system.physmem.perBankRdReqs::5 415207 # Track reads on a per bank basis 102system.physmem.perBankRdReqs::6 415303 # Track reads on a per bank basis 103system.physmem.perBankRdReqs::7 415263 # Track reads on a per bank basis 104system.physmem.perBankRdReqs::8 422360 # Track reads on a per bank basis 105system.physmem.perBankRdReqs::9 415431 # Track reads on a per bank basis 106system.physmem.perBankRdReqs::10 415464 # Track reads on a per bank basis 107system.physmem.perBankRdReqs::11 415652 # Track reads on a per bank basis 108system.physmem.perBankRdReqs::12 415419 # Track reads on a per bank basis 109system.physmem.perBankRdReqs::13 415645 # Track reads on a per bank basis 110system.physmem.perBankRdReqs::14 415452 # Track reads on a per bank basis 111system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis 112system.physmem.perBankWrReqs::0 50727 # Track writes on a per bank basis 113system.physmem.perBankWrReqs::1 50837 # Track writes on a per bank basis 114system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis 115system.physmem.perBankWrReqs::3 50656 # Track writes on a per bank basis 116system.physmem.perBankWrReqs::4 51686 # Track writes on a per bank basis 117system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis 118system.physmem.perBankWrReqs::6 51505 # Track writes on a per bank basis 119system.physmem.perBankWrReqs::7 51451 # Track writes on a per bank basis 120system.physmem.perBankWrReqs::8 51696 # Track writes on a per bank basis 121system.physmem.perBankWrReqs::9 51531 # Track writes on a per bank basis 122system.physmem.perBankWrReqs::10 51439 # Track writes on a per bank basis 123system.physmem.perBankWrReqs::11 51528 # Track writes on a per bank basis 124system.physmem.perBankWrReqs::12 51471 # Track writes on a per bank basis 125system.physmem.perBankWrReqs::13 51659 # Track writes on a per bank basis 126system.physmem.perBankWrReqs::14 51507 # Track writes on a per bank basis 127system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis 128system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 129system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 130system.physmem.totGap 1182877668000 # Total gap between requests 131system.physmem.readPktSize::0 0 # Categorize read packet sizes 132system.physmem.readPktSize::1 0 # Categorize read packet sizes 133system.physmem.readPktSize::2 6825 # Categorize read packet sizes 134system.physmem.readPktSize::3 6488064 # Categorize read packet sizes 135system.physmem.readPktSize::4 0 # Categorize read packet sizes 136system.physmem.readPktSize::5 0 # Categorize read packet sizes 137system.physmem.readPktSize::6 159562 # Categorize read packet sizes 138system.physmem.readPktSize::7 0 # Categorize read packet sizes 139system.physmem.readPktSize::8 0 # Categorize read packet sizes 140system.physmem.writePktSize::0 0 # categorize write packet sizes 141system.physmem.writePktSize::1 0 # categorize write packet sizes 142system.physmem.writePktSize::2 756836 # categorize write packet sizes 143system.physmem.writePktSize::3 0 # categorize write packet sizes 144system.physmem.writePktSize::4 0 # categorize write packet sizes 145system.physmem.writePktSize::5 0 # categorize write packet sizes 146system.physmem.writePktSize::6 64292 # categorize write packet sizes 147system.physmem.writePktSize::7 0 # categorize write packet sizes 148system.physmem.writePktSize::8 0 # categorize write packet sizes 149system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 150system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 151system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 152system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 153system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 154system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 155system.physmem.neitherpktsize::6 11751 # categorize neither packet sizes 156system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 157system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 158system.physmem.rdQLenPdf::0 574129 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::1 411417 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::2 411845 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::3 427327 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::4 1182593 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::5 1193140 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::6 2312606 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::7 25343 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::8 15031 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::9 14611 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::10 14622 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::11 26114 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::12 14563 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::13 25574 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::14 2767 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::15 2575 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 177system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 178system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 179system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 180system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 181system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 182system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 183system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 184system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 185system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 186system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 187system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 188system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 189system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 190system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 191system.physmem.wrQLenPdf::0 35697 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::1 35701 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::2 35702 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::3 35702 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::4 35702 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::5 35701 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::7 35701 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::8 35701 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::9 35701 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::10 35701 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::11 35701 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::12 35701 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::13 35701 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::14 35701 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::15 35701 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::16 35701 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::17 35701 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::18 35701 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::19 35701 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::20 35701 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::21 35701 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::22 35701 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 224system.physmem.totQLat 123719908904 # Total cycles spent in queuing delays 225system.physmem.totMemAccLat 159121708904 # Sum of mem lat for all requests 226system.physmem.totBusLat 26617276000 # Total cycles spent in databus access 227system.physmem.totBankLat 8784524000 # Total cycles spent in bank access 228system.physmem.avgQLat 18592.42 # Average queueing delay per request 229system.physmem.avgBankLat 1320.12 # Average bank access latency per request 230system.physmem.avgBusLat 4000.00 # Average bus latency per request 231system.physmem.avgMemAccLat 23912.55 # Average memory access latency 232system.physmem.avgRdBW 360.04 # Average achieved read bandwidth in MB/s 233system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s 234system.physmem.avgConsumedRdBW 52.54 # Average consumed read bandwidth in MB/s 235system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s 236system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 237system.physmem.busUtil 2.53 # Data bus utilization in percentage 238system.physmem.avgRdQLen 0.13 # Average read queue length over time 239system.physmem.avgWrQLen 15.12 # Average write queue length over time 240system.physmem.readRowHits 6628163 # Number of row buffer hits during reads 241system.physmem.writeRowHits 789308 # Number of row buffer hits during writes 242system.physmem.readRowHitRate 99.61 # Row buffer hit rate for reads 243system.physmem.writeRowHitRate 96.12 # Row buffer hit rate for writes 244system.physmem.avgGap 158232.25 # Average gap between requests 245system.l2c.replacements 69442 # number of replacements 246system.l2c.tagsinuse 53039.972087 # Cycle average of tags in use 247system.l2c.total_refs 1672967 # Total number of references to valid blocks. 248system.l2c.sampled_refs 134589 # Sample count of references to valid blocks. 249system.l2c.avg_refs 12.430191 # Average number of references to valid blocks. 250system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 251system.l2c.occ_blocks::writebacks 40188.045356 # Average occupied blocks per requestor 252system.l2c.occ_blocks::cpu0.dtb.walker 0.000405 # Average occupied blocks per requestor 253system.l2c.occ_blocks::cpu0.itb.walker 0.001414 # Average occupied blocks per requestor 254system.l2c.occ_blocks::cpu0.inst 3727.182104 # Average occupied blocks per requestor 255system.l2c.occ_blocks::cpu0.data 4237.001170 # Average occupied blocks per requestor 256system.l2c.occ_blocks::cpu1.dtb.walker 2.742163 # Average occupied blocks per requestor 257system.l2c.occ_blocks::cpu1.inst 2823.633866 # Average occupied blocks per requestor 258system.l2c.occ_blocks::cpu1.data 2061.365608 # Average occupied blocks per requestor 259system.l2c.occ_percent::writebacks 0.613221 # Average percentage of cache occupancy 260system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 261system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 262system.l2c.occ_percent::cpu0.inst 0.056872 # Average percentage of cache occupancy 263system.l2c.occ_percent::cpu0.data 0.064652 # Average percentage of cache occupancy 264system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy 265system.l2c.occ_percent::cpu1.inst 0.043085 # Average percentage of cache occupancy 266system.l2c.occ_percent::cpu1.data 0.031454 # Average percentage of cache occupancy 267system.l2c.occ_percent::total 0.809326 # Average percentage of cache occupancy 268system.l2c.ReadReq_hits::cpu0.dtb.walker 4055 # number of ReadReq hits 269system.l2c.ReadReq_hits::cpu0.itb.walker 1843 # number of ReadReq hits 270system.l2c.ReadReq_hits::cpu0.inst 419673 # number of ReadReq hits 271system.l2c.ReadReq_hits::cpu0.data 206158 # number of ReadReq hits 272system.l2c.ReadReq_hits::cpu1.dtb.walker 5342 # number of ReadReq hits 273system.l2c.ReadReq_hits::cpu1.itb.walker 1844 # number of ReadReq hits 274system.l2c.ReadReq_hits::cpu1.inst 464150 # number of ReadReq hits 275system.l2c.ReadReq_hits::cpu1.data 143311 # number of ReadReq hits 276system.l2c.ReadReq_hits::total 1246376 # number of ReadReq hits 277system.l2c.Writeback_hits::writebacks 571308 # number of Writeback hits 278system.l2c.Writeback_hits::total 571308 # number of Writeback hits 279system.l2c.UpgradeReq_hits::cpu0.data 1277 # number of UpgradeReq hits 280system.l2c.UpgradeReq_hits::cpu1.data 564 # number of UpgradeReq hits 281system.l2c.UpgradeReq_hits::total 1841 # number of UpgradeReq hits 282system.l2c.SCUpgradeReq_hits::cpu0.data 215 # number of SCUpgradeReq hits 283system.l2c.SCUpgradeReq_hits::cpu1.data 104 # number of SCUpgradeReq hits 284system.l2c.SCUpgradeReq_hits::total 319 # number of SCUpgradeReq hits 285system.l2c.ReadExReq_hits::cpu0.data 56678 # number of ReadExReq hits 286system.l2c.ReadExReq_hits::cpu1.data 52482 # number of ReadExReq hits 287system.l2c.ReadExReq_hits::total 109160 # number of ReadExReq hits 288system.l2c.demand_hits::cpu0.dtb.walker 4055 # number of demand (read+write) hits 289system.l2c.demand_hits::cpu0.itb.walker 1843 # number of demand (read+write) hits 290system.l2c.demand_hits::cpu0.inst 419673 # number of demand (read+write) hits 291system.l2c.demand_hits::cpu0.data 262836 # number of demand (read+write) hits 292system.l2c.demand_hits::cpu1.dtb.walker 5342 # number of demand (read+write) hits 293system.l2c.demand_hits::cpu1.itb.walker 1844 # number of demand (read+write) hits 294system.l2c.demand_hits::cpu1.inst 464150 # number of demand (read+write) hits 295system.l2c.demand_hits::cpu1.data 195793 # number of demand (read+write) hits 296system.l2c.demand_hits::total 1355536 # number of demand (read+write) hits 297system.l2c.overall_hits::cpu0.dtb.walker 4055 # number of overall hits 298system.l2c.overall_hits::cpu0.itb.walker 1843 # number of overall hits 299system.l2c.overall_hits::cpu0.inst 419673 # number of overall hits 300system.l2c.overall_hits::cpu0.data 262836 # number of overall hits 301system.l2c.overall_hits::cpu1.dtb.walker 5342 # number of overall hits 302system.l2c.overall_hits::cpu1.itb.walker 1844 # number of overall hits 303system.l2c.overall_hits::cpu1.inst 464150 # number of overall hits 304system.l2c.overall_hits::cpu1.data 195793 # number of overall hits 305system.l2c.overall_hits::total 1355536 # number of overall hits 306system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 307system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 308system.l2c.ReadReq_misses::cpu0.inst 5736 # number of ReadReq misses 309system.l2c.ReadReq_misses::cpu0.data 7863 # number of ReadReq misses 310system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses 311system.l2c.ReadReq_misses::cpu1.inst 5044 # number of ReadReq misses 312system.l2c.ReadReq_misses::cpu1.data 3621 # number of ReadReq misses 313system.l2c.ReadReq_misses::total 22271 # number of ReadReq misses 314system.l2c.UpgradeReq_misses::cpu0.data 4685 # number of UpgradeReq misses 315system.l2c.UpgradeReq_misses::cpu1.data 3595 # number of UpgradeReq misses 316system.l2c.UpgradeReq_misses::total 8280 # number of UpgradeReq misses 317system.l2c.SCUpgradeReq_misses::cpu0.data 564 # number of SCUpgradeReq misses 318system.l2c.SCUpgradeReq_misses::cpu1.data 469 # number of SCUpgradeReq misses 319system.l2c.SCUpgradeReq_misses::total 1033 # number of SCUpgradeReq misses 320system.l2c.ReadExReq_misses::cpu0.data 67153 # number of ReadExReq misses 321system.l2c.ReadExReq_misses::cpu1.data 72577 # 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number of overall MSHR miss cycles 554system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 196008 # number of overall MSHR miss cycles 555system.l2c.overall_mshr_miss_latency::cpu1.inst 192920490 # number of overall MSHR miss cycles 556system.l2c.overall_mshr_miss_latency::cpu1.data 2677539459 # number of overall MSHR miss cycles 557system.l2c.overall_mshr_miss_latency::total 5515513716 # number of overall MSHR miss cycles 558system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 197971583 # number of ReadReq MSHR uncacheable cycles 559system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12453767609 # number of ReadReq MSHR uncacheable cycles 560system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3031674 # number of ReadReq MSHR uncacheable cycles 561system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154319820043 # number of ReadReq MSHR uncacheable cycles 562system.l2c.ReadReq_mshr_uncacheable_latency::total 166974590909 # number of ReadReq MSHR uncacheable cycles 563system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1000478250 # number of WriteReq MSHR uncacheable cycles 564system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 8214527645 # number of WriteReq MSHR uncacheable cycles 565system.l2c.WriteReq_mshr_uncacheable_latency::total 9215005895 # number of WriteReq MSHR uncacheable cycles 566system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 197971583 # number of overall MSHR uncacheable cycles 567system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13454245859 # number of overall MSHR uncacheable cycles 568system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3031674 # number of overall MSHR uncacheable cycles 569system.l2c.overall_mshr_uncacheable_latency::cpu1.data 162534347688 # number of overall MSHR uncacheable cycles 570system.l2c.overall_mshr_uncacheable_latency::total 176189596804 # number of overall MSHR uncacheable cycles 571system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for ReadReq accesses 572system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for ReadReq accesses 573system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for ReadReq accesses 574system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036739 # mshr miss rate for ReadReq accesses 575system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for ReadReq accesses 576system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for ReadReq accesses 577system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024644 # mshr miss rate for ReadReq accesses 578system.l2c.ReadReq_mshr_miss_rate::total 0.017554 # mshr miss rate for ReadReq accesses 579system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785810 # mshr miss rate for UpgradeReq accesses 580system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.864390 # mshr miss rate for UpgradeReq accesses 581system.l2c.UpgradeReq_mshr_miss_rate::total 0.818101 # mshr miss rate for UpgradeReq accesses 582system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.724005 # mshr miss rate for SCUpgradeReq accesses 583system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.818499 # mshr miss rate for SCUpgradeReq accesses 584system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.764053 # mshr miss rate for SCUpgradeReq accesses 585system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.542296 # mshr miss rate for ReadExReq accesses 586system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.580342 # mshr miss rate for ReadExReq accesses 587system.l2c.ReadExReq_mshr_miss_rate::total 0.561413 # mshr miss rate for ReadExReq accesses 588system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for demand accesses 589system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for demand accesses 590system.l2c.demand_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for demand accesses 591system.l2c.demand_mshr_miss_rate::cpu0.data 0.222038 # mshr miss rate for demand accesses 592system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for demand accesses 593system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for demand accesses 594system.l2c.demand_mshr_miss_rate::cpu1.data 0.280149 # mshr miss rate for demand accesses 595system.l2c.demand_mshr_miss_rate::total 0.106752 # mshr miss rate for demand accesses 596system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000247 # mshr miss rate for overall accesses 597system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001084 # mshr miss rate for overall accesses 598system.l2c.overall_mshr_miss_rate::cpu0.inst 0.013481 # mshr miss rate for overall accesses 599system.l2c.overall_mshr_miss_rate::cpu0.data 0.222038 # mshr miss rate for overall accesses 600system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000748 # mshr miss rate for overall accesses 601system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010750 # mshr miss rate for overall accesses 602system.l2c.overall_mshr_miss_rate::cpu1.data 0.280149 # mshr miss rate for overall accesses 603system.l2c.overall_mshr_miss_rate::total 0.106752 # mshr miss rate for overall accesses 604system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average ReadReq mshr miss latency 605system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average ReadReq mshr miss latency 606system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average ReadReq mshr miss latency 607system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 38319.614905 # average ReadReq mshr miss latency 608system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average ReadReq mshr miss latency 609system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average ReadReq mshr miss latency 610system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45335.030931 # average ReadReq mshr miss latency 611system.l2c.ReadReq_avg_mshr_miss_latency::total 39005.306242 # average ReadReq mshr miss latency 612system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.027962 # average UpgradeReq mshr miss latency 613system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.416690 # average UpgradeReq mshr miss latency 614system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10031.723309 # average UpgradeReq mshr miss latency 615system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.335106 # average SCUpgradeReq mshr miss latency 616system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.230277 # average SCUpgradeReq mshr miss latency 617system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10037.287512 # average SCUpgradeReq mshr miss latency 618system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 31770.497729 # average ReadExReq mshr miss latency 619system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 34630.548411 # average ReadExReq mshr miss latency 620system.l2c.ReadExReq_avg_mshr_miss_latency::total 33256.033393 # average ReadExReq mshr miss latency 621system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency 622system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency 623system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average overall mshr miss latency 624system.l2c.demand_avg_mshr_miss_latency::cpu0.data 32456.960728 # average overall mshr miss latency 625system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency 626system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average overall mshr miss latency 627system.l2c.demand_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency 628system.l2c.demand_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency 629system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 56002 # average overall mshr miss latency 630system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 21002 # average overall mshr miss latency 631system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 36611.750131 # average overall mshr miss latency 632system.l2c.overall_avg_mshr_miss_latency::cpu0.data 32456.960728 # average overall mshr miss latency 633system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 49002 # average overall mshr miss latency 634system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38247.519826 # average overall mshr miss latency 635system.l2c.overall_avg_mshr_miss_latency::cpu1.data 35139.235400 # average overall mshr miss latency 636system.l2c.overall_avg_mshr_miss_latency::total 34046.380963 # average overall mshr miss latency 637system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 638system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 639system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 640system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 641system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 642system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 643system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 644system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 645system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 646system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 647system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 648system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 649system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 650system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 651system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 652system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 653system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 654system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 655system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 656system.cf0.dma_write_txs 0 # Number of DMA write transactions. 657system.cpu0.dtb.inst_hits 0 # ITB inst hits 658system.cpu0.dtb.inst_misses 0 # ITB inst misses 659system.cpu0.dtb.read_hits 7070111 # DTB read hits 660system.cpu0.dtb.read_misses 3764 # DTB read misses 661system.cpu0.dtb.write_hits 5656042 # DTB write hits 662system.cpu0.dtb.write_misses 804 # DTB write misses 663system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 664system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 665system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 666system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 667system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB 668system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 669system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch 670system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 671system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 672system.cpu0.dtb.read_accesses 7073875 # DTB read accesses 673system.cpu0.dtb.write_accesses 5656846 # DTB write accesses 674system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 675system.cpu0.dtb.hits 12726153 # DTB hits 676system.cpu0.dtb.misses 4568 # DTB misses 677system.cpu0.dtb.accesses 12730721 # DTB accesses 678system.cpu0.itb.inst_hits 29570310 # ITB inst hits 679system.cpu0.itb.inst_misses 2205 # ITB inst misses 680system.cpu0.itb.read_hits 0 # DTB read hits 681system.cpu0.itb.read_misses 0 # DTB read misses 682system.cpu0.itb.write_hits 0 # DTB write hits 683system.cpu0.itb.write_misses 0 # DTB write misses 684system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 685system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 686system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 687system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 688system.cpu0.itb.flush_entries 1332 # Number of entries that have been flushed from TLB 689system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 690system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 691system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 692system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 693system.cpu0.itb.read_accesses 0 # DTB read accesses 694system.cpu0.itb.write_accesses 0 # DTB write accesses 695system.cpu0.itb.inst_accesses 29572515 # ITB inst accesses 696system.cpu0.itb.hits 29570310 # DTB hits 697system.cpu0.itb.misses 2205 # DTB misses 698system.cpu0.itb.accesses 29572515 # DTB accesses 699system.cpu0.numCycles 2365764313 # number of cpu cycles simulated 700system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 701system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 702system.cpu0.committedInsts 28872367 # Number of instructions committed 703system.cpu0.committedOps 37211047 # Number of ops (including micro ops) committed 704system.cpu0.num_int_alu_accesses 33098187 # Number of integer alu accesses 705system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses 706system.cpu0.num_func_calls 1241715 # number of times a function call or return occured 707system.cpu0.num_conditional_control_insts 4373222 # number of instructions that are conditional controls 708system.cpu0.num_int_insts 33098187 # number of integer instructions 709system.cpu0.num_fp_insts 3860 # number of float instructions 710system.cpu0.num_int_register_reads 190047206 # number of times the integer registers were read 711system.cpu0.num_int_register_writes 36225366 # number of times the integer registers were written 712system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read 713system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written 714system.cpu0.num_mem_refs 13394441 # number of memory refs 715system.cpu0.num_load_insts 7407672 # Number of load instructions 716system.cpu0.num_store_insts 5986769 # Number of store instructions 717system.cpu0.num_idle_cycles 2224997657.358119 # Number of idle cycles 718system.cpu0.num_busy_cycles 140766655.641881 # Number of busy cycles 719system.cpu0.not_idle_fraction 0.059502 # Percentage of non-idle cycles 720system.cpu0.idle_fraction 0.940498 # Percentage of idle cycles 721system.cpu0.kern.inst.arm 0 # number of arm instructions executed 722system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed 723system.cpu0.icache.replacements 425445 # number of replacements 724system.cpu0.icache.tagsinuse 509.616014 # Cycle average of tags in use 725system.cpu0.icache.total_refs 29144335 # Total number of references to valid blocks. 726system.cpu0.icache.sampled_refs 425957 # Sample count of references to valid blocks. 727system.cpu0.icache.avg_refs 68.420838 # Average number of references to valid blocks. 728system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit. 729system.cpu0.icache.occ_blocks::cpu0.inst 509.616014 # Average occupied blocks per requestor 730system.cpu0.icache.occ_percent::cpu0.inst 0.995344 # Average percentage of cache occupancy 731system.cpu0.icache.occ_percent::total 0.995344 # Average percentage of cache occupancy 732system.cpu0.icache.ReadReq_hits::cpu0.inst 29144335 # number of ReadReq hits 733system.cpu0.icache.ReadReq_hits::total 29144335 # number of ReadReq hits 734system.cpu0.icache.demand_hits::cpu0.inst 29144335 # number of demand (read+write) hits 735system.cpu0.icache.demand_hits::total 29144335 # number of demand (read+write) hits 736system.cpu0.icache.overall_hits::cpu0.inst 29144335 # number of overall hits 737system.cpu0.icache.overall_hits::total 29144335 # number of overall hits 738system.cpu0.icache.ReadReq_misses::cpu0.inst 425958 # number of ReadReq misses 739system.cpu0.icache.ReadReq_misses::total 425958 # number of ReadReq misses 740system.cpu0.icache.demand_misses::cpu0.inst 425958 # number of demand (read+write) misses 741system.cpu0.icache.demand_misses::total 425958 # number of demand (read+write) misses 742system.cpu0.icache.overall_misses::cpu0.inst 425958 # number of overall misses 743system.cpu0.icache.overall_misses::total 425958 # number of overall misses 744system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5792188000 # number of ReadReq miss cycles 745system.cpu0.icache.ReadReq_miss_latency::total 5792188000 # number of ReadReq miss cycles 746system.cpu0.icache.demand_miss_latency::cpu0.inst 5792188000 # number of demand (read+write) miss cycles 747system.cpu0.icache.demand_miss_latency::total 5792188000 # number of demand (read+write) miss cycles 748system.cpu0.icache.overall_miss_latency::cpu0.inst 5792188000 # number of overall miss cycles 749system.cpu0.icache.overall_miss_latency::total 5792188000 # number of overall miss cycles 750system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570293 # number of ReadReq accesses(hits+misses) 751system.cpu0.icache.ReadReq_accesses::total 29570293 # number of ReadReq accesses(hits+misses) 752system.cpu0.icache.demand_accesses::cpu0.inst 29570293 # number of demand (read+write) accesses 753system.cpu0.icache.demand_accesses::total 29570293 # number of demand (read+write) accesses 754system.cpu0.icache.overall_accesses::cpu0.inst 29570293 # number of overall (read+write) accesses 755system.cpu0.icache.overall_accesses::total 29570293 # number of overall (read+write) accesses 756system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses 757system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses 758system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses 759system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses 760system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses 761system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses 762system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.026096 # average ReadReq miss latency 763system.cpu0.icache.ReadReq_avg_miss_latency::total 13598.026096 # average ReadReq miss latency 764system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency 765system.cpu0.icache.demand_avg_miss_latency::total 13598.026096 # average overall miss latency 766system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency 767system.cpu0.icache.overall_avg_miss_latency::total 13598.026096 # average overall miss latency 768system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 769system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 770system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 771system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 772system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 773system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 774system.cpu0.icache.fast_writes 0 # number of fast writes performed 775system.cpu0.icache.cache_copies 0 # number of cache copies performed 776system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425958 # number of ReadReq MSHR misses 777system.cpu0.icache.ReadReq_mshr_misses::total 425958 # number of ReadReq MSHR misses 778system.cpu0.icache.demand_mshr_misses::cpu0.inst 425958 # number of demand (read+write) MSHR misses 779system.cpu0.icache.demand_mshr_misses::total 425958 # number of demand (read+write) MSHR misses 780system.cpu0.icache.overall_mshr_misses::cpu0.inst 425958 # number of overall MSHR misses 781system.cpu0.icache.overall_mshr_misses::total 425958 # number of overall MSHR misses 782system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4940272000 # number of ReadReq MSHR miss cycles 783system.cpu0.icache.ReadReq_mshr_miss_latency::total 4940272000 # number of ReadReq MSHR miss cycles 784system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4940272000 # number of demand (read+write) MSHR miss cycles 785system.cpu0.icache.demand_mshr_miss_latency::total 4940272000 # number of demand (read+write) MSHR miss cycles 786system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4940272000 # number of overall MSHR miss cycles 787system.cpu0.icache.overall_mshr_miss_latency::total 4940272000 # number of overall MSHR miss cycles 788system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288882000 # number of ReadReq MSHR uncacheable cycles 789system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 288882000 # number of ReadReq MSHR uncacheable cycles 790system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288882000 # number of overall MSHR uncacheable cycles 791system.cpu0.icache.overall_mshr_uncacheable_latency::total 288882000 # number of overall MSHR uncacheable cycles 792system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses 793system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses 794system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses 795system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses 796system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses 797system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses 798system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average ReadReq mshr miss latency 799system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11598.026096 # average ReadReq mshr miss latency 800system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency 801system.cpu0.icache.demand_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency 802system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency 803system.cpu0.icache.overall_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency 804system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency 805system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 806system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency 807system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 808system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 809system.cpu0.dcache.replacements 330355 # number of replacements 810system.cpu0.dcache.tagsinuse 453.331528 # Cycle average of tags in use 811system.cpu0.dcache.total_refs 12270860 # Total number of references to valid blocks. 812system.cpu0.dcache.sampled_refs 330867 # Sample count of references to valid blocks. 813system.cpu0.dcache.avg_refs 37.086987 # Average number of references to valid blocks. 814system.cpu0.dcache.warmup_cycle 462692000 # Cycle when the warmup percentage was hit. 815system.cpu0.dcache.occ_blocks::cpu0.data 453.331528 # Average occupied blocks per requestor 816system.cpu0.dcache.occ_percent::cpu0.data 0.885413 # Average percentage of cache occupancy 817system.cpu0.dcache.occ_percent::total 0.885413 # Average percentage of cache occupancy 818system.cpu0.dcache.ReadReq_hits::cpu0.data 6599943 # number of ReadReq hits 819system.cpu0.dcache.ReadReq_hits::total 6599943 # number of ReadReq hits 820system.cpu0.dcache.WriteReq_hits::cpu0.data 5351121 # number of WriteReq hits 821system.cpu0.dcache.WriteReq_hits::total 5351121 # number of WriteReq hits 822system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147941 # number of LoadLockedReq hits 823system.cpu0.dcache.LoadLockedReq_hits::total 147941 # number of LoadLockedReq hits 824system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149661 # number of StoreCondReq hits 825system.cpu0.dcache.StoreCondReq_hits::total 149661 # number of StoreCondReq hits 826system.cpu0.dcache.demand_hits::cpu0.data 11951064 # number of demand (read+write) hits 827system.cpu0.dcache.demand_hits::total 11951064 # number of demand (read+write) hits 828system.cpu0.dcache.overall_hits::cpu0.data 11951064 # number of overall hits 829system.cpu0.dcache.overall_hits::total 11951064 # number of overall hits 830system.cpu0.dcache.ReadReq_misses::cpu0.data 227863 # number of ReadReq misses 831system.cpu0.dcache.ReadReq_misses::total 227863 # number of ReadReq misses 832system.cpu0.dcache.WriteReq_misses::cpu0.data 141515 # number of WriteReq misses 833system.cpu0.dcache.WriteReq_misses::total 141515 # number of WriteReq misses 834system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9301 # number of LoadLockedReq misses 835system.cpu0.dcache.LoadLockedReq_misses::total 9301 # number of LoadLockedReq misses 836system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7492 # number of StoreCondReq misses 837system.cpu0.dcache.StoreCondReq_misses::total 7492 # number of StoreCondReq misses 838system.cpu0.dcache.demand_misses::cpu0.data 369378 # number of demand (read+write) misses 839system.cpu0.dcache.demand_misses::total 369378 # number of demand (read+write) misses 840system.cpu0.dcache.overall_misses::cpu0.data 369378 # number of overall misses 841system.cpu0.dcache.overall_misses::total 369378 # number of overall misses 842system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3130112000 # number of ReadReq miss cycles 843system.cpu0.dcache.ReadReq_miss_latency::total 3130112000 # number of ReadReq miss cycles 844system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4103795500 # number of WriteReq miss cycles 845system.cpu0.dcache.WriteReq_miss_latency::total 4103795500 # number of WriteReq miss cycles 846system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87984000 # number of LoadLockedReq miss cycles 847system.cpu0.dcache.LoadLockedReq_miss_latency::total 87984000 # number of LoadLockedReq miss cycles 848system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44508500 # number of StoreCondReq miss cycles 849system.cpu0.dcache.StoreCondReq_miss_latency::total 44508500 # number of StoreCondReq miss cycles 850system.cpu0.dcache.demand_miss_latency::cpu0.data 7233907500 # number of demand (read+write) miss cycles 851system.cpu0.dcache.demand_miss_latency::total 7233907500 # number of demand (read+write) miss cycles 852system.cpu0.dcache.overall_miss_latency::cpu0.data 7233907500 # number of overall miss cycles 853system.cpu0.dcache.overall_miss_latency::total 7233907500 # number of overall miss cycles 854system.cpu0.dcache.ReadReq_accesses::cpu0.data 6827806 # number of ReadReq accesses(hits+misses) 855system.cpu0.dcache.ReadReq_accesses::total 6827806 # number of ReadReq accesses(hits+misses) 856system.cpu0.dcache.WriteReq_accesses::cpu0.data 5492636 # number of WriteReq accesses(hits+misses) 857system.cpu0.dcache.WriteReq_accesses::total 5492636 # number of WriteReq accesses(hits+misses) 858system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157242 # number of LoadLockedReq accesses(hits+misses) 859system.cpu0.dcache.LoadLockedReq_accesses::total 157242 # number of LoadLockedReq accesses(hits+misses) 860system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157153 # number of StoreCondReq accesses(hits+misses) 861system.cpu0.dcache.StoreCondReq_accesses::total 157153 # number of StoreCondReq accesses(hits+misses) 862system.cpu0.dcache.demand_accesses::cpu0.data 12320442 # number of demand (read+write) accesses 863system.cpu0.dcache.demand_accesses::total 12320442 # number of demand (read+write) accesses 864system.cpu0.dcache.overall_accesses::cpu0.data 12320442 # number of overall (read+write) accesses 865system.cpu0.dcache.overall_accesses::total 12320442 # number of overall (read+write) accesses 866system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033373 # miss rate for ReadReq accesses 867system.cpu0.dcache.ReadReq_miss_rate::total 0.033373 # miss rate for ReadReq accesses 868system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025764 # miss rate for WriteReq accesses 869system.cpu0.dcache.WriteReq_miss_rate::total 0.025764 # miss rate for WriteReq accesses 870system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059151 # miss rate for LoadLockedReq accesses 871system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059151 # miss rate for LoadLockedReq accesses 872system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047673 # miss rate for StoreCondReq accesses 873system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047673 # miss rate for StoreCondReq accesses 874system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029981 # miss rate for demand accesses 875system.cpu0.dcache.demand_miss_rate::total 0.029981 # miss rate for demand accesses 876system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029981 # miss rate for overall accesses 877system.cpu0.dcache.overall_miss_rate::total 0.029981 # miss rate for overall accesses 878system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13736.815543 # average ReadReq miss latency 879system.cpu0.dcache.ReadReq_avg_miss_latency::total 13736.815543 # average ReadReq miss latency 880system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28999.014239 # average WriteReq miss latency 881system.cpu0.dcache.WriteReq_avg_miss_latency::total 28999.014239 # average WriteReq miss latency 882system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9459.627997 # average LoadLockedReq miss latency 883system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9459.627997 # average LoadLockedReq miss latency 884system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5940.803524 # average StoreCondReq miss latency 885system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5940.803524 # average StoreCondReq miss latency 886system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19584.023683 # average overall miss latency 887system.cpu0.dcache.demand_avg_miss_latency::total 19584.023683 # average overall miss latency 888system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19584.023683 # average overall miss latency 889system.cpu0.dcache.overall_avg_miss_latency::total 19584.023683 # average overall miss latency 890system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 891system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 892system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 893system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 894system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 895system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 896system.cpu0.dcache.fast_writes 0 # number of fast writes performed 897system.cpu0.dcache.cache_copies 0 # number of cache copies performed 898system.cpu0.dcache.writebacks::writebacks 306206 # number of writebacks 899system.cpu0.dcache.writebacks::total 306206 # number of writebacks 900system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227863 # number of ReadReq MSHR misses 901system.cpu0.dcache.ReadReq_mshr_misses::total 227863 # number of ReadReq MSHR misses 902system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141515 # number of WriteReq MSHR misses 903system.cpu0.dcache.WriteReq_mshr_misses::total 141515 # number of WriteReq MSHR misses 904system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9301 # number of LoadLockedReq MSHR misses 905system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9301 # number of LoadLockedReq MSHR misses 906system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7489 # number of StoreCondReq MSHR misses 907system.cpu0.dcache.StoreCondReq_mshr_misses::total 7489 # number of StoreCondReq MSHR misses 908system.cpu0.dcache.demand_mshr_misses::cpu0.data 369378 # number of demand (read+write) MSHR misses 909system.cpu0.dcache.demand_mshr_misses::total 369378 # number of demand (read+write) MSHR misses 910system.cpu0.dcache.overall_mshr_misses::cpu0.data 369378 # number of overall MSHR misses 911system.cpu0.dcache.overall_mshr_misses::total 369378 # number of overall MSHR misses 912system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2674386000 # number of ReadReq MSHR miss cycles 913system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2674386000 # number of ReadReq MSHR miss cycles 914system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3820765500 # number of WriteReq MSHR miss cycles 915system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3820765500 # number of WriteReq MSHR miss cycles 916system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69382000 # number of LoadLockedReq MSHR miss cycles 917system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 69382000 # number of LoadLockedReq MSHR miss cycles 918system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29532500 # number of StoreCondReq MSHR miss cycles 919system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29532500 # number of StoreCondReq MSHR miss cycles 920system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles 921system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 922system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6495151500 # number of demand (read+write) MSHR miss cycles 923system.cpu0.dcache.demand_mshr_miss_latency::total 6495151500 # number of demand (read+write) MSHR miss cycles 924system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6495151500 # number of overall MSHR miss cycles 925system.cpu0.dcache.overall_mshr_miss_latency::total 6495151500 # number of overall MSHR miss cycles 926system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13561363000 # number of ReadReq MSHR uncacheable cycles 927system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13561363000 # number of ReadReq MSHR uncacheable cycles 928system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128479500 # number of WriteReq MSHR uncacheable cycles 929system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128479500 # number of WriteReq MSHR uncacheable cycles 930system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14689842500 # number of overall MSHR uncacheable cycles 931system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14689842500 # number of overall MSHR uncacheable cycles 932system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033373 # mshr miss rate for ReadReq accesses 933system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033373 # mshr miss rate for ReadReq accesses 934system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses 935system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses 936system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059151 # mshr miss rate for LoadLockedReq accesses 937system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059151 # mshr miss rate for LoadLockedReq accesses 938system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047654 # mshr miss rate for StoreCondReq accesses 939system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047654 # mshr miss rate for StoreCondReq accesses 940system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for demand accesses 941system.cpu0.dcache.demand_mshr_miss_rate::total 0.029981 # mshr miss rate for demand accesses 942system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for overall accesses 943system.cpu0.dcache.overall_mshr_miss_rate::total 0.029981 # mshr miss rate for overall accesses 944system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11736.815543 # average ReadReq mshr miss latency 945system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543 # average ReadReq mshr miss latency 946system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239 # average WriteReq mshr miss latency 947system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239 # average WriteReq mshr miss latency 948system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7459.627997 # average LoadLockedReq mshr miss latency 949system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7459.627997 # average LoadLockedReq mshr miss latency 950system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3943.450394 # average StoreCondReq mshr miss latency 951system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3943.450394 # average StoreCondReq mshr miss latency 952system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 953system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 954system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency 955system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency 956system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency 957system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency 958system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency 959system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 960system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency 961system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 962system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency 963system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 964system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 965system.cpu1.dtb.inst_hits 0 # ITB inst hits 966system.cpu1.dtb.inst_misses 0 # ITB inst misses 967system.cpu1.dtb.read_hits 8310545 # DTB read hits 968system.cpu1.dtb.read_misses 3643 # DTB read misses 969system.cpu1.dtb.write_hits 5827351 # DTB write hits 970system.cpu1.dtb.write_misses 1434 # DTB write misses 971system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 972system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 973system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 974system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 975system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB 976system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 977system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch 978system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 979system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 980system.cpu1.dtb.read_accesses 8314188 # DTB read accesses 981system.cpu1.dtb.write_accesses 5828785 # DTB write accesses 982system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 983system.cpu1.dtb.hits 14137896 # DTB hits 984system.cpu1.dtb.misses 5077 # DTB misses 985system.cpu1.dtb.accesses 14142973 # DTB accesses 986system.cpu1.itb.inst_hits 33189113 # ITB inst hits 987system.cpu1.itb.inst_misses 2171 # ITB inst misses 988system.cpu1.itb.read_hits 0 # DTB read hits 989system.cpu1.itb.read_misses 0 # DTB read misses 990system.cpu1.itb.write_hits 0 # DTB write hits 991system.cpu1.itb.write_misses 0 # DTB write misses 992system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 993system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 994system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 995system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 996system.cpu1.itb.flush_entries 1495 # Number of entries that have been flushed from TLB 997system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 998system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 999system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1000system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1001system.cpu1.itb.read_accesses 0 # DTB read accesses 1002system.cpu1.itb.write_accesses 0 # DTB write accesses 1003system.cpu1.itb.inst_accesses 33191284 # ITB inst accesses 1004system.cpu1.itb.hits 33189113 # DTB hits 1005system.cpu1.itb.misses 2171 # DTB misses 1006system.cpu1.itb.accesses 33191284 # DTB accesses 1007system.cpu1.numCycles 2364318212 # number of cpu cycles simulated 1008system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1009system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1010system.cpu1.committedInsts 32578626 # Number of instructions committed 1011system.cpu1.committedOps 41088668 # Number of ops (including micro ops) committed 1012system.cpu1.num_int_alu_accesses 37313171 # Number of integer alu accesses 1013system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses 1014system.cpu1.num_func_calls 962009 # number of times a function call or return occured 1015system.cpu1.num_conditional_control_insts 3732639 # number of instructions that are conditional controls 1016system.cpu1.num_int_insts 37313171 # number of integer instructions 1017system.cpu1.num_fp_insts 6793 # number of float instructions 1018system.cpu1.num_int_register_reads 213663418 # number of times the integer registers were read 1019system.cpu1.num_int_register_writes 39454743 # number of times the integer registers were written 1020system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read 1021system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written 1022system.cpu1.num_mem_refs 14675641 # number of memory refs 1023system.cpu1.num_load_insts 8632449 # Number of load instructions 1024system.cpu1.num_store_insts 6043192 # Number of store instructions 1025system.cpu1.num_idle_cycles 1868258895.232782 # Number of idle cycles 1026system.cpu1.num_busy_cycles 496059316.767218 # Number of busy cycles 1027system.cpu1.not_idle_fraction 0.209811 # Percentage of non-idle cycles 1028system.cpu1.idle_fraction 0.790189 # Percentage of idle cycles 1029system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1030system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed 1031system.cpu1.icache.replacements 469194 # number of replacements 1032system.cpu1.icache.tagsinuse 478.783096 # Cycle average of tags in use 1033system.cpu1.icache.total_refs 32719403 # Total number of references to valid blocks. 1034system.cpu1.icache.sampled_refs 469706 # Sample count of references to valid blocks. 1035system.cpu1.icache.avg_refs 69.659325 # Average number of references to valid blocks. 1036system.cpu1.icache.warmup_cycle 92023963500 # Cycle when the warmup percentage was hit. 1037system.cpu1.icache.occ_blocks::cpu1.inst 478.783096 # Average occupied blocks per requestor 1038system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy 1039system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy 1040system.cpu1.icache.ReadReq_hits::cpu1.inst 32719403 # number of ReadReq hits 1041system.cpu1.icache.ReadReq_hits::total 32719403 # number of ReadReq hits 1042system.cpu1.icache.demand_hits::cpu1.inst 32719403 # number of demand (read+write) hits 1043system.cpu1.icache.demand_hits::total 32719403 # number of demand (read+write) hits 1044system.cpu1.icache.overall_hits::cpu1.inst 32719403 # number of overall hits 1045system.cpu1.icache.overall_hits::total 32719403 # number of overall hits 1046system.cpu1.icache.ReadReq_misses::cpu1.inst 469706 # number of ReadReq misses 1047system.cpu1.icache.ReadReq_misses::total 469706 # number of ReadReq misses 1048system.cpu1.icache.demand_misses::cpu1.inst 469706 # number of demand (read+write) misses 1049system.cpu1.icache.demand_misses::total 469706 # number of demand (read+write) misses 1050system.cpu1.icache.overall_misses::cpu1.inst 469706 # number of overall misses 1051system.cpu1.icache.overall_misses::total 469706 # number of overall misses 1052system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6343605000 # number of ReadReq miss cycles 1053system.cpu1.icache.ReadReq_miss_latency::total 6343605000 # number of ReadReq miss cycles 1054system.cpu1.icache.demand_miss_latency::cpu1.inst 6343605000 # number of demand (read+write) miss cycles 1055system.cpu1.icache.demand_miss_latency::total 6343605000 # number of demand (read+write) miss cycles 1056system.cpu1.icache.overall_miss_latency::cpu1.inst 6343605000 # number of overall miss cycles 1057system.cpu1.icache.overall_miss_latency::total 6343605000 # number of overall miss cycles 1058system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189109 # number of ReadReq accesses(hits+misses) 1059system.cpu1.icache.ReadReq_accesses::total 33189109 # number of ReadReq accesses(hits+misses) 1060system.cpu1.icache.demand_accesses::cpu1.inst 33189109 # number of demand (read+write) accesses 1061system.cpu1.icache.demand_accesses::total 33189109 # number of demand (read+write) accesses 1062system.cpu1.icache.overall_accesses::cpu1.inst 33189109 # number of overall (read+write) accesses 1063system.cpu1.icache.overall_accesses::total 33189109 # number of overall (read+write) accesses 1064system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014152 # miss rate for ReadReq accesses 1065system.cpu1.icache.ReadReq_miss_rate::total 0.014152 # miss rate for ReadReq accesses 1066system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014152 # miss rate for demand accesses 1067system.cpu1.icache.demand_miss_rate::total 0.014152 # miss rate for demand accesses 1068system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014152 # miss rate for overall accesses 1069system.cpu1.icache.overall_miss_rate::total 0.014152 # miss rate for overall accesses 1070system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.480024 # average ReadReq miss latency 1071system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.480024 # average ReadReq miss latency 1072system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency 1073system.cpu1.icache.demand_avg_miss_latency::total 13505.480024 # average overall miss latency 1074system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency 1075system.cpu1.icache.overall_avg_miss_latency::total 13505.480024 # average overall miss latency 1076system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1077system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1078system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1079system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1080system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1081system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1082system.cpu1.icache.fast_writes 0 # number of fast writes performed 1083system.cpu1.icache.cache_copies 0 # number of cache copies performed 1084system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469706 # number of ReadReq MSHR misses 1085system.cpu1.icache.ReadReq_mshr_misses::total 469706 # number of ReadReq MSHR misses 1086system.cpu1.icache.demand_mshr_misses::cpu1.inst 469706 # number of demand (read+write) MSHR misses 1087system.cpu1.icache.demand_mshr_misses::total 469706 # number of demand (read+write) MSHR misses 1088system.cpu1.icache.overall_mshr_misses::cpu1.inst 469706 # number of overall MSHR misses 1089system.cpu1.icache.overall_mshr_misses::total 469706 # number of overall MSHR misses 1090system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5404193000 # number of ReadReq MSHR miss cycles 1091system.cpu1.icache.ReadReq_mshr_miss_latency::total 5404193000 # number of ReadReq MSHR miss cycles 1092system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5404193000 # number of demand (read+write) MSHR miss cycles 1093system.cpu1.icache.demand_mshr_miss_latency::total 5404193000 # number of demand (read+write) MSHR miss cycles 1094system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5404193000 # number of overall MSHR miss cycles 1095system.cpu1.icache.overall_mshr_miss_latency::total 5404193000 # number of overall MSHR miss cycles 1096system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles 1097system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles 1098system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles 1099system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles 1100system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for ReadReq accesses 1101system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014152 # mshr miss rate for ReadReq accesses 1102system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for demand accesses 1103system.cpu1.icache.demand_mshr_miss_rate::total 0.014152 # mshr miss rate for demand accesses 1104system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for overall accesses 1105system.cpu1.icache.overall_mshr_miss_rate::total 0.014152 # mshr miss rate for overall accesses 1106system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average ReadReq mshr miss latency 1107system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11505.480024 # average ReadReq mshr miss latency 1108system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency 1109system.cpu1.icache.demand_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency 1110system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency 1111system.cpu1.icache.overall_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency 1112system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency 1113system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1114system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 1115system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1116system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1117system.cpu1.dcache.replacements 292054 # number of replacements 1118system.cpu1.dcache.tagsinuse 471.972808 # Cycle average of tags in use 1119system.cpu1.dcache.total_refs 11961234 # Total number of references to valid blocks. 1120system.cpu1.dcache.sampled_refs 292426 # Sample count of references to valid blocks. 1121system.cpu1.dcache.avg_refs 40.903456 # Average number of references to valid blocks. 1122system.cpu1.dcache.warmup_cycle 83625409000 # Cycle when the warmup percentage was hit. 1123system.cpu1.dcache.occ_blocks::cpu1.data 471.972808 # Average occupied blocks per requestor 1124system.cpu1.dcache.occ_percent::cpu1.data 0.921822 # Average percentage of cache occupancy 1125system.cpu1.dcache.occ_percent::total 0.921822 # Average percentage of cache occupancy 1126system.cpu1.dcache.ReadReq_hits::cpu1.data 6946091 # number of ReadReq hits 1127system.cpu1.dcache.ReadReq_hits::total 6946091 # number of ReadReq hits 1128system.cpu1.dcache.WriteReq_hits::cpu1.data 4827134 # number of WriteReq hits 1129system.cpu1.dcache.WriteReq_hits::total 4827134 # number of WriteReq hits 1130system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81752 # number of LoadLockedReq hits 1131system.cpu1.dcache.LoadLockedReq_hits::total 81752 # number of LoadLockedReq hits 1132system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82714 # number of StoreCondReq hits 1133system.cpu1.dcache.StoreCondReq_hits::total 82714 # number of StoreCondReq hits 1134system.cpu1.dcache.demand_hits::cpu1.data 11773225 # number of demand (read+write) hits 1135system.cpu1.dcache.demand_hits::total 11773225 # number of demand (read+write) hits 1136system.cpu1.dcache.overall_hits::cpu1.data 11773225 # number of overall hits 1137system.cpu1.dcache.overall_hits::total 11773225 # number of overall hits 1138system.cpu1.dcache.ReadReq_misses::cpu1.data 170515 # number of ReadReq misses 1139system.cpu1.dcache.ReadReq_misses::total 170515 # number of ReadReq misses 1140system.cpu1.dcache.WriteReq_misses::cpu1.data 149924 # number of WriteReq misses 1141system.cpu1.dcache.WriteReq_misses::total 149924 # number of WriteReq misses 1142system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11068 # number of LoadLockedReq misses 1143system.cpu1.dcache.LoadLockedReq_misses::total 11068 # number of LoadLockedReq misses 1144system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10031 # number of StoreCondReq misses 1145system.cpu1.dcache.StoreCondReq_misses::total 10031 # number of StoreCondReq misses 1146system.cpu1.dcache.demand_misses::cpu1.data 320439 # number of demand (read+write) misses 1147system.cpu1.dcache.demand_misses::total 320439 # number of demand (read+write) misses 1148system.cpu1.dcache.overall_misses::cpu1.data 320439 # number of overall misses 1149system.cpu1.dcache.overall_misses::total 320439 # number of overall misses 1150system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2149232000 # number of ReadReq miss cycles 1151system.cpu1.dcache.ReadReq_miss_latency::total 2149232000 # number of ReadReq miss cycles 1152system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4527081500 # number of WriteReq miss cycles 1153system.cpu1.dcache.WriteReq_miss_latency::total 4527081500 # number of WriteReq miss cycles 1154system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92245500 # number of LoadLockedReq miss cycles 1155system.cpu1.dcache.LoadLockedReq_miss_latency::total 92245500 # number of LoadLockedReq miss cycles 1156system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51683000 # number of StoreCondReq miss cycles 1157system.cpu1.dcache.StoreCondReq_miss_latency::total 51683000 # number of StoreCondReq miss cycles 1158system.cpu1.dcache.demand_miss_latency::cpu1.data 6676313500 # number of demand (read+write) miss cycles 1159system.cpu1.dcache.demand_miss_latency::total 6676313500 # number of demand (read+write) miss cycles 1160system.cpu1.dcache.overall_miss_latency::cpu1.data 6676313500 # number of overall miss cycles 1161system.cpu1.dcache.overall_miss_latency::total 6676313500 # number of overall miss cycles 1162system.cpu1.dcache.ReadReq_accesses::cpu1.data 7116606 # number of ReadReq accesses(hits+misses) 1163system.cpu1.dcache.ReadReq_accesses::total 7116606 # number of ReadReq accesses(hits+misses) 1164system.cpu1.dcache.WriteReq_accesses::cpu1.data 4977058 # number of WriteReq accesses(hits+misses) 1165system.cpu1.dcache.WriteReq_accesses::total 4977058 # number of WriteReq accesses(hits+misses) 1166system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 92820 # number of LoadLockedReq accesses(hits+misses) 1167system.cpu1.dcache.LoadLockedReq_accesses::total 92820 # number of LoadLockedReq accesses(hits+misses) 1168system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92745 # number of StoreCondReq accesses(hits+misses) 1169system.cpu1.dcache.StoreCondReq_accesses::total 92745 # number of StoreCondReq accesses(hits+misses) 1170system.cpu1.dcache.demand_accesses::cpu1.data 12093664 # number of demand (read+write) accesses 1171system.cpu1.dcache.demand_accesses::total 12093664 # number of demand (read+write) accesses 1172system.cpu1.dcache.overall_accesses::cpu1.data 12093664 # number of overall (read+write) accesses 1173system.cpu1.dcache.overall_accesses::total 12093664 # number of overall (read+write) accesses 1174system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023960 # miss rate for ReadReq accesses 1175system.cpu1.dcache.ReadReq_miss_rate::total 0.023960 # miss rate for ReadReq accesses 1176system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030123 # miss rate for WriteReq accesses 1177system.cpu1.dcache.WriteReq_miss_rate::total 0.030123 # miss rate for WriteReq accesses 1178system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119242 # miss rate for LoadLockedReq accesses 1179system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119242 # miss rate for LoadLockedReq accesses 1180system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108157 # miss rate for StoreCondReq accesses 1181system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108157 # miss rate for StoreCondReq accesses 1182system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026496 # miss rate for demand accesses 1183system.cpu1.dcache.demand_miss_rate::total 0.026496 # miss rate for demand accesses 1184system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026496 # miss rate for overall accesses 1185system.cpu1.dcache.overall_miss_rate::total 0.026496 # miss rate for overall accesses 1186system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12604.357388 # average ReadReq miss latency 1187system.cpu1.dcache.ReadReq_avg_miss_latency::total 12604.357388 # average ReadReq miss latency 1188system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30195.842560 # average WriteReq miss latency 1189system.cpu1.dcache.WriteReq_avg_miss_latency::total 30195.842560 # average WriteReq miss latency 1190system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8334.432598 # average LoadLockedReq miss latency 1191system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8334.432598 # average LoadLockedReq miss latency 1192system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5152.327784 # average StoreCondReq miss latency 1193system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5152.327784 # average StoreCondReq miss latency 1194system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency 1195system.cpu1.dcache.demand_avg_miss_latency::total 20834.896813 # average overall miss latency 1196system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency 1197system.cpu1.dcache.overall_avg_miss_latency::total 20834.896813 # average overall miss latency 1198system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1199system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1200system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1201system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1202system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1203system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1204system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1205system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1206system.cpu1.dcache.writebacks::writebacks 265102 # number of writebacks 1207system.cpu1.dcache.writebacks::total 265102 # number of writebacks 1208system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170515 # number of ReadReq MSHR misses 1209system.cpu1.dcache.ReadReq_mshr_misses::total 170515 # number of ReadReq MSHR misses 1210system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149924 # number of WriteReq MSHR misses 1211system.cpu1.dcache.WriteReq_mshr_misses::total 149924 # number of WriteReq MSHR misses 1212system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11068 # number of LoadLockedReq MSHR misses 1213system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11068 # number of LoadLockedReq MSHR misses 1214system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10026 # number of StoreCondReq MSHR misses 1215system.cpu1.dcache.StoreCondReq_mshr_misses::total 10026 # number of StoreCondReq MSHR misses 1216system.cpu1.dcache.demand_mshr_misses::cpu1.data 320439 # number of demand (read+write) MSHR misses 1217system.cpu1.dcache.demand_mshr_misses::total 320439 # number of demand (read+write) MSHR misses 1218system.cpu1.dcache.overall_mshr_misses::cpu1.data 320439 # number of overall MSHR misses 1219system.cpu1.dcache.overall_mshr_misses::total 320439 # number of overall MSHR misses 1220system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1808202000 # number of ReadReq MSHR miss cycles 1221system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1808202000 # number of ReadReq MSHR miss cycles 1222system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4227233500 # number of WriteReq MSHR miss cycles 1223system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4227233500 # number of WriteReq MSHR miss cycles 1224system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70109500 # number of LoadLockedReq MSHR miss cycles 1225system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70109500 # number of LoadLockedReq MSHR miss cycles 1226system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31633000 # number of StoreCondReq MSHR miss cycles 1227system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31633000 # number of StoreCondReq MSHR miss cycles 1228system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles 1229system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles 1230system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6035435500 # number of demand (read+write) MSHR miss cycles 1231system.cpu1.dcache.demand_mshr_miss_latency::total 6035435500 # number of demand (read+write) MSHR miss cycles 1232system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6035435500 # number of overall MSHR miss cycles 1233system.cpu1.dcache.overall_mshr_miss_latency::total 6035435500 # number of overall MSHR miss cycles 1234system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168635770000 # number of ReadReq MSHR uncacheable cycles 1235system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168635770000 # number of ReadReq MSHR uncacheable cycles 1236system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17673871500 # number of WriteReq MSHR uncacheable cycles 1237system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17673871500 # number of WriteReq MSHR uncacheable cycles 1238system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186309641500 # number of overall MSHR uncacheable cycles 1239system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186309641500 # number of overall MSHR uncacheable cycles 1240system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023960 # mshr miss rate for ReadReq accesses 1241system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023960 # mshr miss rate for ReadReq accesses 1242system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses 1243system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses 1244system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119242 # mshr miss rate for LoadLockedReq accesses 1245system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119242 # mshr miss rate for LoadLockedReq accesses 1246system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108103 # mshr miss rate for StoreCondReq accesses 1247system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108103 # mshr miss rate for StoreCondReq accesses 1248system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for demand accesses 1249system.cpu1.dcache.demand_mshr_miss_rate::total 0.026496 # mshr miss rate for demand accesses 1250system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for overall accesses 1251system.cpu1.dcache.overall_mshr_miss_rate::total 0.026496 # mshr miss rate for overall accesses 1252system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10604.357388 # average ReadReq mshr miss latency 1253system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388 # average ReadReq mshr miss latency 1254system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560 # average WriteReq mshr miss latency 1255system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560 # average WriteReq mshr miss latency 1256system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6334.432598 # average LoadLockedReq mshr miss latency 1257system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6334.432598 # average LoadLockedReq mshr miss latency 1258system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3155.096748 # average StoreCondReq mshr miss latency 1259system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3155.096748 # average StoreCondReq mshr miss latency 1260system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1261system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1262system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency 1263system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency 1264system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency 1265system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency 1266system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency 1267system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1268system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency 1269system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1270system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency 1271system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1272system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1273system.iocache.replacements 0 # number of replacements 1274system.iocache.tagsinuse 0 # Cycle average of tags in use 1275system.iocache.total_refs 0 # Total number of references to valid blocks. 1276system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 1277system.iocache.avg_refs nan # Average number of references to valid blocks. 1278system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1279system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1280system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1281system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1282system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1283system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1284system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1285system.iocache.fast_writes 0 # number of fast writes performed 1286system.iocache.cache_copies 0 # number of cache copies performed 1287system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298 # number of ReadReq MSHR uncacheable cycles 1288system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298 # number of ReadReq MSHR uncacheable cycles 1289system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298 # number of overall MSHR uncacheable cycles 1290system.iocache.overall_mshr_uncacheable_latency::total 479634051298 # number of overall MSHR uncacheable cycles 1291system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency 1292system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1293system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency 1294system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1295system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1296 1297---------- End Simulation Statistics ---------- 1298