stats.txt revision 11312:3d7a85d71bd1
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.871850 # Number of seconds simulated 4sim_ticks 2871850306000 # Number of ticks simulated 5final_tick 2871850306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 312956 # Simulator instruction rate (inst/s) 8host_op_rate 378531 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6832247646 # Simulator tick rate (ticks/s) 10host_mem_usage 599868 # Number of bytes of host memory used 11host_seconds 420.34 # Real time elapsed on the host 12sim_insts 131546959 # Number of instructions simulated 13sim_ops 159110973 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1178404 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 1267556 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 8608576 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.inst 129300 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.data 549908 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.l2cache.prefetcher 341632 # Number of bytes read from this memory 25system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 26system.physmem.bytes_read::total 12076912 # Number of bytes read from this memory 27system.physmem.bytes_inst_read::cpu0.inst 1178404 # Number of instructions bytes read from this memory 28system.physmem.bytes_inst_read::cpu1.inst 129300 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::total 1307704 # Number of instructions bytes read from this memory 30system.physmem.bytes_written::writebacks 8530240 # Number of bytes written to this memory 31system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 33system.physmem.bytes_written::total 8547804 # Number of bytes written to this memory 34system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.inst 26866 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.data 20325 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.l2cache.prefetcher 134509 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.inst 2175 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.data 8613 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.l2cache.prefetcher 5338 # Number of read requests responded to by this memory 43system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 44system.physmem.num_reads::total 197850 # Number of read requests responded to by this memory 45system.physmem.num_writes::writebacks 133285 # Number of write requests responded to by this memory 46system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 47system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 48system.physmem.num_writes::total 137676 # Number of write requests responded to by this memory 49system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::cpu0.inst 410329 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.data 441373 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.l2cache.prefetcher 2997571 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu1.inst 45023 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.data 191482 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.l2cache.prefetcher 118959 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::realview.ide 334 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::total 4205272 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_inst_read::cpu0.inst 410329 # Instruction read bandwidth from this memory (bytes/s) 61system.physmem.bw_inst_read::cpu1.inst 45023 # Instruction read bandwidth from this memory (bytes/s) 62system.physmem.bw_inst_read::total 455352 # Instruction read bandwidth from this memory (bytes/s) 63system.physmem.bw_write::writebacks 2970294 # Write bandwidth from this memory (bytes/s) 64system.physmem.bw_write::cpu0.data 6102 # Write bandwidth from this memory (bytes/s) 65system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 66system.physmem.bw_write::total 2976410 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_total::writebacks 2970294 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s) 69system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) 70system.physmem.bw_total::cpu0.inst 410329 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.data 447475 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.l2cache.prefetcher 2997571 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu1.inst 45023 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu1.data 191496 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.l2cache.prefetcher 118959 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::realview.ide 334 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::total 7181682 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.readReqs 197850 # Number of read requests accepted 80system.physmem.writeReqs 137676 # Number of write requests accepted 81system.physmem.readBursts 197850 # Number of DRAM read bursts, including those serviced by the write queue 82system.physmem.writeBursts 137676 # Number of DRAM write bursts, including those merged in the write queue 83system.physmem.bytesReadDRAM 12652352 # Total number of bytes read from DRAM 84system.physmem.bytesReadWrQ 10048 # Total number of bytes read from write queue 85system.physmem.bytesWritten 8560960 # Total number of bytes written to DRAM 86system.physmem.bytesReadSys 12076912 # Total read bytes from the system interface side 87system.physmem.bytesWrittenSys 8547804 # Total written bytes from the system interface side 88system.physmem.servicedByWrQ 157 # Number of DRAM read bursts serviced by the write queue 89system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one 90system.physmem.neitherReadNorWriteReqs 64578 # Number of requests that are neither read nor write 91system.physmem.perBankRdBursts::0 11583 # Per bank write bursts 92system.physmem.perBankRdBursts::1 11800 # Per bank write bursts 93system.physmem.perBankRdBursts::2 11971 # Per bank write bursts 94system.physmem.perBankRdBursts::3 11847 # Per bank write bursts 95system.physmem.perBankRdBursts::4 20098 # Per bank write bursts 96system.physmem.perBankRdBursts::5 11961 # Per bank write bursts 97system.physmem.perBankRdBursts::6 12460 # Per bank write bursts 98system.physmem.perBankRdBursts::7 12487 # Per bank write bursts 99system.physmem.perBankRdBursts::8 11821 # Per bank write bursts 100system.physmem.perBankRdBursts::9 12495 # Per bank write bursts 101system.physmem.perBankRdBursts::10 11828 # Per bank write bursts 102system.physmem.perBankRdBursts::11 11338 # Per bank write bursts 103system.physmem.perBankRdBursts::12 11476 # Per bank write bursts 104system.physmem.perBankRdBursts::13 11922 # Per bank write bursts 105system.physmem.perBankRdBursts::14 11270 # Per bank write bursts 106system.physmem.perBankRdBursts::15 11336 # Per bank write bursts 107system.physmem.perBankWrBursts::0 8288 # Per bank write bursts 108system.physmem.perBankWrBursts::1 8566 # Per bank write bursts 109system.physmem.perBankWrBursts::2 8821 # Per bank write bursts 110system.physmem.perBankWrBursts::3 8522 # Per bank write bursts 111system.physmem.perBankWrBursts::4 7854 # Per bank write bursts 112system.physmem.perBankWrBursts::5 8398 # Per bank write bursts 113system.physmem.perBankWrBursts::6 8910 # Per bank write bursts 114system.physmem.perBankWrBursts::7 8793 # Per bank write bursts 115system.physmem.perBankWrBursts::8 8333 # Per bank write bursts 116system.physmem.perBankWrBursts::9 8912 # Per bank write bursts 117system.physmem.perBankWrBursts::10 8495 # Per bank write bursts 118system.physmem.perBankWrBursts::11 8357 # Per bank write bursts 119system.physmem.perBankWrBursts::12 8083 # Per bank write bursts 120system.physmem.perBankWrBursts::13 7998 # Per bank write bursts 121system.physmem.perBankWrBursts::14 7822 # Per bank write bursts 122system.physmem.perBankWrBursts::15 7613 # Per bank write bursts 123system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 124system.physmem.numWrRetry 27 # Number of times write queue was full causing retry 125system.physmem.totGap 2871849883000 # Total gap between requests 126system.physmem.readPktSize::0 0 # Read request sizes (log2) 127system.physmem.readPktSize::1 0 # Read request sizes (log2) 128system.physmem.readPktSize::2 9732 # Read request sizes (log2) 129system.physmem.readPktSize::3 28 # Read request sizes (log2) 130system.physmem.readPktSize::4 0 # Read request sizes (log2) 131system.physmem.readPktSize::5 0 # Read request sizes (log2) 132system.physmem.readPktSize::6 188090 # Read request sizes (log2) 133system.physmem.writePktSize::0 0 # Write request sizes (log2) 134system.physmem.writePktSize::1 0 # Write request sizes (log2) 135system.physmem.writePktSize::2 4391 # Write request sizes (log2) 136system.physmem.writePktSize::3 0 # Write request sizes (log2) 137system.physmem.writePktSize::4 0 # Write request sizes (log2) 138system.physmem.writePktSize::5 0 # Write request sizes (log2) 139system.physmem.writePktSize::6 133285 # Write request sizes (log2) 140system.physmem.rdQLenPdf::0 138613 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::1 15680 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::2 10206 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::3 8777 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::4 7036 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::5 5467 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::6 4577 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::7 3802 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::8 3339 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::9 81 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::10 56 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::11 33 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::12 15 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 172system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::15 2732 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::16 3200 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::17 4416 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::18 5092 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::19 6151 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::20 6617 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::21 7823 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::22 7841 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::23 8781 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::24 8913 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::25 9011 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::26 10422 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::27 8444 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::28 8402 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::29 9645 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::30 8273 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::31 7347 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::32 6958 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::33 367 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::34 363 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::35 241 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::36 219 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::38 194 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::40 122 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::41 115 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::42 142 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::44 133 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::46 98 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::47 135 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::48 126 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::53 93 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::54 47 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::57 36 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::58 53 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::59 32 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::61 33 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::63 80 # What write queue length does an incoming req see 236system.physmem.bytesPerActivate::samples 87676 # Bytes accessed per row activation 237system.physmem.bytesPerActivate::mean 241.950454 # Bytes accessed per row activation 238system.physmem.bytesPerActivate::gmean 136.764211 # Bytes accessed per row activation 239system.physmem.bytesPerActivate::stdev 303.933653 # Bytes accessed per row activation 240system.physmem.bytesPerActivate::0-127 46396 52.92% 52.92% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::128-255 17641 20.12% 73.04% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::256-383 5908 6.74% 79.78% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::384-511 3515 4.01% 83.79% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::512-639 2504 2.86% 86.64% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::640-767 1565 1.78% 88.43% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::768-895 855 0.98% 89.40% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::896-1023 945 1.08% 90.48% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::1024-1151 8347 9.52% 100.00% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::total 87676 # Bytes accessed per row activation 250system.physmem.rdPerTurnAround::samples 6535 # Reads before turning the bus around for writes 251system.physmem.rdPerTurnAround::mean 30.251262 # Reads before turning the bus around for writes 252system.physmem.rdPerTurnAround::stdev 585.438505 # Reads before turning the bus around for writes 253system.physmem.rdPerTurnAround::0-2047 6533 99.97% 99.97% # Reads before turning the bus around for writes 254system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::total 6535 # Reads before turning the bus around for writes 257system.physmem.wrPerTurnAround::samples 6535 # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::mean 20.469013 # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::gmean 18.883832 # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::stdev 12.598321 # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::16-19 5330 81.56% 81.56% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::20-23 483 7.39% 88.95% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::24-27 73 1.12% 90.07% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::28-31 153 2.34% 92.41% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::32-35 33 0.50% 92.92% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::36-39 123 1.88% 94.80% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::40-43 36 0.55% 95.35% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::44-47 26 0.40% 95.75% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::48-51 25 0.38% 96.13% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::52-55 15 0.23% 96.36% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::56-59 6 0.09% 96.45% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::60-63 6 0.09% 96.54% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::64-67 152 2.33% 98.87% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::68-71 6 0.09% 98.96% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::72-75 2 0.03% 98.99% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::76-79 26 0.40% 99.39% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::80-83 7 0.11% 99.50% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::84-87 1 0.02% 99.51% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::88-91 1 0.02% 99.53% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::92-95 2 0.03% 99.56% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::100-103 2 0.03% 99.59% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::104-107 2 0.03% 99.62% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::112-115 1 0.02% 99.63% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::116-119 1 0.02% 99.65% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::124-127 2 0.03% 99.68% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::128-131 13 0.20% 99.88% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::140-143 3 0.05% 99.92% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::152-155 1 0.02% 99.94% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::156-159 2 0.03% 99.97% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::244-247 1 0.02% 100.00% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::total 6535 # Writes before turning the bus around for reads 293system.physmem.totQLat 4503336233 # Total ticks spent queuing 294system.physmem.totMemAccLat 8210079983 # Total ticks spent from burst creation until serviced by the DRAM 295system.physmem.totBusLat 988465000 # Total ticks spent in databus transfers 296system.physmem.avgQLat 22779.44 # Average queueing delay per DRAM burst 297system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 298system.physmem.avgMemAccLat 41529.44 # Average memory access latency per DRAM burst 299system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s 300system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s 301system.physmem.avgRdBWSys 4.21 # Average system read bandwidth in MiByte/s 302system.physmem.avgWrBWSys 2.98 # Average system write bandwidth in MiByte/s 303system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 304system.physmem.busUtil 0.06 # Data bus utilization in percentage 305system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads 306system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 307system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing 308system.physmem.avgWrQLen 22.35 # Average write queue length when enqueuing 309system.physmem.readRowHits 165103 # Number of row buffer hits during reads 310system.physmem.writeRowHits 78678 # Number of row buffer hits during writes 311system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads 312system.physmem.writeRowHitRate 58.81 # Row buffer hit rate for writes 313system.physmem.avgGap 8559246.92 # Average gap between requests 314system.physmem.pageHitRate 73.54 # Row buffer hit rate, read and write combined 315system.physmem_0.actEnergy 341250840 # Energy for activate commands per rank (pJ) 316system.physmem_0.preEnergy 186198375 # Energy for precharge commands per rank (pJ) 317system.physmem_0.readEnergy 812814600 # Energy for read commands per rank (pJ) 318system.physmem_0.writeEnergy 441624960 # Energy for write commands per rank (pJ) 319system.physmem_0.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ) 320system.physmem_0.actBackEnergy 85820448015 # Energy for active background per rank (pJ) 321system.physmem_0.preBackEnergy 1647828636000 # Energy for precharge background per rank (pJ) 322system.physmem_0.totalEnergy 1923006208950 # Total energy per rank (pJ) 323system.physmem_0.averagePower 669.605484 # Core power per rank (mW) 324system.physmem_0.memoryStateTime::IDLE 2741162536487 # Time in different power states 325system.physmem_0.memoryStateTime::REF 95897360000 # Time in different power states 326system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 327system.physmem_0.memoryStateTime::ACT 34789668513 # Time in different power states 328system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 329system.physmem_1.actEnergy 321579720 # Energy for activate commands per rank (pJ) 330system.physmem_1.preEnergy 175465125 # Energy for precharge commands per rank (pJ) 331system.physmem_1.readEnergy 729183000 # Energy for read commands per rank (pJ) 332system.physmem_1.writeEnergy 425172240 # Energy for write commands per rank (pJ) 333system.physmem_1.refreshEnergy 187575236160 # Energy for refresh commands per rank (pJ) 334system.physmem_1.actBackEnergy 84866434740 # Energy for active background per rank (pJ) 335system.physmem_1.preBackEnergy 1648665489750 # Energy for precharge background per rank (pJ) 336system.physmem_1.totalEnergy 1922758560735 # Total energy per rank (pJ) 337system.physmem_1.averagePower 669.519251 # Core power per rank (mW) 338system.physmem_1.memoryStateTime::IDLE 2742561244982 # Time in different power states 339system.physmem_1.memoryStateTime::REF 95897360000 # Time in different power states 340system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 341system.physmem_1.memoryStateTime::ACT 33391555518 # Time in different power states 342system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 343system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 344system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 345system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 346system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 347system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 348system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 349system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 350system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 351system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 352system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 356system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 357system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 358system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 359system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 360system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 361system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 362system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 363system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 364system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 365system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 366system.cf0.dma_write_txs 631 # Number of DMA write transactions. 367system.cpu_clk_domain.clock 500 # Clock period in ticks 368system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 369system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 370system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 371system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 372system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 373system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 374system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 375system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 376system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 377system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 378system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 379system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 380system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 381system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 382system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 383system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 384system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 385system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 386system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 387system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 388system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 389system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 390system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 391system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 392system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 393system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 394system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 395system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 396system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 397system.cpu0.dtb.walker.walks 8830 # Table walker walks requested 398system.cpu0.dtb.walker.walksShort 8830 # Table walker walks initiated with short descriptors 399system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1617 # Level at which table walker walks with short descriptors terminate 400system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 7213 # Level at which table walker walks with short descriptors terminate 401system.cpu0.dtb.walker.walkWaitTime::samples 8830 # Table walker wait (enqueue to first request) latency 402system.cpu0.dtb.walker.walkWaitTime::0 8830 100.00% 100.00% # Table walker wait (enqueue to first request) latency 403system.cpu0.dtb.walker.walkWaitTime::total 8830 # Table walker wait (enqueue to first request) latency 404system.cpu0.dtb.walker.walkCompletionTime::samples 7312 # Table walker service (enqueue to completion) latency 405system.cpu0.dtb.walker.walkCompletionTime::mean 12253.145514 # Table walker service (enqueue to completion) latency 406system.cpu0.dtb.walker.walkCompletionTime::gmean 11429.774492 # Table walker service (enqueue to completion) latency 407system.cpu0.dtb.walker.walkCompletionTime::stdev 6252.045789 # Table walker service (enqueue to completion) latency 408system.cpu0.dtb.walker.walkCompletionTime::0-32767 7284 99.62% 99.62% # Table walker service (enqueue to completion) latency 409system.cpu0.dtb.walker.walkCompletionTime::32768-65535 24 0.33% 99.95% # Table walker service (enqueue to completion) latency 410system.cpu0.dtb.walker.walkCompletionTime::131072-163839 3 0.04% 99.99% # Table walker service (enqueue to completion) latency 411system.cpu0.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency 412system.cpu0.dtb.walker.walkCompletionTime::total 7312 # Table walker service (enqueue to completion) latency 413system.cpu0.dtb.walker.walksPending::samples 1809726500 # Table walker pending requests distribution 414system.cpu0.dtb.walker.walksPending::0 1809726500 100.00% 100.00% # Table walker pending requests distribution 415system.cpu0.dtb.walker.walksPending::total 1809726500 # Table walker pending requests distribution 416system.cpu0.dtb.walker.walkPageSizes::4K 5742 78.53% 78.53% # Table walker page sizes translated 417system.cpu0.dtb.walker.walkPageSizes::1M 1570 21.47% 100.00% # Table walker page sizes translated 418system.cpu0.dtb.walker.walkPageSizes::total 7312 # Table walker page sizes translated 419system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 8830 # Table walker requests started/completed, data/inst 420system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 421system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 8830 # Table walker requests started/completed, data/inst 422system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7312 # Table walker requests started/completed, data/inst 423system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 424system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7312 # Table walker requests started/completed, data/inst 425system.cpu0.dtb.walker.walkRequestOrigin::total 16142 # Table walker requests started/completed, data/inst 426system.cpu0.dtb.inst_hits 0 # ITB inst hits 427system.cpu0.dtb.inst_misses 0 # ITB inst misses 428system.cpu0.dtb.read_hits 25809403 # DTB read hits 429system.cpu0.dtb.read_misses 7606 # DTB read misses 430system.cpu0.dtb.write_hits 19327142 # DTB write hits 431system.cpu0.dtb.write_misses 1224 # DTB write misses 432system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 433system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 434system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 435system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 436system.cpu0.dtb.flush_entries 3761 # Number of entries that have been flushed from TLB 437system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 438system.cpu0.dtb.prefetch_faults 1861 # Number of TLB faults due to prefetch 439system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 440system.cpu0.dtb.perms_faults 321 # Number of TLB faults due to permissions restrictions 441system.cpu0.dtb.read_accesses 25817009 # DTB read accesses 442system.cpu0.dtb.write_accesses 19328366 # DTB write accesses 443system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 444system.cpu0.dtb.hits 45136545 # DTB hits 445system.cpu0.dtb.misses 8830 # DTB misses 446system.cpu0.dtb.accesses 45145375 # DTB accesses 447system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 448system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 449system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 450system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 451system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 452system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 453system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 454system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 455system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 456system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 457system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 458system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 459system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 460system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 461system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 462system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 463system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 464system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 465system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 466system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 467system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 468system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 469system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 470system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 471system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 472system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 473system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 474system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 475system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 476system.cpu0.itb.walker.walks 3674 # Table walker walks requested 477system.cpu0.itb.walker.walksShort 3674 # Table walker walks initiated with short descriptors 478system.cpu0.itb.walker.walksShortTerminationLevel::Level1 320 # Level at which table walker walks with short descriptors terminate 479system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3354 # Level at which table walker walks with short descriptors terminate 480system.cpu0.itb.walker.walkWaitTime::samples 3674 # Table walker wait (enqueue to first request) latency 481system.cpu0.itb.walker.walkWaitTime::0 3674 100.00% 100.00% # Table walker wait (enqueue to first request) latency 482system.cpu0.itb.walker.walkWaitTime::total 3674 # Table walker wait (enqueue to first request) latency 483system.cpu0.itb.walker.walkCompletionTime::samples 2576 # Table walker service (enqueue to completion) latency 484system.cpu0.itb.walker.walkCompletionTime::mean 12688.276398 # Table walker service (enqueue to completion) latency 485system.cpu0.itb.walker.walkCompletionTime::gmean 11839.861434 # Table walker service (enqueue to completion) latency 486system.cpu0.itb.walker.walkCompletionTime::stdev 6240.244766 # Table walker service (enqueue to completion) latency 487system.cpu0.itb.walker.walkCompletionTime::0-16383 2261 87.77% 87.77% # Table walker service (enqueue to completion) latency 488system.cpu0.itb.walker.walkCompletionTime::16384-32767 282 10.95% 98.72% # Table walker service (enqueue to completion) latency 489system.cpu0.itb.walker.walkCompletionTime::32768-49151 30 1.16% 99.88% # Table walker service (enqueue to completion) latency 490system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency 491system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 99.96% # Table walker service (enqueue to completion) latency 492system.cpu0.itb.walker.walkCompletionTime::163840-180223 1 0.04% 100.00% # Table walker service (enqueue to completion) latency 493system.cpu0.itb.walker.walkCompletionTime::total 2576 # Table walker service (enqueue to completion) latency 494system.cpu0.itb.walker.walksPending::samples 1809154500 # Table walker pending requests distribution 495system.cpu0.itb.walker.walksPending::0 1809154500 100.00% 100.00% # Table walker pending requests distribution 496system.cpu0.itb.walker.walksPending::total 1809154500 # Table walker pending requests distribution 497system.cpu0.itb.walker.walkPageSizes::4K 2256 87.58% 87.58% # Table walker page sizes translated 498system.cpu0.itb.walker.walkPageSizes::1M 320 12.42% 100.00% # Table walker page sizes translated 499system.cpu0.itb.walker.walkPageSizes::total 2576 # Table walker page sizes translated 500system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 501system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3674 # Table walker requests started/completed, data/inst 502system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3674 # Table walker requests started/completed, data/inst 503system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 504system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2576 # Table walker requests started/completed, data/inst 505system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2576 # Table walker requests started/completed, data/inst 506system.cpu0.itb.walker.walkRequestOrigin::total 6250 # Table walker requests started/completed, data/inst 507system.cpu0.itb.inst_hits 121850168 # ITB inst hits 508system.cpu0.itb.inst_misses 3674 # ITB inst misses 509system.cpu0.itb.read_hits 0 # DTB read hits 510system.cpu0.itb.read_misses 0 # DTB read misses 511system.cpu0.itb.write_hits 0 # DTB write hits 512system.cpu0.itb.write_misses 0 # DTB write misses 513system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 514system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 515system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 516system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 517system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB 518system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 519system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 520system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 521system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 522system.cpu0.itb.read_accesses 0 # DTB read accesses 523system.cpu0.itb.write_accesses 0 # DTB write accesses 524system.cpu0.itb.inst_accesses 121853842 # ITB inst accesses 525system.cpu0.itb.hits 121850168 # DTB hits 526system.cpu0.itb.misses 3674 # DTB misses 527system.cpu0.itb.accesses 121853842 # DTB accesses 528system.cpu0.numCycles 5743700612 # number of cpu cycles simulated 529system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 530system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 531system.cpu0.kern.inst.arm 0 # number of arm instructions executed 532system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed 533system.cpu0.committedInsts 118029542 # Number of instructions committed 534system.cpu0.committedOps 142673635 # Number of ops (including micro ops) committed 535system.cpu0.num_int_alu_accesses 126253590 # Number of integer alu accesses 536system.cpu0.num_fp_alu_accesses 11483 # Number of float alu accesses 537system.cpu0.num_func_calls 12792333 # number of times a function call or return occured 538system.cpu0.num_conditional_control_insts 16043976 # number of instructions that are conditional controls 539system.cpu0.num_int_insts 126253590 # number of integer instructions 540system.cpu0.num_fp_insts 11483 # number of float instructions 541system.cpu0.num_int_register_reads 232324144 # number of times the integer registers were read 542system.cpu0.num_int_register_writes 87654298 # number of times the integer registers were written 543system.cpu0.num_fp_register_reads 8771 # number of times the floating registers were read 544system.cpu0.num_fp_register_writes 2716 # number of times the floating registers were written 545system.cpu0.num_cc_register_reads 516734560 # number of times the CC registers were read 546system.cpu0.num_cc_register_writes 53610723 # number of times the CC registers were written 547system.cpu0.num_mem_refs 46299073 # number of memory refs 548system.cpu0.num_load_insts 26069844 # Number of load instructions 549system.cpu0.num_store_insts 20229229 # Number of store instructions 550system.cpu0.num_idle_cycles 5455076908.366100 # Number of idle cycles 551system.cpu0.num_busy_cycles 288623703.633900 # Number of busy cycles 552system.cpu0.not_idle_fraction 0.050250 # Percentage of non-idle cycles 553system.cpu0.idle_fraction 0.949750 # Percentage of idle cycles 554system.cpu0.Branches 29603215 # Number of branches fetched 555system.cpu0.op_class::No_OpClass 2315 0.00% 0.00% # Class of executed instruction 556system.cpu0.op_class::IntAlu 100054313 68.31% 68.31% # Class of executed instruction 557system.cpu0.op_class::IntMult 112340 0.08% 68.39% # Class of executed instruction 558system.cpu0.op_class::IntDiv 0 0.00% 68.39% # Class of executed instruction 559system.cpu0.op_class::FloatAdd 0 0.00% 68.39% # Class of executed instruction 560system.cpu0.op_class::FloatCmp 0 0.00% 68.39% # Class of executed instruction 561system.cpu0.op_class::FloatCvt 0 0.00% 68.39% # Class of executed instruction 562system.cpu0.op_class::FloatMult 0 0.00% 68.39% # Class of executed instruction 563system.cpu0.op_class::FloatDiv 0 0.00% 68.39% # Class of executed instruction 564system.cpu0.op_class::FloatSqrt 0 0.00% 68.39% # Class of executed instruction 565system.cpu0.op_class::SimdAdd 0 0.00% 68.39% # Class of executed instruction 566system.cpu0.op_class::SimdAddAcc 0 0.00% 68.39% # Class of executed instruction 567system.cpu0.op_class::SimdAlu 0 0.00% 68.39% # Class of executed instruction 568system.cpu0.op_class::SimdCmp 0 0.00% 68.39% # Class of executed instruction 569system.cpu0.op_class::SimdCvt 0 0.00% 68.39% # Class of executed instruction 570system.cpu0.op_class::SimdMisc 0 0.00% 68.39% # Class of executed instruction 571system.cpu0.op_class::SimdMult 0 0.00% 68.39% # Class of executed instruction 572system.cpu0.op_class::SimdMultAcc 0 0.00% 68.39% # Class of executed instruction 573system.cpu0.op_class::SimdShift 0 0.00% 68.39% # Class of executed instruction 574system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.39% # Class of executed instruction 575system.cpu0.op_class::SimdSqrt 0 0.00% 68.39% # Class of executed instruction 576system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.39% # Class of executed instruction 577system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.39% # Class of executed instruction 578system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.39% # Class of executed instruction 579system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.39% # Class of executed instruction 580system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.39% # Class of executed instruction 581system.cpu0.op_class::SimdFloatMisc 8369 0.01% 68.39% # Class of executed instruction 582system.cpu0.op_class::SimdFloatMult 0 0.00% 68.39% # Class of executed instruction 583system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.39% # Class of executed instruction 584system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.39% # Class of executed instruction 585system.cpu0.op_class::MemRead 26069844 17.80% 86.19% # Class of executed instruction 586system.cpu0.op_class::MemWrite 20229229 13.81% 100.00% # Class of executed instruction 587system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 588system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 589system.cpu0.op_class::total 146476410 # Class of executed instruction 590system.cpu0.dcache.tags.replacements 740882 # number of replacements 591system.cpu0.dcache.tags.tagsinuse 488.760528 # Cycle average of tags in use 592system.cpu0.dcache.tags.total_refs 44216040 # Total number of references to valid blocks. 593system.cpu0.dcache.tags.sampled_refs 741394 # Sample count of references to valid blocks. 594system.cpu0.dcache.tags.avg_refs 59.639058 # Average number of references to valid blocks. 595system.cpu0.dcache.tags.warmup_cycle 1836359000 # Cycle when the warmup percentage was hit. 596system.cpu0.dcache.tags.occ_blocks::cpu0.data 488.760528 # Average occupied blocks per requestor 597system.cpu0.dcache.tags.occ_percent::cpu0.data 0.954610 # Average percentage of cache occupancy 598system.cpu0.dcache.tags.occ_percent::total 0.954610 # Average percentage of cache occupancy 599system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 600system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 601system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id 602system.cpu0.dcache.tags.age_task_id_blocks_1024::2 90 # Occupied blocks per task id 603system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 604system.cpu0.dcache.tags.tag_accesses 90957934 # Number of tag accesses 605system.cpu0.dcache.tags.data_accesses 90957934 # Number of data accesses 606system.cpu0.dcache.ReadReq_hits::cpu0.data 24496228 # number of ReadReq hits 607system.cpu0.dcache.ReadReq_hits::total 24496228 # number of ReadReq hits 608system.cpu0.dcache.WriteReq_hits::cpu0.data 18570022 # number of WriteReq hits 609system.cpu0.dcache.WriteReq_hits::total 18570022 # number of WriteReq hits 610system.cpu0.dcache.SoftPFReq_hits::cpu0.data 327271 # number of SoftPFReq hits 611system.cpu0.dcache.SoftPFReq_hits::total 327271 # number of SoftPFReq hits 612system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374846 # number of LoadLockedReq hits 613system.cpu0.dcache.LoadLockedReq_hits::total 374846 # number of LoadLockedReq hits 614system.cpu0.dcache.StoreCondReq_hits::cpu0.data 372508 # number of StoreCondReq hits 615system.cpu0.dcache.StoreCondReq_hits::total 372508 # number of StoreCondReq hits 616system.cpu0.dcache.demand_hits::cpu0.data 43066250 # number of demand (read+write) hits 617system.cpu0.dcache.demand_hits::total 43066250 # number of demand (read+write) hits 618system.cpu0.dcache.overall_hits::cpu0.data 43393521 # number of overall hits 619system.cpu0.dcache.overall_hits::total 43393521 # number of overall hits 620system.cpu0.dcache.ReadReq_misses::cpu0.data 423502 # number of ReadReq misses 621system.cpu0.dcache.ReadReq_misses::total 423502 # number of ReadReq misses 622system.cpu0.dcache.WriteReq_misses::cpu0.data 340254 # number of WriteReq misses 623system.cpu0.dcache.WriteReq_misses::total 340254 # number of WriteReq misses 624system.cpu0.dcache.SoftPFReq_misses::cpu0.data 133712 # number of SoftPFReq misses 625system.cpu0.dcache.SoftPFReq_misses::total 133712 # number of SoftPFReq misses 626system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 22535 # number of LoadLockedReq misses 627system.cpu0.dcache.LoadLockedReq_misses::total 22535 # number of LoadLockedReq misses 628system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19849 # number of StoreCondReq misses 629system.cpu0.dcache.StoreCondReq_misses::total 19849 # number of StoreCondReq misses 630system.cpu0.dcache.demand_misses::cpu0.data 763756 # number of demand (read+write) misses 631system.cpu0.dcache.demand_misses::total 763756 # number of demand (read+write) misses 632system.cpu0.dcache.overall_misses::cpu0.data 897468 # number of overall misses 633system.cpu0.dcache.overall_misses::total 897468 # number of overall misses 634system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5717292500 # number of ReadReq miss cycles 635system.cpu0.dcache.ReadReq_miss_latency::total 5717292500 # number of ReadReq miss cycles 636system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6989183500 # number of WriteReq miss cycles 637system.cpu0.dcache.WriteReq_miss_latency::total 6989183500 # number of WriteReq miss cycles 638system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 344979500 # number of LoadLockedReq miss cycles 639system.cpu0.dcache.LoadLockedReq_miss_latency::total 344979500 # number of LoadLockedReq miss cycles 640system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 511150000 # number of StoreCondReq miss cycles 641system.cpu0.dcache.StoreCondReq_miss_latency::total 511150000 # number of StoreCondReq miss cycles 642system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1456500 # number of StoreCondFailReq miss cycles 643system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1456500 # number of StoreCondFailReq miss cycles 644system.cpu0.dcache.demand_miss_latency::cpu0.data 12706476000 # number of demand (read+write) miss cycles 645system.cpu0.dcache.demand_miss_latency::total 12706476000 # number of demand (read+write) miss cycles 646system.cpu0.dcache.overall_miss_latency::cpu0.data 12706476000 # number of overall miss cycles 647system.cpu0.dcache.overall_miss_latency::total 12706476000 # number of overall miss cycles 648system.cpu0.dcache.ReadReq_accesses::cpu0.data 24919730 # number of ReadReq accesses(hits+misses) 649system.cpu0.dcache.ReadReq_accesses::total 24919730 # number of ReadReq accesses(hits+misses) 650system.cpu0.dcache.WriteReq_accesses::cpu0.data 18910276 # number of WriteReq accesses(hits+misses) 651system.cpu0.dcache.WriteReq_accesses::total 18910276 # number of WriteReq accesses(hits+misses) 652system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 460983 # number of SoftPFReq accesses(hits+misses) 653system.cpu0.dcache.SoftPFReq_accesses::total 460983 # number of SoftPFReq accesses(hits+misses) 654system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397381 # number of LoadLockedReq accesses(hits+misses) 655system.cpu0.dcache.LoadLockedReq_accesses::total 397381 # number of LoadLockedReq accesses(hits+misses) 656system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 392357 # number of StoreCondReq accesses(hits+misses) 657system.cpu0.dcache.StoreCondReq_accesses::total 392357 # number of StoreCondReq accesses(hits+misses) 658system.cpu0.dcache.demand_accesses::cpu0.data 43830006 # number of demand (read+write) accesses 659system.cpu0.dcache.demand_accesses::total 43830006 # number of demand (read+write) accesses 660system.cpu0.dcache.overall_accesses::cpu0.data 44290989 # number of overall (read+write) accesses 661system.cpu0.dcache.overall_accesses::total 44290989 # number of overall (read+write) accesses 662system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016995 # miss rate for ReadReq accesses 663system.cpu0.dcache.ReadReq_miss_rate::total 0.016995 # miss rate for ReadReq accesses 664system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017993 # miss rate for WriteReq accesses 665system.cpu0.dcache.WriteReq_miss_rate::total 0.017993 # miss rate for WriteReq accesses 666system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.290058 # miss rate for SoftPFReq accesses 667system.cpu0.dcache.SoftPFReq_miss_rate::total 0.290058 # miss rate for SoftPFReq accesses 668system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056709 # miss rate for LoadLockedReq accesses 669system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056709 # miss rate for LoadLockedReq accesses 670system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.050589 # miss rate for StoreCondReq accesses 671system.cpu0.dcache.StoreCondReq_miss_rate::total 0.050589 # miss rate for StoreCondReq accesses 672system.cpu0.dcache.demand_miss_rate::cpu0.data 0.017425 # miss rate for demand accesses 673system.cpu0.dcache.demand_miss_rate::total 0.017425 # miss rate for demand accesses 674system.cpu0.dcache.overall_miss_rate::cpu0.data 0.020263 # miss rate for overall accesses 675system.cpu0.dcache.overall_miss_rate::total 0.020263 # miss rate for overall accesses 676system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13500.036600 # average ReadReq miss latency 677system.cpu0.dcache.ReadReq_avg_miss_latency::total 13500.036600 # average ReadReq miss latency 678system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20541.076666 # average WriteReq miss latency 679system.cpu0.dcache.WriteReq_avg_miss_latency::total 20541.076666 # average WriteReq miss latency 680system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15308.608831 # average LoadLockedReq miss latency 681system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15308.608831 # average LoadLockedReq miss latency 682system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 25751.927049 # average StoreCondReq miss latency 683system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25751.927049 # average StoreCondReq miss latency 684system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 685system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 686system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16636.826421 # average overall miss latency 687system.cpu0.dcache.demand_avg_miss_latency::total 16636.826421 # average overall miss latency 688system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14158.138229 # average overall miss latency 689system.cpu0.dcache.overall_avg_miss_latency::total 14158.138229 # average overall miss latency 690system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 691system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 692system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 693system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 694system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 695system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 696system.cpu0.dcache.fast_writes 0 # number of fast writes performed 697system.cpu0.dcache.cache_copies 0 # number of cache copies performed 698system.cpu0.dcache.writebacks::writebacks 740882 # number of writebacks 699system.cpu0.dcache.writebacks::total 740882 # number of writebacks 700system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25304 # number of ReadReq MSHR hits 701system.cpu0.dcache.ReadReq_mshr_hits::total 25304 # number of ReadReq MSHR hits 702system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15852 # number of LoadLockedReq MSHR hits 703system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15852 # number of LoadLockedReq MSHR hits 704system.cpu0.dcache.demand_mshr_hits::cpu0.data 25304 # number of demand (read+write) MSHR hits 705system.cpu0.dcache.demand_mshr_hits::total 25304 # number of demand (read+write) MSHR hits 706system.cpu0.dcache.overall_mshr_hits::cpu0.data 25304 # number of overall MSHR hits 707system.cpu0.dcache.overall_mshr_hits::total 25304 # number of overall MSHR hits 708system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 398198 # number of ReadReq MSHR misses 709system.cpu0.dcache.ReadReq_mshr_misses::total 398198 # number of ReadReq MSHR misses 710system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 340254 # number of WriteReq MSHR misses 711system.cpu0.dcache.WriteReq_mshr_misses::total 340254 # number of WriteReq MSHR misses 712system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 106613 # number of SoftPFReq MSHR misses 713system.cpu0.dcache.SoftPFReq_mshr_misses::total 106613 # number of SoftPFReq MSHR misses 714system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6683 # number of LoadLockedReq MSHR misses 715system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6683 # number of LoadLockedReq MSHR misses 716system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19849 # number of StoreCondReq MSHR misses 717system.cpu0.dcache.StoreCondReq_mshr_misses::total 19849 # number of StoreCondReq MSHR misses 718system.cpu0.dcache.demand_mshr_misses::cpu0.data 738452 # number of demand (read+write) MSHR misses 719system.cpu0.dcache.demand_mshr_misses::total 738452 # number of demand (read+write) MSHR misses 720system.cpu0.dcache.overall_mshr_misses::cpu0.data 845065 # number of overall MSHR misses 721system.cpu0.dcache.overall_mshr_misses::total 845065 # number of overall MSHR misses 722system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable 723system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31860 # number of ReadReq MSHR uncacheable 724system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable 725system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28553 # number of WriteReq MSHR uncacheable 726system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses 727system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60413 # number of overall MSHR uncacheable misses 728system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4887280000 # number of ReadReq MSHR miss cycles 729system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4887280000 # number of ReadReq MSHR miss cycles 730system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6648929500 # number of WriteReq MSHR miss cycles 731system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6648929500 # number of WriteReq MSHR miss cycles 732system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1745313500 # number of SoftPFReq MSHR miss cycles 733system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1745313500 # number of SoftPFReq MSHR miss cycles 734system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102495000 # number of LoadLockedReq MSHR miss cycles 735system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102495000 # number of LoadLockedReq MSHR miss cycles 736system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 491343000 # number of StoreCondReq MSHR miss cycles 737system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 491343000 # number of StoreCondReq MSHR miss cycles 738system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1414500 # number of StoreCondFailReq MSHR miss cycles 739system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1414500 # number of StoreCondFailReq MSHR miss cycles 740system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11536209500 # number of demand (read+write) MSHR miss cycles 741system.cpu0.dcache.demand_mshr_miss_latency::total 11536209500 # number of demand (read+write) MSHR miss cycles 742system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13281523000 # number of overall MSHR miss cycles 743system.cpu0.dcache.overall_mshr_miss_latency::total 13281523000 # number of overall MSHR miss cycles 744system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6641550500 # number of ReadReq MSHR uncacheable cycles 745system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6641550500 # number of ReadReq MSHR uncacheable cycles 746system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5414724500 # number of WriteReq MSHR uncacheable cycles 747system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5414724500 # number of WriteReq MSHR uncacheable cycles 748system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12056275000 # number of overall MSHR uncacheable cycles 749system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12056275000 # number of overall MSHR uncacheable cycles 750system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015979 # mshr miss rate for ReadReq accesses 751system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015979 # mshr miss rate for ReadReq accesses 752system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017993 # mshr miss rate for WriteReq accesses 753system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017993 # mshr miss rate for WriteReq accesses 754system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.231273 # mshr miss rate for SoftPFReq accesses 755system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.231273 # mshr miss rate for SoftPFReq accesses 756system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016818 # mshr miss rate for LoadLockedReq accesses 757system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016818 # mshr miss rate for LoadLockedReq accesses 758system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.050589 # mshr miss rate for StoreCondReq accesses 759system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.050589 # mshr miss rate for StoreCondReq accesses 760system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016848 # mshr miss rate for demand accesses 761system.cpu0.dcache.demand_mshr_miss_rate::total 0.016848 # mshr miss rate for demand accesses 762system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019080 # mshr miss rate for overall accesses 763system.cpu0.dcache.overall_mshr_miss_rate::total 0.019080 # mshr miss rate for overall accesses 764system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12273.492082 # average ReadReq mshr miss latency 765system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12273.492082 # average ReadReq mshr miss latency 766system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 19541.076666 # average WriteReq mshr miss latency 767system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 19541.076666 # average WriteReq mshr miss latency 768system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16370.550496 # average SoftPFReq mshr miss latency 769system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16370.550496 # average SoftPFReq mshr miss latency 770system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15336.675146 # average LoadLockedReq mshr miss latency 771system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15336.675146 # average LoadLockedReq mshr miss latency 772system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24754.043025 # average StoreCondReq mshr miss latency 773system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 24754.043025 # average StoreCondReq mshr miss latency 774system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 775system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 776system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15622.152151 # average overall mshr miss latency 777system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15622.152151 # average overall mshr miss latency 778system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15716.569731 # average overall mshr miss latency 779system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15716.569731 # average overall mshr miss latency 780system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208460.467671 # average ReadReq mshr uncacheable latency 781system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208460.467671 # average ReadReq mshr uncacheable latency 782system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189637.673800 # average WriteReq mshr uncacheable latency 783system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189637.673800 # average WriteReq mshr uncacheable latency 784system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199564.249417 # average overall mshr uncacheable latency 785system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199564.249417 # average overall mshr uncacheable latency 786system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 787system.cpu0.icache.tags.replacements 1154605 # number of replacements 788system.cpu0.icache.tags.tagsinuse 511.321447 # Cycle average of tags in use 789system.cpu0.icache.tags.total_refs 120695042 # Total number of references to valid blocks. 790system.cpu0.icache.tags.sampled_refs 1155117 # Sample count of references to valid blocks. 791system.cpu0.icache.tags.avg_refs 104.487287 # Average number of references to valid blocks. 792system.cpu0.icache.tags.warmup_cycle 14862010000 # Cycle when the warmup percentage was hit. 793system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.321447 # Average occupied blocks per requestor 794system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998675 # Average percentage of cache occupancy 795system.cpu0.icache.tags.occ_percent::total 0.998675 # Average percentage of cache occupancy 796system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 797system.cpu0.icache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id 798system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id 799system.cpu0.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id 800system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 801system.cpu0.icache.tags.tag_accesses 244855462 # Number of tag accesses 802system.cpu0.icache.tags.data_accesses 244855462 # Number of data accesses 803system.cpu0.icache.ReadReq_hits::cpu0.inst 120695042 # number of ReadReq hits 804system.cpu0.icache.ReadReq_hits::total 120695042 # number of ReadReq hits 805system.cpu0.icache.demand_hits::cpu0.inst 120695042 # number of demand (read+write) hits 806system.cpu0.icache.demand_hits::total 120695042 # number of demand (read+write) hits 807system.cpu0.icache.overall_hits::cpu0.inst 120695042 # number of overall hits 808system.cpu0.icache.overall_hits::total 120695042 # number of overall hits 809system.cpu0.icache.ReadReq_misses::cpu0.inst 1155126 # number of ReadReq misses 810system.cpu0.icache.ReadReq_misses::total 1155126 # number of ReadReq misses 811system.cpu0.icache.demand_misses::cpu0.inst 1155126 # number of demand (read+write) misses 812system.cpu0.icache.demand_misses::total 1155126 # number of demand (read+write) misses 813system.cpu0.icache.overall_misses::cpu0.inst 1155126 # number of overall misses 814system.cpu0.icache.overall_misses::total 1155126 # number of overall misses 815system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12352499000 # number of ReadReq miss cycles 816system.cpu0.icache.ReadReq_miss_latency::total 12352499000 # number of ReadReq miss cycles 817system.cpu0.icache.demand_miss_latency::cpu0.inst 12352499000 # number of demand (read+write) miss cycles 818system.cpu0.icache.demand_miss_latency::total 12352499000 # number of demand (read+write) miss cycles 819system.cpu0.icache.overall_miss_latency::cpu0.inst 12352499000 # number of overall miss cycles 820system.cpu0.icache.overall_miss_latency::total 12352499000 # number of overall miss cycles 821system.cpu0.icache.ReadReq_accesses::cpu0.inst 121850168 # number of ReadReq accesses(hits+misses) 822system.cpu0.icache.ReadReq_accesses::total 121850168 # number of ReadReq accesses(hits+misses) 823system.cpu0.icache.demand_accesses::cpu0.inst 121850168 # number of demand (read+write) accesses 824system.cpu0.icache.demand_accesses::total 121850168 # number of demand (read+write) accesses 825system.cpu0.icache.overall_accesses::cpu0.inst 121850168 # number of overall (read+write) accesses 826system.cpu0.icache.overall_accesses::total 121850168 # number of overall (read+write) accesses 827system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009480 # miss rate for ReadReq accesses 828system.cpu0.icache.ReadReq_miss_rate::total 0.009480 # miss rate for ReadReq accesses 829system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009480 # miss rate for demand accesses 830system.cpu0.icache.demand_miss_rate::total 0.009480 # miss rate for demand accesses 831system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009480 # miss rate for overall accesses 832system.cpu0.icache.overall_miss_rate::total 0.009480 # miss rate for overall accesses 833system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10693.637750 # average ReadReq miss latency 834system.cpu0.icache.ReadReq_avg_miss_latency::total 10693.637750 # average ReadReq miss latency 835system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency 836system.cpu0.icache.demand_avg_miss_latency::total 10693.637750 # average overall miss latency 837system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10693.637750 # average overall miss latency 838system.cpu0.icache.overall_avg_miss_latency::total 10693.637750 # average overall miss latency 839system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 840system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 841system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 842system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 843system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 844system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 845system.cpu0.icache.fast_writes 0 # number of fast writes performed 846system.cpu0.icache.cache_copies 0 # number of cache copies performed 847system.cpu0.icache.writebacks::writebacks 1154605 # number of writebacks 848system.cpu0.icache.writebacks::total 1154605 # number of writebacks 849system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1155126 # number of ReadReq MSHR misses 850system.cpu0.icache.ReadReq_mshr_misses::total 1155126 # number of ReadReq MSHR misses 851system.cpu0.icache.demand_mshr_misses::cpu0.inst 1155126 # number of demand (read+write) MSHR misses 852system.cpu0.icache.demand_mshr_misses::total 1155126 # number of demand (read+write) MSHR misses 853system.cpu0.icache.overall_mshr_misses::cpu0.inst 1155126 # number of overall MSHR misses 854system.cpu0.icache.overall_mshr_misses::total 1155126 # number of overall MSHR misses 855system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 856system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable 857system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 858system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses 859system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11774936000 # number of ReadReq MSHR miss cycles 860system.cpu0.icache.ReadReq_mshr_miss_latency::total 11774936000 # number of ReadReq MSHR miss cycles 861system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11774936000 # number of demand (read+write) MSHR miss cycles 862system.cpu0.icache.demand_mshr_miss_latency::total 11774936000 # number of demand (read+write) MSHR miss cycles 863system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11774936000 # number of overall MSHR miss cycles 864system.cpu0.icache.overall_mshr_miss_latency::total 11774936000 # number of overall MSHR miss cycles 865system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of ReadReq MSHR uncacheable cycles 866system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1253876500 # number of ReadReq MSHR uncacheable cycles 867system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1253876500 # number of overall MSHR uncacheable cycles 868system.cpu0.icache.overall_mshr_uncacheable_latency::total 1253876500 # number of overall MSHR uncacheable cycles 869system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for ReadReq accesses 870system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009480 # mshr miss rate for ReadReq accesses 871system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for demand accesses 872system.cpu0.icache.demand_mshr_miss_rate::total 0.009480 # mshr miss rate for demand accesses 873system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009480 # mshr miss rate for overall accesses 874system.cpu0.icache.overall_mshr_miss_rate::total 0.009480 # mshr miss rate for overall accesses 875system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average ReadReq mshr miss latency 876system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10193.637750 # average ReadReq mshr miss latency 877system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average overall mshr miss latency 878system.cpu0.icache.demand_avg_mshr_miss_latency::total 10193.637750 # average overall mshr miss latency 879system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10193.637750 # average overall mshr miss latency 880system.cpu0.icache.overall_avg_mshr_miss_latency::total 10193.637750 # average overall mshr miss latency 881system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average ReadReq mshr uncacheable latency 882system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138979.882509 # average ReadReq mshr uncacheable latency 883system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138979.882509 # average overall mshr uncacheable latency 884system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138979.882509 # average overall mshr uncacheable latency 885system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 886system.cpu0.l2cache.prefetcher.num_hwpf_issued 1946486 # number of hwpf issued 887system.cpu0.l2cache.prefetcher.pfIdentified 1946511 # number of prefetch candidates identified 888system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue 889system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 890system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 891system.cpu0.l2cache.prefetcher.pfSpanPage 246425 # number of prefetches not generated due to page crossing 892system.cpu0.l2cache.tags.replacements 273842 # number of replacements 893system.cpu0.l2cache.tags.tagsinuse 16083.519419 # Cycle average of tags in use 894system.cpu0.l2cache.tags.total_refs 3089138 # Total number of references to valid blocks. 895system.cpu0.l2cache.tags.sampled_refs 289977 # Sample count of references to valid blocks. 896system.cpu0.l2cache.tags.avg_refs 10.653045 # Average number of references to valid blocks. 897system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 898system.cpu0.l2cache.tags.occ_blocks::writebacks 14593.575431 # Average occupied blocks per requestor 899system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.644607 # Average occupied blocks per requestor 900system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.130850 # Average occupied blocks per requestor 901system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1489.168531 # Average occupied blocks per requestor 902system.cpu0.l2cache.tags.occ_percent::writebacks 0.890721 # Average percentage of cache occupancy 903system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000039 # Average percentage of cache occupancy 904system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000008 # Average percentage of cache occupancy 905system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.090892 # Average percentage of cache occupancy 906system.cpu0.l2cache.tags.occ_percent::total 0.981660 # Average percentage of cache occupancy 907system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1031 # Occupied blocks per task id 908system.cpu0.l2cache.tags.occ_task_id_blocks::1023 3 # Occupied blocks per task id 909system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15101 # Occupied blocks per task id 910system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 10 # Occupied blocks per task id 911system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 282 # Occupied blocks per task id 912system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 325 # Occupied blocks per task id 913system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 414 # Occupied blocks per task id 914system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 915system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id 916system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 917system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 918system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3285 # Occupied blocks per task id 919system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7655 # Occupied blocks per task id 920system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3857 # Occupied blocks per task id 921system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062927 # Percentage of cache occupancy per task id 922system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000183 # Percentage of cache occupancy per task id 923system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id 924system.cpu0.l2cache.tags.tag_accesses 63340451 # Number of tag accesses 925system.cpu0.l2cache.tags.data_accesses 63340451 # Number of data accesses 926system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 11537 # number of ReadReq hits 927system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4979 # number of ReadReq hits 928system.cpu0.l2cache.ReadReq_hits::total 16516 # number of ReadReq hits 929system.cpu0.l2cache.WritebackDirty_hits::writebacks 507696 # number of WritebackDirty hits 930system.cpu0.l2cache.WritebackDirty_hits::total 507696 # number of WritebackDirty hits 931system.cpu0.l2cache.WritebackClean_hits::writebacks 1358751 # number of WritebackClean hits 932system.cpu0.l2cache.WritebackClean_hits::total 1358751 # number of WritebackClean hits 933system.cpu0.l2cache.ReadExReq_hits::cpu0.data 241135 # number of ReadExReq hits 934system.cpu0.l2cache.ReadExReq_hits::total 241135 # number of ReadExReq hits 935system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1108628 # number of ReadCleanReq hits 936system.cpu0.l2cache.ReadCleanReq_hits::total 1108628 # number of ReadCleanReq hits 937system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 416937 # number of ReadSharedReq hits 938system.cpu0.l2cache.ReadSharedReq_hits::total 416937 # number of ReadSharedReq hits 939system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 11537 # number of demand (read+write) hits 940system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4979 # number of demand (read+write) hits 941system.cpu0.l2cache.demand_hits::cpu0.inst 1108628 # number of demand (read+write) hits 942system.cpu0.l2cache.demand_hits::cpu0.data 658072 # number of demand (read+write) hits 943system.cpu0.l2cache.demand_hits::total 1783216 # number of demand (read+write) hits 944system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 11537 # number of overall hits 945system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4979 # number of overall hits 946system.cpu0.l2cache.overall_hits::cpu0.inst 1108628 # number of overall hits 947system.cpu0.l2cache.overall_hits::cpu0.data 658072 # number of overall hits 948system.cpu0.l2cache.overall_hits::total 1783216 # number of overall hits 949system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 155 # number of ReadReq misses 950system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 97 # number of ReadReq misses 951system.cpu0.l2cache.ReadReq_misses::total 252 # number of ReadReq misses 952system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55316 # number of UpgradeReq misses 953system.cpu0.l2cache.UpgradeReq_misses::total 55316 # number of UpgradeReq misses 954system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19844 # number of SCUpgradeReq misses 955system.cpu0.l2cache.SCUpgradeReq_misses::total 19844 # number of SCUpgradeReq misses 956system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 957system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 958system.cpu0.l2cache.ReadExReq_misses::cpu0.data 43803 # number of ReadExReq misses 959system.cpu0.l2cache.ReadExReq_misses::total 43803 # number of ReadExReq misses 960system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 46498 # number of ReadCleanReq misses 961system.cpu0.l2cache.ReadCleanReq_misses::total 46498 # number of ReadCleanReq misses 962system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 94557 # number of ReadSharedReq misses 963system.cpu0.l2cache.ReadSharedReq_misses::total 94557 # number of ReadSharedReq misses 964system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 155 # number of demand (read+write) misses 965system.cpu0.l2cache.demand_misses::cpu0.itb.walker 97 # number of demand (read+write) misses 966system.cpu0.l2cache.demand_misses::cpu0.inst 46498 # number of demand (read+write) misses 967system.cpu0.l2cache.demand_misses::cpu0.data 138360 # number of demand (read+write) misses 968system.cpu0.l2cache.demand_misses::total 185110 # number of demand (read+write) misses 969system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 155 # number of overall misses 970system.cpu0.l2cache.overall_misses::cpu0.itb.walker 97 # number of overall misses 971system.cpu0.l2cache.overall_misses::cpu0.inst 46498 # number of overall misses 972system.cpu0.l2cache.overall_misses::cpu0.data 138360 # number of overall misses 973system.cpu0.l2cache.overall_misses::total 185110 # number of overall misses 974system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4266000 # number of ReadReq miss cycles 975system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2540500 # number of ReadReq miss cycles 976system.cpu0.l2cache.ReadReq_miss_latency::total 6806500 # number of ReadReq miss cycles 977system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 172322000 # number of UpgradeReq miss cycles 978system.cpu0.l2cache.UpgradeReq_miss_latency::total 172322000 # number of UpgradeReq miss cycles 979system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 43306000 # number of SCUpgradeReq miss cycles 980system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 43306000 # number of SCUpgradeReq miss cycles 981system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1349997 # number of SCUpgradeFailReq miss cycles 982system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1349997 # number of SCUpgradeFailReq miss cycles 983system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2802544000 # number of ReadExReq miss cycles 984system.cpu0.l2cache.ReadExReq_miss_latency::total 2802544000 # number of ReadExReq miss cycles 985system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 3338173500 # number of ReadCleanReq miss cycles 986system.cpu0.l2cache.ReadCleanReq_miss_latency::total 3338173500 # number of ReadCleanReq miss cycles 987system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3246573500 # number of ReadSharedReq miss cycles 988system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3246573500 # number of ReadSharedReq miss cycles 989system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4266000 # number of demand (read+write) miss cycles 990system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2540500 # number of demand (read+write) miss cycles 991system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3338173500 # number of demand (read+write) miss cycles 992system.cpu0.l2cache.demand_miss_latency::cpu0.data 6049117500 # number of demand (read+write) miss cycles 993system.cpu0.l2cache.demand_miss_latency::total 9394097500 # number of demand (read+write) miss cycles 994system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4266000 # number of overall miss cycles 995system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2540500 # number of overall miss cycles 996system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3338173500 # number of overall miss cycles 997system.cpu0.l2cache.overall_miss_latency::cpu0.data 6049117500 # number of overall miss cycles 998system.cpu0.l2cache.overall_miss_latency::total 9394097500 # number of overall miss cycles 999system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 11692 # number of ReadReq accesses(hits+misses) 1000system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5076 # number of ReadReq accesses(hits+misses) 1001system.cpu0.l2cache.ReadReq_accesses::total 16768 # number of ReadReq accesses(hits+misses) 1002system.cpu0.l2cache.WritebackDirty_accesses::writebacks 507696 # number of WritebackDirty accesses(hits+misses) 1003system.cpu0.l2cache.WritebackDirty_accesses::total 507696 # number of WritebackDirty accesses(hits+misses) 1004system.cpu0.l2cache.WritebackClean_accesses::writebacks 1358751 # number of WritebackClean accesses(hits+misses) 1005system.cpu0.l2cache.WritebackClean_accesses::total 1358751 # number of WritebackClean accesses(hits+misses) 1006system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55316 # number of UpgradeReq accesses(hits+misses) 1007system.cpu0.l2cache.UpgradeReq_accesses::total 55316 # number of UpgradeReq accesses(hits+misses) 1008system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19844 # number of SCUpgradeReq accesses(hits+misses) 1009system.cpu0.l2cache.SCUpgradeReq_accesses::total 19844 # number of SCUpgradeReq accesses(hits+misses) 1010system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 1011system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 1012system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 284938 # number of ReadExReq accesses(hits+misses) 1013system.cpu0.l2cache.ReadExReq_accesses::total 284938 # number of ReadExReq accesses(hits+misses) 1014system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1155126 # number of ReadCleanReq accesses(hits+misses) 1015system.cpu0.l2cache.ReadCleanReq_accesses::total 1155126 # number of ReadCleanReq accesses(hits+misses) 1016system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 511494 # number of ReadSharedReq accesses(hits+misses) 1017system.cpu0.l2cache.ReadSharedReq_accesses::total 511494 # number of ReadSharedReq accesses(hits+misses) 1018system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 11692 # number of demand (read+write) accesses 1019system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5076 # number of demand (read+write) accesses 1020system.cpu0.l2cache.demand_accesses::cpu0.inst 1155126 # number of demand (read+write) accesses 1021system.cpu0.l2cache.demand_accesses::cpu0.data 796432 # number of demand (read+write) accesses 1022system.cpu0.l2cache.demand_accesses::total 1968326 # number of demand (read+write) accesses 1023system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 11692 # number of overall (read+write) accesses 1024system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5076 # number of overall (read+write) accesses 1025system.cpu0.l2cache.overall_accesses::cpu0.inst 1155126 # number of overall (read+write) accesses 1026system.cpu0.l2cache.overall_accesses::cpu0.data 796432 # number of overall (read+write) accesses 1027system.cpu0.l2cache.overall_accesses::total 1968326 # number of overall (read+write) accesses 1028system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for ReadReq accesses 1029system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.019110 # miss rate for ReadReq accesses 1030system.cpu0.l2cache.ReadReq_miss_rate::total 0.015029 # miss rate for ReadReq accesses 1031system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1032system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1033system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1034system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1035system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1036system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1037system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.153728 # miss rate for ReadExReq accesses 1038system.cpu0.l2cache.ReadExReq_miss_rate::total 0.153728 # miss rate for ReadExReq accesses 1039system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040254 # miss rate for ReadCleanReq accesses 1040system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040254 # miss rate for ReadCleanReq accesses 1041system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.184864 # miss rate for ReadSharedReq accesses 1042system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.184864 # miss rate for ReadSharedReq accesses 1043system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for demand accesses 1044system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.019110 # miss rate for demand accesses 1045system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040254 # miss rate for demand accesses 1046system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.173725 # miss rate for demand accesses 1047system.cpu0.l2cache.demand_miss_rate::total 0.094044 # miss rate for demand accesses 1048system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.013257 # miss rate for overall accesses 1049system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.019110 # miss rate for overall accesses 1050system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040254 # miss rate for overall accesses 1051system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.173725 # miss rate for overall accesses 1052system.cpu0.l2cache.overall_miss_rate::total 0.094044 # miss rate for overall accesses 1053system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average ReadReq miss latency 1054system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 26190.721649 # average ReadReq miss latency 1055system.cpu0.l2cache.ReadReq_avg_miss_latency::total 27009.920635 # average ReadReq miss latency 1056system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3115.228867 # average UpgradeReq miss latency 1057system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3115.228867 # average UpgradeReq miss latency 1058system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 2182.322112 # average SCUpgradeReq miss latency 1059system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 2182.322112 # average SCUpgradeReq miss latency 1060system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 269999.400000 # average SCUpgradeFailReq miss latency 1061system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 269999.400000 # average SCUpgradeFailReq miss latency 1062system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 63980.640595 # average ReadExReq miss latency 1063system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 63980.640595 # average ReadExReq miss latency 1064system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 71791.765237 # average ReadCleanReq miss latency 1065system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 71791.765237 # average ReadCleanReq miss latency 1066system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 34334.565394 # average ReadSharedReq miss latency 1067system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 34334.565394 # average ReadSharedReq miss latency 1068system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average overall miss latency 1069system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 26190.721649 # average overall miss latency 1070system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 71791.765237 # average overall miss latency 1071system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 43720.132264 # average overall miss latency 1072system.cpu0.l2cache.demand_avg_miss_latency::total 50748.730485 # average overall miss latency 1073system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27522.580645 # average overall miss latency 1074system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 26190.721649 # average overall miss latency 1075system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 71791.765237 # average overall miss latency 1076system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 43720.132264 # average overall miss latency 1077system.cpu0.l2cache.overall_avg_miss_latency::total 50748.730485 # average overall miss latency 1078system.cpu0.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked 1079system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1080system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1081system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1082system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked 1083system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1084system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1085system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1086system.cpu0.l2cache.writebacks::writebacks 232272 # number of writebacks 1087system.cpu0.l2cache.writebacks::total 232272 # number of writebacks 1088system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1851 # number of ReadExReq MSHR hits 1089system.cpu0.l2cache.ReadExReq_mshr_hits::total 1851 # number of ReadExReq MSHR hits 1090system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 57 # number of ReadSharedReq MSHR hits 1091system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 57 # number of ReadSharedReq MSHR hits 1092system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1908 # number of demand (read+write) MSHR hits 1093system.cpu0.l2cache.demand_mshr_hits::total 1908 # number of demand (read+write) MSHR hits 1094system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1908 # number of overall MSHR hits 1095system.cpu0.l2cache.overall_mshr_hits::total 1908 # number of overall MSHR hits 1096system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 155 # number of ReadReq MSHR misses 1097system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 97 # number of ReadReq MSHR misses 1098system.cpu0.l2cache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses 1099system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 264558 # number of HardPFReq MSHR misses 1100system.cpu0.l2cache.HardPFReq_mshr_misses::total 264558 # number of HardPFReq MSHR misses 1101system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 55316 # number of UpgradeReq MSHR misses 1102system.cpu0.l2cache.UpgradeReq_mshr_misses::total 55316 # number of UpgradeReq MSHR misses 1103system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19844 # number of SCUpgradeReq MSHR misses 1104system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19844 # number of SCUpgradeReq MSHR misses 1105system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 1106system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 1107system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41952 # number of ReadExReq MSHR misses 1108system.cpu0.l2cache.ReadExReq_mshr_misses::total 41952 # number of ReadExReq MSHR misses 1109system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 46498 # number of ReadCleanReq MSHR misses 1110system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 46498 # number of ReadCleanReq MSHR misses 1111system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 94500 # number of ReadSharedReq MSHR misses 1112system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 94500 # number of ReadSharedReq MSHR misses 1113system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 155 # number of demand (read+write) MSHR misses 1114system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 97 # number of demand (read+write) MSHR misses 1115system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 46498 # number of demand (read+write) MSHR misses 1116system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136452 # number of demand (read+write) MSHR misses 1117system.cpu0.l2cache.demand_mshr_misses::total 183202 # number of demand (read+write) MSHR misses 1118system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 155 # number of overall MSHR misses 1119system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 97 # number of overall MSHR misses 1120system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 46498 # number of overall MSHR misses 1121system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136452 # number of overall MSHR misses 1122system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 264558 # number of overall MSHR misses 1123system.cpu0.l2cache.overall_mshr_misses::total 447760 # number of overall MSHR misses 1124system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 1125system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable 1126system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 40882 # number of ReadReq MSHR uncacheable 1127system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable 1128system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 28553 # number of WriteReq MSHR uncacheable 1129system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 1130system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses 1131system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 69435 # number of overall MSHR uncacheable misses 1132system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of ReadReq MSHR miss cycles 1133system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1958500 # number of ReadReq MSHR miss cycles 1134system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 5294500 # number of ReadReq MSHR miss cycles 1135system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 20402670222 # number of HardPFReq MSHR miss cycles 1136system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 20402670222 # number of HardPFReq MSHR miss cycles 1137system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 1434169000 # number of UpgradeReq MSHR miss cycles 1138system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 1434169000 # number of UpgradeReq MSHR miss cycles 1139system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 342730000 # number of SCUpgradeReq MSHR miss cycles 1140system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 342730000 # number of SCUpgradeReq MSHR miss cycles 1141system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1097997 # number of SCUpgradeFailReq MSHR miss cycles 1142system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1097997 # number of SCUpgradeFailReq MSHR miss cycles 1143system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 2366849000 # number of ReadExReq MSHR miss cycles 1144system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 2366849000 # number of ReadExReq MSHR miss cycles 1145system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 3059185500 # number of ReadCleanReq MSHR miss cycles 1146system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 3059185500 # number of ReadCleanReq MSHR miss cycles 1147system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2673492000 # number of ReadSharedReq MSHR miss cycles 1148system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2673492000 # number of ReadSharedReq MSHR miss cycles 1149system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of demand (read+write) MSHR miss cycles 1150system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1958500 # number of demand (read+write) MSHR miss cycles 1151system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3059185500 # number of demand (read+write) MSHR miss cycles 1152system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 5040341000 # number of demand (read+write) MSHR miss cycles 1153system.cpu0.l2cache.demand_mshr_miss_latency::total 8104821000 # number of demand (read+write) MSHR miss cycles 1154system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3336000 # number of overall MSHR miss cycles 1155system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1958500 # number of overall MSHR miss cycles 1156system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3059185500 # number of overall MSHR miss cycles 1157system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 5040341000 # number of overall MSHR miss cycles 1158system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 20402670222 # number of overall MSHR miss cycles 1159system.cpu0.l2cache.overall_mshr_miss_latency::total 28507491222 # number of overall MSHR miss cycles 1160system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of ReadReq MSHR uncacheable cycles 1161system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6386259500 # number of ReadReq MSHR uncacheable cycles 1162system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7572471000 # number of ReadReq MSHR uncacheable cycles 1163system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5200454500 # number of WriteReq MSHR uncacheable cycles 1164system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5200454500 # number of WriteReq MSHR uncacheable cycles 1165system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1186211500 # number of overall MSHR uncacheable cycles 1166system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11586714000 # number of overall MSHR uncacheable cycles 1167system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12772925500 # number of overall MSHR uncacheable cycles 1168system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for ReadReq accesses 1169system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for ReadReq accesses 1170system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.015029 # mshr miss rate for ReadReq accesses 1171system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1172system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1173system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1174system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1175system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1176system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1177system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1178system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1179system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.147232 # mshr miss rate for ReadExReq accesses 1180system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.147232 # mshr miss rate for ReadExReq accesses 1181system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for ReadCleanReq accesses 1182system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040254 # mshr miss rate for ReadCleanReq accesses 1183system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.184753 # mshr miss rate for ReadSharedReq accesses 1184system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.184753 # mshr miss rate for ReadSharedReq accesses 1185system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for demand accesses 1186system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for demand accesses 1187system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for demand accesses 1188system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for demand accesses 1189system.cpu0.l2cache.demand_mshr_miss_rate::total 0.093075 # mshr miss rate for demand accesses 1190system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.013257 # mshr miss rate for overall accesses 1191system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.019110 # mshr miss rate for overall accesses 1192system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040254 # mshr miss rate for overall accesses 1193system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.171329 # mshr miss rate for overall accesses 1194system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1195system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227483 # mshr miss rate for overall accesses 1196system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average ReadReq mshr miss latency 1197system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average ReadReq mshr miss latency 1198system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21009.920635 # average ReadReq mshr miss latency 1199system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average HardPFReq mshr miss latency 1200system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 77119.838455 # average HardPFReq mshr miss latency 1201system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 25926.838528 # average UpgradeReq mshr miss latency 1202system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25926.838528 # average UpgradeReq mshr miss latency 1203system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17271.215481 # average SCUpgradeReq mshr miss latency 1204system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17271.215481 # average SCUpgradeReq mshr miss latency 1205system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 219599.400000 # average SCUpgradeFailReq mshr miss latency 1206system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 219599.400000 # average SCUpgradeFailReq mshr miss latency 1207system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56418.025362 # average ReadExReq mshr miss latency 1208system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56418.025362 # average ReadExReq mshr miss latency 1209system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average ReadCleanReq mshr miss latency 1210system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65791.765237 # average ReadCleanReq mshr miss latency 1211system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28290.920635 # average ReadSharedReq mshr miss latency 1212system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28290.920635 # average ReadSharedReq mshr miss latency 1213system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency 1214system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency 1215system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency 1216system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency 1217system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44239.806334 # average overall mshr miss latency 1218system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21522.580645 # average overall mshr miss latency 1219system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20190.721649 # average overall mshr miss latency 1220system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 65791.765237 # average overall mshr miss latency 1221system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 36938.564477 # average overall mshr miss latency 1222system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 77119.838455 # average overall mshr miss latency 1223system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63666.900174 # average overall mshr miss latency 1224system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average ReadReq mshr uncacheable latency 1225system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200447.567483 # average ReadReq mshr uncacheable latency 1226system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185227.508439 # average ReadReq mshr uncacheable latency 1227system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182133.383532 # average WriteReq mshr uncacheable latency 1228system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182133.383532 # average WriteReq mshr uncacheable latency 1229system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 131479.882509 # average overall mshr uncacheable latency 1230system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191791.733567 # average overall mshr uncacheable latency 1231system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 183955.145100 # average overall mshr uncacheable latency 1232system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1233system.cpu0.toL2Bus.snoop_filter.tot_requests 3935499 # Total number of requests made to the snoop filter. 1234system.cpu0.toL2Bus.snoop_filter.hit_single_requests 1983981 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1235system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 29039 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1236system.cpu0.toL2Bus.snoop_filter.tot_snoops 320941 # Total number of snoops made to the snoop filter. 1237system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 317478 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1238system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3463 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1239system.cpu0.toL2Bus.trans_dist::ReadReq 63971 # Transaction distribution 1240system.cpu0.toL2Bus.trans_dist::ReadResp 1779248 # Transaction distribution 1241system.cpu0.toL2Bus.trans_dist::WriteReq 28553 # Transaction distribution 1242system.cpu0.toL2Bus.trans_dist::WriteResp 28553 # Transaction distribution 1243system.cpu0.toL2Bus.trans_dist::WritebackDirty 740475 # Transaction distribution 1244system.cpu0.toL2Bus.trans_dist::WritebackClean 1358751 # Transaction distribution 1245system.cpu0.toL2Bus.trans_dist::CleanEvict 190136 # Transaction distribution 1246system.cpu0.toL2Bus.trans_dist::HardPFReq 311790 # Transaction distribution 1247system.cpu0.toL2Bus.trans_dist::UpgradeReq 85728 # Transaction distribution 1248system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 41989 # Transaction distribution 1249system.cpu0.toL2Bus.trans_dist::UpgradeResp 112642 # Transaction distribution 1250system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 35 # Transaction distribution 1251system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution 1252system.cpu0.toL2Bus.trans_dist::ReadExReq 304006 # Transaction distribution 1253system.cpu0.toL2Bus.trans_dist::ReadExResp 300714 # Transaction distribution 1254system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1155126 # Transaction distribution 1255system.cpu0.toL2Bus.trans_dist::ReadSharedReq 580591 # Transaction distribution 1256system.cpu0.toL2Bus.trans_dist::InvalidateReq 3227 # Transaction distribution 1257system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3461069 # Packet count per connected master and slave (bytes) 1258system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2699694 # Packet count per connected master and slave (bytes) 1259system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12104 # Packet count per connected master and slave (bytes) 1260system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 27735 # Packet count per connected master and slave (bytes) 1261system.cpu0.toL2Bus.pkt_count::total 6200602 # Packet count per connected master and slave (bytes) 1262system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 146461624 # Cumulative packet size per connected master and slave (bytes) 1263system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 102248167 # Cumulative packet size per connected master and slave (bytes) 1264system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20304 # Cumulative packet size per connected master and slave (bytes) 1265system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46768 # Cumulative packet size per connected master and slave (bytes) 1266system.cpu0.toL2Bus.pkt_size::total 248776863 # Cumulative packet size per connected master and slave (bytes) 1267system.cpu0.toL2Bus.snoops 987005 # Total snoops (count) 1268system.cpu0.toL2Bus.snoop_fanout::samples 2997932 # Request fanout histogram 1269system.cpu0.toL2Bus.snoop_fanout::mean 0.122336 # Request fanout histogram 1270system.cpu0.toL2Bus.snoop_fanout::stdev 0.331180 # Request fanout histogram 1271system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1272system.cpu0.toL2Bus.snoop_fanout::0 2634639 87.88% 87.88% # Request fanout histogram 1273system.cpu0.toL2Bus.snoop_fanout::1 359830 12.00% 99.88% # Request fanout histogram 1274system.cpu0.toL2Bus.snoop_fanout::2 3463 0.12% 100.00% # Request fanout histogram 1275system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1276system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1277system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1278system.cpu0.toL2Bus.snoop_fanout::total 2997932 # Request fanout histogram 1279system.cpu0.toL2Bus.reqLayer0.occupancy 3917122496 # Layer occupancy (ticks) 1280system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1281system.cpu0.toL2Bus.snoopLayer0.occupancy 115533329 # Layer occupancy (ticks) 1282system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1283system.cpu0.toL2Bus.respLayer0.occupancy 1741711000 # Layer occupancy (ticks) 1284system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1285system.cpu0.toL2Bus.respLayer1.occupancy 1278424980 # Layer occupancy (ticks) 1286system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1287system.cpu0.toL2Bus.respLayer2.occupancy 7028000 # Layer occupancy (ticks) 1288system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1289system.cpu0.toL2Bus.respLayer3.occupancy 16050485 # Layer occupancy (ticks) 1290system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1291system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1292system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1293system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1294system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1295system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1296system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1297system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1298system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1299system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1300system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1301system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1302system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1303system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1304system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1305system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1306system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1307system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1308system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1309system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1310system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1311system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1312system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1313system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1314system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1315system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1316system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1317system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1318system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1319system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1320system.cpu1.dtb.walker.walks 2352 # Table walker walks requested 1321system.cpu1.dtb.walker.walksShort 2352 # Table walker walks initiated with short descriptors 1322system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 487 # Level at which table walker walks with short descriptors terminate 1323system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1865 # Level at which table walker walks with short descriptors terminate 1324system.cpu1.dtb.walker.walkWaitTime::samples 2352 # Table walker wait (enqueue to first request) latency 1325system.cpu1.dtb.walker.walkWaitTime::0 2352 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1326system.cpu1.dtb.walker.walkWaitTime::total 2352 # Table walker wait (enqueue to first request) latency 1327system.cpu1.dtb.walker.walkCompletionTime::samples 1706 # Table walker service (enqueue to completion) latency 1328system.cpu1.dtb.walker.walkCompletionTime::mean 11672.919109 # Table walker service (enqueue to completion) latency 1329system.cpu1.dtb.walker.walkCompletionTime::gmean 11010.748339 # Table walker service (enqueue to completion) latency 1330system.cpu1.dtb.walker.walkCompletionTime::stdev 5645.878722 # Table walker service (enqueue to completion) latency 1331system.cpu1.dtb.walker.walkCompletionTime::0-16383 1558 91.32% 91.32% # Table walker service (enqueue to completion) latency 1332system.cpu1.dtb.walker.walkCompletionTime::16384-32767 139 8.15% 99.47% # Table walker service (enqueue to completion) latency 1333system.cpu1.dtb.walker.walkCompletionTime::32768-49151 5 0.29% 99.77% # Table walker service (enqueue to completion) latency 1334system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.18% 99.94% # Table walker service (enqueue to completion) latency 1335system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.06% 100.00% # Table walker service (enqueue to completion) latency 1336system.cpu1.dtb.walker.walkCompletionTime::total 1706 # Table walker service (enqueue to completion) latency 1337system.cpu1.dtb.walker.walksPending::samples -1207257828 # Table walker pending requests distribution 1338system.cpu1.dtb.walker.walksPending::0 -1207257828 100.00% 100.00% # Table walker pending requests distribution 1339system.cpu1.dtb.walker.walksPending::total -1207257828 # Table walker pending requests distribution 1340system.cpu1.dtb.walker.walkPageSizes::4K 1219 71.45% 71.45% # Table walker page sizes translated 1341system.cpu1.dtb.walker.walkPageSizes::1M 487 28.55% 100.00% # Table walker page sizes translated 1342system.cpu1.dtb.walker.walkPageSizes::total 1706 # Table walker page sizes translated 1343system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 2352 # Table walker requests started/completed, data/inst 1344system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1345system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 2352 # Table walker requests started/completed, data/inst 1346system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1706 # Table walker requests started/completed, data/inst 1347system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1348system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1706 # Table walker requests started/completed, data/inst 1349system.cpu1.dtb.walker.walkRequestOrigin::total 4058 # Table walker requests started/completed, data/inst 1350system.cpu1.dtb.inst_hits 0 # ITB inst hits 1351system.cpu1.dtb.inst_misses 0 # ITB inst misses 1352system.cpu1.dtb.read_hits 3283088 # DTB read hits 1353system.cpu1.dtb.read_misses 1969 # DTB read misses 1354system.cpu1.dtb.write_hits 2849660 # DTB write hits 1355system.cpu1.dtb.write_misses 383 # DTB write misses 1356system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 1357system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1358system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1359system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1360system.cpu1.dtb.flush_entries 1653 # Number of entries that have been flushed from TLB 1361system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1362system.cpu1.dtb.prefetch_faults 218 # Number of TLB faults due to prefetch 1363system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1364system.cpu1.dtb.perms_faults 124 # Number of TLB faults due to permissions restrictions 1365system.cpu1.dtb.read_accesses 3285057 # DTB read accesses 1366system.cpu1.dtb.write_accesses 2850043 # DTB write accesses 1367system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1368system.cpu1.dtb.hits 6132748 # DTB hits 1369system.cpu1.dtb.misses 2352 # DTB misses 1370system.cpu1.dtb.accesses 6135100 # DTB accesses 1371system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1372system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1373system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1374system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1375system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1376system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1377system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1378system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1379system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1380system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1381system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1382system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1383system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1384system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1385system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1386system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1387system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1388system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1389system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1390system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1391system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1392system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1393system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1394system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1395system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1396system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1397system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1398system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1399system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1400system.cpu1.itb.walker.walks 1376 # Table walker walks requested 1401system.cpu1.itb.walker.walksShort 1376 # Table walker walks initiated with short descriptors 1402system.cpu1.itb.walker.walksShortTerminationLevel::Level1 134 # Level at which table walker walks with short descriptors terminate 1403system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1242 # Level at which table walker walks with short descriptors terminate 1404system.cpu1.itb.walker.walkWaitTime::samples 1376 # Table walker wait (enqueue to first request) latency 1405system.cpu1.itb.walker.walkWaitTime::0 1376 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1406system.cpu1.itb.walker.walkWaitTime::total 1376 # Table walker wait (enqueue to first request) latency 1407system.cpu1.itb.walker.walkCompletionTime::samples 819 # Table walker service (enqueue to completion) latency 1408system.cpu1.itb.walker.walkCompletionTime::mean 11896.825397 # Table walker service (enqueue to completion) latency 1409system.cpu1.itb.walker.walkCompletionTime::gmean 11258.920739 # Table walker service (enqueue to completion) latency 1410system.cpu1.itb.walker.walkCompletionTime::stdev 5216.232861 # Table walker service (enqueue to completion) latency 1411system.cpu1.itb.walker.walkCompletionTime::4096-8191 112 13.68% 13.68% # Table walker service (enqueue to completion) latency 1412system.cpu1.itb.walker.walkCompletionTime::8192-12287 592 72.28% 85.96% # Table walker service (enqueue to completion) latency 1413system.cpu1.itb.walker.walkCompletionTime::12288-16383 66 8.06% 94.02% # Table walker service (enqueue to completion) latency 1414system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.85% 94.87% # Table walker service (enqueue to completion) latency 1415system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 95.12% # Table walker service (enqueue to completion) latency 1416system.cpu1.itb.walker.walkCompletionTime::24576-28671 24 2.93% 98.05% # Table walker service (enqueue to completion) latency 1417system.cpu1.itb.walker.walkCompletionTime::28672-32767 5 0.61% 98.66% # Table walker service (enqueue to completion) latency 1418system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 98.78% # Table walker service (enqueue to completion) latency 1419system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.73% 99.51% # Table walker service (enqueue to completion) latency 1420system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.24% 99.76% # Table walker service (enqueue to completion) latency 1421system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency 1422system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency 1423system.cpu1.itb.walker.walkCompletionTime::total 819 # Table walker service (enqueue to completion) latency 1424system.cpu1.itb.walker.walksPending::samples -1208095828 # Table walker pending requests distribution 1425system.cpu1.itb.walker.walksPending::0 -1208095828 100.00% 100.00% # Table walker pending requests distribution 1426system.cpu1.itb.walker.walksPending::total -1208095828 # Table walker pending requests distribution 1427system.cpu1.itb.walker.walkPageSizes::4K 685 83.64% 83.64% # Table walker page sizes translated 1428system.cpu1.itb.walker.walkPageSizes::1M 134 16.36% 100.00% # Table walker page sizes translated 1429system.cpu1.itb.walker.walkPageSizes::total 819 # Table walker page sizes translated 1430system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1431system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1376 # Table walker requests started/completed, data/inst 1432system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1376 # Table walker requests started/completed, data/inst 1433system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1434system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 819 # Table walker requests started/completed, data/inst 1435system.cpu1.itb.walker.walkRequestOrigin_Completed::total 819 # Table walker requests started/completed, data/inst 1436system.cpu1.itb.walker.walkRequestOrigin::total 2195 # Table walker requests started/completed, data/inst 1437system.cpu1.itb.inst_hits 13713445 # ITB inst hits 1438system.cpu1.itb.inst_misses 1376 # ITB inst misses 1439system.cpu1.itb.read_hits 0 # DTB read hits 1440system.cpu1.itb.read_misses 0 # DTB read misses 1441system.cpu1.itb.write_hits 0 # DTB write hits 1442system.cpu1.itb.write_misses 0 # DTB write misses 1443system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 1444system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 1445system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1446system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1447system.cpu1.itb.flush_entries 883 # Number of entries that have been flushed from TLB 1448system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1449system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1450system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1451system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1452system.cpu1.itb.read_accesses 0 # DTB read accesses 1453system.cpu1.itb.write_accesses 0 # DTB write accesses 1454system.cpu1.itb.inst_accesses 13714821 # ITB inst accesses 1455system.cpu1.itb.hits 13713445 # DTB hits 1456system.cpu1.itb.misses 1376 # DTB misses 1457system.cpu1.itb.accesses 13714821 # DTB accesses 1458system.cpu1.numCycles 5742759797 # number of cpu cycles simulated 1459system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1460system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1461system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1462system.cpu1.kern.inst.quiesce 2753 # number of quiesce instructions executed 1463system.cpu1.committedInsts 13517417 # Number of instructions committed 1464system.cpu1.committedOps 16437338 # Number of ops (including micro ops) committed 1465system.cpu1.num_int_alu_accesses 14911378 # Number of integer alu accesses 1466system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses 1467system.cpu1.num_func_calls 901174 # number of times a function call or return occured 1468system.cpu1.num_conditional_control_insts 1468136 # number of instructions that are conditional controls 1469system.cpu1.num_int_insts 14911378 # number of integer instructions 1470system.cpu1.num_fp_insts 0 # number of float instructions 1471system.cpu1.num_int_register_reads 27063131 # number of times the integer registers were read 1472system.cpu1.num_int_register_writes 10536793 # number of times the integer registers were written 1473system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read 1474system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written 1475system.cpu1.num_cc_register_reads 60344215 # number of times the CC registers were read 1476system.cpu1.num_cc_register_writes 5099594 # number of times the CC registers were written 1477system.cpu1.num_mem_refs 6349896 # number of memory refs 1478system.cpu1.num_load_insts 3389045 # Number of load instructions 1479system.cpu1.num_store_insts 2960851 # Number of store instructions 1480system.cpu1.num_idle_cycles 5696813538.222876 # Number of idle cycles 1481system.cpu1.num_busy_cycles 45946258.777124 # Number of busy cycles 1482system.cpu1.not_idle_fraction 0.008001 # Percentage of non-idle cycles 1483system.cpu1.idle_fraction 0.991999 # Percentage of idle cycles 1484system.cpu1.Branches 2418797 # Number of branches fetched 1485system.cpu1.op_class::No_OpClass 24 0.00% 0.00% # Class of executed instruction 1486system.cpu1.op_class::IntAlu 10377527 61.94% 61.94% # Class of executed instruction 1487system.cpu1.op_class::IntMult 24492 0.15% 62.08% # Class of executed instruction 1488system.cpu1.op_class::IntDiv 0 0.00% 62.08% # Class of executed instruction 1489system.cpu1.op_class::FloatAdd 0 0.00% 62.08% # Class of executed instruction 1490system.cpu1.op_class::FloatCmp 0 0.00% 62.08% # Class of executed instruction 1491system.cpu1.op_class::FloatCvt 0 0.00% 62.08% # Class of executed instruction 1492system.cpu1.op_class::FloatMult 0 0.00% 62.08% # Class of executed instruction 1493system.cpu1.op_class::FloatDiv 0 0.00% 62.08% # Class of executed instruction 1494system.cpu1.op_class::FloatSqrt 0 0.00% 62.08% # Class of executed instruction 1495system.cpu1.op_class::SimdAdd 0 0.00% 62.08% # Class of executed instruction 1496system.cpu1.op_class::SimdAddAcc 0 0.00% 62.08% # Class of executed instruction 1497system.cpu1.op_class::SimdAlu 0 0.00% 62.08% # Class of executed instruction 1498system.cpu1.op_class::SimdCmp 0 0.00% 62.08% # Class of executed instruction 1499system.cpu1.op_class::SimdCvt 0 0.00% 62.08% # Class of executed instruction 1500system.cpu1.op_class::SimdMisc 0 0.00% 62.08% # Class of executed instruction 1501system.cpu1.op_class::SimdMult 0 0.00% 62.08% # Class of executed instruction 1502system.cpu1.op_class::SimdMultAcc 0 0.00% 62.08% # Class of executed instruction 1503system.cpu1.op_class::SimdShift 0 0.00% 62.08% # Class of executed instruction 1504system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.08% # Class of executed instruction 1505system.cpu1.op_class::SimdSqrt 0 0.00% 62.08% # Class of executed instruction 1506system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.08% # Class of executed instruction 1507system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.08% # Class of executed instruction 1508system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.08% # Class of executed instruction 1509system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.08% # Class of executed instruction 1510system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.08% # Class of executed instruction 1511system.cpu1.op_class::SimdFloatMisc 3134 0.02% 62.10% # Class of executed instruction 1512system.cpu1.op_class::SimdFloatMult 0 0.00% 62.10% # Class of executed instruction 1513system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.10% # Class of executed instruction 1514system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.10% # Class of executed instruction 1515system.cpu1.op_class::MemRead 3389045 20.23% 82.33% # Class of executed instruction 1516system.cpu1.op_class::MemWrite 2960851 17.67% 100.00% # Class of executed instruction 1517system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1518system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1519system.cpu1.op_class::total 16755073 # Class of executed instruction 1520system.cpu1.dcache.tags.replacements 144073 # number of replacements 1521system.cpu1.dcache.tags.tagsinuse 473.219627 # Cycle average of tags in use 1522system.cpu1.dcache.tags.total_refs 5912733 # Total number of references to valid blocks. 1523system.cpu1.dcache.tags.sampled_refs 144418 # Sample count of references to valid blocks. 1524system.cpu1.dcache.tags.avg_refs 40.941801 # Average number of references to valid blocks. 1525system.cpu1.dcache.tags.warmup_cycle 106295131000 # Cycle when the warmup percentage was hit. 1526system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.219627 # Average occupied blocks per requestor 1527system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924257 # Average percentage of cache occupancy 1528system.cpu1.dcache.tags.occ_percent::total 0.924257 # Average percentage of cache occupancy 1529system.cpu1.dcache.tags.occ_task_id_blocks::1024 345 # Occupied blocks per task id 1530system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id 1531system.cpu1.dcache.tags.age_task_id_blocks_1024::3 26 # Occupied blocks per task id 1532system.cpu1.dcache.tags.occ_task_id_percent::1024 0.673828 # Percentage of cache occupancy per task id 1533system.cpu1.dcache.tags.tag_accesses 12441829 # Number of tag accesses 1534system.cpu1.dcache.tags.data_accesses 12441829 # Number of data accesses 1535system.cpu1.dcache.ReadReq_hits::cpu1.data 3018165 # number of ReadReq hits 1536system.cpu1.dcache.ReadReq_hits::total 3018165 # number of ReadReq hits 1537system.cpu1.dcache.WriteReq_hits::cpu1.data 2685196 # number of WriteReq hits 1538system.cpu1.dcache.WriteReq_hits::total 2685196 # number of WriteReq hits 1539system.cpu1.dcache.SoftPFReq_hits::cpu1.data 41245 # number of SoftPFReq hits 1540system.cpu1.dcache.SoftPFReq_hits::total 41245 # number of SoftPFReq hits 1541system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 69563 # number of LoadLockedReq hits 1542system.cpu1.dcache.LoadLockedReq_hits::total 69563 # number of LoadLockedReq hits 1543system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61182 # number of StoreCondReq hits 1544system.cpu1.dcache.StoreCondReq_hits::total 61182 # number of StoreCondReq hits 1545system.cpu1.dcache.demand_hits::cpu1.data 5703361 # number of demand (read+write) hits 1546system.cpu1.dcache.demand_hits::total 5703361 # number of demand (read+write) hits 1547system.cpu1.dcache.overall_hits::cpu1.data 5744606 # number of overall hits 1548system.cpu1.dcache.overall_hits::total 5744606 # number of overall hits 1549system.cpu1.dcache.ReadReq_misses::cpu1.data 110713 # number of ReadReq misses 1550system.cpu1.dcache.ReadReq_misses::total 110713 # number of ReadReq misses 1551system.cpu1.dcache.WriteReq_misses::cpu1.data 77621 # number of WriteReq misses 1552system.cpu1.dcache.WriteReq_misses::total 77621 # number of WriteReq misses 1553system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23905 # number of SoftPFReq misses 1554system.cpu1.dcache.SoftPFReq_misses::total 23905 # number of SoftPFReq misses 1555system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16417 # number of LoadLockedReq misses 1556system.cpu1.dcache.LoadLockedReq_misses::total 16417 # number of LoadLockedReq misses 1557system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23076 # number of StoreCondReq misses 1558system.cpu1.dcache.StoreCondReq_misses::total 23076 # number of StoreCondReq misses 1559system.cpu1.dcache.demand_misses::cpu1.data 188334 # number of demand (read+write) misses 1560system.cpu1.dcache.demand_misses::total 188334 # number of demand (read+write) misses 1561system.cpu1.dcache.overall_misses::cpu1.data 212239 # number of overall misses 1562system.cpu1.dcache.overall_misses::total 212239 # number of overall misses 1563system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1730591500 # number of ReadReq miss cycles 1564system.cpu1.dcache.ReadReq_miss_latency::total 1730591500 # number of ReadReq miss cycles 1565system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2713528000 # number of WriteReq miss cycles 1566system.cpu1.dcache.WriteReq_miss_latency::total 2713528000 # number of WriteReq miss cycles 1567system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 316809000 # number of LoadLockedReq miss cycles 1568system.cpu1.dcache.LoadLockedReq_miss_latency::total 316809000 # number of LoadLockedReq miss cycles 1569system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 632764000 # number of StoreCondReq miss cycles 1570system.cpu1.dcache.StoreCondReq_miss_latency::total 632764000 # number of StoreCondReq miss cycles 1571system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3307000 # number of StoreCondFailReq miss cycles 1572system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3307000 # number of StoreCondFailReq miss cycles 1573system.cpu1.dcache.demand_miss_latency::cpu1.data 4444119500 # number of demand (read+write) miss cycles 1574system.cpu1.dcache.demand_miss_latency::total 4444119500 # number of demand (read+write) miss cycles 1575system.cpu1.dcache.overall_miss_latency::cpu1.data 4444119500 # number of overall miss cycles 1576system.cpu1.dcache.overall_miss_latency::total 4444119500 # number of overall miss cycles 1577system.cpu1.dcache.ReadReq_accesses::cpu1.data 3128878 # number of ReadReq accesses(hits+misses) 1578system.cpu1.dcache.ReadReq_accesses::total 3128878 # number of ReadReq accesses(hits+misses) 1579system.cpu1.dcache.WriteReq_accesses::cpu1.data 2762817 # number of WriteReq accesses(hits+misses) 1580system.cpu1.dcache.WriteReq_accesses::total 2762817 # number of WriteReq accesses(hits+misses) 1581system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 65150 # number of SoftPFReq accesses(hits+misses) 1582system.cpu1.dcache.SoftPFReq_accesses::total 65150 # number of SoftPFReq accesses(hits+misses) 1583system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 85980 # number of LoadLockedReq accesses(hits+misses) 1584system.cpu1.dcache.LoadLockedReq_accesses::total 85980 # number of LoadLockedReq accesses(hits+misses) 1585system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84258 # number of StoreCondReq accesses(hits+misses) 1586system.cpu1.dcache.StoreCondReq_accesses::total 84258 # number of StoreCondReq accesses(hits+misses) 1587system.cpu1.dcache.demand_accesses::cpu1.data 5891695 # number of demand (read+write) accesses 1588system.cpu1.dcache.demand_accesses::total 5891695 # number of demand (read+write) accesses 1589system.cpu1.dcache.overall_accesses::cpu1.data 5956845 # number of overall (read+write) accesses 1590system.cpu1.dcache.overall_accesses::total 5956845 # number of overall (read+write) accesses 1591system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035384 # miss rate for ReadReq accesses 1592system.cpu1.dcache.ReadReq_miss_rate::total 0.035384 # miss rate for ReadReq accesses 1593system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028095 # miss rate for WriteReq accesses 1594system.cpu1.dcache.WriteReq_miss_rate::total 0.028095 # miss rate for WriteReq accesses 1595system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.366922 # miss rate for SoftPFReq accesses 1596system.cpu1.dcache.SoftPFReq_miss_rate::total 0.366922 # miss rate for SoftPFReq accesses 1597system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190940 # miss rate for LoadLockedReq accesses 1598system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190940 # miss rate for LoadLockedReq accesses 1599system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.273873 # miss rate for StoreCondReq accesses 1600system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273873 # miss rate for StoreCondReq accesses 1601system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031966 # miss rate for demand accesses 1602system.cpu1.dcache.demand_miss_rate::total 0.031966 # miss rate for demand accesses 1603system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035629 # miss rate for overall accesses 1604system.cpu1.dcache.overall_miss_rate::total 0.035629 # miss rate for overall accesses 1605system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15631.330557 # average ReadReq miss latency 1606system.cpu1.dcache.ReadReq_avg_miss_latency::total 15631.330557 # average ReadReq miss latency 1607system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34958.683861 # average WriteReq miss latency 1608system.cpu1.dcache.WriteReq_avg_miss_latency::total 34958.683861 # average WriteReq miss latency 1609system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19297.618322 # average LoadLockedReq miss latency 1610system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19297.618322 # average LoadLockedReq miss latency 1611system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27420.870168 # average StoreCondReq miss latency 1612system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27420.870168 # average StoreCondReq miss latency 1613system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1614system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1615system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23597.011161 # average overall miss latency 1616system.cpu1.dcache.demand_avg_miss_latency::total 23597.011161 # average overall miss latency 1617system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20939.221821 # average overall miss latency 1618system.cpu1.dcache.overall_avg_miss_latency::total 20939.221821 # average overall miss latency 1619system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1620system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1621system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1622system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1623system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1624system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1625system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1626system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1627system.cpu1.dcache.writebacks::writebacks 144073 # number of writebacks 1628system.cpu1.dcache.writebacks::total 144073 # number of writebacks 1629system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168 # number of ReadReq MSHR hits 1630system.cpu1.dcache.ReadReq_mshr_hits::total 168 # number of ReadReq MSHR hits 1631system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11530 # number of LoadLockedReq MSHR hits 1632system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11530 # number of LoadLockedReq MSHR hits 1633system.cpu1.dcache.demand_mshr_hits::cpu1.data 168 # number of demand (read+write) MSHR hits 1634system.cpu1.dcache.demand_mshr_hits::total 168 # number of demand (read+write) MSHR hits 1635system.cpu1.dcache.overall_mshr_hits::cpu1.data 168 # number of overall MSHR hits 1636system.cpu1.dcache.overall_mshr_hits::total 168 # number of overall MSHR hits 1637system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 110545 # number of ReadReq MSHR misses 1638system.cpu1.dcache.ReadReq_mshr_misses::total 110545 # number of ReadReq MSHR misses 1639system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 77621 # number of WriteReq MSHR misses 1640system.cpu1.dcache.WriteReq_mshr_misses::total 77621 # number of WriteReq MSHR misses 1641system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23508 # number of SoftPFReq MSHR misses 1642system.cpu1.dcache.SoftPFReq_mshr_misses::total 23508 # number of SoftPFReq MSHR misses 1643system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4887 # number of LoadLockedReq MSHR misses 1644system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4887 # number of LoadLockedReq MSHR misses 1645system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23076 # number of StoreCondReq MSHR misses 1646system.cpu1.dcache.StoreCondReq_mshr_misses::total 23076 # number of StoreCondReq MSHR misses 1647system.cpu1.dcache.demand_mshr_misses::cpu1.data 188166 # number of demand (read+write) MSHR misses 1648system.cpu1.dcache.demand_mshr_misses::total 188166 # number of demand (read+write) MSHR misses 1649system.cpu1.dcache.overall_mshr_misses::cpu1.data 211674 # number of overall MSHR misses 1650system.cpu1.dcache.overall_mshr_misses::total 211674 # number of overall MSHR misses 1651system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3107 # number of ReadReq MSHR uncacheable 1652system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3107 # number of ReadReq MSHR uncacheable 1653system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable 1654system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2430 # number of WriteReq MSHR uncacheable 1655system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5537 # number of overall MSHR uncacheable misses 1656system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5537 # number of overall MSHR uncacheable misses 1657system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1611627000 # number of ReadReq MSHR miss cycles 1658system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1611627000 # number of ReadReq MSHR miss cycles 1659system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2635907000 # number of WriteReq MSHR miss cycles 1660system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2635907000 # number of WriteReq MSHR miss cycles 1661system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 421753500 # number of SoftPFReq MSHR miss cycles 1662system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 421753500 # number of SoftPFReq MSHR miss cycles 1663system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88480500 # number of LoadLockedReq MSHR miss cycles 1664system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88480500 # number of LoadLockedReq MSHR miss cycles 1665system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 609718000 # number of StoreCondReq MSHR miss cycles 1666system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 609718000 # number of StoreCondReq MSHR miss cycles 1667system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3277000 # number of StoreCondFailReq MSHR miss cycles 1668system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3277000 # number of StoreCondFailReq MSHR miss cycles 1669system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4247534000 # number of demand (read+write) MSHR miss cycles 1670system.cpu1.dcache.demand_mshr_miss_latency::total 4247534000 # number of demand (read+write) MSHR miss cycles 1671system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4669287500 # number of overall MSHR miss cycles 1672system.cpu1.dcache.overall_mshr_miss_latency::total 4669287500 # number of overall MSHR miss cycles 1673system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 430617000 # number of ReadReq MSHR uncacheable cycles 1674system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 430617000 # number of ReadReq MSHR uncacheable cycles 1675system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 292641500 # number of WriteReq MSHR uncacheable cycles 1676system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 292641500 # number of WriteReq MSHR uncacheable cycles 1677system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 723258500 # number of overall MSHR uncacheable cycles 1678system.cpu1.dcache.overall_mshr_uncacheable_latency::total 723258500 # number of overall MSHR uncacheable cycles 1679system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035331 # mshr miss rate for ReadReq accesses 1680system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035331 # mshr miss rate for ReadReq accesses 1681system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028095 # mshr miss rate for WriteReq accesses 1682system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028095 # mshr miss rate for WriteReq accesses 1683system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360829 # mshr miss rate for SoftPFReq accesses 1684system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360829 # mshr miss rate for SoftPFReq accesses 1685system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056839 # mshr miss rate for LoadLockedReq accesses 1686system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056839 # mshr miss rate for LoadLockedReq accesses 1687system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.273873 # mshr miss rate for StoreCondReq accesses 1688system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273873 # mshr miss rate for StoreCondReq accesses 1689system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031937 # mshr miss rate for demand accesses 1690system.cpu1.dcache.demand_mshr_miss_rate::total 0.031937 # mshr miss rate for demand accesses 1691system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035535 # mshr miss rate for overall accesses 1692system.cpu1.dcache.overall_mshr_miss_rate::total 0.035535 # mshr miss rate for overall accesses 1693system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14578.922611 # average ReadReq mshr miss latency 1694system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14578.922611 # average ReadReq mshr miss latency 1695system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33958.683861 # average WriteReq mshr miss latency 1696system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 33958.683861 # average WriteReq mshr miss latency 1697system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17940.849923 # average SoftPFReq mshr miss latency 1698system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17940.849923 # average SoftPFReq mshr miss latency 1699system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18105.279312 # average LoadLockedReq mshr miss latency 1700system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18105.279312 # average LoadLockedReq mshr miss latency 1701system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26422.170220 # average StoreCondReq mshr miss latency 1702system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26422.170220 # average StoreCondReq mshr miss latency 1703system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1704system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1705system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22573.334184 # average overall mshr miss latency 1706system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22573.334184 # average overall mshr miss latency 1707system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22058.861740 # average overall mshr miss latency 1708system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22058.861740 # average overall mshr miss latency 1709system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 138595.751529 # average ReadReq mshr uncacheable latency 1710system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 138595.751529 # average ReadReq mshr uncacheable latency 1711system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 120428.600823 # average WriteReq mshr uncacheable latency 1712system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 120428.600823 # average WriteReq mshr uncacheable latency 1713system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 130622.810186 # average overall mshr uncacheable latency 1714system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 130622.810186 # average overall mshr uncacheable latency 1715system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1716system.cpu1.icache.tags.replacements 461792 # number of replacements 1717system.cpu1.icache.tags.tagsinuse 498.311266 # Cycle average of tags in use 1718system.cpu1.icache.tags.total_refs 13251136 # Total number of references to valid blocks. 1719system.cpu1.icache.tags.sampled_refs 462304 # Sample count of references to valid blocks. 1720system.cpu1.icache.tags.avg_refs 28.663252 # Average number of references to valid blocks. 1721system.cpu1.icache.tags.warmup_cycle 106195905000 # Cycle when the warmup percentage was hit. 1722system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.311266 # Average occupied blocks per requestor 1723system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973264 # Average percentage of cache occupancy 1724system.cpu1.icache.tags.occ_percent::total 0.973264 # Average percentage of cache occupancy 1725system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1726system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id 1727system.cpu1.icache.tags.age_task_id_blocks_1024::3 118 # Occupied blocks per task id 1728system.cpu1.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id 1729system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1730system.cpu1.icache.tags.tag_accesses 27889184 # Number of tag accesses 1731system.cpu1.icache.tags.data_accesses 27889184 # Number of data accesses 1732system.cpu1.icache.ReadReq_hits::cpu1.inst 13251136 # number of ReadReq hits 1733system.cpu1.icache.ReadReq_hits::total 13251136 # number of ReadReq hits 1734system.cpu1.icache.demand_hits::cpu1.inst 13251136 # number of demand (read+write) hits 1735system.cpu1.icache.demand_hits::total 13251136 # number of demand (read+write) hits 1736system.cpu1.icache.overall_hits::cpu1.inst 13251136 # number of overall hits 1737system.cpu1.icache.overall_hits::total 13251136 # number of overall hits 1738system.cpu1.icache.ReadReq_misses::cpu1.inst 462304 # number of ReadReq misses 1739system.cpu1.icache.ReadReq_misses::total 462304 # number of ReadReq misses 1740system.cpu1.icache.demand_misses::cpu1.inst 462304 # number of demand (read+write) misses 1741system.cpu1.icache.demand_misses::total 462304 # number of demand (read+write) misses 1742system.cpu1.icache.overall_misses::cpu1.inst 462304 # number of overall misses 1743system.cpu1.icache.overall_misses::total 462304 # number of overall misses 1744system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4149723500 # number of ReadReq miss cycles 1745system.cpu1.icache.ReadReq_miss_latency::total 4149723500 # number of ReadReq miss cycles 1746system.cpu1.icache.demand_miss_latency::cpu1.inst 4149723500 # number of demand (read+write) miss cycles 1747system.cpu1.icache.demand_miss_latency::total 4149723500 # number of demand (read+write) miss cycles 1748system.cpu1.icache.overall_miss_latency::cpu1.inst 4149723500 # number of overall miss cycles 1749system.cpu1.icache.overall_miss_latency::total 4149723500 # number of overall miss cycles 1750system.cpu1.icache.ReadReq_accesses::cpu1.inst 13713440 # number of ReadReq accesses(hits+misses) 1751system.cpu1.icache.ReadReq_accesses::total 13713440 # number of ReadReq accesses(hits+misses) 1752system.cpu1.icache.demand_accesses::cpu1.inst 13713440 # number of demand (read+write) accesses 1753system.cpu1.icache.demand_accesses::total 13713440 # number of demand (read+write) accesses 1754system.cpu1.icache.overall_accesses::cpu1.inst 13713440 # number of overall (read+write) accesses 1755system.cpu1.icache.overall_accesses::total 13713440 # number of overall (read+write) accesses 1756system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033712 # miss rate for ReadReq accesses 1757system.cpu1.icache.ReadReq_miss_rate::total 0.033712 # miss rate for ReadReq accesses 1758system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033712 # miss rate for demand accesses 1759system.cpu1.icache.demand_miss_rate::total 0.033712 # miss rate for demand accesses 1760system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033712 # miss rate for overall accesses 1761system.cpu1.icache.overall_miss_rate::total 0.033712 # miss rate for overall accesses 1762system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8976.179094 # average ReadReq miss latency 1763system.cpu1.icache.ReadReq_avg_miss_latency::total 8976.179094 # average ReadReq miss latency 1764system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8976.179094 # average overall miss latency 1765system.cpu1.icache.demand_avg_miss_latency::total 8976.179094 # average overall miss latency 1766system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8976.179094 # average overall miss latency 1767system.cpu1.icache.overall_avg_miss_latency::total 8976.179094 # average overall miss latency 1768system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1769system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1770system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1771system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1772system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1773system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1774system.cpu1.icache.fast_writes 0 # number of fast writes performed 1775system.cpu1.icache.cache_copies 0 # number of cache copies performed 1776system.cpu1.icache.writebacks::writebacks 461792 # number of writebacks 1777system.cpu1.icache.writebacks::total 461792 # number of writebacks 1778system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 462304 # number of ReadReq MSHR misses 1779system.cpu1.icache.ReadReq_mshr_misses::total 462304 # number of ReadReq MSHR misses 1780system.cpu1.icache.demand_mshr_misses::cpu1.inst 462304 # number of demand (read+write) MSHR misses 1781system.cpu1.icache.demand_mshr_misses::total 462304 # number of demand (read+write) MSHR misses 1782system.cpu1.icache.overall_mshr_misses::cpu1.inst 462304 # number of overall MSHR misses 1783system.cpu1.icache.overall_mshr_misses::total 462304 # number of overall MSHR misses 1784system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 1785system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable 1786system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 1787system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses 1788system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3918571500 # number of ReadReq MSHR miss cycles 1789system.cpu1.icache.ReadReq_mshr_miss_latency::total 3918571500 # number of ReadReq MSHR miss cycles 1790system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3918571500 # number of demand (read+write) MSHR miss cycles 1791system.cpu1.icache.demand_mshr_miss_latency::total 3918571500 # number of demand (read+write) MSHR miss cycles 1792system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3918571500 # number of overall MSHR miss cycles 1793system.cpu1.icache.overall_mshr_miss_latency::total 3918571500 # number of overall MSHR miss cycles 1794system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 23546500 # number of ReadReq MSHR uncacheable cycles 1795system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 23546500 # number of ReadReq MSHR uncacheable cycles 1796system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 23546500 # number of overall MSHR uncacheable cycles 1797system.cpu1.icache.overall_mshr_uncacheable_latency::total 23546500 # number of overall MSHR uncacheable cycles 1798system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for ReadReq accesses 1799system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.033712 # mshr miss rate for ReadReq accesses 1800system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for demand accesses 1801system.cpu1.icache.demand_mshr_miss_rate::total 0.033712 # mshr miss rate for demand accesses 1802system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.033712 # mshr miss rate for overall accesses 1803system.cpu1.icache.overall_mshr_miss_rate::total 0.033712 # mshr miss rate for overall accesses 1804system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average ReadReq mshr miss latency 1805system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8476.179094 # average ReadReq mshr miss latency 1806system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency 1807system.cpu1.icache.demand_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency 1808system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8476.179094 # average overall mshr miss latency 1809system.cpu1.icache.overall_avg_mshr_miss_latency::total 8476.179094 # average overall mshr miss latency 1810system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average ReadReq mshr uncacheable latency 1811system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 133031.073446 # average ReadReq mshr uncacheable latency 1812system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 133031.073446 # average overall mshr uncacheable latency 1813system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 133031.073446 # average overall mshr uncacheable latency 1814system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1815system.cpu1.l2cache.prefetcher.num_hwpf_issued 106104 # number of hwpf issued 1816system.cpu1.l2cache.prefetcher.pfIdentified 106112 # number of prefetch candidates identified 1817system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue 1818system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1819system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1820system.cpu1.l2cache.prefetcher.pfSpanPage 50448 # number of prefetches not generated due to page crossing 1821system.cpu1.l2cache.tags.replacements 30131 # number of replacements 1822system.cpu1.l2cache.tags.tagsinuse 14949.290291 # Cycle average of tags in use 1823system.cpu1.l2cache.tags.total_refs 1034569 # Total number of references to valid blocks. 1824system.cpu1.l2cache.tags.sampled_refs 45193 # Sample count of references to valid blocks. 1825system.cpu1.l2cache.tags.avg_refs 22.892240 # Average number of references to valid blocks. 1826system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1827system.cpu1.l2cache.tags.occ_blocks::writebacks 14514.476865 # Average occupied blocks per requestor 1828system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.312401 # Average occupied blocks per requestor 1829system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.041451 # Average occupied blocks per requestor 1830system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 430.459574 # Average occupied blocks per requestor 1831system.cpu1.l2cache.tags.occ_percent::writebacks 0.885893 # Average percentage of cache occupancy 1832system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000141 # Average percentage of cache occupancy 1833system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000125 # Average percentage of cache occupancy 1834system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.026273 # Average percentage of cache occupancy 1835system.cpu1.l2cache.tags.occ_percent::total 0.912432 # Average percentage of cache occupancy 1836system.cpu1.l2cache.tags.occ_task_id_blocks::1022 971 # Occupied blocks per task id 1837system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id 1838system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14059 # Occupied blocks per task id 1839system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id 1840system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 54 # Occupied blocks per task id 1841system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 913 # Occupied blocks per task id 1842system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id 1843system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id 1844system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 390 # Occupied blocks per task id 1845system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1365 # Occupied blocks per task id 1846system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12304 # Occupied blocks per task id 1847system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059265 # Percentage of cache occupancy per task id 1848system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id 1849system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.858093 # Percentage of cache occupancy per task id 1850system.cpu1.l2cache.tags.tag_accesses 20957142 # Number of tag accesses 1851system.cpu1.l2cache.tags.data_accesses 20957142 # Number of data accesses 1852system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2443 # number of ReadReq hits 1853system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1453 # number of ReadReq hits 1854system.cpu1.l2cache.ReadReq_hits::total 3896 # number of ReadReq hits 1855system.cpu1.l2cache.WritebackDirty_hits::writebacks 89055 # number of WritebackDirty hits 1856system.cpu1.l2cache.WritebackDirty_hits::total 89055 # number of WritebackDirty hits 1857system.cpu1.l2cache.WritebackClean_hits::writebacks 506752 # number of WritebackClean hits 1858system.cpu1.l2cache.WritebackClean_hits::total 506752 # number of WritebackClean hits 1859system.cpu1.l2cache.ReadExReq_hits::cpu1.data 16650 # number of ReadExReq hits 1860system.cpu1.l2cache.ReadExReq_hits::total 16650 # number of ReadExReq hits 1861system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 453968 # number of ReadCleanReq hits 1862system.cpu1.l2cache.ReadCleanReq_hits::total 453968 # number of ReadCleanReq hits 1863system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 75407 # number of ReadSharedReq hits 1864system.cpu1.l2cache.ReadSharedReq_hits::total 75407 # number of ReadSharedReq hits 1865system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2443 # number of demand (read+write) hits 1866system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1453 # number of demand (read+write) hits 1867system.cpu1.l2cache.demand_hits::cpu1.inst 453968 # number of demand (read+write) hits 1868system.cpu1.l2cache.demand_hits::cpu1.data 92057 # number of demand (read+write) hits 1869system.cpu1.l2cache.demand_hits::total 549921 # number of demand (read+write) hits 1870system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2443 # number of overall hits 1871system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1453 # number of overall hits 1872system.cpu1.l2cache.overall_hits::cpu1.inst 453968 # number of overall hits 1873system.cpu1.l2cache.overall_hits::cpu1.data 92057 # number of overall hits 1874system.cpu1.l2cache.overall_hits::total 549921 # number of overall hits 1875system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 349 # number of ReadReq misses 1876system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 301 # number of ReadReq misses 1877system.cpu1.l2cache.ReadReq_misses::total 650 # number of ReadReq misses 1878system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28928 # number of UpgradeReq misses 1879system.cpu1.l2cache.UpgradeReq_misses::total 28928 # number of UpgradeReq misses 1880system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23076 # number of SCUpgradeReq misses 1881system.cpu1.l2cache.SCUpgradeReq_misses::total 23076 # number of SCUpgradeReq misses 1882system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32043 # number of ReadExReq misses 1883system.cpu1.l2cache.ReadExReq_misses::total 32043 # number of ReadExReq misses 1884system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 8336 # number of ReadCleanReq misses 1885system.cpu1.l2cache.ReadCleanReq_misses::total 8336 # number of ReadCleanReq misses 1886system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 63533 # number of ReadSharedReq misses 1887system.cpu1.l2cache.ReadSharedReq_misses::total 63533 # number of ReadSharedReq misses 1888system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 349 # number of demand (read+write) misses 1889system.cpu1.l2cache.demand_misses::cpu1.itb.walker 301 # number of demand (read+write) misses 1890system.cpu1.l2cache.demand_misses::cpu1.inst 8336 # number of demand (read+write) misses 1891system.cpu1.l2cache.demand_misses::cpu1.data 95576 # number of demand (read+write) misses 1892system.cpu1.l2cache.demand_misses::total 104562 # number of demand (read+write) misses 1893system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 349 # number of overall misses 1894system.cpu1.l2cache.overall_misses::cpu1.itb.walker 301 # number of overall misses 1895system.cpu1.l2cache.overall_misses::cpu1.inst 8336 # number of overall misses 1896system.cpu1.l2cache.overall_misses::cpu1.data 95576 # number of overall misses 1897system.cpu1.l2cache.overall_misses::total 104562 # number of overall misses 1898system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 7078500 # number of ReadReq miss cycles 1899system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 6021500 # number of ReadReq miss cycles 1900system.cpu1.l2cache.ReadReq_miss_latency::total 13100000 # number of ReadReq miss cycles 1901system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 62132500 # number of UpgradeReq miss cycles 1902system.cpu1.l2cache.UpgradeReq_miss_latency::total 62132500 # number of UpgradeReq miss cycles 1903system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 59033500 # number of SCUpgradeReq miss cycles 1904system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 59033500 # number of SCUpgradeReq miss cycles 1905system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3231500 # number of SCUpgradeFailReq miss cycles 1906system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3231500 # number of SCUpgradeFailReq miss cycles 1907system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1646554500 # number of ReadExReq miss cycles 1908system.cpu1.l2cache.ReadExReq_miss_latency::total 1646554500 # number of ReadExReq miss cycles 1909system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 475139500 # number of ReadCleanReq miss cycles 1910system.cpu1.l2cache.ReadCleanReq_miss_latency::total 475139500 # number of ReadCleanReq miss cycles 1911system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1418811000 # number of ReadSharedReq miss cycles 1912system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1418811000 # number of ReadSharedReq miss cycles 1913system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 7078500 # number of demand (read+write) miss cycles 1914system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 6021500 # number of demand (read+write) miss cycles 1915system.cpu1.l2cache.demand_miss_latency::cpu1.inst 475139500 # number of demand (read+write) miss cycles 1916system.cpu1.l2cache.demand_miss_latency::cpu1.data 3065365500 # number of demand (read+write) miss cycles 1917system.cpu1.l2cache.demand_miss_latency::total 3553605000 # number of demand (read+write) miss cycles 1918system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 7078500 # number of overall miss cycles 1919system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 6021500 # number of overall miss cycles 1920system.cpu1.l2cache.overall_miss_latency::cpu1.inst 475139500 # number of overall miss cycles 1921system.cpu1.l2cache.overall_miss_latency::cpu1.data 3065365500 # number of overall miss cycles 1922system.cpu1.l2cache.overall_miss_latency::total 3553605000 # number of overall miss cycles 1923system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 2792 # number of ReadReq accesses(hits+misses) 1924system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1754 # number of ReadReq accesses(hits+misses) 1925system.cpu1.l2cache.ReadReq_accesses::total 4546 # number of ReadReq accesses(hits+misses) 1926system.cpu1.l2cache.WritebackDirty_accesses::writebacks 89055 # number of WritebackDirty accesses(hits+misses) 1927system.cpu1.l2cache.WritebackDirty_accesses::total 89055 # number of WritebackDirty accesses(hits+misses) 1928system.cpu1.l2cache.WritebackClean_accesses::writebacks 506752 # number of WritebackClean accesses(hits+misses) 1929system.cpu1.l2cache.WritebackClean_accesses::total 506752 # number of WritebackClean accesses(hits+misses) 1930system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28928 # number of UpgradeReq accesses(hits+misses) 1931system.cpu1.l2cache.UpgradeReq_accesses::total 28928 # number of UpgradeReq accesses(hits+misses) 1932system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23076 # number of SCUpgradeReq accesses(hits+misses) 1933system.cpu1.l2cache.SCUpgradeReq_accesses::total 23076 # number of SCUpgradeReq accesses(hits+misses) 1934system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 48693 # number of ReadExReq accesses(hits+misses) 1935system.cpu1.l2cache.ReadExReq_accesses::total 48693 # number of ReadExReq accesses(hits+misses) 1936system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 462304 # number of ReadCleanReq accesses(hits+misses) 1937system.cpu1.l2cache.ReadCleanReq_accesses::total 462304 # number of ReadCleanReq accesses(hits+misses) 1938system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 138940 # number of ReadSharedReq accesses(hits+misses) 1939system.cpu1.l2cache.ReadSharedReq_accesses::total 138940 # number of ReadSharedReq accesses(hits+misses) 1940system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 2792 # number of demand (read+write) accesses 1941system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1754 # number of demand (read+write) accesses 1942system.cpu1.l2cache.demand_accesses::cpu1.inst 462304 # number of demand (read+write) accesses 1943system.cpu1.l2cache.demand_accesses::cpu1.data 187633 # number of demand (read+write) accesses 1944system.cpu1.l2cache.demand_accesses::total 654483 # number of demand (read+write) accesses 1945system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 2792 # number of overall (read+write) accesses 1946system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1754 # number of overall (read+write) accesses 1947system.cpu1.l2cache.overall_accesses::cpu1.inst 462304 # number of overall (read+write) accesses 1948system.cpu1.l2cache.overall_accesses::cpu1.data 187633 # number of overall (read+write) accesses 1949system.cpu1.l2cache.overall_accesses::total 654483 # number of overall (read+write) accesses 1950system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for ReadReq accesses 1951system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.171608 # miss rate for ReadReq accesses 1952system.cpu1.l2cache.ReadReq_miss_rate::total 0.142983 # miss rate for ReadReq accesses 1953system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 1954system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1955system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1956system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1957system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.658062 # miss rate for ReadExReq accesses 1958system.cpu1.l2cache.ReadExReq_miss_rate::total 0.658062 # miss rate for ReadExReq accesses 1959system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.018031 # miss rate for ReadCleanReq accesses 1960system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.018031 # miss rate for ReadCleanReq accesses 1961system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.457269 # miss rate for ReadSharedReq accesses 1962system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.457269 # miss rate for ReadSharedReq accesses 1963system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for demand accesses 1964system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.171608 # miss rate for demand accesses 1965system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.018031 # miss rate for demand accesses 1966system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.509377 # miss rate for demand accesses 1967system.cpu1.l2cache.demand_miss_rate::total 0.159763 # miss rate for demand accesses 1968system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.125000 # miss rate for overall accesses 1969system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.171608 # miss rate for overall accesses 1970system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.018031 # miss rate for overall accesses 1971system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.509377 # miss rate for overall accesses 1972system.cpu1.l2cache.overall_miss_rate::total 0.159763 # miss rate for overall accesses 1973system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average ReadReq miss latency 1974system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20004.983389 # average ReadReq miss latency 1975system.cpu1.l2cache.ReadReq_avg_miss_latency::total 20153.846154 # average ReadReq miss latency 1976system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 2147.832550 # average UpgradeReq miss latency 1977system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 2147.832550 # average UpgradeReq miss latency 1978system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 2558.220662 # average SCUpgradeReq miss latency 1979system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 2558.220662 # average SCUpgradeReq miss latency 1980system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency 1981system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency 1982system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51385.778485 # average ReadExReq miss latency 1983system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51385.778485 # average ReadExReq miss latency 1984system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 56998.500480 # average ReadCleanReq miss latency 1985system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 56998.500480 # average ReadCleanReq miss latency 1986system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 22331.874774 # average ReadSharedReq miss latency 1987system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 22331.874774 # average ReadSharedReq miss latency 1988system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average overall miss latency 1989system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20004.983389 # average overall miss latency 1990system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 56998.500480 # average overall miss latency 1991system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32072.544363 # average overall miss latency 1992system.cpu1.l2cache.demand_avg_miss_latency::total 33985.625753 # average overall miss latency 1993system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20282.234957 # average overall miss latency 1994system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20004.983389 # average overall miss latency 1995system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 56998.500480 # average overall miss latency 1996system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32072.544363 # average overall miss latency 1997system.cpu1.l2cache.overall_avg_miss_latency::total 33985.625753 # average overall miss latency 1998system.cpu1.l2cache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked 1999system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2000system.cpu1.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 2001system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2002system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 32 # average number of cycles each access was blocked 2003system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2004system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2005system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2006system.cpu1.l2cache.writebacks::writebacks 25259 # number of writebacks 2007system.cpu1.l2cache.writebacks::total 25259 # number of writebacks 2008system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 80 # number of ReadExReq MSHR hits 2009system.cpu1.l2cache.ReadExReq_mshr_hits::total 80 # number of ReadExReq MSHR hits 2010system.cpu1.l2cache.demand_mshr_hits::cpu1.data 80 # number of demand (read+write) MSHR hits 2011system.cpu1.l2cache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits 2012system.cpu1.l2cache.overall_mshr_hits::cpu1.data 80 # number of overall MSHR hits 2013system.cpu1.l2cache.overall_mshr_hits::total 80 # number of overall MSHR hits 2014system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 349 # number of ReadReq MSHR misses 2015system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 301 # number of ReadReq MSHR misses 2016system.cpu1.l2cache.ReadReq_mshr_misses::total 650 # number of ReadReq MSHR misses 2017system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 18771 # number of HardPFReq MSHR misses 2018system.cpu1.l2cache.HardPFReq_mshr_misses::total 18771 # number of HardPFReq MSHR misses 2019system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28928 # number of UpgradeReq MSHR misses 2020system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28928 # number of UpgradeReq MSHR misses 2021system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 23076 # number of SCUpgradeReq MSHR misses 2022system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 23076 # number of SCUpgradeReq MSHR misses 2023system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 31963 # number of ReadExReq MSHR misses 2024system.cpu1.l2cache.ReadExReq_mshr_misses::total 31963 # number of ReadExReq MSHR misses 2025system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 8336 # number of ReadCleanReq MSHR misses 2026system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 8336 # number of ReadCleanReq MSHR misses 2027system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 63533 # number of ReadSharedReq MSHR misses 2028system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 63533 # number of ReadSharedReq MSHR misses 2029system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 349 # number of demand (read+write) MSHR misses 2030system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 301 # number of demand (read+write) MSHR misses 2031system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 8336 # number of demand (read+write) MSHR misses 2032system.cpu1.l2cache.demand_mshr_misses::cpu1.data 95496 # number of demand (read+write) MSHR misses 2033system.cpu1.l2cache.demand_mshr_misses::total 104482 # number of demand (read+write) MSHR misses 2034system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 349 # number of overall MSHR misses 2035system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 301 # number of overall MSHR misses 2036system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 8336 # number of overall MSHR misses 2037system.cpu1.l2cache.overall_mshr_misses::cpu1.data 95496 # number of overall MSHR misses 2038system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 18771 # number of overall MSHR misses 2039system.cpu1.l2cache.overall_mshr_misses::total 123253 # number of overall MSHR misses 2040system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2041system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 3107 # number of ReadReq MSHR uncacheable 2042system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 3284 # number of ReadReq MSHR uncacheable 2043system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable 2044system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 2430 # number of WriteReq MSHR uncacheable 2045system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2046system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 5537 # number of overall MSHR uncacheable misses 2047system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 5714 # number of overall MSHR uncacheable misses 2048system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of ReadReq MSHR miss cycles 2049system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4215500 # number of ReadReq MSHR miss cycles 2050system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 9200000 # number of ReadReq MSHR miss cycles 2051system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 917123117 # number of HardPFReq MSHR miss cycles 2052system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 917123117 # number of HardPFReq MSHR miss cycles 2053system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 588451500 # number of UpgradeReq MSHR miss cycles 2054system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 588451500 # number of UpgradeReq MSHR miss cycles 2055system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 436537000 # number of SCUpgradeReq MSHR miss cycles 2056system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 436537000 # number of SCUpgradeReq MSHR miss cycles 2057system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3051500 # number of SCUpgradeFailReq MSHR miss cycles 2058system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3051500 # number of SCUpgradeFailReq MSHR miss cycles 2059system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1446140000 # number of ReadExReq MSHR miss cycles 2060system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1446140000 # number of ReadExReq MSHR miss cycles 2061system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 425123500 # number of ReadCleanReq MSHR miss cycles 2062system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 425123500 # number of ReadCleanReq MSHR miss cycles 2063system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1037613000 # number of ReadSharedReq MSHR miss cycles 2064system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1037613000 # number of ReadSharedReq MSHR miss cycles 2065system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of demand (read+write) MSHR miss cycles 2066system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4215500 # number of demand (read+write) MSHR miss cycles 2067system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 425123500 # number of demand (read+write) MSHR miss cycles 2068system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2483753000 # number of demand (read+write) MSHR miss cycles 2069system.cpu1.l2cache.demand_mshr_miss_latency::total 2918076500 # number of demand (read+write) MSHR miss cycles 2070system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4984500 # number of overall MSHR miss cycles 2071system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4215500 # number of overall MSHR miss cycles 2072system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 425123500 # number of overall MSHR miss cycles 2073system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2483753000 # number of overall MSHR miss cycles 2074system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 917123117 # number of overall MSHR miss cycles 2075system.cpu1.l2cache.overall_mshr_miss_latency::total 3835199617 # number of overall MSHR miss cycles 2076system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 22219000 # number of ReadReq MSHR uncacheable cycles 2077system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 405408000 # number of ReadReq MSHR uncacheable cycles 2078system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 427627000 # number of ReadReq MSHR uncacheable cycles 2079system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 274409000 # number of WriteReq MSHR uncacheable cycles 2080system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 274409000 # number of WriteReq MSHR uncacheable cycles 2081system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 22219000 # number of overall MSHR uncacheable cycles 2082system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 679817000 # number of overall MSHR uncacheable cycles 2083system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 702036000 # number of overall MSHR uncacheable cycles 2084system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadReq accesses 2085system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for ReadReq accesses 2086system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.142983 # mshr miss rate for ReadReq accesses 2087system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2088system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2089system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2090system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2091system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2092system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2093system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.656419 # mshr miss rate for ReadExReq accesses 2094system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.656419 # mshr miss rate for ReadExReq accesses 2095system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for ReadCleanReq accesses 2096system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.018031 # mshr miss rate for ReadCleanReq accesses 2097system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.457269 # mshr miss rate for ReadSharedReq accesses 2098system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.457269 # mshr miss rate for ReadSharedReq accesses 2099system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses 2100system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for demand accesses 2101system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for demand accesses 2102system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for demand accesses 2103system.cpu1.l2cache.demand_mshr_miss_rate::total 0.159641 # mshr miss rate for demand accesses 2104system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses 2105system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.171608 # mshr miss rate for overall accesses 2106system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.018031 # mshr miss rate for overall accesses 2107system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.508951 # mshr miss rate for overall accesses 2108system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2109system.cpu1.l2cache.overall_mshr_miss_rate::total 0.188321 # mshr miss rate for overall accesses 2110system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average ReadReq mshr miss latency 2111system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average ReadReq mshr miss latency 2112system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 14153.846154 # average ReadReq mshr miss latency 2113system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average HardPFReq mshr miss latency 2114system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48858.511374 # average HardPFReq mshr miss latency 2115system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20341.935149 # average UpgradeReq mshr miss latency 2116system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20341.935149 # average UpgradeReq mshr miss latency 2117system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18917.360028 # average SCUpgradeReq mshr miss latency 2118system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18917.360028 # average SCUpgradeReq mshr miss latency 2119system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency 2120system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency 2121system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45244.188593 # average ReadExReq mshr miss latency 2122system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45244.188593 # average ReadExReq mshr miss latency 2123system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average ReadCleanReq mshr miss latency 2124system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50998.500480 # average ReadCleanReq mshr miss latency 2125system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16331.874774 # average ReadSharedReq mshr miss latency 2126system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16331.874774 # average ReadSharedReq mshr miss latency 2127system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency 2128system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency 2129system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency 2130system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency 2131system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27928.987768 # average overall mshr miss latency 2132system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14282.234957 # average overall mshr miss latency 2133system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14004.983389 # average overall mshr miss latency 2134system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 50998.500480 # average overall mshr miss latency 2135system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26008.974198 # average overall mshr miss latency 2136system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48858.511374 # average overall mshr miss latency 2137system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 31116.480873 # average overall mshr miss latency 2138system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average ReadReq mshr uncacheable latency 2139system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130482.137110 # average ReadReq mshr uncacheable latency 2140system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 130215.286236 # average ReadReq mshr uncacheable latency 2141system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112925.514403 # average WriteReq mshr uncacheable latency 2142system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 112925.514403 # average WriteReq mshr uncacheable latency 2143system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125531.073446 # average overall mshr uncacheable latency 2144system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 122777.135633 # average overall mshr uncacheable latency 2145system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 122862.443122 # average overall mshr uncacheable latency 2146system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2147system.cpu1.toL2Bus.snoop_filter.tot_requests 1312846 # Total number of requests made to the snoop filter. 2148system.cpu1.toL2Bus.snoop_filter.hit_single_requests 662941 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2149system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 10057 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2150system.cpu1.toL2Bus.snoop_filter.tot_snoops 166384 # Total number of snoops made to the snoop filter. 2151system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164278 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2152system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2106 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2153system.cpu1.toL2Bus.trans_dist::ReadReq 10119 # Transaction distribution 2154system.cpu1.toL2Bus.trans_dist::ReadResp 648543 # Transaction distribution 2155system.cpu1.toL2Bus.trans_dist::WriteReq 2430 # Transaction distribution 2156system.cpu1.toL2Bus.trans_dist::WriteResp 2430 # Transaction distribution 2157system.cpu1.toL2Bus.trans_dist::WritebackDirty 115438 # Transaction distribution 2158system.cpu1.toL2Bus.trans_dist::WritebackClean 506752 # Transaction distribution 2159system.cpu1.toL2Bus.trans_dist::CleanEvict 85166 # Transaction distribution 2160system.cpu1.toL2Bus.trans_dist::HardPFReq 22864 # Transaction distribution 2161system.cpu1.toL2Bus.trans_dist::UpgradeReq 70245 # Transaction distribution 2162system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 40855 # Transaction distribution 2163system.cpu1.toL2Bus.trans_dist::UpgradeResp 84598 # Transaction distribution 2164system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution 2165system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution 2166system.cpu1.toL2Bus.trans_dist::ReadExReq 55915 # Transaction distribution 2167system.cpu1.toL2Bus.trans_dist::ReadExResp 53326 # Transaction distribution 2168system.cpu1.toL2Bus.trans_dist::ReadCleanReq 462304 # Transaction distribution 2169system.cpu1.toL2Bus.trans_dist::ReadSharedReq 211564 # Transaction distribution 2170system.cpu1.toL2Bus.trans_dist::InvalidateReq 31 # Transaction distribution 2171system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1378500 # Packet count per connected master and slave (bytes) 2172system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707096 # Packet count per connected master and slave (bytes) 2173system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 4372 # Packet count per connected master and slave (bytes) 2174system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 7009 # Packet count per connected master and slave (bytes) 2175system.cpu1.toL2Bus.pkt_count::total 2096977 # Packet count per connected master and slave (bytes) 2176system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58614596 # Cumulative packet size per connected master and slave (bytes) 2177system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 23813135 # Cumulative packet size per connected master and slave (bytes) 2178system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7016 # Cumulative packet size per connected master and slave (bytes) 2179system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 11168 # Cumulative packet size per connected master and slave (bytes) 2180system.cpu1.toL2Bus.pkt_size::total 82445915 # Cumulative packet size per connected master and slave (bytes) 2181system.cpu1.toL2Bus.snoops 350196 # Total snoops (count) 2182system.cpu1.toL2Bus.snoop_fanout::samples 987919 # Request fanout histogram 2183system.cpu1.toL2Bus.snoop_fanout::mean 0.185835 # Request fanout histogram 2184system.cpu1.toL2Bus.snoop_fanout::stdev 0.394416 # Request fanout histogram 2185system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2186system.cpu1.toL2Bus.snoop_fanout::0 806435 81.63% 81.63% # Request fanout histogram 2187system.cpu1.toL2Bus.snoop_fanout::1 179378 18.16% 99.79% # Request fanout histogram 2188system.cpu1.toL2Bus.snoop_fanout::2 2106 0.21% 100.00% # Request fanout histogram 2189system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2190system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2191system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2192system.cpu1.toL2Bus.snoop_fanout::total 987919 # Request fanout histogram 2193system.cpu1.toL2Bus.reqLayer0.occupancy 1267256999 # Layer occupancy (ticks) 2194system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2195system.cpu1.toL2Bus.snoopLayer0.occupancy 79126203 # Layer occupancy (ticks) 2196system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2197system.cpu1.toL2Bus.respLayer0.occupancy 693633000 # Layer occupancy (ticks) 2198system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2199system.cpu1.toL2Bus.respLayer1.occupancy 311803500 # Layer occupancy (ticks) 2200system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2201system.cpu1.toL2Bus.respLayer2.occupancy 2618000 # Layer occupancy (ticks) 2202system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2203system.cpu1.toL2Bus.respLayer3.occupancy 4217000 # Layer occupancy (ticks) 2204system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2205system.iobus.trans_dist::ReadReq 31009 # Transaction distribution 2206system.iobus.trans_dist::ReadResp 31009 # Transaction distribution 2207system.iobus.trans_dist::WriteReq 59425 # Transaction distribution 2208system.iobus.trans_dist::WriteResp 59425 # Transaction distribution 2209system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) 2210system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 2211system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2212system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 2213system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 2214system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) 2215system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) 2216system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 2217system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2218system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2219system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2220system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 2221system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2222system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 2223system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 2224system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 2225system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 2226system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 2227system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 2228system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) 2229system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) 2230system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) 2231system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) 2232system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) 2233system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 2234system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 2235system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 2236system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 2237system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) 2238system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) 2239system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 2240system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2241system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2242system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2243system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 2244system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2245system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2246system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 2247system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 2248system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2249system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 2250system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 2251system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) 2252system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) 2253system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) 2254system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) 2255system.iobus.reqLayer0.occupancy 48738000 # Layer occupancy (ticks) 2256system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2257system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) 2258system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2259system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) 2260system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2261system.iobus.reqLayer3.occupancy 32500 # Layer occupancy (ticks) 2262system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2263system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) 2264system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2265system.iobus.reqLayer7.occupancy 93500 # Layer occupancy (ticks) 2266system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 2267system.iobus.reqLayer8.occupancy 610000 # Layer occupancy (ticks) 2268system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 2269system.iobus.reqLayer10.occupancy 23500 # Layer occupancy (ticks) 2270system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2271system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) 2272system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2273system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 2274system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2275system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) 2276system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2277system.iobus.reqLayer16.occupancy 48500 # Layer occupancy (ticks) 2278system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2279system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) 2280system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2281system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) 2282system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 2283system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) 2284system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 2285system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) 2286system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 2287system.iobus.reqLayer21.occupancy 12000 # Layer occupancy (ticks) 2288system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) 2289system.iobus.reqLayer23.occupancy 6150500 # Layer occupancy (ticks) 2290system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2291system.iobus.reqLayer24.occupancy 32045500 # Layer occupancy (ticks) 2292system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2293system.iobus.reqLayer25.occupancy 186301036 # Layer occupancy (ticks) 2294system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2295system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) 2296system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2297system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) 2298system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2299system.iocache.tags.replacements 36433 # number of replacements 2300system.iocache.tags.tagsinuse 1.018273 # Cycle average of tags in use 2301system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 2302system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. 2303system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 2304system.iocache.tags.warmup_cycle 290654223000 # Cycle when the warmup percentage was hit. 2305system.iocache.tags.occ_blocks::realview.ide 1.018273 # Average occupied blocks per requestor 2306system.iocache.tags.occ_percent::realview.ide 0.063642 # Average percentage of cache occupancy 2307system.iocache.tags.occ_percent::total 0.063642 # Average percentage of cache occupancy 2308system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2309system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2310system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2311system.iocache.tags.tag_accesses 328203 # Number of tag accesses 2312system.iocache.tags.data_accesses 328203 # Number of data accesses 2313system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses 2314system.iocache.ReadReq_misses::total 243 # number of ReadReq misses 2315system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 2316system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 2317system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses 2318system.iocache.demand_misses::total 243 # number of demand (read+write) misses 2319system.iocache.overall_misses::realview.ide 243 # number of overall misses 2320system.iocache.overall_misses::total 243 # number of overall misses 2321system.iocache.ReadReq_miss_latency::realview.ide 31405376 # number of ReadReq miss cycles 2322system.iocache.ReadReq_miss_latency::total 31405376 # number of ReadReq miss cycles 2323system.iocache.WriteLineReq_miss_latency::realview.ide 4738596660 # number of WriteLineReq miss cycles 2324system.iocache.WriteLineReq_miss_latency::total 4738596660 # number of WriteLineReq miss cycles 2325system.iocache.demand_miss_latency::realview.ide 31405376 # number of demand (read+write) miss cycles 2326system.iocache.demand_miss_latency::total 31405376 # number of demand (read+write) miss cycles 2327system.iocache.overall_miss_latency::realview.ide 31405376 # number of overall miss cycles 2328system.iocache.overall_miss_latency::total 31405376 # number of overall miss cycles 2329system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) 2330system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) 2331system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 2332system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 2333system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses 2334system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses 2335system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses 2336system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses 2337system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2338system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2339system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2340system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2341system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2342system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2343system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2344system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2345system.iocache.ReadReq_avg_miss_latency::realview.ide 129240.230453 # average ReadReq miss latency 2346system.iocache.ReadReq_avg_miss_latency::total 129240.230453 # average ReadReq miss latency 2347system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130813.732884 # average WriteLineReq miss latency 2348system.iocache.WriteLineReq_avg_miss_latency::total 130813.732884 # average WriteLineReq miss latency 2349system.iocache.demand_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency 2350system.iocache.demand_avg_miss_latency::total 129240.230453 # average overall miss latency 2351system.iocache.overall_avg_miss_latency::realview.ide 129240.230453 # average overall miss latency 2352system.iocache.overall_avg_miss_latency::total 129240.230453 # average overall miss latency 2353system.iocache.blocked_cycles::no_mshrs 816 # number of cycles access was blocked 2354system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2355system.iocache.blocked::no_mshrs 79 # number of cycles access was blocked 2356system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2357system.iocache.avg_blocked_cycles::no_mshrs 10.329114 # average number of cycles each access was blocked 2358system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2359system.iocache.fast_writes 0 # number of fast writes performed 2360system.iocache.cache_copies 0 # number of cache copies performed 2361system.iocache.writebacks::writebacks 36190 # number of writebacks 2362system.iocache.writebacks::total 36190 # number of writebacks 2363system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses 2364system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses 2365system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses 2366system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses 2367system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses 2368system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses 2369system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses 2370system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses 2371system.iocache.ReadReq_mshr_miss_latency::realview.ide 19255376 # number of ReadReq MSHR miss cycles 2372system.iocache.ReadReq_mshr_miss_latency::total 19255376 # number of ReadReq MSHR miss cycles 2373system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2927396660 # number of WriteLineReq MSHR miss cycles 2374system.iocache.WriteLineReq_mshr_miss_latency::total 2927396660 # number of WriteLineReq MSHR miss cycles 2375system.iocache.demand_mshr_miss_latency::realview.ide 19255376 # number of demand (read+write) MSHR miss cycles 2376system.iocache.demand_mshr_miss_latency::total 19255376 # number of demand (read+write) MSHR miss cycles 2377system.iocache.overall_mshr_miss_latency::realview.ide 19255376 # number of overall MSHR miss cycles 2378system.iocache.overall_mshr_miss_latency::total 19255376 # number of overall MSHR miss cycles 2379system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2380system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2381system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2382system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2383system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2384system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2385system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2386system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2387system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79240.230453 # average ReadReq mshr miss latency 2388system.iocache.ReadReq_avg_mshr_miss_latency::total 79240.230453 # average ReadReq mshr miss latency 2389system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80813.732884 # average WriteLineReq mshr miss latency 2390system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80813.732884 # average WriteLineReq mshr miss latency 2391system.iocache.demand_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency 2392system.iocache.demand_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency 2393system.iocache.overall_avg_mshr_miss_latency::realview.ide 79240.230453 # average overall mshr miss latency 2394system.iocache.overall_avg_mshr_miss_latency::total 79240.230453 # average overall mshr miss latency 2395system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2396system.l2c.tags.replacements 123618 # number of replacements 2397system.l2c.tags.tagsinuse 63093.840837 # Cycle average of tags in use 2398system.l2c.tags.total_refs 421259 # Total number of references to valid blocks. 2399system.l2c.tags.sampled_refs 187589 # Sample count of references to valid blocks. 2400system.l2c.tags.avg_refs 2.245649 # Average number of references to valid blocks. 2401system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2402system.l2c.tags.occ_blocks::writebacks 13244.114990 # Average occupied blocks per requestor 2403system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.878668 # Average occupied blocks per requestor 2404system.l2c.tags.occ_blocks::cpu0.itb.walker 0.996497 # Average occupied blocks per requestor 2405system.l2c.tags.occ_blocks::cpu0.inst 7731.277102 # Average occupied blocks per requestor 2406system.l2c.tags.occ_blocks::cpu0.data 2849.874177 # Average occupied blocks per requestor 2407system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36272.088123 # Average occupied blocks per requestor 2408system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.954483 # Average occupied blocks per requestor 2409system.l2c.tags.occ_blocks::cpu1.inst 1120.568935 # Average occupied blocks per requestor 2410system.l2c.tags.occ_blocks::cpu1.data 367.321258 # Average occupied blocks per requestor 2411system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1502.766604 # Average occupied blocks per requestor 2412system.l2c.tags.occ_percent::writebacks 0.202089 # Average percentage of cache occupancy 2413system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000059 # Average percentage of cache occupancy 2414system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy 2415system.l2c.tags.occ_percent::cpu0.inst 0.117970 # Average percentage of cache occupancy 2416system.l2c.tags.occ_percent::cpu0.data 0.043486 # Average percentage of cache occupancy 2417system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.553468 # Average percentage of cache occupancy 2418system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy 2419system.l2c.tags.occ_percent::cpu1.inst 0.017099 # Average percentage of cache occupancy 2420system.l2c.tags.occ_percent::cpu1.data 0.005605 # Average percentage of cache occupancy 2421system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022930 # Average percentage of cache occupancy 2422system.l2c.tags.occ_percent::total 0.962736 # Average percentage of cache occupancy 2423system.l2c.tags.occ_task_id_blocks::1022 32107 # Occupied blocks per task id 2424system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 2425system.l2c.tags.occ_task_id_blocks::1024 31859 # Occupied blocks per task id 2426system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 2427system.l2c.tags.age_task_id_blocks_1022::2 131 # Occupied blocks per task id 2428system.l2c.tags.age_task_id_blocks_1022::3 4716 # Occupied blocks per task id 2429system.l2c.tags.age_task_id_blocks_1022::4 27259 # Occupied blocks per task id 2430system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 2431system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id 2432system.l2c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 2433system.l2c.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id 2434system.l2c.tags.age_task_id_blocks_1024::3 2381 # Occupied blocks per task id 2435system.l2c.tags.age_task_id_blocks_1024::4 29068 # Occupied blocks per task id 2436system.l2c.tags.occ_task_id_percent::1022 0.489914 # Percentage of cache occupancy per task id 2437system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 2438system.l2c.tags.occ_task_id_percent::1024 0.486130 # Percentage of cache occupancy per task id 2439system.l2c.tags.tag_accesses 5836461 # Number of tag accesses 2440system.l2c.tags.data_accesses 5836461 # Number of data accesses 2441system.l2c.WritebackDirty_hits::writebacks 257531 # number of WritebackDirty hits 2442system.l2c.WritebackDirty_hits::total 257531 # number of WritebackDirty hits 2443system.l2c.UpgradeReq_hits::cpu0.data 32441 # number of UpgradeReq hits 2444system.l2c.UpgradeReq_hits::cpu1.data 1723 # number of UpgradeReq hits 2445system.l2c.UpgradeReq_hits::total 34164 # number of UpgradeReq hits 2446system.l2c.SCUpgradeReq_hits::cpu0.data 2115 # number of SCUpgradeReq hits 2447system.l2c.SCUpgradeReq_hits::cpu1.data 899 # number of SCUpgradeReq hits 2448system.l2c.SCUpgradeReq_hits::total 3014 # number of SCUpgradeReq hits 2449system.l2c.ReadExReq_hits::cpu0.data 4177 # number of ReadExReq hits 2450system.l2c.ReadExReq_hits::cpu1.data 1342 # number of ReadExReq hits 2451system.l2c.ReadExReq_hits::total 5519 # number of ReadExReq hits 2452system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 81 # number of ReadSharedReq hits 2453system.l2c.ReadSharedReq_hits::cpu0.itb.walker 92 # number of ReadSharedReq hits 2454system.l2c.ReadSharedReq_hits::cpu0.inst 28642 # number of ReadSharedReq hits 2455system.l2c.ReadSharedReq_hits::cpu0.data 47295 # number of ReadSharedReq hits 2456system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47544 # number of ReadSharedReq hits 2457system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 15 # number of ReadSharedReq hits 2458system.l2c.ReadSharedReq_hits::cpu1.itb.walker 18 # number of ReadSharedReq hits 2459system.l2c.ReadSharedReq_hits::cpu1.inst 6315 # number of ReadSharedReq hits 2460system.l2c.ReadSharedReq_hits::cpu1.data 4707 # number of ReadSharedReq hits 2461system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3005 # number of ReadSharedReq hits 2462system.l2c.ReadSharedReq_hits::total 137714 # number of ReadSharedReq hits 2463system.l2c.demand_hits::cpu0.dtb.walker 81 # number of demand (read+write) hits 2464system.l2c.demand_hits::cpu0.itb.walker 92 # number of demand (read+write) hits 2465system.l2c.demand_hits::cpu0.inst 28642 # number of demand (read+write) hits 2466system.l2c.demand_hits::cpu0.data 51472 # number of demand (read+write) hits 2467system.l2c.demand_hits::cpu0.l2cache.prefetcher 47544 # number of demand (read+write) hits 2468system.l2c.demand_hits::cpu1.dtb.walker 15 # number of demand (read+write) hits 2469system.l2c.demand_hits::cpu1.itb.walker 18 # number of demand (read+write) hits 2470system.l2c.demand_hits::cpu1.inst 6315 # number of demand (read+write) hits 2471system.l2c.demand_hits::cpu1.data 6049 # number of demand (read+write) hits 2472system.l2c.demand_hits::cpu1.l2cache.prefetcher 3005 # number of demand (read+write) hits 2473system.l2c.demand_hits::total 143233 # number of demand (read+write) hits 2474system.l2c.overall_hits::cpu0.dtb.walker 81 # number of overall hits 2475system.l2c.overall_hits::cpu0.itb.walker 92 # number of overall hits 2476system.l2c.overall_hits::cpu0.inst 28642 # number of overall hits 2477system.l2c.overall_hits::cpu0.data 51472 # number of overall hits 2478system.l2c.overall_hits::cpu0.l2cache.prefetcher 47544 # number of overall hits 2479system.l2c.overall_hits::cpu1.dtb.walker 15 # number of overall hits 2480system.l2c.overall_hits::cpu1.itb.walker 18 # number of overall hits 2481system.l2c.overall_hits::cpu1.inst 6315 # number of overall hits 2482system.l2c.overall_hits::cpu1.data 6049 # number of overall hits 2483system.l2c.overall_hits::cpu1.l2cache.prefetcher 3005 # number of overall hits 2484system.l2c.overall_hits::total 143233 # number of overall hits 2485system.l2c.UpgradeReq_misses::cpu0.data 9610 # number of UpgradeReq misses 2486system.l2c.UpgradeReq_misses::cpu1.data 2300 # number of UpgradeReq misses 2487system.l2c.UpgradeReq_misses::total 11910 # number of UpgradeReq misses 2488system.l2c.SCUpgradeReq_misses::cpu0.data 655 # number of SCUpgradeReq misses 2489system.l2c.SCUpgradeReq_misses::cpu1.data 1322 # number of SCUpgradeReq misses 2490system.l2c.SCUpgradeReq_misses::total 1977 # number of SCUpgradeReq misses 2491system.l2c.ReadExReq_misses::cpu0.data 11124 # number of ReadExReq misses 2492system.l2c.ReadExReq_misses::cpu1.data 7851 # number of ReadExReq misses 2493system.l2c.ReadExReq_misses::total 18975 # number of ReadExReq misses 2494system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 6 # number of ReadSharedReq misses 2495system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 2496system.l2c.ReadSharedReq_misses::cpu0.inst 17856 # number of ReadSharedReq misses 2497system.l2c.ReadSharedReq_misses::cpu0.data 8887 # number of ReadSharedReq misses 2498system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 134682 # number of ReadSharedReq misses 2499system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses 2500system.l2c.ReadSharedReq_misses::cpu1.inst 2021 # number of ReadSharedReq misses 2501system.l2c.ReadSharedReq_misses::cpu1.data 752 # number of ReadSharedReq misses 2502system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5338 # number of ReadSharedReq misses 2503system.l2c.ReadSharedReq_misses::total 169545 # number of ReadSharedReq misses 2504system.l2c.demand_misses::cpu0.dtb.walker 6 # number of demand (read+write) misses 2505system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 2506system.l2c.demand_misses::cpu0.inst 17856 # number of demand (read+write) misses 2507system.l2c.demand_misses::cpu0.data 20011 # number of demand (read+write) misses 2508system.l2c.demand_misses::cpu0.l2cache.prefetcher 134682 # number of demand (read+write) misses 2509system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses 2510system.l2c.demand_misses::cpu1.inst 2021 # number of demand (read+write) misses 2511system.l2c.demand_misses::cpu1.data 8603 # number of demand (read+write) misses 2512system.l2c.demand_misses::cpu1.l2cache.prefetcher 5338 # number of demand (read+write) misses 2513system.l2c.demand_misses::total 188520 # number of demand (read+write) misses 2514system.l2c.overall_misses::cpu0.dtb.walker 6 # number of overall misses 2515system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 2516system.l2c.overall_misses::cpu0.inst 17856 # number of overall misses 2517system.l2c.overall_misses::cpu0.data 20011 # number of overall misses 2518system.l2c.overall_misses::cpu0.l2cache.prefetcher 134682 # number of overall misses 2519system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses 2520system.l2c.overall_misses::cpu1.inst 2021 # number of overall misses 2521system.l2c.overall_misses::cpu1.data 8603 # number of overall misses 2522system.l2c.overall_misses::cpu1.l2cache.prefetcher 5338 # number of overall misses 2523system.l2c.overall_misses::total 188520 # number of overall misses 2524system.l2c.UpgradeReq_miss_latency::cpu0.data 34729000 # number of UpgradeReq miss cycles 2525system.l2c.UpgradeReq_miss_latency::cpu1.data 5015500 # number of UpgradeReq miss cycles 2526system.l2c.UpgradeReq_miss_latency::total 39744500 # number of UpgradeReq miss cycles 2527system.l2c.SCUpgradeReq_miss_latency::cpu0.data 3979500 # number of SCUpgradeReq miss cycles 2528system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2518000 # number of SCUpgradeReq miss cycles 2529system.l2c.SCUpgradeReq_miss_latency::total 6497500 # number of SCUpgradeReq miss cycles 2530system.l2c.ReadExReq_miss_latency::cpu0.data 1612676500 # number of ReadExReq miss cycles 2531system.l2c.ReadExReq_miss_latency::cpu1.data 1029832500 # number of ReadExReq miss cycles 2532system.l2c.ReadExReq_miss_latency::total 2642509000 # number of ReadExReq miss cycles 2533system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 823500 # number of ReadSharedReq miss cycles 2534system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 272000 # number of ReadSharedReq miss cycles 2535system.l2c.ReadSharedReq_miss_latency::cpu0.inst 2350559500 # number of ReadSharedReq miss cycles 2536system.l2c.ReadSharedReq_miss_latency::cpu0.data 1210448500 # number of ReadSharedReq miss cycles 2537system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of ReadSharedReq miss cycles 2538system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 132500 # number of ReadSharedReq miss cycles 2539system.l2c.ReadSharedReq_miss_latency::cpu1.inst 268405000 # number of ReadSharedReq miss cycles 2540system.l2c.ReadSharedReq_miss_latency::cpu1.data 104648000 # number of ReadSharedReq miss cycles 2541system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of ReadSharedReq miss cycles 2542system.l2c.ReadSharedReq_miss_latency::total 24352402389 # number of ReadSharedReq miss cycles 2543system.l2c.demand_miss_latency::cpu0.dtb.walker 823500 # number of demand (read+write) miss cycles 2544system.l2c.demand_miss_latency::cpu0.itb.walker 272000 # number of demand (read+write) miss cycles 2545system.l2c.demand_miss_latency::cpu0.inst 2350559500 # number of demand (read+write) miss cycles 2546system.l2c.demand_miss_latency::cpu0.data 2823125000 # number of demand (read+write) miss cycles 2547system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of demand (read+write) miss cycles 2548system.l2c.demand_miss_latency::cpu1.dtb.walker 132500 # number of demand (read+write) miss cycles 2549system.l2c.demand_miss_latency::cpu1.inst 268405000 # number of demand (read+write) miss cycles 2550system.l2c.demand_miss_latency::cpu1.data 1134480500 # number of demand (read+write) miss cycles 2551system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of demand (read+write) miss cycles 2552system.l2c.demand_miss_latency::total 26994911389 # number of demand (read+write) miss cycles 2553system.l2c.overall_miss_latency::cpu0.dtb.walker 823500 # number of overall miss cycles 2554system.l2c.overall_miss_latency::cpu0.itb.walker 272000 # number of overall miss cycles 2555system.l2c.overall_miss_latency::cpu0.inst 2350559500 # number of overall miss cycles 2556system.l2c.overall_miss_latency::cpu0.data 2823125000 # number of overall miss cycles 2557system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19570272761 # number of overall miss cycles 2558system.l2c.overall_miss_latency::cpu1.dtb.walker 132500 # number of overall miss cycles 2559system.l2c.overall_miss_latency::cpu1.inst 268405000 # number of overall miss cycles 2560system.l2c.overall_miss_latency::cpu1.data 1134480500 # number of overall miss cycles 2561system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 846840628 # number of overall miss cycles 2562system.l2c.overall_miss_latency::total 26994911389 # number of overall miss cycles 2563system.l2c.WritebackDirty_accesses::writebacks 257531 # number of WritebackDirty accesses(hits+misses) 2564system.l2c.WritebackDirty_accesses::total 257531 # number of WritebackDirty accesses(hits+misses) 2565system.l2c.UpgradeReq_accesses::cpu0.data 42051 # number of UpgradeReq accesses(hits+misses) 2566system.l2c.UpgradeReq_accesses::cpu1.data 4023 # number of UpgradeReq accesses(hits+misses) 2567system.l2c.UpgradeReq_accesses::total 46074 # number of UpgradeReq accesses(hits+misses) 2568system.l2c.SCUpgradeReq_accesses::cpu0.data 2770 # number of SCUpgradeReq accesses(hits+misses) 2569system.l2c.SCUpgradeReq_accesses::cpu1.data 2221 # number of SCUpgradeReq accesses(hits+misses) 2570system.l2c.SCUpgradeReq_accesses::total 4991 # number of SCUpgradeReq accesses(hits+misses) 2571system.l2c.ReadExReq_accesses::cpu0.data 15301 # number of ReadExReq accesses(hits+misses) 2572system.l2c.ReadExReq_accesses::cpu1.data 9193 # number of ReadExReq accesses(hits+misses) 2573system.l2c.ReadExReq_accesses::total 24494 # number of ReadExReq accesses(hits+misses) 2574system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 87 # number of ReadSharedReq accesses(hits+misses) 2575system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 94 # number of ReadSharedReq accesses(hits+misses) 2576system.l2c.ReadSharedReq_accesses::cpu0.inst 46498 # number of ReadSharedReq accesses(hits+misses) 2577system.l2c.ReadSharedReq_accesses::cpu0.data 56182 # number of ReadSharedReq accesses(hits+misses) 2578system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 182226 # number of ReadSharedReq accesses(hits+misses) 2579system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 16 # number of ReadSharedReq accesses(hits+misses) 2580system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 18 # number of ReadSharedReq accesses(hits+misses) 2581system.l2c.ReadSharedReq_accesses::cpu1.inst 8336 # number of ReadSharedReq accesses(hits+misses) 2582system.l2c.ReadSharedReq_accesses::cpu1.data 5459 # number of ReadSharedReq accesses(hits+misses) 2583system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 8343 # number of ReadSharedReq accesses(hits+misses) 2584system.l2c.ReadSharedReq_accesses::total 307259 # number of ReadSharedReq accesses(hits+misses) 2585system.l2c.demand_accesses::cpu0.dtb.walker 87 # number of demand (read+write) accesses 2586system.l2c.demand_accesses::cpu0.itb.walker 94 # number of demand (read+write) accesses 2587system.l2c.demand_accesses::cpu0.inst 46498 # number of demand (read+write) accesses 2588system.l2c.demand_accesses::cpu0.data 71483 # number of demand (read+write) accesses 2589system.l2c.demand_accesses::cpu0.l2cache.prefetcher 182226 # number of demand (read+write) accesses 2590system.l2c.demand_accesses::cpu1.dtb.walker 16 # number of demand (read+write) accesses 2591system.l2c.demand_accesses::cpu1.itb.walker 18 # number of demand (read+write) accesses 2592system.l2c.demand_accesses::cpu1.inst 8336 # number of demand (read+write) accesses 2593system.l2c.demand_accesses::cpu1.data 14652 # number of demand (read+write) accesses 2594system.l2c.demand_accesses::cpu1.l2cache.prefetcher 8343 # number of demand (read+write) accesses 2595system.l2c.demand_accesses::total 331753 # number of demand (read+write) accesses 2596system.l2c.overall_accesses::cpu0.dtb.walker 87 # number of overall (read+write) accesses 2597system.l2c.overall_accesses::cpu0.itb.walker 94 # number of overall (read+write) accesses 2598system.l2c.overall_accesses::cpu0.inst 46498 # number of overall (read+write) accesses 2599system.l2c.overall_accesses::cpu0.data 71483 # number of overall (read+write) accesses 2600system.l2c.overall_accesses::cpu0.l2cache.prefetcher 182226 # number of overall (read+write) accesses 2601system.l2c.overall_accesses::cpu1.dtb.walker 16 # number of overall (read+write) accesses 2602system.l2c.overall_accesses::cpu1.itb.walker 18 # number of overall (read+write) accesses 2603system.l2c.overall_accesses::cpu1.inst 8336 # number of overall (read+write) accesses 2604system.l2c.overall_accesses::cpu1.data 14652 # number of overall (read+write) accesses 2605system.l2c.overall_accesses::cpu1.l2cache.prefetcher 8343 # number of overall (read+write) accesses 2606system.l2c.overall_accesses::total 331753 # number of overall (read+write) accesses 2607system.l2c.UpgradeReq_miss_rate::cpu0.data 0.228532 # miss rate for UpgradeReq accesses 2608system.l2c.UpgradeReq_miss_rate::cpu1.data 0.571713 # miss rate for UpgradeReq accesses 2609system.l2c.UpgradeReq_miss_rate::total 0.258497 # miss rate for UpgradeReq accesses 2610system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.236462 # miss rate for SCUpgradeReq accesses 2611system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.595227 # miss rate for SCUpgradeReq accesses 2612system.l2c.SCUpgradeReq_miss_rate::total 0.396113 # miss rate for SCUpgradeReq accesses 2613system.l2c.ReadExReq_miss_rate::cpu0.data 0.727011 # miss rate for ReadExReq accesses 2614system.l2c.ReadExReq_miss_rate::cpu1.data 0.854019 # miss rate for ReadExReq accesses 2615system.l2c.ReadExReq_miss_rate::total 0.774680 # miss rate for ReadExReq accesses 2616system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for ReadSharedReq accesses 2617system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.021277 # miss rate for ReadSharedReq accesses 2618system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.384017 # miss rate for ReadSharedReq accesses 2619system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.158182 # miss rate for ReadSharedReq accesses 2620system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for ReadSharedReq accesses 2621system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for ReadSharedReq accesses 2622system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.242442 # miss rate for ReadSharedReq accesses 2623system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.137754 # miss rate for ReadSharedReq accesses 2624system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for ReadSharedReq accesses 2625system.l2c.ReadSharedReq_miss_rate::total 0.551798 # miss rate for ReadSharedReq accesses 2626system.l2c.demand_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for demand accesses 2627system.l2c.demand_miss_rate::cpu0.itb.walker 0.021277 # miss rate for demand accesses 2628system.l2c.demand_miss_rate::cpu0.inst 0.384017 # miss rate for demand accesses 2629system.l2c.demand_miss_rate::cpu0.data 0.279941 # miss rate for demand accesses 2630system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for demand accesses 2631system.l2c.demand_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for demand accesses 2632system.l2c.demand_miss_rate::cpu1.inst 0.242442 # miss rate for demand accesses 2633system.l2c.demand_miss_rate::cpu1.data 0.587155 # miss rate for demand accesses 2634system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for demand accesses 2635system.l2c.demand_miss_rate::total 0.568254 # miss rate for demand accesses 2636system.l2c.overall_miss_rate::cpu0.dtb.walker 0.068966 # miss rate for overall accesses 2637system.l2c.overall_miss_rate::cpu0.itb.walker 0.021277 # miss rate for overall accesses 2638system.l2c.overall_miss_rate::cpu0.inst 0.384017 # miss rate for overall accesses 2639system.l2c.overall_miss_rate::cpu0.data 0.279941 # miss rate for overall accesses 2640system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.739093 # miss rate for overall accesses 2641system.l2c.overall_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for overall accesses 2642system.l2c.overall_miss_rate::cpu1.inst 0.242442 # miss rate for overall accesses 2643system.l2c.overall_miss_rate::cpu1.data 0.587155 # miss rate for overall accesses 2644system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.639818 # miss rate for overall accesses 2645system.l2c.overall_miss_rate::total 0.568254 # miss rate for overall accesses 2646system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3613.839750 # average UpgradeReq miss latency 2647system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2180.652174 # average UpgradeReq miss latency 2648system.l2c.UpgradeReq_avg_miss_latency::total 3337.069689 # average UpgradeReq miss latency 2649system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 6075.572519 # average SCUpgradeReq miss latency 2650system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1904.689864 # average SCUpgradeReq miss latency 2651system.l2c.SCUpgradeReq_avg_miss_latency::total 3286.545271 # average SCUpgradeReq miss latency 2652system.l2c.ReadExReq_avg_miss_latency::cpu0.data 144972.716649 # average ReadExReq miss latency 2653system.l2c.ReadExReq_avg_miss_latency::cpu1.data 131172.143676 # average ReadExReq miss latency 2654system.l2c.ReadExReq_avg_miss_latency::total 139262.661397 # average ReadExReq miss latency 2655system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 137250 # average ReadSharedReq miss latency 2656system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 136000 # average ReadSharedReq miss latency 2657system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 131639.756944 # average ReadSharedReq miss latency 2658system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 136204.399685 # average ReadSharedReq miss latency 2659system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average ReadSharedReq miss latency 2660system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 132500 # average ReadSharedReq miss latency 2661system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 132808.015834 # average ReadSharedReq miss latency 2662system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 139159.574468 # average ReadSharedReq miss latency 2663system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average ReadSharedReq miss latency 2664system.l2c.ReadSharedReq_avg_miss_latency::total 143633.857613 # average ReadSharedReq miss latency 2665system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 137250 # average overall miss latency 2666system.l2c.demand_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency 2667system.l2c.demand_avg_miss_latency::cpu0.inst 131639.756944 # average overall miss latency 2668system.l2c.demand_avg_miss_latency::cpu0.data 141078.656739 # average overall miss latency 2669system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average overall miss latency 2670system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency 2671system.l2c.demand_avg_miss_latency::cpu1.inst 132808.015834 # average overall miss latency 2672system.l2c.demand_avg_miss_latency::cpu1.data 131870.335929 # average overall miss latency 2673system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average overall miss latency 2674system.l2c.demand_avg_miss_latency::total 143193.886001 # average overall miss latency 2675system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 137250 # average overall miss latency 2676system.l2c.overall_avg_miss_latency::cpu0.itb.walker 136000 # average overall miss latency 2677system.l2c.overall_avg_miss_latency::cpu0.inst 131639.756944 # average overall miss latency 2678system.l2c.overall_avg_miss_latency::cpu0.data 141078.656739 # average overall miss latency 2679system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 145307.262745 # average overall miss latency 2680system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 132500 # average overall miss latency 2681system.l2c.overall_avg_miss_latency::cpu1.inst 132808.015834 # average overall miss latency 2682system.l2c.overall_avg_miss_latency::cpu1.data 131870.335929 # average overall miss latency 2683system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 158643.804421 # average overall miss latency 2684system.l2c.overall_avg_miss_latency::total 143193.886001 # average overall miss latency 2685system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2686system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2687system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2688system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2689system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2690system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2691system.l2c.fast_writes 0 # number of fast writes performed 2692system.l2c.cache_copies 0 # number of cache copies performed 2693system.l2c.writebacks::writebacks 97095 # number of writebacks 2694system.l2c.writebacks::total 97095 # number of writebacks 2695system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits 2696system.l2c.ReadSharedReq_mshr_hits::cpu0.data 1 # number of ReadSharedReq MSHR hits 2697system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 11 # number of ReadSharedReq MSHR hits 2698system.l2c.ReadSharedReq_mshr_hits::total 17 # number of ReadSharedReq MSHR hits 2699system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits 2700system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits 2701system.l2c.demand_mshr_hits::cpu1.inst 11 # number of demand (read+write) MSHR hits 2702system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 2703system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits 2704system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits 2705system.l2c.overall_mshr_hits::cpu1.inst 11 # number of overall MSHR hits 2706system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits 2707system.l2c.CleanEvict_mshr_misses::writebacks 2818 # number of CleanEvict MSHR misses 2708system.l2c.CleanEvict_mshr_misses::total 2818 # number of CleanEvict MSHR misses 2709system.l2c.UpgradeReq_mshr_misses::cpu0.data 9610 # number of UpgradeReq MSHR misses 2710system.l2c.UpgradeReq_mshr_misses::cpu1.data 2300 # number of UpgradeReq MSHR misses 2711system.l2c.UpgradeReq_mshr_misses::total 11910 # number of UpgradeReq MSHR misses 2712system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 655 # number of SCUpgradeReq MSHR misses 2713system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1322 # number of SCUpgradeReq MSHR misses 2714system.l2c.SCUpgradeReq_mshr_misses::total 1977 # number of SCUpgradeReq MSHR misses 2715system.l2c.ReadExReq_mshr_misses::cpu0.data 11124 # number of ReadExReq MSHR misses 2716system.l2c.ReadExReq_mshr_misses::cpu1.data 7851 # number of ReadExReq MSHR misses 2717system.l2c.ReadExReq_mshr_misses::total 18975 # number of ReadExReq MSHR misses 2718system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 6 # number of ReadSharedReq MSHR misses 2719system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2 # number of ReadSharedReq MSHR misses 2720system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17851 # number of ReadSharedReq MSHR misses 2721system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8886 # number of ReadSharedReq MSHR misses 2722system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of ReadSharedReq MSHR misses 2723system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR misses 2724system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 2010 # number of ReadSharedReq MSHR misses 2725system.l2c.ReadSharedReq_mshr_misses::cpu1.data 752 # number of ReadSharedReq MSHR misses 2726system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of ReadSharedReq MSHR misses 2727system.l2c.ReadSharedReq_mshr_misses::total 169528 # number of ReadSharedReq MSHR misses 2728system.l2c.demand_mshr_misses::cpu0.dtb.walker 6 # number of demand (read+write) MSHR misses 2729system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses 2730system.l2c.demand_mshr_misses::cpu0.inst 17851 # number of demand (read+write) MSHR misses 2731system.l2c.demand_mshr_misses::cpu0.data 20010 # number of demand (read+write) MSHR misses 2732system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of demand (read+write) MSHR misses 2733system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses 2734system.l2c.demand_mshr_misses::cpu1.inst 2010 # number of demand (read+write) MSHR misses 2735system.l2c.demand_mshr_misses::cpu1.data 8603 # number of demand (read+write) MSHR misses 2736system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of demand (read+write) MSHR misses 2737system.l2c.demand_mshr_misses::total 188503 # number of demand (read+write) MSHR misses 2738system.l2c.overall_mshr_misses::cpu0.dtb.walker 6 # number of overall MSHR misses 2739system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses 2740system.l2c.overall_mshr_misses::cpu0.inst 17851 # number of overall MSHR misses 2741system.l2c.overall_mshr_misses::cpu0.data 20010 # number of overall MSHR misses 2742system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134682 # number of overall MSHR misses 2743system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses 2744system.l2c.overall_mshr_misses::cpu1.inst 2010 # number of overall MSHR misses 2745system.l2c.overall_mshr_misses::cpu1.data 8603 # number of overall MSHR misses 2746system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5338 # number of overall MSHR misses 2747system.l2c.overall_mshr_misses::total 188503 # number of overall MSHR misses 2748system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable 2749system.l2c.ReadReq_mshr_uncacheable::cpu0.data 31860 # number of ReadReq MSHR uncacheable 2750system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 177 # number of ReadReq MSHR uncacheable 2751system.l2c.ReadReq_mshr_uncacheable::cpu1.data 3104 # number of ReadReq MSHR uncacheable 2752system.l2c.ReadReq_mshr_uncacheable::total 44163 # number of ReadReq MSHR uncacheable 2753system.l2c.WriteReq_mshr_uncacheable::cpu0.data 28553 # number of WriteReq MSHR uncacheable 2754system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2430 # number of WriteReq MSHR uncacheable 2755system.l2c.WriteReq_mshr_uncacheable::total 30983 # number of WriteReq MSHR uncacheable 2756system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses 2757system.l2c.overall_mshr_uncacheable_misses::cpu0.data 60413 # number of overall MSHR uncacheable misses 2758system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 177 # number of overall MSHR uncacheable misses 2759system.l2c.overall_mshr_uncacheable_misses::cpu1.data 5534 # number of overall MSHR uncacheable misses 2760system.l2c.overall_mshr_uncacheable_misses::total 75146 # number of overall MSHR uncacheable misses 2761system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 725072500 # number of UpgradeReq MSHR miss cycles 2762system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 172861000 # number of UpgradeReq MSHR miss cycles 2763system.l2c.UpgradeReq_mshr_miss_latency::total 897933500 # number of UpgradeReq MSHR miss cycles 2764system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 50674000 # number of SCUpgradeReq MSHR miss cycles 2765system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 101405500 # number of SCUpgradeReq MSHR miss cycles 2766system.l2c.SCUpgradeReq_mshr_miss_latency::total 152079500 # number of SCUpgradeReq MSHR miss cycles 2767system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 1501436500 # number of ReadExReq MSHR miss cycles 2768system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 951322500 # number of ReadExReq MSHR miss cycles 2769system.l2c.ReadExReq_mshr_miss_latency::total 2452759000 # number of ReadExReq MSHR miss cycles 2770system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 763500 # number of ReadSharedReq MSHR miss cycles 2771system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 252000 # number of ReadSharedReq MSHR miss cycles 2772system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 2171508000 # number of ReadSharedReq MSHR miss cycles 2773system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 1121559000 # number of ReadSharedReq MSHR miss cycles 2774system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of ReadSharedReq MSHR miss cycles 2775system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 122500 # number of ReadSharedReq MSHR miss cycles 2776system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 247283000 # number of ReadSharedReq MSHR miss cycles 2777system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 97128000 # number of ReadSharedReq MSHR miss cycles 2778system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of ReadSharedReq MSHR miss cycles 2779system.l2c.ReadSharedReq_mshr_miss_latency::total 22655529389 # number of ReadSharedReq MSHR miss cycles 2780system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 763500 # number of demand (read+write) MSHR miss cycles 2781system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 252000 # number of demand (read+write) MSHR miss cycles 2782system.l2c.demand_mshr_miss_latency::cpu0.inst 2171508000 # number of demand (read+write) MSHR miss cycles 2783system.l2c.demand_mshr_miss_latency::cpu0.data 2622995500 # number of demand (read+write) MSHR miss cycles 2784system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of demand (read+write) MSHR miss cycles 2785system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 122500 # number of demand (read+write) MSHR miss cycles 2786system.l2c.demand_mshr_miss_latency::cpu1.inst 247283000 # number of demand (read+write) MSHR miss cycles 2787system.l2c.demand_mshr_miss_latency::cpu1.data 1048450500 # number of demand (read+write) MSHR miss cycles 2788system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of demand (read+write) MSHR miss cycles 2789system.l2c.demand_mshr_miss_latency::total 25108288389 # number of demand (read+write) MSHR miss cycles 2790system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 763500 # number of overall MSHR miss cycles 2791system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 252000 # number of overall MSHR miss cycles 2792system.l2c.overall_mshr_miss_latency::cpu0.inst 2171508000 # number of overall MSHR miss cycles 2793system.l2c.overall_mshr_miss_latency::cpu0.data 2622995500 # number of overall MSHR miss cycles 2794system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 18223452761 # number of overall MSHR miss cycles 2795system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 122500 # number of overall MSHR miss cycles 2796system.l2c.overall_mshr_miss_latency::cpu1.inst 247283000 # number of overall MSHR miss cycles 2797system.l2c.overall_mshr_miss_latency::cpu1.data 1048450500 # number of overall MSHR miss cycles 2798system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 793460628 # number of overall MSHR miss cycles 2799system.l2c.overall_mshr_miss_latency::total 25108288389 # number of overall MSHR miss cycles 2800system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of ReadReq MSHR uncacheable cycles 2801system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5812758500 # number of ReadReq MSHR uncacheable cycles 2802system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 19032500 # number of ReadReq MSHR uncacheable cycles 2803system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 349483000 # number of ReadReq MSHR uncacheable cycles 2804system.l2c.ReadReq_mshr_uncacheable_latency::total 7205089000 # number of ReadReq MSHR uncacheable cycles 2805system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4715021500 # number of WriteReq MSHR uncacheable cycles 2806system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 233050000 # number of WriteReq MSHR uncacheable cycles 2807system.l2c.WriteReq_mshr_uncacheable_latency::total 4948071500 # number of WriteReq MSHR uncacheable cycles 2808system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1023815000 # number of overall MSHR uncacheable cycles 2809system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10527780000 # number of overall MSHR uncacheable cycles 2810system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 19032500 # number of overall MSHR uncacheable cycles 2811system.l2c.overall_mshr_uncacheable_latency::cpu1.data 582533000 # number of overall MSHR uncacheable cycles 2812system.l2c.overall_mshr_uncacheable_latency::total 12153160500 # number of overall MSHR uncacheable cycles 2813system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2814system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2815system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.228532 # mshr miss rate for UpgradeReq accesses 2816system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.571713 # mshr miss rate for UpgradeReq accesses 2817system.l2c.UpgradeReq_mshr_miss_rate::total 0.258497 # mshr miss rate for UpgradeReq accesses 2818system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.236462 # mshr miss rate for SCUpgradeReq accesses 2819system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.595227 # mshr miss rate for SCUpgradeReq accesses 2820system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.396113 # mshr miss rate for SCUpgradeReq accesses 2821system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.727011 # mshr miss rate for ReadExReq accesses 2822system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854019 # mshr miss rate for ReadExReq accesses 2823system.l2c.ReadExReq_mshr_miss_rate::total 0.774680 # mshr miss rate for ReadExReq accesses 2824system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for ReadSharedReq accesses 2825system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for ReadSharedReq accesses 2826system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for ReadSharedReq accesses 2827system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.158165 # mshr miss rate for ReadSharedReq accesses 2828system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for ReadSharedReq accesses 2829system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for ReadSharedReq accesses 2830system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for ReadSharedReq accesses 2831system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.137754 # mshr miss rate for ReadSharedReq accesses 2832system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for ReadSharedReq accesses 2833system.l2c.ReadSharedReq_mshr_miss_rate::total 0.551743 # mshr miss rate for ReadSharedReq accesses 2834system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for demand accesses 2835system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for demand accesses 2836system.l2c.demand_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for demand accesses 2837system.l2c.demand_mshr_miss_rate::cpu0.data 0.279927 # mshr miss rate for demand accesses 2838system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for demand accesses 2839system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for demand accesses 2840system.l2c.demand_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for demand accesses 2841system.l2c.demand_mshr_miss_rate::cpu1.data 0.587155 # mshr miss rate for demand accesses 2842system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for demand accesses 2843system.l2c.demand_mshr_miss_rate::total 0.568203 # mshr miss rate for demand accesses 2844system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.068966 # mshr miss rate for overall accesses 2845system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.021277 # mshr miss rate for overall accesses 2846system.l2c.overall_mshr_miss_rate::cpu0.inst 0.383909 # mshr miss rate for overall accesses 2847system.l2c.overall_mshr_miss_rate::cpu0.data 0.279927 # mshr miss rate for overall accesses 2848system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739093 # mshr miss rate for overall accesses 2849system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for overall accesses 2850system.l2c.overall_mshr_miss_rate::cpu1.inst 0.241123 # mshr miss rate for overall accesses 2851system.l2c.overall_mshr_miss_rate::cpu1.data 0.587155 # mshr miss rate for overall accesses 2852system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.639818 # mshr miss rate for overall accesses 2853system.l2c.overall_mshr_miss_rate::total 0.568203 # mshr miss rate for overall accesses 2854system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75449.791883 # average UpgradeReq mshr miss latency 2855system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75156.956522 # average UpgradeReq mshr miss latency 2856system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75393.240974 # average UpgradeReq mshr miss latency 2857system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77364.885496 # average SCUpgradeReq mshr miss latency 2858system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76706.127080 # average SCUpgradeReq mshr miss latency 2859system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76924.380374 # average SCUpgradeReq mshr miss latency 2860system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 134972.716649 # average ReadExReq mshr miss latency 2861system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 121172.143676 # average ReadExReq mshr miss latency 2862system.l2c.ReadExReq_avg_mshr_miss_latency::total 129262.661397 # average ReadExReq mshr miss latency 2863system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average ReadSharedReq mshr miss latency 2864system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average ReadSharedReq mshr miss latency 2865system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average ReadSharedReq mshr miss latency 2866system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 126216.407833 # average ReadSharedReq mshr miss latency 2867system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average ReadSharedReq mshr miss latency 2868system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average ReadSharedReq mshr miss latency 2869system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average ReadSharedReq mshr miss latency 2870system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129159.574468 # average ReadSharedReq mshr miss latency 2871system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average ReadSharedReq mshr miss latency 2872system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 133638.864312 # average ReadSharedReq mshr miss latency 2873system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average overall mshr miss latency 2874system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency 2875system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average overall mshr miss latency 2876system.l2c.demand_avg_mshr_miss_latency::cpu0.data 131084.232884 # average overall mshr miss latency 2877system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average overall mshr miss latency 2878system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency 2879system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average overall mshr miss latency 2880system.l2c.demand_avg_mshr_miss_latency::cpu1.data 121870.335929 # average overall mshr miss latency 2881system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average overall mshr miss latency 2882system.l2c.demand_avg_mshr_miss_latency::total 133198.349040 # average overall mshr miss latency 2883system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127250 # average overall mshr miss latency 2884system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 126000 # average overall mshr miss latency 2885system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121646.294325 # average overall mshr miss latency 2886system.l2c.overall_avg_mshr_miss_latency::cpu0.data 131084.232884 # average overall mshr miss latency 2887system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135307.262745 # average overall mshr miss latency 2888system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122500 # average overall mshr miss latency 2889system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123026.368159 # average overall mshr miss latency 2890system.l2c.overall_avg_mshr_miss_latency::cpu1.data 121870.335929 # average overall mshr miss latency 2891system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 148643.804421 # average overall mshr miss latency 2892system.l2c.overall_avg_mshr_miss_latency::total 133198.349040 # average overall mshr miss latency 2893system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average ReadReq mshr uncacheable latency 2894system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182446.908349 # average ReadReq mshr uncacheable latency 2895system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average ReadReq mshr uncacheable latency 2896system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 112591.172680 # average ReadReq mshr uncacheable latency 2897system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 163147.634898 # average ReadReq mshr uncacheable latency 2898system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165132.262810 # average WriteReq mshr uncacheable latency 2899system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 95905.349794 # average WriteReq mshr uncacheable latency 2900system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159702.788626 # average WriteReq mshr uncacheable latency 2901system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113479.827089 # average overall mshr uncacheable latency 2902system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174263.486336 # average overall mshr uncacheable latency 2903system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107528.248588 # average overall mshr uncacheable latency 2904system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 105264.365739 # average overall mshr uncacheable latency 2905system.l2c.overall_avg_mshr_uncacheable_latency::total 161727.310835 # average overall mshr uncacheable latency 2906system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2907system.membus.trans_dist::ReadReq 44163 # Transaction distribution 2908system.membus.trans_dist::ReadResp 213934 # Transaction distribution 2909system.membus.trans_dist::WriteReq 30983 # Transaction distribution 2910system.membus.trans_dist::WriteResp 30983 # Transaction distribution 2911system.membus.trans_dist::WritebackDirty 133285 # Transaction distribution 2912system.membus.trans_dist::CleanEvict 14406 # Transaction distribution 2913system.membus.trans_dist::UpgradeReq 73490 # Transaction distribution 2914system.membus.trans_dist::SCUpgradeReq 39839 # Transaction distribution 2915system.membus.trans_dist::UpgradeResp 13966 # Transaction distribution 2916system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 2917system.membus.trans_dist::ReadExReq 39499 # Transaction distribution 2918system.membus.trans_dist::ReadExResp 18896 # Transaction distribution 2919system.membus.trans_dist::ReadSharedReq 169771 # Transaction distribution 2920system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 2921system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 2922system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) 2923system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 2924system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14022 # Packet count per connected master and slave (bytes) 2925system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664172 # Packet count per connected master and slave (bytes) 2926system.membus.pkt_count_system.l2c.mem_side::total 786162 # Packet count per connected master and slave (bytes) 2927system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108909 # Packet count per connected master and slave (bytes) 2928system.membus.pkt_count_system.iocache.mem_side::total 108909 # Packet count per connected master and slave (bytes) 2929system.membus.pkt_count::total 895071 # Packet count per connected master and slave (bytes) 2930system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) 2931system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 2932system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28044 # Cumulative packet size per connected master and slave (bytes) 2933system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18307596 # Cumulative packet size per connected master and slave (bytes) 2934system.membus.pkt_size_system.l2c.mem_side::total 18498522 # Cumulative packet size per connected master and slave (bytes) 2935system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) 2936system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) 2937system.membus.pkt_size::total 20815642 # Cumulative packet size per connected master and slave (bytes) 2938system.membus.snoops 120564 # Total snoops (count) 2939system.membus.snoop_fanout::samples 581920 # Request fanout histogram 2940system.membus.snoop_fanout::mean 1 # Request fanout histogram 2941system.membus.snoop_fanout::stdev 0 # Request fanout histogram 2942system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2943system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2944system.membus.snoop_fanout::1 581920 100.00% 100.00% # Request fanout histogram 2945system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 2946system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2947system.membus.snoop_fanout::min_value 1 # Request fanout histogram 2948system.membus.snoop_fanout::max_value 1 # Request fanout histogram 2949system.membus.snoop_fanout::total 581920 # Request fanout histogram 2950system.membus.reqLayer0.occupancy 88268000 # Layer occupancy (ticks) 2951system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 2952system.membus.reqLayer1.occupancy 19000 # Layer occupancy (ticks) 2953system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 2954system.membus.reqLayer2.occupancy 11611500 # Layer occupancy (ticks) 2955system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 2956system.membus.reqLayer5.occupancy 967762037 # Layer occupancy (ticks) 2957system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 2958system.membus.respLayer2.occupancy 1134685490 # Layer occupancy (ticks) 2959system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 2960system.membus.respLayer3.occupancy 64105002 # Layer occupancy (ticks) 2961system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 2962system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 2963system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 2964system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 2965system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 2966system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 2967system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 2968system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 2969system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 2970system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 2971system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 2972system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 2973system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 2974system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 2975system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 2976system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 2977system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 2978system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 2979system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 2980system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 2981system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 2982system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 2983system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 2984system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 2985system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 2986system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 2987system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 2988system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 2989system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 2990system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 2991system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 2992system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 2993system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 2994system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 2995system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 2996system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 2997system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 2998system.realview.ethernet.droppedPackets 0 # number of packets dropped 2999system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3000system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3001system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3002system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3003system.toL2Bus.snoop_filter.tot_requests 959770 # Total number of requests made to the snoop filter. 3004system.toL2Bus.snoop_filter.hit_single_requests 518663 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3005system.toL2Bus.snoop_filter.hit_multi_requests 138023 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3006system.toL2Bus.snoop_filter.tot_snoops 20272 # Total number of snoops made to the snoop filter. 3007system.toL2Bus.snoop_filter.hit_single_snoops 19432 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3008system.toL2Bus.snoop_filter.hit_multi_snoops 840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3009system.toL2Bus.trans_dist::ReadReq 44166 # Transaction distribution 3010system.toL2Bus.trans_dist::ReadResp 467162 # Transaction distribution 3011system.toL2Bus.trans_dist::WriteReq 30983 # Transaction distribution 3012system.toL2Bus.trans_dist::WriteResp 30983 # Transaction distribution 3013system.toL2Bus.trans_dist::WritebackDirty 390842 # Transaction distribution 3014system.toL2Bus.trans_dist::CleanEvict 84262 # Transaction distribution 3015system.toL2Bus.trans_dist::UpgradeReq 107575 # Transaction distribution 3016system.toL2Bus.trans_dist::SCUpgradeReq 42853 # Transaction distribution 3017system.toL2Bus.trans_dist::UpgradeResp 150428 # Transaction distribution 3018system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution 3019system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution 3020system.toL2Bus.trans_dist::ReadExReq 50605 # Transaction distribution 3021system.toL2Bus.trans_dist::ReadExResp 50605 # Transaction distribution 3022system.toL2Bus.trans_dist::ReadSharedReq 423011 # Transaction distribution 3023system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution 3024system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1226424 # Packet count per connected master and slave (bytes) 3025system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 245800 # Packet count per connected master and slave (bytes) 3026system.toL2Bus.pkt_count::total 1472224 # Packet count per connected master and slave (bytes) 3027system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34332563 # Cumulative packet size per connected master and slave (bytes) 3028system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3643847 # Cumulative packet size per connected master and slave (bytes) 3029system.toL2Bus.pkt_size::total 37976410 # Cumulative packet size per connected master and slave (bytes) 3030system.toL2Bus.snoops 437847 # Total snoops (count) 3031system.toL2Bus.snoop_fanout::samples 895583 # Request fanout histogram 3032system.toL2Bus.snoop_fanout::mean 0.335708 # Request fanout histogram 3033system.toL2Bus.snoop_fanout::stdev 0.474219 # Request fanout histogram 3034system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3035system.toL2Bus.snoop_fanout::0 595769 66.52% 66.52% # Request fanout histogram 3036system.toL2Bus.snoop_fanout::1 298974 33.38% 99.91% # Request fanout histogram 3037system.toL2Bus.snoop_fanout::2 840 0.09% 100.00% # Request fanout histogram 3038system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3039system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3040system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3041system.toL2Bus.snoop_fanout::total 895583 # Request fanout histogram 3042system.toL2Bus.reqLayer0.occupancy 863469481 # Layer occupancy (ticks) 3043system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3044system.toL2Bus.snoopLayer0.occupancy 342622 # Layer occupancy (ticks) 3045system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3046system.toL2Bus.respLayer0.occupancy 647119226 # Layer occupancy (ticks) 3047system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3048system.toL2Bus.respLayer1.occupancy 200312901 # Layer occupancy (ticks) 3049system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3050 3051---------- End Simulation Statistics ---------- 3052