simerr revision 11957:90bb43dfc028
1warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
2info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
3warn: Sockets disabled, not accepting vnc client connections
4warn: Sockets disabled, not accepting terminal connections
5warn: Sockets disabled, not accepting gdb connections
6warn: ClockedObject: More than one power state change request encountered within the same simulation tick
7warn: ClockedObject: More than one power state change request encountered within the same simulation tick
8info: Using bootloader at address 0x10
9info: Using kernel entry physical address at 0x80008000
10info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
11warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
12info: Entering event queue @ 0.  Starting simulation...
13warn: Not doing anything for miscreg ACTLR
14warn: Not doing anything for write of miscreg ACTLR
15warn: The clidr register always reports 0 caches.
16warn: clidr LoUIS field of 0b001 to match current ARM implementations.
17warn: The csselr register isn't implemented.
18warn: 	instruction 'mcr dccmvau' unimplemented
19warn: 	instruction 'mcr icimvau' unimplemented
20warn: 	instruction 'mcr bpiallis' unimplemented
21warn: 	instruction 'mcr icialluis' unimplemented
22warn: 	instruction 'mcr dccimvac' unimplemented
23warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
24warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
25warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
26warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
27warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
28warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
29warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
30warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
31warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
32warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
33info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
34info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
35info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
36info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
37info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
38info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
39info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
40warn: Not doing anything for miscreg ACTLR
41warn: Not doing anything for write of miscreg ACTLR
42warn: 	instruction 'mcr bpiall' unimplemented
43info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
44info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
45info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
46info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
47info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
48info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
49info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
50info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
51warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
52warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
53warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
54warn: Returning zero for read from miscreg pmcr
55warn: Ignoring write to miscreg pmcntenclr
56warn: Ignoring write to miscreg pmintenclr
57warn: Ignoring write to miscreg pmovsr
58warn: Ignoring write to miscreg pmcr
59warn: Ignoring write to miscreg pmcntenclr
60warn: Ignoring write to miscreg pmintenclr
61warn: Ignoring write to miscreg pmovsr
62warn: Ignoring write to miscreg pmcr
63