simerr revision 11957:90bb43dfc028 
19241Sandreas.hansson@arm.comwarn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
29241Sandreas.hansson@arm.cominfo: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
39241Sandreas.hansson@arm.comwarn: Sockets disabled, not accepting vnc client connections
49241Sandreas.hansson@arm.comwarn: Sockets disabled, not accepting terminal connections
59241Sandreas.hansson@arm.comwarn: Sockets disabled, not accepting gdb connections
69241Sandreas.hansson@arm.comwarn: ClockedObject: More than one power state change request encountered within the same simulation tick
79241Sandreas.hansson@arm.comwarn: ClockedObject: More than one power state change request encountered within the same simulation tick
89241Sandreas.hansson@arm.cominfo: Using bootloader at address 0x10
99241Sandreas.hansson@arm.cominfo: Using kernel entry physical address at 0x80008000
109241Sandreas.hansson@arm.cominfo: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000
119241Sandreas.hansson@arm.comwarn: Existing EnergyCtrl, but no enabled DVFSHandler found.
129241Sandreas.hansson@arm.cominfo: Entering event queue @ 0.  Starting simulation...
139241Sandreas.hansson@arm.comwarn: Not doing anything for miscreg ACTLR
149241Sandreas.hansson@arm.comwarn: Not doing anything for write of miscreg ACTLR
159241Sandreas.hansson@arm.comwarn: The clidr register always reports 0 caches.
169241Sandreas.hansson@arm.comwarn: clidr LoUIS field of 0b001 to match current ARM implementations.
179241Sandreas.hansson@arm.comwarn: The csselr register isn't implemented.
189241Sandreas.hansson@arm.comwarn: 	instruction 'mcr dccmvau' unimplemented
199241Sandreas.hansson@arm.comwarn: 	instruction 'mcr icimvau' unimplemented
209241Sandreas.hansson@arm.comwarn: 	instruction 'mcr bpiallis' unimplemented
219241Sandreas.hansson@arm.comwarn: 	instruction 'mcr icialluis' unimplemented
229241Sandreas.hansson@arm.comwarn: 	instruction 'mcr dccimvac' unimplemented
239241Sandreas.hansson@arm.comwarn: Tried to read RealView I/O at offset 0x60 that doesn't exist
249241Sandreas.hansson@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
259241Sandreas.hansson@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
269241Sandreas.hansson@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
279241Sandreas.hansson@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
289241Sandreas.hansson@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
299241Sandreas.hansson@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
309241Sandreas.hansson@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
319241Sandreas.hansson@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
329241Sandreas.hansson@arm.comwarn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
339241Sandreas.hansson@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
349241Sandreas.hansson@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
359241Sandreas.hansson@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
369241Sandreas.hansson@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
379241Sandreas.hansson@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
389241Sandreas.hansson@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
399241Sandreas.hansson@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
409241Sandreas.hansson@arm.comwarn: Not doing anything for miscreg ACTLR
419241Sandreas.hansson@arm.comwarn: Not doing anything for write of miscreg ACTLR
429241Sandreas.hansson@arm.comwarn: 	instruction 'mcr bpiall' unimplemented
439241Sandreas.hansson@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
449241Sandreas.hansson@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
459241Sandreas.hansson@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
469241Sandreas.hansson@arm.cominfo: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
47info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
48info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
49info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
50info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0
51warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
52warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
53warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
54warn: Returning zero for read from miscreg pmcr
55warn: Ignoring write to miscreg pmcntenclr
56warn: Ignoring write to miscreg pmintenclr
57warn: Ignoring write to miscreg pmovsr
58warn: Ignoring write to miscreg pmcr
59warn: Ignoring write to miscreg pmcntenclr
60warn: Ignoring write to miscreg pmintenclr
61warn: Ignoring write to miscreg pmovsr
62warn: Ignoring write to miscreg pmcr
63