stats.txt revision 10535:4ccec5baf82c
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783854 # Number of seconds simulated 4sim_ticks 2783854461500 # Number of ticks simulated 5final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1414038 # Simulator instruction rate (inst/s) 8host_op_rate 1721363 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 27571822204 # Simulator tick rate (ticks/s) 10host_mem_usage 560116 # Number of bytes of host memory used 11host_seconds 100.97 # Real time elapsed on the host 12sim_insts 142771592 # Number of instructions simulated 13sim_ops 173801445 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 26system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 27system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 36system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 37system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory 38system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) 46system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) 49system.physmem.bw_write::total 3181702 # Write bandwidth from this memory (bytes/s) 50system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::total 7333646 # Total bandwidth to/from this memory (bytes/s) 57system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 58system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 59system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 60system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 61system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 62system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 63system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 67system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 68system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 69system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 70system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 71system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 72system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 73system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 74system.cf0.dma_write_txs 631 # Number of DMA write transactions. 75system.cpu_clk_domain.clock 500 # Clock period in ticks 76system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 77system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 78system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 79system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 80system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 81system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 82system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 83system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 84system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 85system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 86system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 87system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 88system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 89system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 90system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 91system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 92system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 93system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 94system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 95system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 96system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 97system.cpu.dtb.inst_hits 0 # ITB inst hits 98system.cpu.dtb.inst_misses 0 # ITB inst misses 99system.cpu.dtb.read_hits 31525959 # DTB read hits 100system.cpu.dtb.read_misses 8580 # DTB read misses 101system.cpu.dtb.write_hits 23124081 # DTB write hits 102system.cpu.dtb.write_misses 1448 # DTB write misses 103system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 104system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 105system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 106system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 107system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 108system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 109system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 110system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 111system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 112system.cpu.dtb.read_accesses 31534539 # DTB read accesses 113system.cpu.dtb.write_accesses 23125529 # DTB write accesses 114system.cpu.dtb.inst_accesses 0 # ITB inst accesses 115system.cpu.dtb.hits 54650040 # DTB hits 116system.cpu.dtb.misses 10028 # DTB misses 117system.cpu.dtb.accesses 54660068 # DTB accesses 118system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 119system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 120system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 121system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 122system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 123system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 124system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 125system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 126system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 127system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 128system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 129system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 130system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 131system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 132system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 133system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 134system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 135system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 136system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 137system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 138system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 139system.cpu.itb.inst_hits 147038107 # ITB inst hits 140system.cpu.itb.inst_misses 4762 # ITB inst misses 141system.cpu.itb.read_hits 0 # DTB read hits 142system.cpu.itb.read_misses 0 # DTB read misses 143system.cpu.itb.write_hits 0 # DTB write hits 144system.cpu.itb.write_misses 0 # DTB write misses 145system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 146system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 147system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 148system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 149system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 150system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 151system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 152system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 153system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 154system.cpu.itb.read_accesses 0 # DTB read accesses 155system.cpu.itb.write_accesses 0 # DTB write accesses 156system.cpu.itb.inst_accesses 147042869 # ITB inst accesses 157system.cpu.itb.hits 147038107 # DTB hits 158system.cpu.itb.misses 4762 # DTB misses 159system.cpu.itb.accesses 147042869 # DTB accesses 160system.cpu.numCycles 5567712004 # number of cpu cycles simulated 161system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 162system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 163system.cpu.committedInsts 142771592 # Number of instructions committed 164system.cpu.committedOps 173801445 # Number of ops (including micro ops) committed 165system.cpu.num_int_alu_accesses 153161099 # Number of integer alu accesses 166system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 167system.cpu.num_func_calls 16873874 # number of times a function call or return occured 168system.cpu.num_conditional_control_insts 18730301 # number of instructions that are conditional controls 169system.cpu.num_int_insts 153161099 # number of integer instructions 170system.cpu.num_fp_insts 11484 # number of float instructions 171system.cpu.num_int_register_reads 285057250 # number of times the integer registers were read 172system.cpu.num_int_register_writes 107178308 # number of times the integer registers were written 173system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 174system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 175system.cpu.num_cc_register_reads 530849099 # number of times the CC registers were read 176system.cpu.num_cc_register_writes 62363961 # number of times the CC registers were written 177system.cpu.num_mem_refs 55938603 # number of memory refs 178system.cpu.num_load_insts 31855595 # Number of load instructions 179system.cpu.num_store_insts 24083008 # Number of store instructions 180system.cpu.num_idle_cycles 5389630193.939086 # Number of idle cycles 181system.cpu.num_busy_cycles 178081810.060914 # Number of busy cycles 182system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles 183system.cpu.idle_fraction 0.968015 # Percentage of idle cycles 184system.cpu.Branches 36396923 # Number of branches fetched 185system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 186system.cpu.op_class::IntAlu 121151902 68.36% 68.36% # Class of executed instruction 187system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction 188system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction 189system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction 190system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction 191system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction 192system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction 193system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction 194system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction 195system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction 196system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction 197system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction 198system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction 199system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction 200system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction 201system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction 202system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction 203system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction 204system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction 205system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction 206system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction 207system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction 208system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction 209system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction 210system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction 211system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction 212system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction 213system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction 214system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 215system.cpu.op_class::MemRead 31855595 17.98% 86.41% # Class of executed instruction 216system.cpu.op_class::MemWrite 24083008 13.59% 100.00% # Class of executed instruction 217system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 218system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 219system.cpu.op_class::total 177218284 # Class of executed instruction 220system.cpu.kern.inst.arm 0 # number of arm instructions executed 221system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed 222system.cpu.dcache.tags.replacements 819396 # number of replacements 223system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 224system.cpu.dcache.tags.total_refs 53783832 # Total number of references to valid blocks. 225system.cpu.dcache.tags.sampled_refs 819908 # Sample count of references to valid blocks. 226system.cpu.dcache.tags.avg_refs 65.597399 # Average number of references to valid blocks. 227system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 228system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 229system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 230system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 231system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 232system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 233system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 234system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 235system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 236system.cpu.dcache.tags.tag_accesses 219234948 # Number of tag accesses 237system.cpu.dcache.tags.data_accesses 219234948 # Number of data accesses 238system.cpu.dcache.ReadReq_hits::cpu.data 30128799 # number of ReadReq hits 239system.cpu.dcache.ReadReq_hits::total 30128799 # number of ReadReq hits 240system.cpu.dcache.WriteReq_hits::cpu.data 22339754 # number of WriteReq hits 241system.cpu.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits 242system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits 243system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits 244system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits 245system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits 246system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits 247system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits 248system.cpu.dcache.demand_hits::cpu.data 52468553 # number of demand (read+write) hits 249system.cpu.dcache.demand_hits::total 52468553 # number of demand (read+write) hits 250system.cpu.dcache.overall_hits::cpu.data 52863618 # number of overall hits 251system.cpu.dcache.overall_hits::total 52863618 # number of overall hits 252system.cpu.dcache.ReadReq_misses::cpu.data 396285 # number of ReadReq misses 253system.cpu.dcache.ReadReq_misses::total 396285 # number of ReadReq misses 254system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses 255system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses 256system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses 257system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses 258system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses 259system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses 260system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 261system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 262system.cpu.dcache.demand_misses::cpu.data 697948 # number of demand (read+write) misses 263system.cpu.dcache.demand_misses::total 697948 # number of demand (read+write) misses 264system.cpu.dcache.overall_misses::cpu.data 814069 # number of overall misses 265system.cpu.dcache.overall_misses::total 814069 # number of overall misses 266system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses) 267system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses) 268system.cpu.dcache.WriteReq_accesses::cpu.data 22641417 # number of WriteReq accesses(hits+misses) 269system.cpu.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses) 270system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) 271system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) 272system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) 273system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) 274system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) 275system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) 276system.cpu.dcache.demand_accesses::cpu.data 53166501 # number of demand (read+write) accesses 277system.cpu.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses 278system.cpu.dcache.overall_accesses::cpu.data 53677687 # number of overall (read+write) accesses 279system.cpu.dcache.overall_accesses::total 53677687 # number of overall (read+write) accesses 280system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses 281system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses 282system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses 283system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses 284system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses 285system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses 286system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses 287system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses 288system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 289system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 290system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses 291system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses 292system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses 293system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses 294system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 295system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 296system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 297system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 298system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 299system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 300system.cpu.dcache.fast_writes 0 # number of fast writes performed 301system.cpu.dcache.cache_copies 0 # number of cache copies performed 302system.cpu.dcache.writebacks::writebacks 682037 # number of writebacks 303system.cpu.dcache.writebacks::total 682037 # number of writebacks 304system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 305system.cpu.icache.tags.replacements 1699006 # number of replacements 306system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use 307system.cpu.icache.tags.total_refs 145341690 # Total number of references to valid blocks. 308system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. 309system.cpu.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks. 310system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. 311system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor 312system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy 313system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy 314system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 315system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 316system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 317system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 318system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 319system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 320system.cpu.icache.tags.tag_accesses 148740738 # Number of tag accesses 321system.cpu.icache.tags.data_accesses 148740738 # Number of data accesses 322system.cpu.icache.ReadReq_hits::cpu.inst 145341690 # number of ReadReq hits 323system.cpu.icache.ReadReq_hits::total 145341690 # number of ReadReq hits 324system.cpu.icache.demand_hits::cpu.inst 145341690 # number of demand (read+write) hits 325system.cpu.icache.demand_hits::total 145341690 # number of demand (read+write) hits 326system.cpu.icache.overall_hits::cpu.inst 145341690 # number of overall hits 327system.cpu.icache.overall_hits::total 145341690 # number of overall hits 328system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses 329system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses 330system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses 331system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses 332system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses 333system.cpu.icache.overall_misses::total 1699524 # number of overall misses 334system.cpu.icache.ReadReq_accesses::cpu.inst 147041214 # number of ReadReq accesses(hits+misses) 335system.cpu.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses) 336system.cpu.icache.demand_accesses::cpu.inst 147041214 # number of demand (read+write) accesses 337system.cpu.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses 338system.cpu.icache.overall_accesses::cpu.inst 147041214 # number of overall (read+write) accesses 339system.cpu.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses 340system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses 341system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses 342system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses 343system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses 344system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses 345system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses 346system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 347system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 348system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 351system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 352system.cpu.icache.fast_writes 0 # number of fast writes performed 353system.cpu.icache.cache_copies 0 # number of cache copies performed 354system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 355system.cpu.l2cache.tags.replacements 110027 # number of replacements 356system.cpu.l2cache.tags.tagsinuse 65155.314992 # Cycle average of tags in use 357system.cpu.l2cache.tags.total_refs 2727662 # Total number of references to valid blocks. 358system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. 359system.cpu.l2cache.tags.avg_refs 15.559256 # Average number of references to valid blocks. 360system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 361system.cpu.l2cache.tags.occ_blocks::writebacks 48893.413815 # Average occupied blocks per requestor 362system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor 363system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor 364system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654834 # Average occupied blocks per requestor 365system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.310003 # Average occupied blocks per requestor 366system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy 367system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 368system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 369system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy 370system.cpu.l2cache.tags.occ_percent::cpu.data 0.109776 # Average percentage of cache occupancy 371system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy 372system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 373system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id 374system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 375system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 376system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id 377system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id 378system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id 379system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id 380system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 381system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id 382system.cpu.l2cache.tags.tag_accesses 26202418 # Number of tag accesses 383system.cpu.l2cache.tags.data_accesses 26202418 # Number of data accesses 384system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits 385system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits 386system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits 387system.cpu.l2cache.ReadReq_hits::cpu.data 505483 # number of ReadReq hits 388system.cpu.l2cache.ReadReq_hits::total 2197850 # number of ReadReq hits 389system.cpu.l2cache.Writeback_hits::writebacks 682037 # number of Writeback hits 390system.cpu.l2cache.Writeback_hits::total 682037 # number of Writeback hits 391system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 392system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 393system.cpu.l2cache.ReadExReq_hits::cpu.data 151043 # number of ReadExReq hits 394system.cpu.l2cache.ReadExReq_hits::total 151043 # number of ReadExReq hits 395system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits 396system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits 397system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits 398system.cpu.l2cache.demand_hits::cpu.data 656526 # number of demand (read+write) hits 399system.cpu.l2cache.demand_hits::total 2348893 # number of demand (read+write) hits 400system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits 401system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits 402system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits 403system.cpu.l2cache.overall_hits::cpu.data 656526 # number of overall hits 404system.cpu.l2cache.overall_hits::total 2348893 # number of overall hits 405system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 406system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 407system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses 408system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses 409system.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses 410system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses 411system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses 412system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 413system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 414system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses 415system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses 416system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 417system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 418system.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses 419system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses 420system.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses 421system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 422system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 423system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses 424system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses 425system.cpu.l2cache.overall_misses::total 181765 # number of overall misses 426system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) 427system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) 428system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses) 429system.cpu.l2cache.ReadReq_accesses::cpu.data 521017 # number of ReadReq accesses(hits+misses) 430system.cpu.l2cache.ReadReq_accesses::total 2231751 # number of ReadReq accesses(hits+misses) 431system.cpu.l2cache.Writeback_accesses::writebacks 682037 # number of Writeback accesses(hits+misses) 432system.cpu.l2cache.Writeback_accesses::total 682037 # number of Writeback accesses(hits+misses) 433system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) 434system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) 435system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 436system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 437system.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) 438system.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) 439system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses 440system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses 441system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses 442system.cpu.l2cache.demand_accesses::cpu.data 819924 # number of demand (read+write) accesses 443system.cpu.l2cache.demand_accesses::total 2530658 # number of demand (read+write) accesses 444system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses 445system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses 446system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses 447system.cpu.l2cache.overall_accesses::cpu.data 819924 # number of overall (read+write) accesses 448system.cpu.l2cache.overall_accesses::total 2530658 # number of overall (read+write) accesses 449system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses 450system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses 451system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses 452system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses 453system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses 454system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses 455system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses 456system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 457system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 458system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494682 # miss rate for ReadExReq accesses 459system.cpu.l2cache.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses 460system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses 461system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses 462system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses 463system.cpu.l2cache.demand_miss_rate::cpu.data 0.199284 # miss rate for demand accesses 464system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses 465system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses 466system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses 467system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses 468system.cpu.l2cache.overall_miss_rate::cpu.data 0.199284 # miss rate for overall accesses 469system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses 470system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 471system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 472system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 473system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 474system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 475system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 476system.cpu.l2cache.fast_writes 0 # number of fast writes performed 477system.cpu.l2cache.cache_copies 0 # number of cache copies performed 478system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks 479system.cpu.l2cache.writebacks::total 101899 # number of writebacks 480system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 481system.cpu.toL2Bus.trans_dist::ReadReq 2288348 # Transaction distribution 482system.cpu.toL2Bus.trans_dist::ReadResp 2288348 # Transaction distribution 483system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution 484system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution 485system.cpu.toL2Bus.trans_dist::Writeback 682037 # Transaction distribution 486system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution 487system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 488system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution 489system.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution 490system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution 491system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes) 492system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444665 # Packet count per connected master and slave (bytes) 493system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) 494system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) 495system.cpu.toL2Bus.pkt_count::total 5917183 # Packet count per connected master and slave (bytes) 496system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) 497system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308299 # Cumulative packet size per connected master and slave (bytes) 498system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) 499system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) 500system.cpu.toL2Bus.pkt_size::total 205224775 # Cumulative packet size per connected master and slave (bytes) 501system.cpu.toL2Bus.snoops 36632 # Total snoops (count) 502system.cpu.toL2Bus.snoop_fanout::samples 3268420 # Request fanout histogram 503system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram 504system.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram 505system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 506system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 507system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 508system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 509system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 510system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 511system.cpu.toL2Bus.snoop_fanout::5 3231956 98.88% 98.88% # Request fanout histogram 512system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram 513system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 514system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 515system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 516system.cpu.toL2Bus.snoop_fanout::total 3268420 # Request fanout histogram 517system.iobus.trans_dist::ReadReq 30171 # Transaction distribution 518system.iobus.trans_dist::ReadResp 30171 # Transaction distribution 519system.iobus.trans_dist::WriteReq 59016 # Transaction distribution 520system.iobus.trans_dist::WriteResp 22792 # Transaction distribution 521system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 522system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) 523system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 524system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 525system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 526system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 527system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 528system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 529system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 530system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 531system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 532system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 533system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 534system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 535system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 536system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 537system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 538system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 539system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 540system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 541system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 542system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 543system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) 544system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) 545system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) 546system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) 547system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) 548system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 549system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 550system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 551system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 552system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 553system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 554system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 555system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 556system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 557system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 558system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 559system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 560system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 561system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 562system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 563system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 564system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 565system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 566system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 567system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 568system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) 569system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) 570system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) 571system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) 572system.iocache.tags.replacements 36430 # number of replacements 573system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use 574system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 575system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. 576system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 577system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. 578system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor 579system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy 580system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy 581system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 582system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 583system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 584system.iocache.tags.tag_accesses 328176 # Number of tag accesses 585system.iocache.tags.data_accesses 328176 # Number of data accesses 586system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 587system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 588system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses 589system.iocache.ReadReq_misses::total 240 # number of ReadReq misses 590system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses 591system.iocache.demand_misses::total 240 # number of demand (read+write) misses 592system.iocache.overall_misses::realview.ide 240 # number of overall misses 593system.iocache.overall_misses::total 240 # number of overall misses 594system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) 595system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) 596system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 597system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 598system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses 599system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses 600system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses 601system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses 602system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 603system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 604system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 605system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 606system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 607system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 608system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 609system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 610system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 611system.iocache.blocked::no_targets 0 # number of cycles access was blocked 612system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 613system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 614system.iocache.fast_writes 36224 # number of fast writes performed 615system.iocache.cache_copies 0 # number of cache copies performed 616system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 617system.membus.trans_dist::ReadReq 74235 # Transaction distribution 618system.membus.trans_dist::ReadResp 74235 # Transaction distribution 619system.membus.trans_dist::WriteReq 27560 # Transaction distribution 620system.membus.trans_dist::WriteResp 27560 # Transaction distribution 621system.membus.trans_dist::Writeback 101899 # Transaction distribution 622system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 623system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 624system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution 625system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 626system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution 627system.membus.trans_dist::ReadExReq 146085 # Transaction distribution 628system.membus.trans_dist::ReadExResp 146085 # Transaction distribution 629system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) 630system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 631system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) 632system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes) 633system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes) 634system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) 635system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) 636system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes) 637system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) 638system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 639system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) 640system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes) 641system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes) 642system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) 643system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) 644system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes) 645system.membus.snoops 0 # Total snoops (count) 646system.membus.snoop_fanout::samples 322858 # Request fanout histogram 647system.membus.snoop_fanout::mean 1 # Request fanout histogram 648system.membus.snoop_fanout::stdev 0 # Request fanout histogram 649system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 650system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 651system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram 652system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 653system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 654system.membus.snoop_fanout::min_value 1 # Request fanout histogram 655system.membus.snoop_fanout::max_value 1 # Request fanout histogram 656system.membus.snoop_fanout::total 322858 # Request fanout histogram 657system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 658system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 659system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 660system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 661system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 662system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 663system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 664system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 665system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 666system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 667system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 668system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 669system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 670system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 671system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 672system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 673system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 674system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 675system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 676system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 677system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 678system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 679system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 680system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 681system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 682system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 683system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 684system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 685system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 686system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 687system.realview.ethernet.droppedPackets 0 # number of packets dropped 688 689---------- End Simulation Statistics ---------- 690