stats.txt revision 10517:ba51f8572571
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.783854 # Number of seconds simulated 4sim_ticks 2783854177000 # Number of ticks simulated 5final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1378246 # Simulator instruction rate (inst/s) 8host_op_rate 1677793 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 26874016957 # Simulator tick rate (ticks/s) 10host_mem_usage 553624 # Number of bytes of host memory used 11host_seconds 103.59 # Real time elapsed on the host 12sim_insts 142771179 # Number of instructions simulated 13sim_ops 173800939 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory 25system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 27system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory 28system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory 35system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 36system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 37system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory 38system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) 46system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) 49system.physmem.bw_write::total 3181703 # Write bandwidth from this memory (bytes/s) 50system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s) 56system.physmem.bw_total::total 7333647 # Total bandwidth to/from this memory (bytes/s) 57system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 58system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 59system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 60system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 61system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 62system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 63system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 64system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 65system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 66system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 67system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 68system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 69system.membus.trans_dist::ReadReq 74235 # Transaction distribution 70system.membus.trans_dist::ReadResp 74235 # Transaction distribution 71system.membus.trans_dist::WriteReq 27560 # Transaction distribution 72system.membus.trans_dist::WriteResp 27560 # Transaction distribution 73system.membus.trans_dist::Writeback 101899 # Transaction distribution 74system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 75system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 76system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution 77system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 78system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution 79system.membus.trans_dist::ReadExReq 146085 # Transaction distribution 80system.membus.trans_dist::ReadExResp 146085 # Transaction distribution 81system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) 82system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 83system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) 84system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes) 85system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes) 86system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) 87system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) 88system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes) 89system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) 90system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 91system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) 92system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes) 93system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes) 94system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) 95system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) 96system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes) 97system.membus.snoops 0 # Total snoops (count) 98system.membus.snoop_fanout::samples 322858 # Request fanout histogram 99system.membus.snoop_fanout::mean 1 # Request fanout histogram 100system.membus.snoop_fanout::stdev 0 # Request fanout histogram 101system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 102system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 103system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram 104system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 105system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 106system.membus.snoop_fanout::min_value 1 # Request fanout histogram 107system.membus.snoop_fanout::max_value 1 # Request fanout histogram 108system.membus.snoop_fanout::total 322858 # Request fanout histogram 109system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 110system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 111system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 112system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 113system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 114system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 115system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 116system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 117system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 118system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 119system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 120system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 121system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 122system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 123system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 124system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 125system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 126system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 127system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 128system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 129system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 130system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 131system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 132system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 133system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 134system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 135system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 136system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 137system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 138system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 139system.realview.ethernet.droppedPackets 0 # number of packets dropped 140system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 141system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 142system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 143system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 144system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 145system.cf0.dma_write_txs 631 # Number of DMA write transactions. 146system.iobus.trans_dist::ReadReq 30171 # Transaction distribution 147system.iobus.trans_dist::ReadResp 30171 # Transaction distribution 148system.iobus.trans_dist::WriteReq 59016 # Transaction distribution 149system.iobus.trans_dist::WriteResp 22792 # Transaction distribution 150system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 151system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) 152system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 153system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 154system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 155system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 156system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 157system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 158system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 159system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 160system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 161system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 162system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 163system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 164system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 165system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 166system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 167system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 168system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 169system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 170system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 171system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 172system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) 173system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) 174system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) 175system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) 176system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) 177system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 178system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 179system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 180system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 181system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 182system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 183system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 184system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 185system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 186system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 187system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 188system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 189system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 190system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 191system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 192system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 193system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 194system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 195system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 196system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 197system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) 198system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) 199system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) 200system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) 201system.cpu_clk_domain.clock 500 # Clock period in ticks 202system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 203system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 204system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 205system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 206system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 207system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 208system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 209system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 210system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 211system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 212system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 213system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 214system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 215system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 216system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 217system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 218system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 219system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 220system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 221system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 222system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 223system.cpu.dtb.inst_hits 0 # ITB inst hits 224system.cpu.dtb.inst_misses 0 # ITB inst misses 225system.cpu.dtb.read_hits 31525864 # DTB read hits 226system.cpu.dtb.read_misses 8580 # DTB read misses 227system.cpu.dtb.write_hits 23124034 # DTB write hits 228system.cpu.dtb.write_misses 1448 # DTB write misses 229system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 230system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 231system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 232system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 233system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 234system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 235system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 236system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 237system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 238system.cpu.dtb.read_accesses 31534444 # DTB read accesses 239system.cpu.dtb.write_accesses 23125482 # DTB write accesses 240system.cpu.dtb.inst_accesses 0 # ITB inst accesses 241system.cpu.dtb.hits 54649898 # DTB hits 242system.cpu.dtb.misses 10028 # DTB misses 243system.cpu.dtb.accesses 54659926 # DTB accesses 244system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 245system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 246system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 247system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 248system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 249system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 250system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 251system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 252system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 253system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 254system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 255system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 256system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 257system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 258system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 259system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 260system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 261system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 262system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 263system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 264system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 265system.cpu.itb.inst_hits 147037671 # ITB inst hits 266system.cpu.itb.inst_misses 4762 # ITB inst misses 267system.cpu.itb.read_hits 0 # DTB read hits 268system.cpu.itb.read_misses 0 # DTB read misses 269system.cpu.itb.write_hits 0 # DTB write hits 270system.cpu.itb.write_misses 0 # DTB write misses 271system.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 272system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 273system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 274system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 275system.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 276system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 277system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 278system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 279system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 280system.cpu.itb.read_accesses 0 # DTB read accesses 281system.cpu.itb.write_accesses 0 # DTB write accesses 282system.cpu.itb.inst_accesses 147042433 # ITB inst accesses 283system.cpu.itb.hits 147037671 # DTB hits 284system.cpu.itb.misses 4762 # DTB misses 285system.cpu.itb.accesses 147042433 # DTB accesses 286system.cpu.numCycles 5567711435 # number of cpu cycles simulated 287system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 288system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 289system.cpu.committedInsts 142771179 # Number of instructions committed 290system.cpu.committedOps 173800939 # Number of ops (including micro ops) committed 291system.cpu.num_int_alu_accesses 153160639 # Number of integer alu accesses 292system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 293system.cpu.num_func_calls 16873782 # number of times a function call or return occured 294system.cpu.num_conditional_control_insts 18730247 # number of instructions that are conditional controls 295system.cpu.num_int_insts 153160639 # number of integer instructions 296system.cpu.num_fp_insts 11484 # number of float instructions 297system.cpu.num_int_register_reads 285056343 # number of times the integer registers were read 298system.cpu.num_int_register_writes 107177999 # number of times the integer registers were written 299system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 300system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 301system.cpu.num_cc_register_reads 530847533 # number of times the CC registers were read 302system.cpu.num_cc_register_writes 62363805 # number of times the CC registers were written 303system.cpu.num_mem_refs 55938446 # number of memory refs 304system.cpu.num_load_insts 31855497 # Number of load instructions 305system.cpu.num_store_insts 24082949 # Number of store instructions 306system.cpu.num_idle_cycles 5389630153.939368 # Number of idle cycles 307system.cpu.num_busy_cycles 178081281.060631 # Number of busy cycles 308system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles 309system.cpu.idle_fraction 0.968015 # Percentage of idle cycles 310system.cpu.Branches 36396779 # Number of branches fetched 311system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 312system.cpu.op_class::IntAlu 121151526 68.36% 68.36% # Class of executed instruction 313system.cpu.op_class::IntMult 116878 0.07% 68.43% # Class of executed instruction 314system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction 315system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction 316system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction 317system.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction 318system.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction 319system.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction 320system.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction 321system.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction 322system.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction 323system.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction 324system.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction 325system.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction 326system.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction 327system.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction 328system.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction 329system.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction 330system.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction 331system.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction 332system.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction 333system.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction 334system.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction 335system.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction 336system.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction 337system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction 338system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction 339system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction 340system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 341system.cpu.op_class::MemRead 31855497 17.98% 86.41% # Class of executed instruction 342system.cpu.op_class::MemWrite 24082949 13.59% 100.00% # Class of executed instruction 343system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 344system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 345system.cpu.op_class::total 177217756 # Class of executed instruction 346system.cpu.kern.inst.arm 0 # number of arm instructions executed 347system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed 348system.cpu.icache.tags.replacements 1699006 # number of replacements 349system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use 350system.cpu.icache.tags.total_refs 145341254 # Total number of references to valid blocks. 351system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. 352system.cpu.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks. 353system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. 354system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor 355system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy 356system.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy 357system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 358system.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 359system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 362system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 363system.cpu.icache.tags.tag_accesses 148740302 # Number of tag accesses 364system.cpu.icache.tags.data_accesses 148740302 # Number of data accesses 365system.cpu.icache.ReadReq_hits::cpu.inst 145341254 # number of ReadReq hits 366system.cpu.icache.ReadReq_hits::total 145341254 # number of ReadReq hits 367system.cpu.icache.demand_hits::cpu.inst 145341254 # number of demand (read+write) hits 368system.cpu.icache.demand_hits::total 145341254 # number of demand (read+write) hits 369system.cpu.icache.overall_hits::cpu.inst 145341254 # number of overall hits 370system.cpu.icache.overall_hits::total 145341254 # number of overall hits 371system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses 372system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses 373system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses 374system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses 375system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses 376system.cpu.icache.overall_misses::total 1699524 # number of overall misses 377system.cpu.icache.ReadReq_accesses::cpu.inst 147040778 # number of ReadReq accesses(hits+misses) 378system.cpu.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses) 379system.cpu.icache.demand_accesses::cpu.inst 147040778 # number of demand (read+write) accesses 380system.cpu.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses 381system.cpu.icache.overall_accesses::cpu.inst 147040778 # number of overall (read+write) accesses 382system.cpu.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses 383system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses 384system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses 385system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses 386system.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses 387system.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses 388system.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses 389system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.icache.fast_writes 0 # number of fast writes performed 396system.cpu.icache.cache_copies 0 # number of cache copies performed 397system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 398system.cpu.l2cache.tags.replacements 110027 # number of replacements 399system.cpu.l2cache.tags.tagsinuse 65155.315047 # Cycle average of tags in use 400system.cpu.l2cache.tags.total_refs 2727658 # Total number of references to valid blocks. 401system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. 402system.cpu.l2cache.tags.avg_refs 15.559233 # Average number of references to valid blocks. 403system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 404system.cpu.l2cache.tags.occ_blocks::writebacks 48893.414337 # Average occupied blocks per requestor 405system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor 406system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor 407system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654547 # Average occupied blocks per requestor 408system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309824 # Average occupied blocks per requestor 409system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy 410system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 411system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 412system.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy 413system.cpu.l2cache.tags.occ_percent::cpu.data 0.109776 # Average percentage of cache occupancy 414system.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy 415system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 416system.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id 417system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 418system.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 419system.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id 420system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id 421system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id 422system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id 423system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 424system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id 425system.cpu.l2cache.tags.tag_accesses 26202377 # Number of tag accesses 426system.cpu.l2cache.tags.data_accesses 26202377 # Number of data accesses 427system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits 428system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits 429system.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits 430system.cpu.l2cache.ReadReq_hits::cpu.data 505480 # number of ReadReq hits 431system.cpu.l2cache.ReadReq_hits::total 2197847 # number of ReadReq hits 432system.cpu.l2cache.Writeback_hits::writebacks 682036 # number of Writeback hits 433system.cpu.l2cache.Writeback_hits::total 682036 # number of Writeback hits 434system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 435system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 436system.cpu.l2cache.ReadExReq_hits::cpu.data 151042 # number of ReadExReq hits 437system.cpu.l2cache.ReadExReq_hits::total 151042 # number of ReadExReq hits 438system.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits 439system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits 440system.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits 441system.cpu.l2cache.demand_hits::cpu.data 656522 # number of demand (read+write) hits 442system.cpu.l2cache.demand_hits::total 2348889 # number of demand (read+write) hits 443system.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits 444system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits 445system.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits 446system.cpu.l2cache.overall_hits::cpu.data 656522 # number of overall hits 447system.cpu.l2cache.overall_hits::total 2348889 # number of overall hits 448system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 449system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 450system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses 451system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses 452system.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses 453system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses 454system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses 455system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 456system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 457system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses 458system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses 459system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 460system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 461system.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses 462system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses 463system.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses 464system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 465system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 466system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses 467system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses 468system.cpu.l2cache.overall_misses::total 181765 # number of overall misses 469system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) 470system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) 471system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses) 472system.cpu.l2cache.ReadReq_accesses::cpu.data 521014 # number of ReadReq accesses(hits+misses) 473system.cpu.l2cache.ReadReq_accesses::total 2231748 # number of ReadReq accesses(hits+misses) 474system.cpu.l2cache.Writeback_accesses::writebacks 682036 # number of Writeback accesses(hits+misses) 475system.cpu.l2cache.Writeback_accesses::total 682036 # number of Writeback accesses(hits+misses) 476system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) 477system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) 478system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 479system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 480system.cpu.l2cache.ReadExReq_accesses::cpu.data 298906 # number of ReadExReq accesses(hits+misses) 481system.cpu.l2cache.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses) 482system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses 483system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses 484system.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses 485system.cpu.l2cache.demand_accesses::cpu.data 819920 # number of demand (read+write) accesses 486system.cpu.l2cache.demand_accesses::total 2530654 # number of demand (read+write) accesses 487system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses 488system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses 489system.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses 490system.cpu.l2cache.overall_accesses::cpu.data 819920 # number of overall (read+write) accesses 491system.cpu.l2cache.overall_accesses::total 2530654 # number of overall (read+write) accesses 492system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses 493system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses 494system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses 495system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses 496system.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses 497system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses 498system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses 499system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 500system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 501system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494684 # miss rate for ReadExReq accesses 502system.cpu.l2cache.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses 503system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses 504system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses 505system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses 506system.cpu.l2cache.demand_miss_rate::cpu.data 0.199285 # miss rate for demand accesses 507system.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses 508system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses 509system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses 510system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses 511system.cpu.l2cache.overall_miss_rate::cpu.data 0.199285 # miss rate for overall accesses 512system.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses 513system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 516system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 517system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 518system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 519system.cpu.l2cache.fast_writes 0 # number of fast writes performed 520system.cpu.l2cache.cache_copies 0 # number of cache copies performed 521system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks 522system.cpu.l2cache.writebacks::total 101899 # number of writebacks 523system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 524system.cpu.dcache.tags.replacements 819392 # number of replacements 525system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 526system.cpu.dcache.tags.total_refs 53783694 # Total number of references to valid blocks. 527system.cpu.dcache.tags.sampled_refs 819904 # Sample count of references to valid blocks. 528system.cpu.dcache.tags.avg_refs 65.597550 # Average number of references to valid blocks. 529system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 530system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 531system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 532system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 533system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 534system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 535system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 536system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 537system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 538system.cpu.dcache.tags.tag_accesses 219234376 # Number of tag accesses 539system.cpu.dcache.tags.data_accesses 219234376 # Number of data accesses 540system.cpu.dcache.ReadReq_hits::cpu.data 30128707 # number of ReadReq hits 541system.cpu.dcache.ReadReq_hits::total 30128707 # number of ReadReq hits 542system.cpu.dcache.WriteReq_hits::cpu.data 22339708 # number of WriteReq hits 543system.cpu.dcache.WriteReq_hits::total 22339708 # number of WriteReq hits 544system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits 545system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits 546system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits 547system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits 548system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits 549system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits 550system.cpu.dcache.demand_hits::cpu.data 52468415 # number of demand (read+write) hits 551system.cpu.dcache.demand_hits::total 52468415 # number of demand (read+write) hits 552system.cpu.dcache.overall_hits::cpu.data 52863480 # number of overall hits 553system.cpu.dcache.overall_hits::total 52863480 # number of overall hits 554system.cpu.dcache.ReadReq_misses::cpu.data 396282 # number of ReadReq misses 555system.cpu.dcache.ReadReq_misses::total 396282 # number of ReadReq misses 556system.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses 557system.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses 558system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses 559system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses 560system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses 561system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses 562system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 563system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 564system.cpu.dcache.demand_misses::cpu.data 697944 # number of demand (read+write) misses 565system.cpu.dcache.demand_misses::total 697944 # number of demand (read+write) misses 566system.cpu.dcache.overall_misses::cpu.data 814065 # number of overall misses 567system.cpu.dcache.overall_misses::total 814065 # number of overall misses 568system.cpu.dcache.ReadReq_accesses::cpu.data 30524989 # number of ReadReq accesses(hits+misses) 569system.cpu.dcache.ReadReq_accesses::total 30524989 # number of ReadReq accesses(hits+misses) 570system.cpu.dcache.WriteReq_accesses::cpu.data 22641370 # number of WriteReq accesses(hits+misses) 571system.cpu.dcache.WriteReq_accesses::total 22641370 # number of WriteReq accesses(hits+misses) 572system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) 573system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) 574system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) 575system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) 576system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) 577system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) 578system.cpu.dcache.demand_accesses::cpu.data 53166359 # number of demand (read+write) accesses 579system.cpu.dcache.demand_accesses::total 53166359 # number of demand (read+write) accesses 580system.cpu.dcache.overall_accesses::cpu.data 53677545 # number of overall (read+write) accesses 581system.cpu.dcache.overall_accesses::total 53677545 # number of overall (read+write) accesses 582system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses 583system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses 584system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses 585system.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses 586system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses 587system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses 588system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses 589system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses 590system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 591system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 592system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses 593system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses 594system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses 595system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses 596system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 597system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 598system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 599system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 600system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 601system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 602system.cpu.dcache.fast_writes 0 # number of fast writes performed 603system.cpu.dcache.cache_copies 0 # number of cache copies performed 604system.cpu.dcache.writebacks::writebacks 682036 # number of writebacks 605system.cpu.dcache.writebacks::total 682036 # number of writebacks 606system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 607system.cpu.toL2Bus.trans_dist::ReadReq 2288345 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution 610system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution 611system.cpu.toL2Bus.trans_dist::Writeback 682036 # Transaction distribution 612system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution 613system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 614system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution 615system.cpu.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution 616system.cpu.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution 617system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes) 618system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444656 # Packet count per connected master and slave (bytes) 619system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) 620system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) 621system.cpu.toL2Bus.pkt_count::total 5917174 # Packet count per connected master and slave (bytes) 622system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) 623system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96307979 # Cumulative packet size per connected master and slave (bytes) 624system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) 625system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) 626system.cpu.toL2Bus.pkt_size::total 205224455 # Cumulative packet size per connected master and slave (bytes) 627system.cpu.toL2Bus.snoops 36632 # Total snoops (count) 628system.cpu.toL2Bus.snoop_fanout::samples 3268415 # Request fanout histogram 629system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram 630system.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram 631system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 632system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 633system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 634system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 635system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 636system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 637system.cpu.toL2Bus.snoop_fanout::5 3231951 98.88% 98.88% # Request fanout histogram 638system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram 639system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 640system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 641system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 642system.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram 643system.iocache.tags.replacements 36430 # number of replacements 644system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use 645system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 646system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. 647system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 648system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. 649system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor 650system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy 651system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy 652system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 653system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 654system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 655system.iocache.tags.tag_accesses 328176 # Number of tag accesses 656system.iocache.tags.data_accesses 328176 # Number of data accesses 657system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 658system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 659system.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses 660system.iocache.ReadReq_misses::total 240 # number of ReadReq misses 661system.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses 662system.iocache.demand_misses::total 240 # number of demand (read+write) misses 663system.iocache.overall_misses::realview.ide 240 # number of overall misses 664system.iocache.overall_misses::total 240 # number of overall misses 665system.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) 666system.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) 667system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 668system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 669system.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses 670system.iocache.demand_accesses::total 240 # number of demand (read+write) accesses 671system.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses 672system.iocache.overall_accesses::total 240 # number of overall (read+write) accesses 673system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 674system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 675system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 676system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 677system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 678system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 679system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 680system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 681system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 682system.iocache.blocked::no_targets 0 # number of cycles access was blocked 683system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 684system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 685system.iocache.fast_writes 36224 # number of fast writes performed 686system.iocache.cache_copies 0 # number of cache copies performed 687system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 688 689---------- End Simulation Statistics ---------- 690