stats.txt revision 9962:7aef35367a21
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.912097 # Number of seconds simulated 4sim_ticks 912096763500 # Number of ticks simulated 5final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1640213 # Simulator instruction rate (inst/s) 8host_op_rate 2111770 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 24275992963 # Simulator tick rate (ticks/s) 10host_mem_usage 394600 # Number of bytes of host memory used 11host_seconds 37.57 # Real time elapsed on the host 12sim_insts 61625970 # Number of instructions simulated 13sim_ops 79343340 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory 22system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory 26system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory 27system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory 29system.physmem.bytes_written::total 7222864 # Number of bytes written to this memory 30system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 822331 # Number of write requests responded to by this memory 43system.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s) 55system.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) 59system.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) 67system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) 68system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s) 69system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 70system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 71system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 72system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 73system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 74system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 75system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 76system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 77system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 78system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 83system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 84system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 85system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 86system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 87system.membus.throughput 64986577 # Throughput (bytes/s) 88system.membus.data_through_bus 59274047 # Total data (bytes) 89system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 90system.l2c.tags.replacements 70658 # number of replacements 91system.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use 92system.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. 93system.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. 94system.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. 95system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 96system.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor 97system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor 98system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor 99system.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor 100system.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor 101system.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor 102system.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor 103system.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor 104system.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy 105system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 106system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 107system.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy 108system.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy 109system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 110system.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy 111system.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy 112system.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy 113system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits 114system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits 115system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits 116system.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits 118system.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits 119system.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits 120system.l2c.ReadReq_hits::cpu1.data 169511 # number of ReadReq hits 121system.l2c.ReadReq_hits::total 1209106 # number of ReadReq hits 122system.l2c.Writeback_hits::writebacks 567807 # number of Writeback hits 123system.l2c.Writeback_hits::total 567807 # number of Writeback hits 124system.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits 125system.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits 126system.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits 127system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits 128system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits 129system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits 130system.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits 131system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits 132system.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits 133system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits 134system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits 135system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits 136system.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits 138system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits 139system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits 140system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits 141system.l2c.demand_hits::total 1317466 # number of demand (read+write) hits 142system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits 143system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits 144system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits 145system.l2c.overall_hits::cpu0.data 233336 # number of overall hits 146system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits 147system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits 148system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits 149system.l2c.overall_hits::cpu1.data 219723 # number of overall hits 150system.l2c.overall_hits::total 1317466 # number of overall hits 151system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 152system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 153system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses 154system.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses 155system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 156system.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses 157system.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses 158system.l2c.ReadReq_misses::total 22454 # number of ReadReq misses 159system.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses 160system.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses 161system.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses 162system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses 163system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses 164system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses 165system.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses 166system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses 167system.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses 168system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 169system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 170system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses 171system.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses 172system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 173system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses 174system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses 175system.l2c.demand_misses::total 163290 # number of demand (read+write) misses 176system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 177system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 178system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses 179system.l2c.overall_misses::cpu0.data 98856 # number of overall misses 180system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 181system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses 182system.l2c.overall_misses::cpu1.data 53648 # number of overall misses 183system.l2c.overall_misses::total 163290 # number of overall misses 184system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) 185system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) 186system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) 187system.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses) 188system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses) 189system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses) 190system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses) 191system.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses) 192system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) 193system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) 194system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) 195system.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses) 196system.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses) 197system.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses) 198system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) 199system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) 200system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) 201system.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses) 202system.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses) 203system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses) 204system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses 205system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses 206system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses 207system.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses 208system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses 209system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses 210system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses 211system.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses 212system.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses 213system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses 214system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses 215system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses 216system.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses 217system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses 218system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses 219system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses 220system.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses 221system.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses 222system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses 223system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses 224system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses 225system.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses 226system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses 227system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses 228system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses 229system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses 230system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses 231system.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses 232system.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses 233system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses 234system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses 235system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses 236system.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses 237system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses 238system.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses 239system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses 240system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses 241system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses 242system.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses 243system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses 244system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses 245system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses 246system.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses 247system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses 248system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses 249system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses 250system.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses 251system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses 252system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses 253system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses 254system.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses 255system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 256system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 257system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 258system.l2c.blocked::no_targets 0 # number of cycles access was blocked 259system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 260system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 261system.l2c.fast_writes 0 # number of fast writes performed 262system.l2c.cache_copies 0 # number of cache copies performed 263system.l2c.writebacks::writebacks 65559 # number of writebacks 264system.l2c.writebacks::total 65559 # number of writebacks 265system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 266system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 267system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 268system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 269system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 270system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 271system.cf0.dma_write_txs 0 # Number of DMA write transactions. 272system.toL2Bus.throughput 154009014 # Throughput (bytes/s) 273system.toL2Bus.data_through_bus 140471123 # Total data (bytes) 274system.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 275system.iobus.throughput 45730949 # Throughput (bytes/s) 276system.iobus.data_through_bus 41711051 # Total data (bytes) 277system.cpu0.dtb.inst_hits 0 # ITB inst hits 278system.cpu0.dtb.inst_misses 0 # ITB inst misses 279system.cpu0.dtb.read_hits 7975768 # DTB read hits 280system.cpu0.dtb.read_misses 3611 # DTB read misses 281system.cpu0.dtb.write_hits 5966574 # DTB write hits 282system.cpu0.dtb.write_misses 672 # DTB write misses 283system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 284system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 285system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 286system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 287system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB 288system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 289system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch 290system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 291system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 292system.cpu0.dtb.read_accesses 7979379 # DTB read accesses 293system.cpu0.dtb.write_accesses 5967246 # DTB write accesses 294system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 295system.cpu0.dtb.hits 13942342 # DTB hits 296system.cpu0.dtb.misses 4283 # DTB misses 297system.cpu0.dtb.accesses 13946625 # DTB accesses 298system.cpu0.itb.inst_hits 30238804 # ITB inst hits 299system.cpu0.itb.inst_misses 2175 # ITB inst misses 300system.cpu0.itb.read_hits 0 # DTB read hits 301system.cpu0.itb.read_misses 0 # DTB read misses 302system.cpu0.itb.write_hits 0 # DTB write hits 303system.cpu0.itb.write_misses 0 # DTB write misses 304system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 305system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 306system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 307system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 308system.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB 309system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 310system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 311system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 312system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 313system.cpu0.itb.read_accesses 0 # DTB read accesses 314system.cpu0.itb.write_accesses 0 # DTB write accesses 315system.cpu0.itb.inst_accesses 30240979 # ITB inst accesses 316system.cpu0.itb.hits 30238804 # DTB hits 317system.cpu0.itb.misses 2175 # DTB misses 318system.cpu0.itb.accesses 30240979 # DTB accesses 319system.cpu0.numCycles 1823633059 # number of cpu cycles simulated 320system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 321system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 322system.cpu0.committedInsts 29750005 # Number of instructions committed 323system.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed 324system.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses 325system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses 326system.cpu0.num_func_calls 1241903 # number of times a function call or return occured 327system.cpu0.num_conditional_control_insts 4044057 # number of instructions that are conditional controls 328system.cpu0.num_int_insts 34471201 # number of integer instructions 329system.cpu0.num_fp_insts 5449 # number of float instructions 330system.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read 331system.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written 332system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read 333system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written 334system.cpu0.num_mem_refs 14626951 # number of memory refs 335system.cpu0.num_load_insts 8357226 # Number of load instructions 336system.cpu0.num_store_insts 6269725 # Number of store instructions 337system.cpu0.num_idle_cycles 1783968822.941743 # Number of idle cycles 338system.cpu0.num_busy_cycles 39664236.058257 # Number of busy cycles 339system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles 340system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles 341system.cpu0.kern.inst.arm 0 # number of arm instructions executed 342system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed 343system.cpu0.icache.tags.replacements 428546 # number of replacements 344system.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use 345system.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks. 346system.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. 347system.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks. 348system.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. 349system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor 350system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy 351system.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy 352system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits 353system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits 354system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits 355system.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits 356system.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits 357system.cpu0.icache.overall_hits::total 29811115 # number of overall hits 358system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses 359system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses 360system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses 361system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses 362system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses 363system.cpu0.icache.overall_misses::total 429059 # number of overall misses 364system.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses) 365system.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses) 366system.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses 367system.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses 368system.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses 369system.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses 370system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses 371system.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses 372system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses 373system.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses 374system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses 375system.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses 376system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 380system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 381system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 382system.cpu0.icache.fast_writes 0 # number of fast writes performed 383system.cpu0.icache.cache_copies 0 # number of cache copies performed 384system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 385system.cpu0.dcache.tags.replacements 323609 # number of replacements 386system.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use 387system.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks. 388system.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. 389system.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks. 390system.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. 391system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor 392system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy 393system.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy 394system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits 395system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits 396system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits 397system.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits 398system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits 399system.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits 400system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits 401system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits 402system.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits 403system.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits 404system.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits 405system.cpu0.dcache.overall_hits::total 12143186 # number of overall hits 406system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses 407system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses 408system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses 409system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses 410system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses 411system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses 412system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7469 # number of StoreCondReq misses 413system.cpu0.dcache.StoreCondReq_misses::total 7469 # number of StoreCondReq misses 414system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses 415system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses 416system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses 417system.cpu0.dcache.overall_misses::total 364509 # number of overall misses 418system.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses) 419system.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses) 420system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses) 421system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) 422system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) 423system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) 424system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160649 # number of StoreCondReq accesses(hits+misses) 425system.cpu0.dcache.StoreCondReq_accesses::total 160649 # number of StoreCondReq accesses(hits+misses) 426system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses 427system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses 428system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses 429system.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses 430system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses 431system.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses 432system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses 433system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses 434system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses 435system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses 436system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046493 # miss rate for StoreCondReq accesses 437system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046493 # miss rate for StoreCondReq accesses 438system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses 439system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses 440system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses 441system.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses 442system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 443system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 444system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 445system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 446system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 447system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 448system.cpu0.dcache.fast_writes 0 # number of fast writes performed 449system.cpu0.dcache.cache_copies 0 # number of cache copies performed 450system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks 451system.cpu0.dcache.writebacks::total 300958 # number of writebacks 452system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 453system.cpu1.dtb.inst_hits 0 # ITB inst hits 454system.cpu1.dtb.inst_misses 0 # ITB inst misses 455system.cpu1.dtb.read_hits 7364781 # DTB read hits 456system.cpu1.dtb.read_misses 3705 # DTB read misses 457system.cpu1.dtb.write_hits 5489656 # DTB write hits 458system.cpu1.dtb.write_misses 1595 # DTB write misses 459system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 460system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 461system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 462system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 463system.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB 464system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 465system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch 466system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 467system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 468system.cpu1.dtb.read_accesses 7368486 # DTB read accesses 469system.cpu1.dtb.write_accesses 5491251 # DTB write accesses 470system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 471system.cpu1.dtb.hits 12854437 # DTB hits 472system.cpu1.dtb.misses 5300 # DTB misses 473system.cpu1.dtb.accesses 12859737 # DTB accesses 474system.cpu1.itb.inst_hits 32412306 # ITB inst hits 475system.cpu1.itb.inst_misses 2200 # ITB inst misses 476system.cpu1.itb.read_hits 0 # DTB read hits 477system.cpu1.itb.read_misses 0 # DTB read misses 478system.cpu1.itb.write_hits 0 # DTB write hits 479system.cpu1.itb.write_misses 0 # DTB write misses 480system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 481system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 482system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 483system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 484system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB 485system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 486system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 487system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 488system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 489system.cpu1.itb.read_accesses 0 # DTB read accesses 490system.cpu1.itb.write_accesses 0 # DTB write accesses 491system.cpu1.itb.inst_accesses 32414506 # ITB inst accesses 492system.cpu1.itb.hits 32412306 # DTB hits 493system.cpu1.itb.misses 2200 # DTB misses 494system.cpu1.itb.accesses 32414506 # DTB accesses 495system.cpu1.numCycles 1824154149 # number of cpu cycles simulated 496system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 497system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 498system.cpu1.committedInsts 31875965 # Number of instructions committed 499system.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed 500system.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses 501system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses 502system.cpu1.num_func_calls 955227 # number of times a function call or return occured 503system.cpu1.num_conditional_control_insts 4048022 # number of instructions that are conditional controls 504system.cpu1.num_int_insts 35797832 # number of integer instructions 505system.cpu1.num_fp_insts 4436 # number of float instructions 506system.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read 507system.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written 508system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read 509system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written 510system.cpu1.num_mem_refs 13370713 # number of memory refs 511system.cpu1.num_load_insts 7642673 # Number of load instructions 512system.cpu1.num_store_insts 5728040 # Number of store instructions 513system.cpu1.num_idle_cycles 1783362859.317266 # Number of idle cycles 514system.cpu1.num_busy_cycles 40791289.682734 # Number of busy cycles 515system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles 516system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles 517system.cpu1.kern.inst.arm 0 # number of arm instructions executed 518system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed 519system.cpu1.icache.tags.replacements 433942 # number of replacements 520system.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use 521system.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks. 522system.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. 523system.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks. 524system.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. 525system.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor 526system.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy 527system.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy 528system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits 529system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits 530system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits 531system.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits 532system.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits 533system.cpu1.icache.overall_hits::total 31979125 # number of overall hits 534system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses 535system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses 536system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses 537system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses 538system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses 539system.cpu1.icache.overall_misses::total 434454 # number of overall misses 540system.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses) 541system.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses) 542system.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses 543system.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses 544system.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses 545system.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses 546system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses 547system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses 548system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses 549system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses 550system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses 551system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses 552system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 553system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 555system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 557system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.cpu1.icache.fast_writes 0 # number of fast writes performed 559system.cpu1.icache.cache_copies 0 # number of cache copies performed 560system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 561system.cpu1.dcache.tags.replacements 294289 # number of replacements 562system.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use 563system.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks. 564system.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. 565system.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks. 566system.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. 567system.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor 568system.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy 569system.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy 570system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits 571system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits 572system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits 573system.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits 574system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits 575system.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits 576system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits 577system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits 578system.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits 579system.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits 580system.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits 581system.cpu1.dcache.overall_hits::total 11522522 # number of overall hits 582system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses 583system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses 584system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses 585system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses 586system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses 587system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses 588system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10139 # number of StoreCondReq misses 589system.cpu1.dcache.StoreCondReq_misses::total 10139 # number of StoreCondReq misses 590system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses 591system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses 592system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses 593system.cpu1.dcache.overall_misses::total 324195 # number of overall misses 594system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses) 595system.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses) 596system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses) 597system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) 598system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) 599system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) 600system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89169 # number of StoreCondReq accesses(hits+misses) 601system.cpu1.dcache.StoreCondReq_accesses::total 89169 # number of StoreCondReq accesses(hits+misses) 602system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses 603system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses 604system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses 605system.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses 606system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses 607system.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses 608system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses 609system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses 610system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses 611system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses 612system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113705 # miss rate for StoreCondReq accesses 613system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113705 # miss rate for StoreCondReq accesses 614system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses 615system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses 616system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses 617system.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses 618system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 619system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 620system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 621system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 622system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 623system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 624system.cpu1.dcache.fast_writes 0 # number of fast writes performed 625system.cpu1.dcache.cache_copies 0 # number of cache copies performed 626system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks 627system.cpu1.dcache.writebacks::total 266849 # number of writebacks 628system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 629system.iocache.tags.replacements 0 # number of replacements 630system.iocache.tags.tagsinuse 0 # Cycle average of tags in use 631system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 632system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 633system.iocache.tags.avg_refs nan # Average number of references to valid blocks. 634system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 635system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 636system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 637system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 638system.iocache.blocked::no_targets 0 # number of cycles access was blocked 639system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 640system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 641system.iocache.fast_writes 0 # number of fast writes performed 642system.iocache.cache_copies 0 # number of cache copies performed 643system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 644 645---------- End Simulation Statistics ---------- 646