stats.txt revision 9079:9a244ebdc3c9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.911654 # Number of seconds simulated 4sim_ticks 911653589000 # Number of ticks simulated 5final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2171864 # Simulator instruction rate (inst/s) 8host_op_rate 2807005 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32664627860 # Simulator tick rate (ticks/s) 10host_mem_usage 382740 # Number of bytes of host memory used 11host_seconds 27.91 # Real time elapsed on the host 12sim_insts 60615585 # Number of instructions simulated 13sim_ops 78342060 # Number of ops (including micro ops) simulated 14system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 15system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 16system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 17system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 18system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 19system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 20system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 21system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 22system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 23system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 24system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 25system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 26system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 27system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 28system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 29system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 30system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 31system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 33system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 34system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 35system.physmem.bytes_read::cpu0.inst 506468 # Number of bytes read from this memory 36system.physmem.bytes_read::cpu0.data 6290740 # Number of bytes read from this memory 37system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 38system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory 39system.physmem.bytes_read::cpu1.inst 210652 # Number of bytes read from this memory 40system.physmem.bytes_read::cpu1.data 3309616 # Number of bytes read from this memory 41system.physmem.bytes_read::total 49639524 # Number of bytes read from this memory 42system.physmem.bytes_inst_read::cpu0.inst 506468 # Number of instructions bytes read from this memory 43system.physmem.bytes_inst_read::cpu1.inst 210652 # Number of instructions bytes read from this memory 44system.physmem.bytes_inst_read::total 717120 # Number of instructions bytes read from this memory 45system.physmem.bytes_written::writebacks 4196032 # Number of bytes written to this memory 46system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 47system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory 48system.physmem.bytes_written::total 7223120 # Number of bytes written to this memory 49system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 50system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 51system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 52system.physmem.num_reads::cpu0.inst 14132 # Number of read requests responded to by this memory 53system.physmem.num_reads::cpu0.data 98365 # Number of read requests responded to by this memory 54system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 55system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory 56system.physmem.num_reads::cpu1.inst 3373 # Number of read requests responded to by this memory 57system.physmem.num_reads::cpu1.data 51739 # Number of read requests responded to by this memory 58system.physmem.num_reads::total 5082816 # Number of read requests responded to by this memory 59system.physmem.num_writes::writebacks 65563 # Number of write requests responded to by this memory 60system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 61system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory 62system.physmem.num_writes::total 822335 # Number of write requests responded to by this memory 63system.physmem.bw_read::realview.clcd 43132173 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) 65system.physmem.bw_read::cpu0.itb.walker 140 # Total read bandwidth from this memory (bytes/s) 66system.physmem.bw_read::cpu0.inst 555549 # Total read bandwidth from this memory (bytes/s) 67system.physmem.bw_read::cpu0.data 6900362 # Total read bandwidth from this memory (bytes/s) 68system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) 69system.physmem.bw_read::cpu1.itb.walker 70 # Total read bandwidth from this memory (bytes/s) 70system.physmem.bw_read::cpu1.inst 231066 # Total read bandwidth from this memory (bytes/s) 71system.physmem.bw_read::cpu1.data 3630344 # Total read bandwidth from this memory (bytes/s) 72system.physmem.bw_read::total 54449985 # Total read bandwidth from this memory (bytes/s) 73system.physmem.bw_inst_read::cpu0.inst 555549 # Instruction read bandwidth from this memory (bytes/s) 74system.physmem.bw_inst_read::cpu1.inst 231066 # Instruction read bandwidth from this memory (bytes/s) 75system.physmem.bw_inst_read::total 786615 # Instruction read bandwidth from this memory (bytes/s) 76system.physmem.bw_write::writebacks 4602661 # Write bandwidth from this memory (bytes/s) 77system.physmem.bw_write::cpu0.data 18647 # Write bandwidth from this memory (bytes/s) 78system.physmem.bw_write::cpu1.data 3301789 # Write bandwidth from this memory (bytes/s) 79system.physmem.bw_write::total 7923097 # Write bandwidth from this memory (bytes/s) 80system.physmem.bw_total::writebacks 4602661 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.clcd 43132173 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::cpu0.itb.walker 140 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.bw_total::cpu0.inst 555549 # Total bandwidth to/from this memory (bytes/s) 85system.physmem.bw_total::cpu0.data 6919010 # Total bandwidth to/from this memory (bytes/s) 86system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) 87system.physmem.bw_total::cpu1.itb.walker 70 # Total bandwidth to/from this memory (bytes/s) 88system.physmem.bw_total::cpu1.inst 231066 # Total bandwidth to/from this memory (bytes/s) 89system.physmem.bw_total::cpu1.data 6932133 # Total bandwidth to/from this memory (bytes/s) 90system.physmem.bw_total::total 62373082 # Total bandwidth to/from this memory (bytes/s) 91system.l2c.replacements 70681 # number of replacements 92system.l2c.tagsinuse 51554.827924 # Cycle average of tags in use 93system.l2c.total_refs 1661073 # Total number of references to valid blocks. 94system.l2c.sampled_refs 135855 # Sample count of references to valid blocks. 95system.l2c.avg_refs 12.226808 # Average number of references to valid blocks. 96system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 97system.l2c.occ_blocks::writebacks 39271.893324 # Average occupied blocks per requestor 98system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor 99system.l2c.occ_blocks::cpu0.itb.walker 0.000326 # Average occupied blocks per requestor 100system.l2c.occ_blocks::cpu0.inst 4360.096185 # Average occupied blocks per requestor 101system.l2c.occ_blocks::cpu0.data 2483.383308 # Average occupied blocks per requestor 102system.l2c.occ_blocks::cpu1.dtb.walker 2.678787 # Average occupied blocks per requestor 103system.l2c.occ_blocks::cpu1.itb.walker 0.000776 # Average occupied blocks per requestor 104system.l2c.occ_blocks::cpu1.inst 2126.160779 # Average occupied blocks per requestor 105system.l2c.occ_blocks::cpu1.data 3310.614391 # Average occupied blocks per requestor 106system.l2c.occ_percent::writebacks 0.599242 # Average percentage of cache occupancy 107system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 108system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 109system.l2c.occ_percent::cpu0.inst 0.066530 # Average percentage of cache occupancy 110system.l2c.occ_percent::cpu0.data 0.037893 # Average percentage of cache occupancy 111system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 112system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy 113system.l2c.occ_percent::cpu1.inst 0.032443 # Average percentage of cache occupancy 114system.l2c.occ_percent::cpu1.data 0.050516 # Average percentage of cache occupancy 115system.l2c.occ_percent::total 0.786664 # Average percentage of cache occupancy 116system.l2c.ReadReq_hits::cpu0.dtb.walker 5302 # number of ReadReq hits 117system.l2c.ReadReq_hits::cpu0.itb.walker 2202 # number of ReadReq hits 118system.l2c.ReadReq_hits::cpu0.inst 487741 # number of ReadReq hits 119system.l2c.ReadReq_hits::cpu0.data 211552 # number of ReadReq hits 120system.l2c.ReadReq_hits::cpu1.dtb.walker 4297 # number of ReadReq hits 121system.l2c.ReadReq_hits::cpu1.itb.walker 1568 # number of ReadReq hits 122system.l2c.ReadReq_hits::cpu1.inst 361833 # number of ReadReq hits 123system.l2c.ReadReq_hits::cpu1.data 130247 # number of ReadReq hits 124system.l2c.ReadReq_hits::total 1204742 # number of ReadReq hits 125system.l2c.Writeback_hits::writebacks 613260 # number of Writeback hits 126system.l2c.Writeback_hits::total 613260 # number of Writeback hits 127system.l2c.UpgradeReq_hits::cpu0.data 827 # number of UpgradeReq hits 128system.l2c.UpgradeReq_hits::cpu1.data 750 # number of UpgradeReq hits 129system.l2c.UpgradeReq_hits::total 1577 # number of UpgradeReq hits 130system.l2c.SCUpgradeReq_hits::cpu0.data 123 # number of SCUpgradeReq hits 131system.l2c.SCUpgradeReq_hits::cpu1.data 53 # number of SCUpgradeReq hits 132system.l2c.SCUpgradeReq_hits::total 176 # number of SCUpgradeReq hits 133system.l2c.ReadExReq_hits::cpu0.data 71506 # number of ReadExReq hits 134system.l2c.ReadExReq_hits::cpu1.data 36206 # number of ReadExReq hits 135system.l2c.ReadExReq_hits::total 107712 # number of ReadExReq hits 136system.l2c.demand_hits::cpu0.dtb.walker 5302 # number of demand (read+write) hits 137system.l2c.demand_hits::cpu0.itb.walker 2202 # number of demand (read+write) hits 138system.l2c.demand_hits::cpu0.inst 487741 # number of demand (read+write) hits 139system.l2c.demand_hits::cpu0.data 283058 # number of demand (read+write) hits 140system.l2c.demand_hits::cpu1.dtb.walker 4297 # number of demand (read+write) hits 141system.l2c.demand_hits::cpu1.itb.walker 1568 # number of demand (read+write) hits 142system.l2c.demand_hits::cpu1.inst 361833 # number of demand (read+write) hits 143system.l2c.demand_hits::cpu1.data 166453 # number of demand (read+write) hits 144system.l2c.demand_hits::total 1312454 # number of demand (read+write) hits 145system.l2c.overall_hits::cpu0.dtb.walker 5302 # number of overall hits 146system.l2c.overall_hits::cpu0.itb.walker 2202 # number of overall hits 147system.l2c.overall_hits::cpu0.inst 487741 # number of overall hits 148system.l2c.overall_hits::cpu0.data 283058 # number of overall hits 149system.l2c.overall_hits::cpu1.dtb.walker 4297 # number of overall hits 150system.l2c.overall_hits::cpu1.itb.walker 1568 # number of overall hits 151system.l2c.overall_hits::cpu1.inst 361833 # number of overall hits 152system.l2c.overall_hits::cpu1.data 166453 # number of overall hits 153system.l2c.overall_hits::total 1312454 # number of overall hits 154system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 155system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses 156system.l2c.ReadReq_misses::cpu0.inst 7499 # number of ReadReq misses 157system.l2c.ReadReq_misses::cpu0.data 6382 # number of ReadReq misses 158system.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 159system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses 160system.l2c.ReadReq_misses::cpu1.inst 3286 # number of ReadReq misses 161system.l2c.ReadReq_misses::cpu1.data 5264 # number of ReadReq misses 162system.l2c.ReadReq_misses::total 22438 # number of ReadReq misses 163system.l2c.UpgradeReq_misses::cpu0.data 6263 # number of UpgradeReq misses 164system.l2c.UpgradeReq_misses::cpu1.data 3008 # number of UpgradeReq misses 165system.l2c.UpgradeReq_misses::total 9271 # number of UpgradeReq misses 166system.l2c.SCUpgradeReq_misses::cpu0.data 734 # number of SCUpgradeReq misses 167system.l2c.SCUpgradeReq_misses::cpu1.data 484 # number of SCUpgradeReq misses 168system.l2c.SCUpgradeReq_misses::total 1218 # number of SCUpgradeReq misses 169system.l2c.ReadExReq_misses::cpu0.data 93870 # number of ReadExReq misses 170system.l2c.ReadExReq_misses::cpu1.data 47031 # number of ReadExReq misses 171system.l2c.ReadExReq_misses::total 140901 # number of ReadExReq misses 172system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 173system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 174system.l2c.demand_misses::cpu0.inst 7499 # number of demand (read+write) misses 175system.l2c.demand_misses::cpu0.data 100252 # number of demand (read+write) misses 176system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 177system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses 178system.l2c.demand_misses::cpu1.inst 3286 # number of demand (read+write) misses 179system.l2c.demand_misses::cpu1.data 52295 # number of demand (read+write) misses 180system.l2c.demand_misses::total 163339 # number of demand (read+write) misses 181system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 182system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 183system.l2c.overall_misses::cpu0.inst 7499 # number of overall misses 184system.l2c.overall_misses::cpu0.data 100252 # number of overall misses 185system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 186system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses 187system.l2c.overall_misses::cpu1.inst 3286 # number of overall misses 188system.l2c.overall_misses::cpu1.data 52295 # number of overall misses 189system.l2c.overall_misses::total 163339 # number of overall misses 190system.l2c.ReadReq_accesses::cpu0.dtb.walker 5303 # number of ReadReq accesses(hits+misses) 191system.l2c.ReadReq_accesses::cpu0.itb.walker 2204 # number of ReadReq accesses(hits+misses) 192system.l2c.ReadReq_accesses::cpu0.inst 495240 # number of ReadReq accesses(hits+misses) 193system.l2c.ReadReq_accesses::cpu0.data 217934 # number of ReadReq accesses(hits+misses) 194system.l2c.ReadReq_accesses::cpu1.dtb.walker 4300 # number of ReadReq accesses(hits+misses) 195system.l2c.ReadReq_accesses::cpu1.itb.walker 1569 # number of ReadReq accesses(hits+misses) 196system.l2c.ReadReq_accesses::cpu1.inst 365119 # number of ReadReq accesses(hits+misses) 197system.l2c.ReadReq_accesses::cpu1.data 135511 # number of ReadReq accesses(hits+misses) 198system.l2c.ReadReq_accesses::total 1227180 # number of ReadReq accesses(hits+misses) 199system.l2c.Writeback_accesses::writebacks 613260 # number of Writeback accesses(hits+misses) 200system.l2c.Writeback_accesses::total 613260 # number of Writeback accesses(hits+misses) 201system.l2c.UpgradeReq_accesses::cpu0.data 7090 # number of UpgradeReq accesses(hits+misses) 202system.l2c.UpgradeReq_accesses::cpu1.data 3758 # number of UpgradeReq accesses(hits+misses) 203system.l2c.UpgradeReq_accesses::total 10848 # number of UpgradeReq accesses(hits+misses) 204system.l2c.SCUpgradeReq_accesses::cpu0.data 857 # number of SCUpgradeReq accesses(hits+misses) 205system.l2c.SCUpgradeReq_accesses::cpu1.data 537 # number of SCUpgradeReq accesses(hits+misses) 206system.l2c.SCUpgradeReq_accesses::total 1394 # number of SCUpgradeReq accesses(hits+misses) 207system.l2c.ReadExReq_accesses::cpu0.data 165376 # number of ReadExReq accesses(hits+misses) 208system.l2c.ReadExReq_accesses::cpu1.data 83237 # number of ReadExReq accesses(hits+misses) 209system.l2c.ReadExReq_accesses::total 248613 # number of ReadExReq accesses(hits+misses) 210system.l2c.demand_accesses::cpu0.dtb.walker 5303 # number of demand (read+write) accesses 211system.l2c.demand_accesses::cpu0.itb.walker 2204 # number of demand (read+write) accesses 212system.l2c.demand_accesses::cpu0.inst 495240 # number of demand (read+write) accesses 213system.l2c.demand_accesses::cpu0.data 383310 # number of demand (read+write) accesses 214system.l2c.demand_accesses::cpu1.dtb.walker 4300 # number of demand (read+write) accesses 215system.l2c.demand_accesses::cpu1.itb.walker 1569 # number of demand (read+write) accesses 216system.l2c.demand_accesses::cpu1.inst 365119 # number of demand (read+write) accesses 217system.l2c.demand_accesses::cpu1.data 218748 # number of demand (read+write) accesses 218system.l2c.demand_accesses::total 1475793 # number of demand (read+write) accesses 219system.l2c.overall_accesses::cpu0.dtb.walker 5303 # number of overall (read+write) accesses 220system.l2c.overall_accesses::cpu0.itb.walker 2204 # number of overall (read+write) accesses 221system.l2c.overall_accesses::cpu0.inst 495240 # number of overall (read+write) accesses 222system.l2c.overall_accesses::cpu0.data 383310 # number of overall (read+write) accesses 223system.l2c.overall_accesses::cpu1.dtb.walker 4300 # number of overall (read+write) accesses 224system.l2c.overall_accesses::cpu1.itb.walker 1569 # number of overall (read+write) accesses 225system.l2c.overall_accesses::cpu1.inst 365119 # number of overall (read+write) accesses 226system.l2c.overall_accesses::cpu1.data 218748 # number of overall (read+write) accesses 227system.l2c.overall_accesses::total 1475793 # number of overall (read+write) accesses 228system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for ReadReq accesses 229system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000907 # miss rate for ReadReq accesses 230system.l2c.ReadReq_miss_rate::cpu0.inst 0.015142 # miss rate for ReadReq accesses 231system.l2c.ReadReq_miss_rate::cpu0.data 0.029284 # miss rate for ReadReq accesses 232system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses 233system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000637 # miss rate for ReadReq accesses 234system.l2c.ReadReq_miss_rate::cpu1.inst 0.009000 # miss rate for ReadReq accesses 235system.l2c.ReadReq_miss_rate::cpu1.data 0.038846 # miss rate for ReadReq accesses 236system.l2c.ReadReq_miss_rate::total 0.018284 # miss rate for ReadReq accesses 237system.l2c.UpgradeReq_miss_rate::cpu0.data 0.883357 # miss rate for UpgradeReq accesses 238system.l2c.UpgradeReq_miss_rate::cpu1.data 0.800426 # miss rate for UpgradeReq accesses 239system.l2c.UpgradeReq_miss_rate::total 0.854628 # miss rate for UpgradeReq accesses 240system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.856476 # miss rate for SCUpgradeReq accesses 241system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901304 # miss rate for SCUpgradeReq accesses 242system.l2c.SCUpgradeReq_miss_rate::total 0.873745 # miss rate for SCUpgradeReq accesses 243system.l2c.ReadExReq_miss_rate::cpu0.data 0.567616 # miss rate for ReadExReq accesses 244system.l2c.ReadExReq_miss_rate::cpu1.data 0.565025 # miss rate for ReadExReq accesses 245system.l2c.ReadExReq_miss_rate::total 0.566748 # miss rate for ReadExReq accesses 246system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for demand accesses 247system.l2c.demand_miss_rate::cpu0.itb.walker 0.000907 # miss rate for demand accesses 248system.l2c.demand_miss_rate::cpu0.inst 0.015142 # miss rate for demand accesses 249system.l2c.demand_miss_rate::cpu0.data 0.261543 # miss rate for demand accesses 250system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses 251system.l2c.demand_miss_rate::cpu1.itb.walker 0.000637 # miss rate for demand accesses 252system.l2c.demand_miss_rate::cpu1.inst 0.009000 # miss rate for demand accesses 253system.l2c.demand_miss_rate::cpu1.data 0.239065 # miss rate for demand accesses 254system.l2c.demand_miss_rate::total 0.110679 # miss rate for demand accesses 255system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for overall accesses 256system.l2c.overall_miss_rate::cpu0.itb.walker 0.000907 # miss rate for overall accesses 257system.l2c.overall_miss_rate::cpu0.inst 0.015142 # miss rate for overall accesses 258system.l2c.overall_miss_rate::cpu0.data 0.261543 # miss rate for overall accesses 259system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses 260system.l2c.overall_miss_rate::cpu1.itb.walker 0.000637 # miss rate for overall accesses 261system.l2c.overall_miss_rate::cpu1.inst 0.009000 # miss rate for overall accesses 262system.l2c.overall_miss_rate::cpu1.data 0.239065 # miss rate for overall accesses 263system.l2c.overall_miss_rate::total 0.110679 # miss rate for overall accesses 264system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 265system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 266system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 267system.l2c.blocked::no_targets 0 # number of cycles access was blocked 268system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 269system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 270system.l2c.fast_writes 0 # number of fast writes performed 271system.l2c.cache_copies 0 # number of cache copies performed 272system.l2c.writebacks::writebacks 65563 # number of writebacks 273system.l2c.writebacks::total 65563 # number of writebacks 274system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 275system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 276system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 277system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 278system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 279system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 280system.cf0.dma_write_txs 0 # Number of DMA write transactions. 281system.cpu0.dtb.inst_hits 0 # ITB inst hits 282system.cpu0.dtb.inst_misses 0 # ITB inst misses 283system.cpu0.dtb.read_hits 9312139 # DTB read hits 284system.cpu0.dtb.read_misses 5476 # DTB read misses 285system.cpu0.dtb.write_hits 6895585 # DTB write hits 286system.cpu0.dtb.write_misses 1137 # DTB write misses 287system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 288system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 289system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 290system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 291system.cpu0.dtb.flush_entries 2449 # Number of entries that have been flushed from TLB 292system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 293system.cpu0.dtb.prefetch_faults 187 # Number of TLB faults due to prefetch 294system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 295system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions 296system.cpu0.dtb.read_accesses 9317615 # DTB read accesses 297system.cpu0.dtb.write_accesses 6896722 # DTB write accesses 298system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 299system.cpu0.dtb.hits 16207724 # DTB hits 300system.cpu0.dtb.misses 6613 # DTB misses 301system.cpu0.dtb.accesses 16214337 # DTB accesses 302system.cpu0.itb.inst_hits 34683994 # ITB inst hits 303system.cpu0.itb.inst_misses 3170 # ITB inst misses 304system.cpu0.itb.read_hits 0 # DTB read hits 305system.cpu0.itb.read_misses 0 # DTB read misses 306system.cpu0.itb.write_hits 0 # DTB write hits 307system.cpu0.itb.write_misses 0 # DTB write misses 308system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 309system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 310system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 311system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 312system.cpu0.itb.flush_entries 1558 # Number of entries that have been flushed from TLB 313system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 314system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 315system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 316system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 317system.cpu0.itb.read_accesses 0 # DTB read accesses 318system.cpu0.itb.write_accesses 0 # DTB write accesses 319system.cpu0.itb.inst_accesses 34687164 # ITB inst accesses 320system.cpu0.itb.hits 34683994 # DTB hits 321system.cpu0.itb.misses 3170 # DTB misses 322system.cpu0.itb.accesses 34687164 # DTB accesses 323system.cpu0.numCycles 1823259919 # number of cpu cycles simulated 324system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 325system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 326system.cpu0.committedInsts 33900598 # Number of instructions committed 327system.cpu0.committedOps 44786074 # Number of ops (including micro ops) committed 328system.cpu0.num_int_alu_accesses 39685287 # Number of integer alu accesses 329system.cpu0.num_fp_alu_accesses 5074 # Number of float alu accesses 330system.cpu0.num_func_calls 1436598 # number of times a function call or return occured 331system.cpu0.num_conditional_control_insts 4494112 # number of instructions that are conditional controls 332system.cpu0.num_int_insts 39685287 # number of integer instructions 333system.cpu0.num_fp_insts 5074 # number of float instructions 334system.cpu0.num_int_register_reads 201262894 # number of times the integer registers were read 335system.cpu0.num_int_register_writes 42034263 # number of times the integer registers were written 336system.cpu0.num_fp_register_reads 3706 # number of times the floating registers were read 337system.cpu0.num_fp_register_writes 1372 # number of times the floating registers were written 338system.cpu0.num_mem_refs 16978573 # number of memory refs 339system.cpu0.num_load_insts 9760184 # Number of load instructions 340system.cpu0.num_store_insts 7218389 # Number of store instructions 341system.cpu0.num_idle_cycles 1777623684.411826 # Number of idle cycles 342system.cpu0.num_busy_cycles 45636234.588174 # Number of busy cycles 343system.cpu0.not_idle_fraction 0.025030 # Percentage of non-idle cycles 344system.cpu0.idle_fraction 0.974970 # Percentage of idle cycles 345system.cpu0.kern.inst.arm 0 # number of arm instructions executed 346system.cpu0.kern.inst.quiesce 58955 # number of quiesce instructions executed 347system.cpu0.icache.replacements 497178 # number of replacements 348system.cpu0.icache.tagsinuse 511.019581 # Cycle average of tags in use 349system.cpu0.icache.total_refs 34187980 # Total number of references to valid blocks. 350system.cpu0.icache.sampled_refs 497690 # Sample count of references to valid blocks. 351system.cpu0.icache.avg_refs 68.693323 # Average number of references to valid blocks. 352system.cpu0.icache.warmup_cycle 64536851000 # Cycle when the warmup percentage was hit. 353system.cpu0.icache.occ_blocks::cpu0.inst 511.019581 # Average occupied blocks per requestor 354system.cpu0.icache.occ_percent::cpu0.inst 0.998085 # Average percentage of cache occupancy 355system.cpu0.icache.occ_percent::total 0.998085 # Average percentage of cache occupancy 356system.cpu0.icache.ReadReq_hits::cpu0.inst 34187980 # number of ReadReq hits 357system.cpu0.icache.ReadReq_hits::total 34187980 # number of ReadReq hits 358system.cpu0.icache.demand_hits::cpu0.inst 34187980 # number of demand (read+write) hits 359system.cpu0.icache.demand_hits::total 34187980 # number of demand (read+write) hits 360system.cpu0.icache.overall_hits::cpu0.inst 34187980 # number of overall hits 361system.cpu0.icache.overall_hits::total 34187980 # number of overall hits 362system.cpu0.icache.ReadReq_misses::cpu0.inst 497690 # number of ReadReq misses 363system.cpu0.icache.ReadReq_misses::total 497690 # number of ReadReq misses 364system.cpu0.icache.demand_misses::cpu0.inst 497690 # number of demand (read+write) misses 365system.cpu0.icache.demand_misses::total 497690 # number of demand (read+write) misses 366system.cpu0.icache.overall_misses::cpu0.inst 497690 # number of overall misses 367system.cpu0.icache.overall_misses::total 497690 # number of overall misses 368system.cpu0.icache.ReadReq_accesses::cpu0.inst 34685670 # number of ReadReq accesses(hits+misses) 369system.cpu0.icache.ReadReq_accesses::total 34685670 # number of ReadReq accesses(hits+misses) 370system.cpu0.icache.demand_accesses::cpu0.inst 34685670 # number of demand (read+write) accesses 371system.cpu0.icache.demand_accesses::total 34685670 # number of demand (read+write) accesses 372system.cpu0.icache.overall_accesses::cpu0.inst 34685670 # number of overall (read+write) accesses 373system.cpu0.icache.overall_accesses::total 34685670 # number of overall (read+write) accesses 374system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014349 # miss rate for ReadReq accesses 375system.cpu0.icache.ReadReq_miss_rate::total 0.014349 # miss rate for ReadReq accesses 376system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014349 # miss rate for demand accesses 377system.cpu0.icache.demand_miss_rate::total 0.014349 # miss rate for demand accesses 378system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014349 # miss rate for overall accesses 379system.cpu0.icache.overall_miss_rate::total 0.014349 # miss rate for overall accesses 380system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 381system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 382system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 383system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 384system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 385system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 386system.cpu0.icache.fast_writes 0 # number of fast writes performed 387system.cpu0.icache.cache_copies 0 # number of cache copies performed 388system.cpu0.icache.writebacks::writebacks 31457 # number of writebacks 389system.cpu0.icache.writebacks::total 31457 # number of writebacks 390system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 391system.cpu0.dcache.replacements 380425 # number of replacements 392system.cpu0.dcache.tagsinuse 495.308430 # Cycle average of tags in use 393system.cpu0.dcache.total_refs 14671885 # Total number of references to valid blocks. 394system.cpu0.dcache.sampled_refs 380937 # Sample count of references to valid blocks. 395system.cpu0.dcache.avg_refs 38.515253 # Average number of references to valid blocks. 396system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. 397system.cpu0.dcache.occ_blocks::cpu0.data 495.308430 # Average occupied blocks per requestor 398system.cpu0.dcache.occ_percent::cpu0.data 0.967399 # Average percentage of cache occupancy 399system.cpu0.dcache.occ_percent::total 0.967399 # Average percentage of cache occupancy 400system.cpu0.dcache.ReadReq_hits::cpu0.data 7779192 # number of ReadReq hits 401system.cpu0.dcache.ReadReq_hits::total 7779192 # number of ReadReq hits 402system.cpu0.dcache.WriteReq_hits::cpu0.data 6519856 # number of WriteReq hits 403system.cpu0.dcache.WriteReq_hits::total 6519856 # number of WriteReq hits 404system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173153 # number of LoadLockedReq hits 405system.cpu0.dcache.LoadLockedReq_hits::total 173153 # number of LoadLockedReq hits 406system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175464 # number of StoreCondReq hits 407system.cpu0.dcache.StoreCondReq_hits::total 175464 # number of StoreCondReq hits 408system.cpu0.dcache.demand_hits::cpu0.data 14299048 # number of demand (read+write) hits 409system.cpu0.dcache.demand_hits::total 14299048 # number of demand (read+write) hits 410system.cpu0.dcache.overall_hits::cpu0.data 14299048 # number of overall hits 411system.cpu0.dcache.overall_hits::total 14299048 # number of overall hits 412system.cpu0.dcache.ReadReq_misses::cpu0.data 237170 # number of ReadReq misses 413system.cpu0.dcache.ReadReq_misses::total 237170 # number of ReadReq misses 414system.cpu0.dcache.WriteReq_misses::cpu0.data 185374 # number of WriteReq misses 415system.cpu0.dcache.WriteReq_misses::total 185374 # number of WriteReq misses 416system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9761 # number of LoadLockedReq misses 417system.cpu0.dcache.LoadLockedReq_misses::total 9761 # number of LoadLockedReq misses 418system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7396 # number of StoreCondReq misses 419system.cpu0.dcache.StoreCondReq_misses::total 7396 # number of StoreCondReq misses 420system.cpu0.dcache.demand_misses::cpu0.data 422544 # number of demand (read+write) misses 421system.cpu0.dcache.demand_misses::total 422544 # number of demand (read+write) misses 422system.cpu0.dcache.overall_misses::cpu0.data 422544 # number of overall misses 423system.cpu0.dcache.overall_misses::total 422544 # number of overall misses 424system.cpu0.dcache.ReadReq_accesses::cpu0.data 8016362 # number of ReadReq accesses(hits+misses) 425system.cpu0.dcache.ReadReq_accesses::total 8016362 # number of ReadReq accesses(hits+misses) 426system.cpu0.dcache.WriteReq_accesses::cpu0.data 6705230 # number of WriteReq accesses(hits+misses) 427system.cpu0.dcache.WriteReq_accesses::total 6705230 # number of WriteReq accesses(hits+misses) 428system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182914 # number of LoadLockedReq accesses(hits+misses) 429system.cpu0.dcache.LoadLockedReq_accesses::total 182914 # number of LoadLockedReq accesses(hits+misses) 430system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182860 # number of StoreCondReq accesses(hits+misses) 431system.cpu0.dcache.StoreCondReq_accesses::total 182860 # number of StoreCondReq accesses(hits+misses) 432system.cpu0.dcache.demand_accesses::cpu0.data 14721592 # number of demand (read+write) accesses 433system.cpu0.dcache.demand_accesses::total 14721592 # number of demand (read+write) accesses 434system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses 435system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses 436system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029586 # miss rate for ReadReq accesses 437system.cpu0.dcache.ReadReq_miss_rate::total 0.029586 # miss rate for ReadReq accesses 438system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027646 # miss rate for WriteReq accesses 439system.cpu0.dcache.WriteReq_miss_rate::total 0.027646 # miss rate for WriteReq accesses 440system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053364 # miss rate for LoadLockedReq accesses 441system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053364 # miss rate for LoadLockedReq accesses 442system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040446 # miss rate for StoreCondReq accesses 443system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040446 # miss rate for StoreCondReq accesses 444system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028702 # miss rate for demand accesses 445system.cpu0.dcache.demand_miss_rate::total 0.028702 # miss rate for demand accesses 446system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028702 # miss rate for overall accesses 447system.cpu0.dcache.overall_miss_rate::total 0.028702 # miss rate for overall accesses 448system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 449system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 450system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 451system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 452system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 453system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 454system.cpu0.dcache.fast_writes 0 # number of fast writes performed 455system.cpu0.dcache.cache_copies 0 # number of cache copies performed 456system.cpu0.dcache.writebacks::writebacks 353901 # number of writebacks 457system.cpu0.dcache.writebacks::total 353901 # number of writebacks 458system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 459system.cpu1.dtb.inst_hits 0 # ITB inst hits 460system.cpu1.dtb.inst_misses 0 # ITB inst misses 461system.cpu1.dtb.read_hits 6036043 # DTB read hits 462system.cpu1.dtb.read_misses 1895 # DTB read misses 463system.cpu1.dtb.write_hits 4565126 # DTB write hits 464system.cpu1.dtb.write_misses 1147 # DTB write misses 465system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 466system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 467system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 468system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 469system.cpu1.dtb.flush_entries 1364 # Number of entries that have been flushed from TLB 470system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 471system.cpu1.dtb.prefetch_faults 95 # Number of TLB faults due to prefetch 472system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 473system.cpu1.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions 474system.cpu1.dtb.read_accesses 6037938 # DTB read accesses 475system.cpu1.dtb.write_accesses 4566273 # DTB write accesses 476system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 477system.cpu1.dtb.hits 10601169 # DTB hits 478system.cpu1.dtb.misses 3042 # DTB misses 479system.cpu1.dtb.accesses 10604211 # DTB accesses 480system.cpu1.itb.inst_hits 26944447 # ITB inst hits 481system.cpu1.itb.inst_misses 1203 # ITB inst misses 482system.cpu1.itb.read_hits 0 # DTB read hits 483system.cpu1.itb.read_misses 0 # DTB read misses 484system.cpu1.itb.write_hits 0 # DTB write hits 485system.cpu1.itb.write_misses 0 # DTB write misses 486system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 487system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 488system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 489system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 490system.cpu1.itb.flush_entries 1228 # Number of entries that have been flushed from TLB 491system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 492system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 493system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 494system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 495system.cpu1.itb.read_accesses 0 # DTB read accesses 496system.cpu1.itb.write_accesses 0 # DTB write accesses 497system.cpu1.itb.inst_accesses 26945650 # ITB inst accesses 498system.cpu1.itb.hits 26944447 # DTB hits 499system.cpu1.itb.misses 1203 # DTB misses 500system.cpu1.itb.accesses 26945650 # DTB accesses 501system.cpu1.numCycles 1822760078 # number of cpu cycles simulated 502system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 503system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 504system.cpu1.committedInsts 26714987 # Number of instructions committed 505system.cpu1.committedOps 33555986 # Number of ops (including micro ops) committed 506system.cpu1.num_int_alu_accesses 30087808 # Number of integer alu accesses 507system.cpu1.num_fp_alu_accesses 5643 # Number of float alu accesses 508system.cpu1.num_func_calls 761024 # number of times a function call or return occured 509system.cpu1.num_conditional_control_insts 3301562 # number of instructions that are conditional controls 510system.cpu1.num_int_insts 30087808 # number of integer instructions 511system.cpu1.num_fp_insts 5643 # number of float instructions 512system.cpu1.num_int_register_reads 152234781 # number of times the integer registers were read 513system.cpu1.num_int_register_writes 32495677 # number of times the integer registers were written 514system.cpu1.num_fp_register_reads 3915 # number of times the floating registers were read 515system.cpu1.num_fp_register_writes 1728 # number of times the floating registers were written 516system.cpu1.num_mem_refs 11031013 # number of memory refs 517system.cpu1.num_load_insts 6247466 # Number of load instructions 518system.cpu1.num_store_insts 4783547 # Number of store instructions 519system.cpu1.num_idle_cycles 1788952556.347001 # Number of idle cycles 520system.cpu1.num_busy_cycles 33807521.652999 # Number of busy cycles 521system.cpu1.not_idle_fraction 0.018547 # Percentage of non-idle cycles 522system.cpu1.idle_fraction 0.981453 # Percentage of idle cycles 523system.cpu1.kern.inst.arm 0 # number of arm instructions executed 524system.cpu1.kern.inst.quiesce 31471 # number of quiesce instructions executed 525system.cpu1.icache.replacements 365832 # number of replacements 526system.cpu1.icache.tagsinuse 475.430525 # Cycle average of tags in use 527system.cpu1.icache.total_refs 26579068 # Total number of references to valid blocks. 528system.cpu1.icache.sampled_refs 366344 # Sample count of references to valid blocks. 529system.cpu1.icache.avg_refs 72.552213 # Average number of references to valid blocks. 530system.cpu1.icache.warmup_cycle 69967043000 # Cycle when the warmup percentage was hit. 531system.cpu1.icache.occ_blocks::cpu1.inst 475.430525 # Average occupied blocks per requestor 532system.cpu1.icache.occ_percent::cpu1.inst 0.928575 # Average percentage of cache occupancy 533system.cpu1.icache.occ_percent::total 0.928575 # Average percentage of cache occupancy 534system.cpu1.icache.ReadReq_hits::cpu1.inst 26579068 # number of ReadReq hits 535system.cpu1.icache.ReadReq_hits::total 26579068 # number of ReadReq hits 536system.cpu1.icache.demand_hits::cpu1.inst 26579068 # number of demand (read+write) hits 537system.cpu1.icache.demand_hits::total 26579068 # number of demand (read+write) hits 538system.cpu1.icache.overall_hits::cpu1.inst 26579068 # number of overall hits 539system.cpu1.icache.overall_hits::total 26579068 # number of overall hits 540system.cpu1.icache.ReadReq_misses::cpu1.inst 366344 # number of ReadReq misses 541system.cpu1.icache.ReadReq_misses::total 366344 # number of ReadReq misses 542system.cpu1.icache.demand_misses::cpu1.inst 366344 # number of demand (read+write) misses 543system.cpu1.icache.demand_misses::total 366344 # number of demand (read+write) misses 544system.cpu1.icache.overall_misses::cpu1.inst 366344 # number of overall misses 545system.cpu1.icache.overall_misses::total 366344 # number of overall misses 546system.cpu1.icache.ReadReq_accesses::cpu1.inst 26945412 # number of ReadReq accesses(hits+misses) 547system.cpu1.icache.ReadReq_accesses::total 26945412 # number of ReadReq accesses(hits+misses) 548system.cpu1.icache.demand_accesses::cpu1.inst 26945412 # number of demand (read+write) accesses 549system.cpu1.icache.demand_accesses::total 26945412 # number of demand (read+write) accesses 550system.cpu1.icache.overall_accesses::cpu1.inst 26945412 # number of overall (read+write) accesses 551system.cpu1.icache.overall_accesses::total 26945412 # number of overall (read+write) accesses 552system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013596 # miss rate for ReadReq accesses 553system.cpu1.icache.ReadReq_miss_rate::total 0.013596 # miss rate for ReadReq accesses 554system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013596 # miss rate for demand accesses 555system.cpu1.icache.demand_miss_rate::total 0.013596 # miss rate for demand accesses 556system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013596 # miss rate for overall accesses 557system.cpu1.icache.overall_miss_rate::total 0.013596 # miss rate for overall accesses 558system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 559system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 560system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 561system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 562system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 563system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 564system.cpu1.icache.fast_writes 0 # number of fast writes performed 565system.cpu1.icache.cache_copies 0 # number of cache copies performed 566system.cpu1.icache.writebacks::writebacks 15197 # number of writebacks 567system.cpu1.icache.writebacks::total 15197 # number of writebacks 568system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 569system.cpu1.dcache.replacements 236700 # number of replacements 570system.cpu1.dcache.tagsinuse 447.071707 # Cycle average of tags in use 571system.cpu1.dcache.total_refs 9515102 # Total number of references to valid blocks. 572system.cpu1.dcache.sampled_refs 237061 # Sample count of references to valid blocks. 573system.cpu1.dcache.avg_refs 40.137779 # Average number of references to valid blocks. 574system.cpu1.dcache.warmup_cycle 67292773000 # Cycle when the warmup percentage was hit. 575system.cpu1.dcache.occ_blocks::cpu1.data 447.071707 # Average occupied blocks per requestor 576system.cpu1.dcache.occ_percent::cpu1.data 0.873187 # Average percentage of cache occupancy 577system.cpu1.dcache.occ_percent::total 0.873187 # Average percentage of cache occupancy 578system.cpu1.dcache.ReadReq_hits::cpu1.data 5742078 # number of ReadReq hits 579system.cpu1.dcache.ReadReq_hits::total 5742078 # number of ReadReq hits 580system.cpu1.dcache.WriteReq_hits::cpu1.data 3635346 # number of WriteReq hits 581system.cpu1.dcache.WriteReq_hits::total 3635346 # number of WriteReq hits 582system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56591 # number of LoadLockedReq hits 583system.cpu1.dcache.LoadLockedReq_hits::total 56591 # number of LoadLockedReq hits 584system.cpu1.dcache.StoreCondReq_hits::cpu1.data 56639 # number of StoreCondReq hits 585system.cpu1.dcache.StoreCondReq_hits::total 56639 # number of StoreCondReq hits 586system.cpu1.dcache.demand_hits::cpu1.data 9377424 # number of demand (read+write) hits 587system.cpu1.dcache.demand_hits::total 9377424 # number of demand (read+write) hits 588system.cpu1.dcache.overall_hits::cpu1.data 9377424 # number of overall hits 589system.cpu1.dcache.overall_hits::total 9377424 # number of overall hits 590system.cpu1.dcache.ReadReq_misses::cpu1.data 159026 # number of ReadReq misses 591system.cpu1.dcache.ReadReq_misses::total 159026 # number of ReadReq misses 592system.cpu1.dcache.WriteReq_misses::cpu1.data 108254 # number of WriteReq misses 593system.cpu1.dcache.WriteReq_misses::total 108254 # number of WriteReq misses 594system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10539 # number of LoadLockedReq misses 595system.cpu1.dcache.LoadLockedReq_misses::total 10539 # number of LoadLockedReq misses 596system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10435 # number of StoreCondReq misses 597system.cpu1.dcache.StoreCondReq_misses::total 10435 # number of StoreCondReq misses 598system.cpu1.dcache.demand_misses::cpu1.data 267280 # number of demand (read+write) misses 599system.cpu1.dcache.demand_misses::total 267280 # number of demand (read+write) misses 600system.cpu1.dcache.overall_misses::cpu1.data 267280 # number of overall misses 601system.cpu1.dcache.overall_misses::total 267280 # number of overall misses 602system.cpu1.dcache.ReadReq_accesses::cpu1.data 5901104 # number of ReadReq accesses(hits+misses) 603system.cpu1.dcache.ReadReq_accesses::total 5901104 # number of ReadReq accesses(hits+misses) 604system.cpu1.dcache.WriteReq_accesses::cpu1.data 3743600 # number of WriteReq accesses(hits+misses) 605system.cpu1.dcache.WriteReq_accesses::total 3743600 # number of WriteReq accesses(hits+misses) 606system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 67130 # number of LoadLockedReq accesses(hits+misses) 607system.cpu1.dcache.LoadLockedReq_accesses::total 67130 # number of LoadLockedReq accesses(hits+misses) 608system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 67074 # number of StoreCondReq accesses(hits+misses) 609system.cpu1.dcache.StoreCondReq_accesses::total 67074 # number of StoreCondReq accesses(hits+misses) 610system.cpu1.dcache.demand_accesses::cpu1.data 9644704 # number of demand (read+write) accesses 611system.cpu1.dcache.demand_accesses::total 9644704 # number of demand (read+write) accesses 612system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses 613system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses 614system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.026949 # miss rate for ReadReq accesses 615system.cpu1.dcache.ReadReq_miss_rate::total 0.026949 # miss rate for ReadReq accesses 616system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028917 # miss rate for WriteReq accesses 617system.cpu1.dcache.WriteReq_miss_rate::total 0.028917 # miss rate for WriteReq accesses 618system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156994 # miss rate for LoadLockedReq accesses 619system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156994 # miss rate for LoadLockedReq accesses 620system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.155574 # miss rate for StoreCondReq accesses 621system.cpu1.dcache.StoreCondReq_miss_rate::total 0.155574 # miss rate for StoreCondReq accesses 622system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027713 # miss rate for demand accesses 623system.cpu1.dcache.demand_miss_rate::total 0.027713 # miss rate for demand accesses 624system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027713 # miss rate for overall accesses 625system.cpu1.dcache.overall_miss_rate::total 0.027713 # miss rate for overall accesses 626system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 627system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 628system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 629system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 630system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 631system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 632system.cpu1.dcache.fast_writes 0 # number of fast writes performed 633system.cpu1.dcache.cache_copies 0 # number of cache copies performed 634system.cpu1.dcache.writebacks::writebacks 212705 # number of writebacks 635system.cpu1.dcache.writebacks::total 212705 # number of writebacks 636system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 637system.iocache.replacements 0 # number of replacements 638system.iocache.tagsinuse 0 # Cycle average of tags in use 639system.iocache.total_refs 0 # Total number of references to valid blocks. 640system.iocache.sampled_refs 0 # Sample count of references to valid blocks. 641system.iocache.avg_refs nan # Average number of references to valid blocks. 642system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 643system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 644system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 645system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 646system.iocache.blocked::no_targets 0 # number of cycles access was blocked 647system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 648system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 649system.iocache.fast_writes 0 # number of fast writes performed 650system.iocache.cache_copies 0 # number of cache copies performed 651system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 652 653---------- End Simulation Statistics ---------- 654