stats.txt revision 10944
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.802895 # Number of seconds simulated 4sim_ticks 2802894699500 # Number of ticks simulated 5final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1692608 # Simulator instruction rate (inst/s) 8host_op_rate 2062417 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 32311218818 # Simulator tick rate (ticks/s) 10host_mem_usage 579900 # Number of bytes of host memory used 11host_seconds 86.75 # Real time elapsed on the host 12sim_insts 146828240 # Number of instructions simulated 13sim_ops 178908039 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 1090916 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 9418084 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu1.inst 146388 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.data 1083988 # Number of bytes read from this memory 22system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 23system.physmem.bytes_read::total 11740912 # Number of bytes read from this memory 24system.physmem.bytes_inst_read::cpu0.inst 1090916 # Number of instructions bytes read from this memory 25system.physmem.bytes_inst_read::cpu1.inst 146388 # Number of instructions bytes read from this memory 26system.physmem.bytes_inst_read::total 1237304 # Number of instructions bytes read from this memory 27system.physmem.bytes_written::writebacks 8475264 # Number of bytes written to this memory 28system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 29system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 30system.physmem.bytes_written::total 8492828 # Number of bytes written to this memory 31system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 32system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 33system.physmem.num_reads::cpu0.inst 25499 # Number of read requests responded to by this memory 34system.physmem.num_reads::cpu0.data 147677 # Number of read requests responded to by this memory 35system.physmem.num_reads::cpu1.inst 2442 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu1.data 16958 # Number of read requests responded to by this memory 37system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 38system.physmem.num_reads::total 192600 # Number of read requests responded to by this memory 39system.physmem.num_writes::writebacks 132426 # Number of write requests responded to by this memory 40system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 41system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 42system.physmem.num_writes::total 136817 # Number of write requests responded to by this memory 43system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 44system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 45system.physmem.bw_read::cpu0.inst 389210 # Total read bandwidth from this memory (bytes/s) 46system.physmem.bw_read::cpu0.data 3360128 # Total read bandwidth from this memory (bytes/s) 47system.physmem.bw_read::cpu1.inst 52227 # Total read bandwidth from this memory (bytes/s) 48system.physmem.bw_read::cpu1.data 386739 # Total read bandwidth from this memory (bytes/s) 49system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 50system.physmem.bw_read::total 4188852 # Total read bandwidth from this memory (bytes/s) 51system.physmem.bw_inst_read::cpu0.inst 389210 # Instruction read bandwidth from this memory (bytes/s) 52system.physmem.bw_inst_read::cpu1.inst 52227 # Instruction read bandwidth from this memory (bytes/s) 53system.physmem.bw_inst_read::total 441438 # Instruction read bandwidth from this memory (bytes/s) 54system.physmem.bw_write::writebacks 3023754 # Write bandwidth from this memory (bytes/s) 55system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 56system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 57system.physmem.bw_write::total 3030020 # Write bandwidth from this memory (bytes/s) 58system.physmem.bw_total::writebacks 3023754 # Total bandwidth to/from this memory (bytes/s) 59system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 60system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 61system.physmem.bw_total::cpu0.inst 389210 # Total bandwidth to/from this memory (bytes/s) 62system.physmem.bw_total::cpu0.data 3366380 # Total bandwidth to/from this memory (bytes/s) 63system.physmem.bw_total::cpu1.inst 52227 # Total bandwidth to/from this memory (bytes/s) 64system.physmem.bw_total::cpu1.data 386753 # Total bandwidth to/from this memory (bytes/s) 65system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 66system.physmem.bw_total::total 7218873 # Total bandwidth to/from this memory (bytes/s) 67system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 68system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 69system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 70system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 71system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 72system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 73system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 74system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 75system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 76system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 77system.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 78system.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 79system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 80system.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 81system.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 82system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 83system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 84system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 85system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 86system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 87system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 88system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 89system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 90system.cf0.dma_write_txs 631 # Number of DMA write transactions. 91system.cpu_clk_domain.clock 500 # Clock period in ticks 92system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 93system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 94system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 95system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 96system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 97system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 98system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 99system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 100system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 101system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 102system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 103system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 104system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 105system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 106system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 107system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 108system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 109system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 110system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 111system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 112system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 113system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 114system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 115system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 116system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 117system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 118system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 119system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 120system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 121system.cpu0.dtb.walker.walks 7967 # Table walker walks requested 122system.cpu0.dtb.walker.walksShort 7967 # Table walker walks initiated with short descriptors 123system.cpu0.dtb.walker.walkWaitTime::samples 7967 # Table walker wait (enqueue to first request) latency 124system.cpu0.dtb.walker.walkWaitTime::0 7967 100.00% 100.00% # Table walker wait (enqueue to first request) latency 125system.cpu0.dtb.walker.walkWaitTime::total 7967 # Table walker wait (enqueue to first request) latency 126system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 127system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 128system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 129system.cpu0.dtb.walker.walkPageSizes::4K 5082 77.32% 77.32% # Table walker page sizes translated 130system.cpu0.dtb.walker.walkPageSizes::1M 1491 22.68% 100.00% # Table walker page sizes translated 131system.cpu0.dtb.walker.walkPageSizes::total 6573 # Table walker page sizes translated 132system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7967 # Table walker requests started/completed, data/inst 133system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 134system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7967 # Table walker requests started/completed, data/inst 135system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6573 # Table walker requests started/completed, data/inst 136system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 137system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 # Table walker requests started/completed, data/inst 138system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst 139system.cpu0.dtb.inst_hits 0 # ITB inst hits 140system.cpu0.dtb.inst_misses 0 # ITB inst misses 141system.cpu0.dtb.read_hits 20339720 # DTB read hits 142system.cpu0.dtb.read_misses 6874 # DTB read misses 143system.cpu0.dtb.write_hits 16391078 # DTB write hits 144system.cpu0.dtb.write_misses 1093 # DTB write misses 145system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 146system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 147system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 148system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 149system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 150system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 151system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 152system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 153system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 154system.cpu0.dtb.read_accesses 20346594 # DTB read accesses 155system.cpu0.dtb.write_accesses 16392171 # DTB write accesses 156system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 157system.cpu0.dtb.hits 36730798 # DTB hits 158system.cpu0.dtb.misses 7967 # DTB misses 159system.cpu0.dtb.accesses 36738765 # DTB accesses 160system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 161system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 162system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 163system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 164system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 165system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 166system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 167system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 168system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 169system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 170system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 171system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 172system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 173system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 174system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 175system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 176system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 177system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 178system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 179system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 180system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 181system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 182system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 183system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 184system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 185system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 186system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 187system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 188system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 189system.cpu0.itb.walker.walks 3358 # Table walker walks requested 190system.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 191system.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 192system.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 193system.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 194system.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 195system.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 196system.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 197system.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 198system.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 199system.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 200system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 201system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 202system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 203system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 204system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 205system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 206system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 207system.cpu0.itb.inst_hits 97439331 # ITB inst hits 208system.cpu0.itb.inst_misses 3358 # ITB inst misses 209system.cpu0.itb.read_hits 0 # DTB read hits 210system.cpu0.itb.read_misses 0 # DTB read misses 211system.cpu0.itb.write_hits 0 # DTB write hits 212system.cpu0.itb.write_misses 0 # DTB write misses 213system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 214system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 215system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 216system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 217system.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 218system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 219system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 220system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 221system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 222system.cpu0.itb.read_accesses 0 # DTB read accesses 223system.cpu0.itb.write_accesses 0 # DTB write accesses 224system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses 225system.cpu0.itb.hits 97439331 # DTB hits 226system.cpu0.itb.misses 3358 # DTB misses 227system.cpu0.itb.accesses 97442689 # DTB accesses 228system.cpu0.numCycles 5605791368 # number of cpu cycles simulated 229system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 230system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 231system.cpu0.committedInsts 95426926 # Number of instructions committed 232system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed 233system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses 234system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 235system.cpu0.num_func_calls 8000180 # number of times a function call or return occured 236system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls 237system.cpu0.num_int_insts 100762696 # number of integer instructions 238system.cpu0.num_fp_insts 9755 # number of float instructions 239system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read 240system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written 241system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 242system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 243system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read 244system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written 245system.cpu0.num_mem_refs 37873810 # number of memory refs 246system.cpu0.num_load_insts 20597310 # Number of load instructions 247system.cpu0.num_store_insts 17276500 # Number of store instructions 248system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles 249system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles 250system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 251system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 252system.cpu0.Branches 21941499 # Number of branches fetched 253system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 254system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction 255system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction 256system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 257system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 258system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 259system.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 260system.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 261system.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 262system.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 263system.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 264system.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 265system.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 266system.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 267system.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 268system.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 269system.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 270system.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 271system.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 272system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 273system.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 274system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 275system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 276system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 277system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 278system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 279system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 280system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 281system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 282system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 283system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction 284system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction 285system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 286system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 287system.cpu0.op_class::total 116882065 # Class of executed instruction 288system.cpu0.kern.inst.arm 0 # number of arm instructions executed 289system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed 290system.cpu0.dcache.tags.replacements 693486 # number of replacements 291system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use 292system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks. 293system.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks. 294system.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks. 295system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 296system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor 297system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 298system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 299system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 300system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 301system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 302system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 303system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 304system.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses 305system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses 306system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits 307system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits 308system.cpu0.dcache.WriteReq_hits::cpu0.data 15690436 # number of WriteReq hits 309system.cpu0.dcache.WriteReq_hits::total 15690436 # number of WriteReq hits 310system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits 311system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits 312system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits 313system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits 314system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363043 # number of StoreCondReq hits 315system.cpu0.dcache.StoreCondReq_hits::total 363043 # number of StoreCondReq hits 316system.cpu0.dcache.demand_hits::cpu0.data 34798977 # number of demand (read+write) hits 317system.cpu0.dcache.demand_hits::total 34798977 # number of demand (read+write) hits 318system.cpu0.dcache.overall_hits::cpu0.data 35145070 # number of overall hits 319system.cpu0.dcache.overall_hits::total 35145070 # number of overall hits 320system.cpu0.dcache.ReadReq_misses::cpu0.data 373103 # number of ReadReq misses 321system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses 322system.cpu0.dcache.WriteReq_misses::cpu0.data 295749 # number of WriteReq misses 323system.cpu0.dcache.WriteReq_misses::total 295749 # number of WriteReq misses 324system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 325system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 326system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses 327system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses 328system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18442 # number of StoreCondReq misses 329system.cpu0.dcache.StoreCondReq_misses::total 18442 # number of StoreCondReq misses 330system.cpu0.dcache.demand_misses::cpu0.data 668852 # number of demand (read+write) misses 331system.cpu0.dcache.demand_misses::total 668852 # number of demand (read+write) misses 332system.cpu0.dcache.overall_misses::cpu0.data 769173 # number of overall misses 333system.cpu0.dcache.overall_misses::total 769173 # number of overall misses 334system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481644 # number of ReadReq accesses(hits+misses) 335system.cpu0.dcache.ReadReq_accesses::total 19481644 # number of ReadReq accesses(hits+misses) 336system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986185 # number of WriteReq accesses(hits+misses) 337system.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses) 338system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) 339system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) 340system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) 341system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) 342system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) 343system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) 344system.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses 345system.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses 346system.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses 347system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses 348system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses 349system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses 350system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018500 # miss rate for WriteReq accesses 351system.cpu0.dcache.WriteReq_miss_rate::total 0.018500 # miss rate for WriteReq accesses 352system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses 353system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses 354system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses 355system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses 356system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048343 # miss rate for StoreCondReq accesses 357system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048343 # miss rate for StoreCondReq accesses 358system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses 359system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses 360system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses 361system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses 362system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 363system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 364system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 365system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 366system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 367system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 368system.cpu0.dcache.fast_writes 0 # number of fast writes performed 369system.cpu0.dcache.cache_copies 0 # number of cache copies performed 370system.cpu0.dcache.writebacks::writebacks 511204 # number of writebacks 371system.cpu0.dcache.writebacks::total 511204 # number of writebacks 372system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 373system.cpu0.icache.tags.replacements 1109735 # number of replacements 374system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use 375system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks. 376system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks. 377system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks. 378system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 379system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor 380system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 381system.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 382system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 383system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 384system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 385system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 386system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 387system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses 388system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses 389system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits 390system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits 391system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits 392system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits 393system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits 394system.cpu0.icache.overall_hits::total 96331417 # number of overall hits 395system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses 396system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses 397system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses 398system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses 399system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses 400system.cpu0.icache.overall_misses::total 1110256 # number of overall misses 401system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses) 402system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses) 403system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses 404system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses 405system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses 406system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses 407system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses 408system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses 409system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses 410system.cpu0.icache.demand_miss_rate::total 0.011394 # miss rate for demand accesses 411system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011394 # miss rate for overall accesses 412system.cpu0.icache.overall_miss_rate::total 0.011394 # miss rate for overall accesses 413system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 414system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 415system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 416system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 417system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 418system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 419system.cpu0.icache.fast_writes 0 # number of fast writes performed 420system.cpu0.icache.cache_copies 0 # number of cache copies performed 421system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 422system.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 423system.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 424system.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 425system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 426system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 427system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 428system.cpu0.l2cache.tags.replacements 252605 # number of replacements 429system.cpu0.l2cache.tags.tagsinuse 16140.025703 # Cycle average of tags in use 430system.cpu0.l2cache.tags.total_refs 3093887 # Total number of references to valid blocks. 431system.cpu0.l2cache.tags.sampled_refs 268799 # Sample count of references to valid blocks. 432system.cpu0.l2cache.tags.avg_refs 11.510039 # Average number of references to valid blocks. 433system.cpu0.l2cache.tags.warmup_cycle 1764261500 # Cycle when the warmup percentage was hit. 434system.cpu0.l2cache.tags.occ_blocks::writebacks 8106.193746 # Average occupied blocks per requestor 435system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.314062 # Average occupied blocks per requestor 436system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.090207 # Average occupied blocks per requestor 437system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4734.889291 # Average occupied blocks per requestor 438system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3298.538396 # Average occupied blocks per requestor 439system.cpu0.l2cache.tags.occ_percent::writebacks 0.494763 # Average percentage of cache occupancy 440system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000019 # Average percentage of cache occupancy 441system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy 442system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.288995 # Average percentage of cache occupancy 443system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201327 # Average percentage of cache occupancy 444system.cpu0.l2cache.tags.occ_percent::total 0.985109 # Average percentage of cache occupancy 445system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 446system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16181 # Occupied blocks per task id 447system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 448system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id 449system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 450system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id 451system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id 452system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5523 # Occupied blocks per task id 453system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7582 # Occupied blocks per task id 454system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2694 # Occupied blocks per task id 455system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 456system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.987610 # Percentage of cache occupancy per task id 457system.cpu0.l2cache.tags.tag_accesses 60120327 # Number of tag accesses 458system.cpu0.l2cache.tags.data_accesses 60120327 # Number of data accesses 459system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7815 # number of ReadReq hits 460system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3333 # number of ReadReq hits 461system.cpu0.l2cache.ReadReq_hits::total 11148 # number of ReadReq hits 462system.cpu0.l2cache.Writeback_hits::writebacks 511204 # number of Writeback hits 463system.cpu0.l2cache.Writeback_hits::total 511204 # number of Writeback hits 464system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits 465system.cpu0.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits 466system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94430 # number of ReadExReq hits 467system.cpu0.l2cache.ReadExReq_hits::total 94430 # number of ReadExReq hits 468system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1065344 # number of ReadCleanReq hits 469system.cpu0.l2cache.ReadCleanReq_hits::total 1065344 # number of ReadCleanReq hits 470system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 351762 # number of ReadSharedReq hits 471system.cpu0.l2cache.ReadSharedReq_hits::total 351762 # number of ReadSharedReq hits 472system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7815 # number of demand (read+write) hits 473system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3333 # number of demand (read+write) hits 474system.cpu0.l2cache.demand_hits::cpu0.inst 1065344 # number of demand (read+write) hits 475system.cpu0.l2cache.demand_hits::cpu0.data 446192 # number of demand (read+write) hits 476system.cpu0.l2cache.demand_hits::total 1522684 # number of demand (read+write) hits 477system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7815 # number of overall hits 478system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3333 # number of overall hits 479system.cpu0.l2cache.overall_hits::cpu0.inst 1065344 # number of overall hits 480system.cpu0.l2cache.overall_hits::cpu0.data 446192 # number of overall hits 481system.cpu0.l2cache.overall_hits::total 1522684 # number of overall hits 482system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 232 # number of ReadReq misses 483system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses 484system.cpu0.l2cache.ReadReq_misses::total 356 # number of ReadReq misses 485system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26210 # number of UpgradeReq misses 486system.cpu0.l2cache.UpgradeReq_misses::total 26210 # number of UpgradeReq misses 487system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18442 # number of SCUpgradeReq misses 488system.cpu0.l2cache.SCUpgradeReq_misses::total 18442 # number of SCUpgradeReq misses 489system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175093 # number of ReadExReq misses 490system.cpu0.l2cache.ReadExReq_misses::total 175093 # number of ReadExReq misses 491system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 44912 # number of ReadCleanReq misses 492system.cpu0.l2cache.ReadCleanReq_misses::total 44912 # number of ReadCleanReq misses 493system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 128404 # number of ReadSharedReq misses 494system.cpu0.l2cache.ReadSharedReq_misses::total 128404 # number of ReadSharedReq misses 495system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 232 # number of demand (read+write) misses 496system.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses 497system.cpu0.l2cache.demand_misses::cpu0.inst 44912 # number of demand (read+write) misses 498system.cpu0.l2cache.demand_misses::cpu0.data 303497 # number of demand (read+write) misses 499system.cpu0.l2cache.demand_misses::total 348765 # number of demand (read+write) misses 500system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 232 # number of overall misses 501system.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses 502system.cpu0.l2cache.overall_misses::cpu0.inst 44912 # number of overall misses 503system.cpu0.l2cache.overall_misses::cpu0.data 303497 # number of overall misses 504system.cpu0.l2cache.overall_misses::total 348765 # number of overall misses 505system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8047 # number of ReadReq accesses(hits+misses) 506system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3457 # number of ReadReq accesses(hits+misses) 507system.cpu0.l2cache.ReadReq_accesses::total 11504 # number of ReadReq accesses(hits+misses) 508system.cpu0.l2cache.Writeback_accesses::writebacks 511204 # number of Writeback accesses(hits+misses) 509system.cpu0.l2cache.Writeback_accesses::total 511204 # number of Writeback accesses(hits+misses) 510system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26226 # number of UpgradeReq accesses(hits+misses) 511system.cpu0.l2cache.UpgradeReq_accesses::total 26226 # number of UpgradeReq accesses(hits+misses) 512system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18442 # number of SCUpgradeReq accesses(hits+misses) 513system.cpu0.l2cache.SCUpgradeReq_accesses::total 18442 # number of SCUpgradeReq accesses(hits+misses) 514system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269523 # number of ReadExReq accesses(hits+misses) 515system.cpu0.l2cache.ReadExReq_accesses::total 269523 # number of ReadExReq accesses(hits+misses) 516system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110256 # number of ReadCleanReq accesses(hits+misses) 517system.cpu0.l2cache.ReadCleanReq_accesses::total 1110256 # number of ReadCleanReq accesses(hits+misses) 518system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480166 # number of ReadSharedReq accesses(hits+misses) 519system.cpu0.l2cache.ReadSharedReq_accesses::total 480166 # number of ReadSharedReq accesses(hits+misses) 520system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8047 # number of demand (read+write) accesses 521system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3457 # number of demand (read+write) accesses 522system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses 523system.cpu0.l2cache.demand_accesses::cpu0.data 749689 # number of demand (read+write) accesses 524system.cpu0.l2cache.demand_accesses::total 1871449 # number of demand (read+write) accesses 525system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8047 # number of overall (read+write) accesses 526system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3457 # number of overall (read+write) accesses 527system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses 528system.cpu0.l2cache.overall_accesses::cpu0.data 749689 # number of overall (read+write) accesses 529system.cpu0.l2cache.overall_accesses::total 1871449 # number of overall (read+write) accesses 530system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for ReadReq accesses 531system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.035869 # miss rate for ReadReq accesses 532system.cpu0.l2cache.ReadReq_miss_rate::total 0.030946 # miss rate for ReadReq accesses 533system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999390 # miss rate for UpgradeReq accesses 534system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999390 # miss rate for UpgradeReq accesses 535system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 536system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 537system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649640 # miss rate for ReadExReq accesses 538system.cpu0.l2cache.ReadExReq_miss_rate::total 0.649640 # miss rate for ReadExReq accesses 539system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.040452 # miss rate for ReadCleanReq accesses 540system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.040452 # miss rate for ReadCleanReq accesses 541system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.267416 # miss rate for ReadSharedReq accesses 542system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.267416 # miss rate for ReadSharedReq accesses 543system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for demand accesses 544system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035869 # miss rate for demand accesses 545system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040452 # miss rate for demand accesses 546system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404831 # miss rate for demand accesses 547system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses 548system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028831 # miss rate for overall accesses 549system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035869 # miss rate for overall accesses 550system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040452 # miss rate for overall accesses 551system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404831 # miss rate for overall accesses 552system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses 553system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 554system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 555system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 556system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 557system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 558system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 559system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 560system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 561system.cpu0.l2cache.writebacks::writebacks 192999 # number of writebacks 562system.cpu0.l2cache.writebacks::total 192999 # number of writebacks 563system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 564system.cpu0.toL2Bus.trans_dist::ReadReq 61416 # Transaction distribution 565system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution 566system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 567system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 568system.cpu0.toL2Bus.trans_dist::Writeback 511204 # Transaction distribution 569system.cpu0.toL2Bus.trans_dist::CleanEvict 1292017 # Transaction distribution 570system.cpu0.toL2Bus.trans_dist::UpgradeReq 26226 # Transaction distribution 571system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18442 # Transaction distribution 572system.cpu0.toL2Bus.trans_dist::UpgradeResp 44668 # Transaction distribution 573system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution 574system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution 575system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110256 # Transaction distribution 576system.cpu0.toL2Bus.trans_dist::ReadSharedReq 480166 # Transaction distribution 577system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348291 # Packet count per connected master and slave (bytes) 578system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402034 # Packet count per connected master and slave (bytes) 579system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 580system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) 581system.cpu0.toL2Bus.pkt_count::total 5791961 # Packet count per connected master and slave (bytes) 582system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) 583system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80887684 # Cumulative packet size per connected master and slave (bytes) 584system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 585system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) 586system.cpu0.toL2Bus.pkt_size::total 152063428 # Cumulative packet size per connected master and slave (bytes) 587system.cpu0.toL2Bus.snoops 327822 # Total snoops (count) 588system.cpu0.toL2Bus.snoop_fanout::samples 4022806 # Request fanout histogram 589system.cpu0.toL2Bus.snoop_fanout::mean 1.061160 # Request fanout histogram 590system.cpu0.toL2Bus.snoop_fanout::stdev 0.239623 # Request fanout histogram 591system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 592system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 593system.cpu0.toL2Bus.snoop_fanout::1 3776773 93.88% 93.88% # Request fanout histogram 594system.cpu0.toL2Bus.snoop_fanout::2 246033 6.12% 100.00% # Request fanout histogram 595system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 596system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 597system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 598system.cpu0.toL2Bus.snoop_fanout::total 4022806 # Request fanout histogram 599system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 600system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 601system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 602system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 603system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 604system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 605system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 606system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 607system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 608system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 609system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 610system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 611system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 612system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 613system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 614system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 615system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 616system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 617system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 618system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 619system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 620system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 621system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 622system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 623system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 624system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 625system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 626system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 627system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 628system.cpu1.dtb.walker.walks 3358 # Table walker walks requested 629system.cpu1.dtb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 630system.cpu1.dtb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 631system.cpu1.dtb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 632system.cpu1.dtb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 633system.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 634system.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 635system.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 636system.cpu1.dtb.walker.walkPageSizes::4K 1919 74.15% 74.15% # Table walker page sizes translated 637system.cpu1.dtb.walker.walkPageSizes::1M 669 25.85% 100.00% # Table walker page sizes translated 638system.cpu1.dtb.walker.walkPageSizes::total 2588 # Table walker page sizes translated 639system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3358 # Table walker requests started/completed, data/inst 640system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 641system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 642system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2588 # Table walker requests started/completed, data/inst 643system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 644system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst 645system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst 646system.cpu1.dtb.inst_hits 0 # ITB inst hits 647system.cpu1.dtb.inst_misses 0 # ITB inst misses 648system.cpu1.dtb.read_hits 12173916 # DTB read hits 649system.cpu1.dtb.read_misses 2852 # DTB read misses 650system.cpu1.dtb.write_hits 7587209 # DTB write hits 651system.cpu1.dtb.write_misses 506 # DTB write misses 652system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 653system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 654system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 655system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 656system.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 657system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 658system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 659system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 660system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 661system.cpu1.dtb.read_accesses 12176768 # DTB read accesses 662system.cpu1.dtb.write_accesses 7587715 # DTB write accesses 663system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 664system.cpu1.dtb.hits 19761125 # DTB hits 665system.cpu1.dtb.misses 3358 # DTB misses 666system.cpu1.dtb.accesses 19764483 # DTB accesses 667system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 668system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 669system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 670system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 671system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 672system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 673system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 674system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 675system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 676system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 677system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 678system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 679system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 680system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 681system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 682system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 683system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 684system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 685system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 686system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 687system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 688system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 689system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 690system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 691system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 692system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 693system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 694system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 695system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 696system.cpu1.itb.walker.walks 1734 # Table walker walks requested 697system.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 698system.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 699system.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 700system.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 701system.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 702system.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 703system.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 704system.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 705system.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 706system.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 707system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 708system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 709system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 710system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 711system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 712system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 713system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 714system.cpu1.itb.inst_hits 53671575 # ITB inst hits 715system.cpu1.itb.inst_misses 1734 # ITB inst misses 716system.cpu1.itb.read_hits 0 # DTB read hits 717system.cpu1.itb.read_misses 0 # DTB read misses 718system.cpu1.itb.write_hits 0 # DTB write hits 719system.cpu1.itb.write_misses 0 # DTB write misses 720system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 721system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 722system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 723system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 724system.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 725system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 726system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 727system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 728system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 729system.cpu1.itb.read_accesses 0 # DTB read accesses 730system.cpu1.itb.write_accesses 0 # DTB write accesses 731system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses 732system.cpu1.itb.hits 53671575 # DTB hits 733system.cpu1.itb.misses 1734 # DTB misses 734system.cpu1.itb.accesses 53673309 # DTB accesses 735system.cpu1.numCycles 5605320274 # number of cpu cycles simulated 736system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 737system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 738system.cpu1.committedInsts 51401314 # Number of instructions committed 739system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed 740system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses 741system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 742system.cpu1.num_func_calls 9170855 # number of times a function call or return occured 743system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls 744system.cpu1.num_int_insts 56984241 # number of integer instructions 745system.cpu1.num_fp_insts 1792 # number of float instructions 746system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read 747system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written 748system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 749system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 750system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read 751system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written 752system.cpu1.num_mem_refs 20026381 # number of memory refs 753system.cpu1.num_load_insts 12289537 # Number of load instructions 754system.cpu1.num_store_insts 7736844 # Number of store instructions 755system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles 756system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles 757system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 758system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 759system.cpu1.Branches 15217493 # Number of branches fetched 760system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 761system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction 762system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction 763system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 764system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 765system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 766system.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 767system.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 768system.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 769system.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 770system.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 771system.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 772system.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 773system.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 774system.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 775system.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 776system.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 777system.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 778system.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 779system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 780system.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 781system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 782system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 783system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 784system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 785system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 786system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 787system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 788system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 789system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 790system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction 791system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction 792system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 793system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 794system.cpu1.op_class::total 65459464 # Class of executed instruction 795system.cpu1.kern.inst.arm 0 # number of arm instructions executed 796system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 797system.cpu1.dcache.tags.replacements 191938 # number of replacements 798system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use 799system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. 800system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. 801system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks. 802system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 803system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor 804system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy 805system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy 806system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 807system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 808system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 809system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 810system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses 811system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses 812system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits 813system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits 814system.cpu1.dcache.WriteReq_hits::cpu1.data 7397498 # number of WriteReq hits 815system.cpu1.dcache.WriteReq_hits::total 7397498 # number of WriteReq hits 816system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits 817system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits 818system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 819system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 820system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72436 # number of StoreCondReq hits 821system.cpu1.dcache.StoreCondReq_hits::total 72436 # number of StoreCondReq hits 822system.cpu1.dcache.demand_hits::cpu1.data 19256192 # number of demand (read+write) hits 823system.cpu1.dcache.demand_hits::total 19256192 # number of demand (read+write) hits 824system.cpu1.dcache.overall_hits::cpu1.data 19306291 # number of overall hits 825system.cpu1.dcache.overall_hits::total 19306291 # number of overall hits 826system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses 827system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses 828system.cpu1.dcache.WriteReq_misses::cpu1.data 92464 # number of WriteReq misses 829system.cpu1.dcache.WriteReq_misses::total 92464 # number of WriteReq misses 830system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses 831system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses 832system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 833system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 834system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22543 # number of StoreCondReq misses 835system.cpu1.dcache.StoreCondReq_misses::total 22543 # number of StoreCondReq misses 836system.cpu1.dcache.demand_misses::cpu1.data 229094 # number of demand (read+write) misses 837system.cpu1.dcache.demand_misses::total 229094 # number of demand (read+write) misses 838system.cpu1.dcache.overall_misses::cpu1.data 259813 # number of overall misses 839system.cpu1.dcache.overall_misses::total 259813 # number of overall misses 840system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) 841system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) 842system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) 843system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses) 844system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 845system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 846system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 847system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 848system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 849system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 850system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses 851system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses 852system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses 853system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses 854system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses 855system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses 856system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses 857system.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses 858system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses 859system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses 860system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 861system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 862system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237347 # miss rate for StoreCondReq accesses 863system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237347 # miss rate for StoreCondReq accesses 864system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 865system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 866system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 867system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 868system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 869system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 870system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 871system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 872system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 873system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 874system.cpu1.dcache.fast_writes 0 # number of fast writes performed 875system.cpu1.dcache.cache_copies 0 # number of cache copies performed 876system.cpu1.dcache.writebacks::writebacks 120813 # number of writebacks 877system.cpu1.dcache.writebacks::total 120813 # number of writebacks 878system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 879system.cpu1.icache.tags.replacements 523373 # number of replacements 880system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use 881system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks. 882system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. 883system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks. 884system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 885system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor 886system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 887system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 888system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 889system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 890system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 891system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 892system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses 893system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses 894system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits 895system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits 896system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits 897system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits 898system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits 899system.cpu1.icache.overall_hits::total 53148780 # number of overall hits 900system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses 901system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses 902system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses 903system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses 904system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses 905system.cpu1.icache.overall_misses::total 523885 # number of overall misses 906system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses) 907system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses) 908system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses 909system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses 910system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses 911system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses 912system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 913system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 914system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 915system.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 916system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 917system.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 918system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 919system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 920system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 921system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 922system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 923system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 924system.cpu1.icache.fast_writes 0 # number of fast writes performed 925system.cpu1.icache.cache_copies 0 # number of cache copies performed 926system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 927system.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 928system.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 929system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 930system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 931system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 932system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 933system.cpu1.l2cache.tags.replacements 48465 # number of replacements 934system.cpu1.l2cache.tags.tagsinuse 15315.522353 # Cycle average of tags in use 935system.cpu1.l2cache.tags.total_refs 1307502 # Total number of references to valid blocks. 936system.cpu1.l2cache.tags.sampled_refs 63323 # Sample count of references to valid blocks. 937system.cpu1.l2cache.tags.avg_refs 20.648137 # Average number of references to valid blocks. 938system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 939system.cpu1.l2cache.tags.occ_blocks::writebacks 8309.782152 # Average occupied blocks per requestor 940system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.119682 # Average occupied blocks per requestor 941system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.019591 # Average occupied blocks per requestor 942system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3270.237857 # Average occupied blocks per requestor 943system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3730.363071 # Average occupied blocks per requestor 944system.cpu1.l2cache.tags.occ_percent::writebacks 0.507189 # Average percentage of cache occupancy 945system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000190 # Average percentage of cache occupancy 946system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 947system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199599 # Average percentage of cache occupancy 948system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.227683 # Average percentage of cache occupancy 949system.cpu1.l2cache.tags.occ_percent::total 0.934785 # Average percentage of cache occupancy 950system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id 951system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14839 # Occupied blocks per task id 952system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 953system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 954system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 955system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 554 # Occupied blocks per task id 956system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9338 # Occupied blocks per task id 957system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4947 # Occupied blocks per task id 958system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id 959system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905701 # Percentage of cache occupancy per task id 960system.cpu1.l2cache.tags.tag_accesses 24723530 # Number of tag accesses 961system.cpu1.l2cache.tags.data_accesses 24723530 # Number of data accesses 962system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3108 # number of ReadReq hits 963system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1684 # number of ReadReq hits 964system.cpu1.l2cache.ReadReq_hits::total 4792 # number of ReadReq hits 965system.cpu1.l2cache.Writeback_hits::writebacks 120813 # number of Writeback hits 966system.cpu1.l2cache.Writeback_hits::total 120813 # number of Writeback hits 967system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits 968system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits 969system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19803 # number of ReadExReq hits 970system.cpu1.l2cache.ReadExReq_hits::total 19803 # number of ReadExReq hits 971system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510140 # number of ReadCleanReq hits 972system.cpu1.l2cache.ReadCleanReq_hits::total 510140 # number of ReadCleanReq hits 973system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99386 # number of ReadSharedReq hits 974system.cpu1.l2cache.ReadSharedReq_hits::total 99386 # number of ReadSharedReq hits 975system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3108 # number of demand (read+write) hits 976system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1684 # number of demand (read+write) hits 977system.cpu1.l2cache.demand_hits::cpu1.inst 510140 # number of demand (read+write) hits 978system.cpu1.l2cache.demand_hits::cpu1.data 119189 # number of demand (read+write) hits 979system.cpu1.l2cache.demand_hits::total 634121 # number of demand (read+write) hits 980system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3108 # number of overall hits 981system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1684 # number of overall hits 982system.cpu1.l2cache.overall_hits::cpu1.inst 510140 # number of overall hits 983system.cpu1.l2cache.overall_hits::cpu1.data 119189 # number of overall hits 984system.cpu1.l2cache.overall_hits::total 634121 # number of overall hits 985system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 340 # number of ReadReq misses 986system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses 987system.cpu1.l2cache.ReadReq_misses::total 610 # number of ReadReq misses 988system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28840 # number of UpgradeReq misses 989system.cpu1.l2cache.UpgradeReq_misses::total 28840 # number of UpgradeReq misses 990system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22543 # number of SCUpgradeReq misses 991system.cpu1.l2cache.SCUpgradeReq_misses::total 22543 # number of SCUpgradeReq misses 992system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43813 # number of ReadExReq misses 993system.cpu1.l2cache.ReadExReq_misses::total 43813 # number of ReadExReq misses 994system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13745 # number of ReadCleanReq misses 995system.cpu1.l2cache.ReadCleanReq_misses::total 13745 # number of ReadCleanReq misses 996system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73281 # number of ReadSharedReq misses 997system.cpu1.l2cache.ReadSharedReq_misses::total 73281 # number of ReadSharedReq misses 998system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 340 # number of demand (read+write) misses 999system.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses 1000system.cpu1.l2cache.demand_misses::cpu1.inst 13745 # number of demand (read+write) misses 1001system.cpu1.l2cache.demand_misses::cpu1.data 117094 # number of demand (read+write) misses 1002system.cpu1.l2cache.demand_misses::total 131449 # number of demand (read+write) misses 1003system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 340 # number of overall misses 1004system.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses 1005system.cpu1.l2cache.overall_misses::cpu1.inst 13745 # number of overall misses 1006system.cpu1.l2cache.overall_misses::cpu1.data 117094 # number of overall misses 1007system.cpu1.l2cache.overall_misses::total 131449 # number of overall misses 1008system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3448 # number of ReadReq accesses(hits+misses) 1009system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1954 # number of ReadReq accesses(hits+misses) 1010system.cpu1.l2cache.ReadReq_accesses::total 5402 # number of ReadReq accesses(hits+misses) 1011system.cpu1.l2cache.Writeback_accesses::writebacks 120813 # number of Writeback accesses(hits+misses) 1012system.cpu1.l2cache.Writeback_accesses::total 120813 # number of Writeback accesses(hits+misses) 1013system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28848 # number of UpgradeReq accesses(hits+misses) 1014system.cpu1.l2cache.UpgradeReq_accesses::total 28848 # number of UpgradeReq accesses(hits+misses) 1015system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22543 # number of SCUpgradeReq accesses(hits+misses) 1016system.cpu1.l2cache.SCUpgradeReq_accesses::total 22543 # number of SCUpgradeReq accesses(hits+misses) 1017system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) 1018system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) 1019system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523885 # number of ReadCleanReq accesses(hits+misses) 1020system.cpu1.l2cache.ReadCleanReq_accesses::total 523885 # number of ReadCleanReq accesses(hits+misses) 1021system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172667 # number of ReadSharedReq accesses(hits+misses) 1022system.cpu1.l2cache.ReadSharedReq_accesses::total 172667 # number of ReadSharedReq accesses(hits+misses) 1023system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3448 # number of demand (read+write) accesses 1024system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1954 # number of demand (read+write) accesses 1025system.cpu1.l2cache.demand_accesses::cpu1.inst 523885 # number of demand (read+write) accesses 1026system.cpu1.l2cache.demand_accesses::cpu1.data 236283 # number of demand (read+write) accesses 1027system.cpu1.l2cache.demand_accesses::total 765570 # number of demand (read+write) accesses 1028system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3448 # number of overall (read+write) accesses 1029system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1954 # number of overall (read+write) accesses 1030system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses 1031system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses 1032system.cpu1.l2cache.overall_accesses::total 765570 # number of overall (read+write) accesses 1033system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for ReadReq accesses 1034system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.138178 # miss rate for ReadReq accesses 1035system.cpu1.l2cache.ReadReq_miss_rate::total 0.112921 # miss rate for ReadReq accesses 1036system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses 1037system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses 1038system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 1039system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1040system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688710 # miss rate for ReadExReq accesses 1041system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688710 # miss rate for ReadExReq accesses 1042system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.026237 # miss rate for ReadCleanReq accesses 1043system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.026237 # miss rate for ReadCleanReq accesses 1044system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.424407 # miss rate for ReadSharedReq accesses 1045system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.424407 # miss rate for ReadSharedReq accesses 1046system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for demand accesses 1047system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.138178 # miss rate for demand accesses 1048system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026237 # miss rate for demand accesses 1049system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495567 # miss rate for demand accesses 1050system.cpu1.l2cache.demand_miss_rate::total 0.171701 # miss rate for demand accesses 1051system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098608 # miss rate for overall accesses 1052system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.138178 # miss rate for overall accesses 1053system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026237 # miss rate for overall accesses 1054system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495567 # miss rate for overall accesses 1055system.cpu1.l2cache.overall_miss_rate::total 0.171701 # miss rate for overall accesses 1056system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1057system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1058system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1059system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1060system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1061system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1062system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 1063system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 1064system.cpu1.l2cache.writebacks::writebacks 32917 # number of writebacks 1065system.cpu1.l2cache.writebacks::total 32917 # number of writebacks 1066system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1067system.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution 1068system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution 1069system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 1070system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 1071system.cpu1.toL2Bus.trans_dist::Writeback 120813 # Transaction distribution 1072system.cpu1.toL2Bus.trans_dist::CleanEvict 594498 # Transaction distribution 1073system.cpu1.toL2Bus.trans_dist::UpgradeReq 28848 # Transaction distribution 1074system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22543 # Transaction distribution 1075system.cpu1.toL2Bus.trans_dist::UpgradeResp 51391 # Transaction distribution 1076system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution 1077system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution 1078system.cpu1.toL2Bus.trans_dist::ReadCleanReq 523885 # Transaction distribution 1079system.cpu1.toL2Bus.trans_dist::ReadSharedReq 172667 # Transaction distribution 1080system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571497 # Packet count per connected master and slave (bytes) 1081system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778746 # Packet count per connected master and slave (bytes) 1082system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 1083system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) 1084system.cpu1.toL2Bus.pkt_count::total 2368937 # Packet count per connected master and slave (bytes) 1085system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) 1086system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22873326 # Cumulative packet size per connected master and slave (bytes) 1087system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 1088system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) 1089system.cpu1.toL2Bus.pkt_size::total 56440062 # Cumulative packet size per connected master and slave (bytes) 1090system.cpu1.toL2Bus.snoops 568500 # Total snoops (count) 1091system.cpu1.toL2Bus.snoop_fanout::samples 2040956 # Request fanout histogram 1092system.cpu1.toL2Bus.snoop_fanout::mean 1.248991 # Request fanout histogram 1093system.cpu1.toL2Bus.snoop_fanout::stdev 0.432428 # Request fanout histogram 1094system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1095system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1096system.cpu1.toL2Bus.snoop_fanout::1 1532777 75.10% 75.10% # Request fanout histogram 1097system.cpu1.toL2Bus.snoop_fanout::2 508179 24.90% 100.00% # Request fanout histogram 1098system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1099system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1100system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1101system.cpu1.toL2Bus.snoop_fanout::total 2040956 # Request fanout histogram 1102system.iobus.trans_dist::ReadReq 30995 # Transaction distribution 1103system.iobus.trans_dist::ReadResp 30995 # Transaction distribution 1104system.iobus.trans_dist::WriteReq 59419 # Transaction distribution 1105system.iobus.trans_dist::WriteResp 59419 # Transaction distribution 1106system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 1107system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 1108system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 1109system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 1110system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 1111system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 1112system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 1113system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1114system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1115system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1116system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 1117system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1118system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 1119system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 1120system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 1121system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 1122system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 1123system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1124system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 1125system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1126system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1127system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 1128system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 1129system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 1130system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 1131system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 1132system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 1133system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 1134system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 1135system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 1136system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 1137system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 1138system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1139system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1140system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1141system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 1142system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1143system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1144system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 1145system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 1146system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1147system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 1148system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 1149system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 1150system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 1151system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1152system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 1153system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 1154system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 1155system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 1156system.iocache.tags.replacements 36442 # number of replacements 1157system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use 1158system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1159system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 1160system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1161system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. 1162system.iocache.tags.occ_blocks::realview.ide 14.586092 # Average occupied blocks per requestor 1163system.iocache.tags.occ_percent::realview.ide 0.911631 # Average percentage of cache occupancy 1164system.iocache.tags.occ_percent::total 0.911631 # Average percentage of cache occupancy 1165system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1166system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1167system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1168system.iocache.tags.tag_accesses 328284 # Number of tag accesses 1169system.iocache.tags.data_accesses 328284 # Number of data accesses 1170system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 1171system.iocache.ReadReq_misses::total 252 # number of ReadReq misses 1172system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 1173system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 1174system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 1175system.iocache.demand_misses::total 252 # number of demand (read+write) misses 1176system.iocache.overall_misses::realview.ide 252 # number of overall misses 1177system.iocache.overall_misses::total 252 # number of overall misses 1178system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 1179system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 1180system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 1181system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 1182system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 1183system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 1184system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 1185system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 1186system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1187system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1188system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1189system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1190system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1191system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1192system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1193system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1194system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1195system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1196system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 1197system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1198system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1199system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1200system.iocache.fast_writes 0 # number of fast writes performed 1201system.iocache.cache_copies 0 # number of cache copies performed 1202system.iocache.writebacks::writebacks 36190 # number of writebacks 1203system.iocache.writebacks::total 36190 # number of writebacks 1204system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1205system.l2c.tags.replacements 106825 # number of replacements 1206system.l2c.tags.tagsinuse 62089.721630 # Cycle average of tags in use 1207system.l2c.tags.total_refs 288805 # Total number of references to valid blocks. 1208system.l2c.tags.sampled_refs 167355 # Sample count of references to valid blocks. 1209system.l2c.tags.avg_refs 1.725703 # Average number of references to valid blocks. 1210system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1211system.l2c.tags.occ_blocks::writebacks 47734.864298 # Average occupied blocks per requestor 1212system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.035923 # Average occupied blocks per requestor 1213system.l2c.tags.occ_blocks::cpu0.itb.walker 0.041981 # Average occupied blocks per requestor 1214system.l2c.tags.occ_blocks::cpu0.inst 7941.182718 # Average occupied blocks per requestor 1215system.l2c.tags.occ_blocks::cpu0.data 4069.651943 # Average occupied blocks per requestor 1216system.l2c.tags.occ_blocks::cpu1.inst 1613.022165 # Average occupied blocks per requestor 1217system.l2c.tags.occ_blocks::cpu1.data 726.922600 # Average occupied blocks per requestor 1218system.l2c.tags.occ_percent::writebacks 0.728376 # Average percentage of cache occupancy 1219system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000062 # Average percentage of cache occupancy 1220system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy 1221system.l2c.tags.occ_percent::cpu0.inst 0.121173 # Average percentage of cache occupancy 1222system.l2c.tags.occ_percent::cpu0.data 0.062098 # Average percentage of cache occupancy 1223system.l2c.tags.occ_percent::cpu1.inst 0.024613 # Average percentage of cache occupancy 1224system.l2c.tags.occ_percent::cpu1.data 0.011092 # Average percentage of cache occupancy 1225system.l2c.tags.occ_percent::total 0.947414 # Average percentage of cache occupancy 1226system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id 1227system.l2c.tags.occ_task_id_blocks::1024 60523 # Occupied blocks per task id 1228system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id 1229system.l2c.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 1230system.l2c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 1231system.l2c.tags.age_task_id_blocks_1024::2 1889 # Occupied blocks per task id 1232system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id 1233system.l2c.tags.age_task_id_blocks_1024::4 45532 # Occupied blocks per task id 1234system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id 1235system.l2c.tags.occ_task_id_percent::1024 0.923508 # Percentage of cache occupancy per task id 1236system.l2c.tags.tag_accesses 5581048 # Number of tag accesses 1237system.l2c.tags.data_accesses 5581048 # Number of data accesses 1238system.l2c.Writeback_hits::writebacks 225916 # number of Writeback hits 1239system.l2c.Writeback_hits::total 225916 # number of Writeback hits 1240system.l2c.UpgradeReq_hits::cpu0.data 290 # number of UpgradeReq hits 1241system.l2c.UpgradeReq_hits::cpu1.data 72 # number of UpgradeReq hits 1242system.l2c.UpgradeReq_hits::total 362 # number of UpgradeReq hits 1243system.l2c.SCUpgradeReq_hits::cpu0.data 60 # number of SCUpgradeReq hits 1244system.l2c.SCUpgradeReq_hits::cpu1.data 8 # number of SCUpgradeReq hits 1245system.l2c.SCUpgradeReq_hits::total 68 # number of SCUpgradeReq hits 1246system.l2c.ReadExReq_hits::cpu0.data 14091 # number of ReadExReq hits 1247system.l2c.ReadExReq_hits::cpu1.data 3087 # number of ReadExReq hits 1248system.l2c.ReadExReq_hits::total 17178 # number of ReadExReq hits 1249system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 93 # number of ReadSharedReq hits 1250system.l2c.ReadSharedReq_hits::cpu0.itb.walker 64 # number of ReadSharedReq hits 1251system.l2c.ReadSharedReq_hits::cpu0.inst 28425 # number of ReadSharedReq hits 1252system.l2c.ReadSharedReq_hits::cpu0.data 76409 # number of ReadSharedReq hits 1253system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 42 # number of ReadSharedReq hits 1254system.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits 1255system.l2c.ReadSharedReq_hits::cpu1.inst 11464 # number of ReadSharedReq hits 1256system.l2c.ReadSharedReq_hits::cpu1.data 11380 # number of ReadSharedReq hits 1257system.l2c.ReadSharedReq_hits::total 127912 # number of ReadSharedReq hits 1258system.l2c.demand_hits::cpu0.dtb.walker 93 # number of demand (read+write) hits 1259system.l2c.demand_hits::cpu0.itb.walker 64 # number of demand (read+write) hits 1260system.l2c.demand_hits::cpu0.inst 28425 # number of demand (read+write) hits 1261system.l2c.demand_hits::cpu0.data 90500 # number of demand (read+write) hits 1262system.l2c.demand_hits::cpu1.dtb.walker 42 # number of demand (read+write) hits 1263system.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits 1264system.l2c.demand_hits::cpu1.inst 11464 # number of demand (read+write) hits 1265system.l2c.demand_hits::cpu1.data 14467 # number of demand (read+write) hits 1266system.l2c.demand_hits::total 145090 # number of demand (read+write) hits 1267system.l2c.overall_hits::cpu0.dtb.walker 93 # number of overall hits 1268system.l2c.overall_hits::cpu0.itb.walker 64 # number of overall hits 1269system.l2c.overall_hits::cpu0.inst 28425 # number of overall hits 1270system.l2c.overall_hits::cpu0.data 90500 # number of overall hits 1271system.l2c.overall_hits::cpu1.dtb.walker 42 # number of overall hits 1272system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits 1273system.l2c.overall_hits::cpu1.inst 11464 # number of overall hits 1274system.l2c.overall_hits::cpu1.data 14467 # number of overall hits 1275system.l2c.overall_hits::total 145090 # number of overall hits 1276system.l2c.UpgradeReq_misses::cpu0.data 9984 # number of UpgradeReq misses 1277system.l2c.UpgradeReq_misses::cpu1.data 3297 # number of UpgradeReq misses 1278system.l2c.UpgradeReq_misses::total 13281 # number of UpgradeReq misses 1279system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses 1280system.l2c.SCUpgradeReq_misses::cpu1.data 1178 # number of SCUpgradeReq misses 1281system.l2c.SCUpgradeReq_misses::total 1936 # number of SCUpgradeReq misses 1282system.l2c.ReadExReq_misses::cpu0.data 136573 # number of ReadExReq misses 1283system.l2c.ReadExReq_misses::cpu1.data 15836 # number of ReadExReq misses 1284system.l2c.ReadExReq_misses::total 152409 # number of ReadExReq misses 1285system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses 1286system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 1287system.l2c.ReadSharedReq_misses::cpu0.inst 16484 # number of ReadSharedReq misses 1288system.l2c.ReadSharedReq_misses::cpu0.data 11221 # number of ReadSharedReq misses 1289system.l2c.ReadSharedReq_misses::cpu1.inst 2277 # number of ReadSharedReq misses 1290system.l2c.ReadSharedReq_misses::cpu1.data 1138 # number of ReadSharedReq misses 1291system.l2c.ReadSharedReq_misses::total 31129 # number of ReadSharedReq misses 1292system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 1293system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 1294system.l2c.demand_misses::cpu0.inst 16484 # number of demand (read+write) misses 1295system.l2c.demand_misses::cpu0.data 147794 # number of demand (read+write) misses 1296system.l2c.demand_misses::cpu1.inst 2277 # number of demand (read+write) misses 1297system.l2c.demand_misses::cpu1.data 16974 # number of demand (read+write) misses 1298system.l2c.demand_misses::total 183538 # number of demand (read+write) misses 1299system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 1300system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 1301system.l2c.overall_misses::cpu0.inst 16484 # number of overall misses 1302system.l2c.overall_misses::cpu0.data 147794 # number of overall misses 1303system.l2c.overall_misses::cpu1.inst 2277 # number of overall misses 1304system.l2c.overall_misses::cpu1.data 16974 # number of overall misses 1305system.l2c.overall_misses::total 183538 # number of overall misses 1306system.l2c.Writeback_accesses::writebacks 225916 # number of Writeback accesses(hits+misses) 1307system.l2c.Writeback_accesses::total 225916 # number of Writeback accesses(hits+misses) 1308system.l2c.UpgradeReq_accesses::cpu0.data 10274 # number of UpgradeReq accesses(hits+misses) 1309system.l2c.UpgradeReq_accesses::cpu1.data 3369 # number of UpgradeReq accesses(hits+misses) 1310system.l2c.UpgradeReq_accesses::total 13643 # number of UpgradeReq accesses(hits+misses) 1311system.l2c.SCUpgradeReq_accesses::cpu0.data 818 # number of SCUpgradeReq accesses(hits+misses) 1312system.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) 1313system.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses) 1314system.l2c.ReadExReq_accesses::cpu0.data 150664 # number of ReadExReq accesses(hits+misses) 1315system.l2c.ReadExReq_accesses::cpu1.data 18923 # number of ReadExReq accesses(hits+misses) 1316system.l2c.ReadExReq_accesses::total 169587 # number of ReadExReq accesses(hits+misses) 1317system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 100 # number of ReadSharedReq accesses(hits+misses) 1318system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 66 # number of ReadSharedReq accesses(hits+misses) 1319system.l2c.ReadSharedReq_accesses::cpu0.inst 44909 # number of ReadSharedReq accesses(hits+misses) 1320system.l2c.ReadSharedReq_accesses::cpu0.data 87630 # number of ReadSharedReq accesses(hits+misses) 1321system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 42 # number of ReadSharedReq accesses(hits+misses) 1322system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) 1323system.l2c.ReadSharedReq_accesses::cpu1.inst 13741 # number of ReadSharedReq accesses(hits+misses) 1324system.l2c.ReadSharedReq_accesses::cpu1.data 12518 # number of ReadSharedReq accesses(hits+misses) 1325system.l2c.ReadSharedReq_accesses::total 159041 # number of ReadSharedReq accesses(hits+misses) 1326system.l2c.demand_accesses::cpu0.dtb.walker 100 # number of demand (read+write) accesses 1327system.l2c.demand_accesses::cpu0.itb.walker 66 # number of demand (read+write) accesses 1328system.l2c.demand_accesses::cpu0.inst 44909 # number of demand (read+write) accesses 1329system.l2c.demand_accesses::cpu0.data 238294 # number of demand (read+write) accesses 1330system.l2c.demand_accesses::cpu1.dtb.walker 42 # number of demand (read+write) accesses 1331system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses 1332system.l2c.demand_accesses::cpu1.inst 13741 # number of demand (read+write) accesses 1333system.l2c.demand_accesses::cpu1.data 31441 # number of demand (read+write) accesses 1334system.l2c.demand_accesses::total 328628 # number of demand (read+write) accesses 1335system.l2c.overall_accesses::cpu0.dtb.walker 100 # number of overall (read+write) accesses 1336system.l2c.overall_accesses::cpu0.itb.walker 66 # number of overall (read+write) accesses 1337system.l2c.overall_accesses::cpu0.inst 44909 # number of overall (read+write) accesses 1338system.l2c.overall_accesses::cpu0.data 238294 # number of overall (read+write) accesses 1339system.l2c.overall_accesses::cpu1.dtb.walker 42 # number of overall (read+write) accesses 1340system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses 1341system.l2c.overall_accesses::cpu1.inst 13741 # number of overall (read+write) accesses 1342system.l2c.overall_accesses::cpu1.data 31441 # number of overall (read+write) accesses 1343system.l2c.overall_accesses::total 328628 # number of overall (read+write) accesses 1344system.l2c.UpgradeReq_miss_rate::cpu0.data 0.971773 # miss rate for UpgradeReq accesses 1345system.l2c.UpgradeReq_miss_rate::cpu1.data 0.978629 # miss rate for UpgradeReq accesses 1346system.l2c.UpgradeReq_miss_rate::total 0.973466 # miss rate for UpgradeReq accesses 1347system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.926650 # miss rate for SCUpgradeReq accesses 1348system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.993255 # miss rate for SCUpgradeReq accesses 1349system.l2c.SCUpgradeReq_miss_rate::total 0.966068 # miss rate for SCUpgradeReq accesses 1350system.l2c.ReadExReq_miss_rate::cpu0.data 0.906474 # miss rate for ReadExReq accesses 1351system.l2c.ReadExReq_miss_rate::cpu1.data 0.836865 # miss rate for ReadExReq accesses 1352system.l2c.ReadExReq_miss_rate::total 0.898707 # miss rate for ReadExReq accesses 1353system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for ReadSharedReq accesses 1354system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.030303 # miss rate for ReadSharedReq accesses 1355system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.367053 # miss rate for ReadSharedReq accesses 1356system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128050 # miss rate for ReadSharedReq accesses 1357system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.165708 # miss rate for ReadSharedReq accesses 1358system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.090909 # miss rate for ReadSharedReq accesses 1359system.l2c.ReadSharedReq_miss_rate::total 0.195729 # miss rate for ReadSharedReq accesses 1360system.l2c.demand_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for demand accesses 1361system.l2c.demand_miss_rate::cpu0.itb.walker 0.030303 # miss rate for demand accesses 1362system.l2c.demand_miss_rate::cpu0.inst 0.367053 # miss rate for demand accesses 1363system.l2c.demand_miss_rate::cpu0.data 0.620217 # miss rate for demand accesses 1364system.l2c.demand_miss_rate::cpu1.inst 0.165708 # miss rate for demand accesses 1365system.l2c.demand_miss_rate::cpu1.data 0.539868 # miss rate for demand accesses 1366system.l2c.demand_miss_rate::total 0.558498 # miss rate for demand accesses 1367system.l2c.overall_miss_rate::cpu0.dtb.walker 0.070000 # miss rate for overall accesses 1368system.l2c.overall_miss_rate::cpu0.itb.walker 0.030303 # miss rate for overall accesses 1369system.l2c.overall_miss_rate::cpu0.inst 0.367053 # miss rate for overall accesses 1370system.l2c.overall_miss_rate::cpu0.data 0.620217 # miss rate for overall accesses 1371system.l2c.overall_miss_rate::cpu1.inst 0.165708 # miss rate for overall accesses 1372system.l2c.overall_miss_rate::cpu1.data 0.539868 # miss rate for overall accesses 1373system.l2c.overall_miss_rate::total 0.558498 # miss rate for overall accesses 1374system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1375system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1376system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1377system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1378system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1379system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1380system.l2c.fast_writes 0 # number of fast writes performed 1381system.l2c.cache_copies 0 # number of cache copies performed 1382system.l2c.writebacks::writebacks 96236 # number of writebacks 1383system.l2c.writebacks::total 96236 # number of writebacks 1384system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 1385system.membus.trans_dist::ReadReq 43997 # Transaction distribution 1386system.membus.trans_dist::ReadResp 75378 # Transaction distribution 1387system.membus.trans_dist::WriteReq 30846 # Transaction distribution 1388system.membus.trans_dist::WriteResp 30846 # Transaction distribution 1389system.membus.trans_dist::Writeback 132426 # Transaction distribution 1390system.membus.trans_dist::CleanEvict 15452 # Transaction distribution 1391system.membus.trans_dist::UpgradeReq 60361 # Transaction distribution 1392system.membus.trans_dist::SCUpgradeReq 40917 # Transaction distribution 1393system.membus.trans_dist::UpgradeResp 15653 # Transaction distribution 1394system.membus.trans_dist::ReadExReq 196055 # Transaction distribution 1395system.membus.trans_dist::ReadExResp 151973 # Transaction distribution 1396system.membus.trans_dist::ReadSharedReq 31381 # Transaction distribution 1397system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1398system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1399system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 1400system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 1401system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 1402system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 666955 # Packet count per connected master and slave (bytes) 1403system.membus.pkt_count_system.l2c.mem_side::total 788339 # Packet count per connected master and slave (bytes) 1404system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 1405system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) 1406system.membus.pkt_count::total 897733 # Packet count per connected master and slave (bytes) 1407system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 1408system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 1409system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 1410system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17934348 # Cumulative packet size per connected master and slave (bytes) 1411system.membus.pkt_size_system.l2c.mem_side::total 18124130 # Cumulative packet size per connected master and slave (bytes) 1412system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 1413system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 1414system.membus.pkt_size::total 20456418 # Cumulative packet size per connected master and slave (bytes) 1415system.membus.snoops 0 # Total snoops (count) 1416system.membus.snoop_fanout::samples 587659 # Request fanout histogram 1417system.membus.snoop_fanout::mean 1 # Request fanout histogram 1418system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1419system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1420system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1421system.membus.snoop_fanout::1 587659 100.00% 100.00% # Request fanout histogram 1422system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1423system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1424system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1425system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1426system.membus.snoop_fanout::total 587659 # Request fanout histogram 1427system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1428system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1429system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1430system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1431system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1432system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1433system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1434system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1435system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1436system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1437system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1438system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1439system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1440system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1441system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1442system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1443system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1444system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1445system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1446system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1447system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1448system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1449system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1450system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1451system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1452system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1453system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1454system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1455system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1456system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1457system.realview.ethernet.droppedPackets 0 # number of packets dropped 1458system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution 1459system.toL2Bus.trans_dist::ReadResp 305308 # Transaction distribution 1460system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 1461system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 1462system.toL2Bus.trans_dist::Writeback 225916 # Transaction distribution 1463system.toL2Bus.trans_dist::CleanEvict 84734 # Transaction distribution 1464system.toL2Bus.trans_dist::UpgradeReq 60287 # Transaction distribution 1465system.toL2Bus.trans_dist::SCUpgradeReq 40985 # Transaction distribution 1466system.toL2Bus.trans_dist::UpgradeResp 101272 # Transaction distribution 1467system.toL2Bus.trans_dist::ReadExReq 213669 # Transaction distribution 1468system.toL2Bus.trans_dist::ReadExResp 213669 # Transaction distribution 1469system.toL2Bus.trans_dist::ReadSharedReq 261308 # Transaction distribution 1470system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1184948 # Packet count per connected master and slave (bytes) 1471system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 427892 # Packet count per connected master and slave (bytes) 1472system.toL2Bus.pkt_count::total 1612840 # Packet count per connected master and slave (bytes) 1473system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34685820 # Cumulative packet size per connected master and slave (bytes) 1474system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10417842 # Cumulative packet size per connected master and slave (bytes) 1475system.toL2Bus.pkt_size::total 45103662 # Cumulative packet size per connected master and slave (bytes) 1476system.toL2Bus.snoops 36713 # Total snoops (count) 1477system.toL2Bus.snoop_fanout::samples 998221 # Request fanout histogram 1478system.toL2Bus.snoop_fanout::mean 1.036541 # Request fanout histogram 1479system.toL2Bus.snoop_fanout::stdev 0.187632 # Request fanout histogram 1480system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1481system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1482system.toL2Bus.snoop_fanout::1 961745 96.35% 96.35% # Request fanout histogram 1483system.toL2Bus.snoop_fanout::2 36476 3.65% 100.00% # Request fanout histogram 1484system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1485system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1486system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1487system.toL2Bus.snoop_fanout::total 998221 # Request fanout histogram 1488 1489---------- End Simulation Statistics ---------- 1490