stats.txt revision 10726
1
2---------- Begin Simulation Statistics ----------
3sim_seconds                                  2.802895                       # Number of seconds simulated
4sim_ticks                                2802894699500                       # Number of ticks simulated
5final_tick                               2802894699500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq                                 1000000000000                       # Frequency of simulated ticks
7host_inst_rate                                1337323                       # Simulator instruction rate (inst/s)
8host_op_rate                                  1629508                       # Simulator op (including micro ops) rate (op/s)
9host_tick_rate                            25528979782                       # Simulator tick rate (ticks/s)
10host_mem_usage                                 626168                       # Number of bytes of host memory used
11host_seconds                                   109.79                       # Real time elapsed on the host
12sim_insts                                   146828240                       # Number of instructions simulated
13sim_ops                                     178908039                       # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage                       1                       # Voltage in Volts
15system.clk_domain.clock                          1000                       # Clock period in ticks
16system.physmem.bytes_read::cpu0.dtb.walker          448                       # Number of bytes read from this memory
17system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
18system.physmem.bytes_read::cpu0.inst          1117604                       # Number of bytes read from this memory
19system.physmem.bytes_read::cpu0.data          9440956                       # Number of bytes read from this memory
20system.physmem.bytes_read::cpu1.dtb.walker          128                       # Number of bytes read from this memory
21system.physmem.bytes_read::cpu1.inst           152020                       # Number of bytes read from this memory
22system.physmem.bytes_read::cpu1.data          1081568                       # Number of bytes read from this memory
23system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
24system.physmem.bytes_read::total             11793812                       # Number of bytes read from this memory
25system.physmem.bytes_inst_read::cpu0.inst      1117604                       # Number of instructions bytes read from this memory
26system.physmem.bytes_inst_read::cpu1.inst       152020                       # Number of instructions bytes read from this memory
27system.physmem.bytes_inst_read::total         1269624                       # Number of instructions bytes read from this memory
28system.physmem.bytes_written::writebacks      8390656                       # Number of bytes written to this memory
29system.physmem.bytes_written::cpu0.data         17704                       # Number of bytes written to this memory
30system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
31system.physmem.bytes_written::total           8408400                       # Number of bytes written to this memory
32system.physmem.num_reads::cpu0.dtb.walker            7                       # Number of read requests responded to by this memory
33system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
34system.physmem.num_reads::cpu0.inst             25916                       # Number of read requests responded to by this memory
35system.physmem.num_reads::cpu0.data            148040                       # Number of read requests responded to by this memory
36system.physmem.num_reads::cpu1.dtb.walker            2                       # Number of read requests responded to by this memory
37system.physmem.num_reads::cpu1.inst              2530                       # Number of read requests responded to by this memory
38system.physmem.num_reads::cpu1.data             16923                       # Number of read requests responded to by this memory
39system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
40system.physmem.num_reads::total                193435                       # Number of read requests responded to by this memory
41system.physmem.num_writes::writebacks          131104                       # Number of write requests responded to by this memory
42system.physmem.num_writes::cpu0.data             4426                       # Number of write requests responded to by this memory
43system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
44system.physmem.num_writes::total               135540                       # Number of write requests responded to by this memory
45system.physmem.bw_read::cpu0.dtb.walker           160                       # Total read bandwidth from this memory (bytes/s)
46system.physmem.bw_read::cpu0.itb.walker            46                       # Total read bandwidth from this memory (bytes/s)
47system.physmem.bw_read::cpu0.inst              398732                       # Total read bandwidth from this memory (bytes/s)
48system.physmem.bw_read::cpu0.data             3368288                       # Total read bandwidth from this memory (bytes/s)
49system.physmem.bw_read::cpu1.dtb.walker            46                       # Total read bandwidth from this memory (bytes/s)
50system.physmem.bw_read::cpu1.inst               54237                       # Total read bandwidth from this memory (bytes/s)
51system.physmem.bw_read::cpu1.data              385875                       # Total read bandwidth from this memory (bytes/s)
52system.physmem.bw_read::realview.ide              343                       # Total read bandwidth from this memory (bytes/s)
53system.physmem.bw_read::total                 4207726                       # Total read bandwidth from this memory (bytes/s)
54system.physmem.bw_inst_read::cpu0.inst         398732                       # Instruction read bandwidth from this memory (bytes/s)
55system.physmem.bw_inst_read::cpu1.inst          54237                       # Instruction read bandwidth from this memory (bytes/s)
56system.physmem.bw_inst_read::total             452969                       # Instruction read bandwidth from this memory (bytes/s)
57system.physmem.bw_write::writebacks           2993568                       # Write bandwidth from this memory (bytes/s)
58system.physmem.bw_write::cpu0.data               6316                       # Write bandwidth from this memory (bytes/s)
59system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
60system.physmem.bw_write::total                2999899                       # Write bandwidth from this memory (bytes/s)
61system.physmem.bw_total::writebacks           2993568                       # Total bandwidth to/from this memory (bytes/s)
62system.physmem.bw_total::cpu0.dtb.walker          160                       # Total bandwidth to/from this memory (bytes/s)
63system.physmem.bw_total::cpu0.itb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
64system.physmem.bw_total::cpu0.inst             398732                       # Total bandwidth to/from this memory (bytes/s)
65system.physmem.bw_total::cpu0.data            3374604                       # Total bandwidth to/from this memory (bytes/s)
66system.physmem.bw_total::cpu1.dtb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
67system.physmem.bw_total::cpu1.inst              54237                       # Total bandwidth to/from this memory (bytes/s)
68system.physmem.bw_total::cpu1.data             385890                       # Total bandwidth to/from this memory (bytes/s)
69system.physmem.bw_total::realview.ide             343                       # Total bandwidth to/from this memory (bytes/s)
70system.physmem.bw_total::total                7207624                       # Total bandwidth to/from this memory (bytes/s)
71system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
72system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
73system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
74system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
75system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
76system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
77system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
78system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
79system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
80system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
81system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
82system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
83system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
84system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
85system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
86system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
87system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
88system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
89system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
90system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
91system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
92system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
93system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
94system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
95system.cpu_clk_domain.clock                       500                       # Clock period in ticks
96system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
97system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
98system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
99system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
100system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
101system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
102system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
103system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
104system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
105system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
106system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
107system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
108system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
109system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
110system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
111system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
112system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
113system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
114system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
115system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
116system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
117system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
118system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
119system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
120system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
121system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
122system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
123system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
124system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
125system.cpu0.dtb.walker.walks                     7967                       # Table walker walks requested
126system.cpu0.dtb.walker.walksShort                7967                       # Table walker walks initiated with short descriptors
127system.cpu0.dtb.walker.walkWaitTime::samples         7967                       # Table walker wait (enqueue to first request) latency
128system.cpu0.dtb.walker.walkWaitTime::0           7967    100.00%    100.00% # Table walker wait (enqueue to first request) latency
129system.cpu0.dtb.walker.walkWaitTime::total         7967                       # Table walker wait (enqueue to first request) latency
130system.cpu0.dtb.walker.walksPending::samples      6705500                       # Table walker pending requests distribution
131system.cpu0.dtb.walker.walksPending::0        6705500    100.00%    100.00% # Table walker pending requests distribution
132system.cpu0.dtb.walker.walksPending::total      6705500                       # Table walker pending requests distribution
133system.cpu0.dtb.walker.walkPageSizes::4K         5082     77.32%     77.32% # Table walker page sizes translated
134system.cpu0.dtb.walker.walkPageSizes::1M         1491     22.68%    100.00% # Table walker page sizes translated
135system.cpu0.dtb.walker.walkPageSizes::total         6573                       # Table walker page sizes translated
136system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7967                       # Table walker requests started/completed, data/inst
137system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
138system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7967                       # Table walker requests started/completed, data/inst
139system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6573                       # Table walker requests started/completed, data/inst
140system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
141system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6573                       # Table walker requests started/completed, data/inst
142system.cpu0.dtb.walker.walkRequestOrigin::total        14540                       # Table walker requests started/completed, data/inst
143system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
144system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
145system.cpu0.dtb.read_hits                    20339720                       # DTB read hits
146system.cpu0.dtb.read_misses                      6874                       # DTB read misses
147system.cpu0.dtb.write_hits                   16391078                       # DTB write hits
148system.cpu0.dtb.write_misses                     1093                       # DTB write misses
149system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
150system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
151system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
152system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
153system.cpu0.dtb.flush_entries                    3499                       # Number of entries that have been flushed from TLB
154system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
155system.cpu0.dtb.prefetch_faults                  1788                       # Number of TLB faults due to prefetch
156system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
157system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
158system.cpu0.dtb.read_accesses                20346594                       # DTB read accesses
159system.cpu0.dtb.write_accesses               16392171                       # DTB write accesses
160system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
161system.cpu0.dtb.hits                         36730798                       # DTB hits
162system.cpu0.dtb.misses                           7967                       # DTB misses
163system.cpu0.dtb.accesses                     36738765                       # DTB accesses
164system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
165system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
166system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
167system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
168system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
169system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
170system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
171system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
172system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
173system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
174system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
175system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
176system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
177system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
178system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
179system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
180system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
181system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
182system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
183system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
184system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
185system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
186system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
187system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
188system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
189system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
190system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
191system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
192system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
193system.cpu0.itb.walker.walks                     3358                       # Table walker walks requested
194system.cpu0.itb.walker.walksShort                3358                       # Table walker walks initiated with short descriptors
195system.cpu0.itb.walker.walkWaitTime::samples         3358                       # Table walker wait (enqueue to first request) latency
196system.cpu0.itb.walker.walkWaitTime::0           3358    100.00%    100.00% # Table walker wait (enqueue to first request) latency
197system.cpu0.itb.walker.walkWaitTime::total         3358                       # Table walker wait (enqueue to first request) latency
198system.cpu0.itb.walker.walksPending::samples      6702500                       # Table walker pending requests distribution
199system.cpu0.itb.walker.walksPending::0        6702500    100.00%    100.00% # Table walker pending requests distribution
200system.cpu0.itb.walker.walksPending::total      6702500                       # Table walker pending requests distribution
201system.cpu0.itb.walker.walkPageSizes::4K         2040     87.11%     87.11% # Table walker page sizes translated
202system.cpu0.itb.walker.walkPageSizes::1M          302     12.89%    100.00% # Table walker page sizes translated
203system.cpu0.itb.walker.walkPageSizes::total         2342                       # Table walker page sizes translated
204system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
205system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3358                       # Table walker requests started/completed, data/inst
206system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3358                       # Table walker requests started/completed, data/inst
207system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
208system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2342                       # Table walker requests started/completed, data/inst
209system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2342                       # Table walker requests started/completed, data/inst
210system.cpu0.itb.walker.walkRequestOrigin::total         5700                       # Table walker requests started/completed, data/inst
211system.cpu0.itb.inst_hits                    97439331                       # ITB inst hits
212system.cpu0.itb.inst_misses                      3358                       # ITB inst misses
213system.cpu0.itb.read_hits                           0                       # DTB read hits
214system.cpu0.itb.read_misses                         0                       # DTB read misses
215system.cpu0.itb.write_hits                          0                       # DTB write hits
216system.cpu0.itb.write_misses                        0                       # DTB write misses
217system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
218system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
219system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
220system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
221system.cpu0.itb.flush_entries                    2160                       # Number of entries that have been flushed from TLB
222system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
223system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
224system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
225system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
226system.cpu0.itb.read_accesses                       0                       # DTB read accesses
227system.cpu0.itb.write_accesses                      0                       # DTB write accesses
228system.cpu0.itb.inst_accesses                97442689                       # ITB inst accesses
229system.cpu0.itb.hits                         97439331                       # DTB hits
230system.cpu0.itb.misses                           3358                       # DTB misses
231system.cpu0.itb.accesses                     97442689                       # DTB accesses
232system.cpu0.numCycles                      5605791368                       # number of cpu cycles simulated
233system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
234system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
235system.cpu0.committedInsts                   95426926                       # Number of instructions committed
236system.cpu0.committedOps                    115560427                       # Number of ops (including micro ops) committed
237system.cpu0.num_int_alu_accesses            100762696                       # Number of integer alu accesses
238system.cpu0.num_fp_alu_accesses                  9755                       # Number of float alu accesses
239system.cpu0.num_func_calls                    8000180                       # number of times a function call or return occured
240system.cpu0.num_conditional_control_insts     13204202                       # number of instructions that are conditional controls
241system.cpu0.num_int_insts                   100762696                       # number of integer instructions
242system.cpu0.num_fp_insts                         9755                       # number of float instructions
243system.cpu0.num_int_register_reads          182457229                       # number of times the integer registers were read
244system.cpu0.num_int_register_writes          69135541                       # number of times the integer registers were written
245system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
246system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
247system.cpu0.num_cc_register_reads           349971383                       # number of times the CC registers were read
248system.cpu0.num_cc_register_writes           44907438                       # number of times the CC registers were written
249system.cpu0.num_mem_refs                     37873810                       # number of memory refs
250system.cpu0.num_load_insts                   20597310                       # Number of load instructions
251system.cpu0.num_store_insts                  17276500                       # Number of store instructions
252system.cpu0.num_idle_cycles              5488206876.247207                       # Number of idle cycles
253system.cpu0.num_busy_cycles              117584491.752793                       # Number of busy cycles
254system.cpu0.not_idle_fraction                0.020976                       # Percentage of non-idle cycles
255system.cpu0.idle_fraction                    0.979024                       # Percentage of idle cycles
256system.cpu0.Branches                         21941499                       # Number of branches fetched
257system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
258system.cpu0.op_class::IntAlu                 78887256     67.49%     67.49% # Class of executed instruction
259system.cpu0.op_class::IntMult                  110639      0.09%     67.59% # Class of executed instruction
260system.cpu0.op_class::IntDiv                        0      0.00%     67.59% # Class of executed instruction
261system.cpu0.op_class::FloatAdd                      0      0.00%     67.59% # Class of executed instruction
262system.cpu0.op_class::FloatCmp                      0      0.00%     67.59% # Class of executed instruction
263system.cpu0.op_class::FloatCvt                      0      0.00%     67.59% # Class of executed instruction
264system.cpu0.op_class::FloatMult                     0      0.00%     67.59% # Class of executed instruction
265system.cpu0.op_class::FloatDiv                      0      0.00%     67.59% # Class of executed instruction
266system.cpu0.op_class::FloatSqrt                     0      0.00%     67.59% # Class of executed instruction
267system.cpu0.op_class::SimdAdd                       0      0.00%     67.59% # Class of executed instruction
268system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.59% # Class of executed instruction
269system.cpu0.op_class::SimdAlu                       0      0.00%     67.59% # Class of executed instruction
270system.cpu0.op_class::SimdCmp                       0      0.00%     67.59% # Class of executed instruction
271system.cpu0.op_class::SimdCvt                       0      0.00%     67.59% # Class of executed instruction
272system.cpu0.op_class::SimdMisc                      0      0.00%     67.59% # Class of executed instruction
273system.cpu0.op_class::SimdMult                      0      0.00%     67.59% # Class of executed instruction
274system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.59% # Class of executed instruction
275system.cpu0.op_class::SimdShift                     0      0.00%     67.59% # Class of executed instruction
276system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.59% # Class of executed instruction
277system.cpu0.op_class::SimdSqrt                      0      0.00%     67.59% # Class of executed instruction
278system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.59% # Class of executed instruction
279system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.59% # Class of executed instruction
280system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.59% # Class of executed instruction
281system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.59% # Class of executed instruction
282system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.59% # Class of executed instruction
283system.cpu0.op_class::SimdFloatMisc              8087      0.01%     67.60% # Class of executed instruction
284system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.60% # Class of executed instruction
285system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.60% # Class of executed instruction
286system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.60% # Class of executed instruction
287system.cpu0.op_class::MemRead                20597310     17.62%     85.22% # Class of executed instruction
288system.cpu0.op_class::MemWrite               17276500     14.78%    100.00% # Class of executed instruction
289system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
290system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
291system.cpu0.op_class::total                 116882065                       # Class of executed instruction
292system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
293system.cpu0.kern.inst.quiesce                    1968                       # number of quiesce instructions executed
294system.cpu0.dcache.tags.replacements           693477                       # number of replacements
295system.cpu0.dcache.tags.tagsinuse          494.853657                       # Cycle average of tags in use
296system.cpu0.dcache.tags.total_refs           35932369                       # Total number of references to valid blocks.
297system.cpu0.dcache.tags.sampled_refs           693989                       # Sample count of references to valid blocks.
298system.cpu0.dcache.tags.avg_refs            51.776569                       # Average number of references to valid blocks.
299system.cpu0.dcache.tags.warmup_cycle         23661500                       # Cycle when the warmup percentage was hit.
300system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.853657                       # Average occupied blocks per requestor
301system.cpu0.dcache.tags.occ_percent::cpu0.data     0.966511                       # Average percentage of cache occupancy
302system.cpu0.dcache.tags.occ_percent::total     0.966511                       # Average percentage of cache occupancy
303system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
304system.cpu0.dcache.tags.age_task_id_blocks_1024::0          277                       # Occupied blocks per task id
305system.cpu0.dcache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
306system.cpu0.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
307system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
308system.cpu0.dcache.tags.tag_accesses         74113775                       # Number of tag accesses
309system.cpu0.dcache.tags.data_accesses        74113775                       # Number of data accesses
310system.cpu0.dcache.ReadReq_hits::cpu0.data     19108539                       # number of ReadReq hits
311system.cpu0.dcache.ReadReq_hits::total       19108539                       # number of ReadReq hits
312system.cpu0.dcache.WriteReq_hits::cpu0.data     15690376                       # number of WriteReq hits
313system.cpu0.dcache.WriteReq_hits::total      15690376                       # number of WriteReq hits
314system.cpu0.dcache.SoftPFReq_hits::cpu0.data       346093                       # number of SoftPFReq hits
315system.cpu0.dcache.SoftPFReq_hits::total       346093                       # number of SoftPFReq hits
316system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       379629                       # number of LoadLockedReq hits
317system.cpu0.dcache.LoadLockedReq_hits::total       379629                       # number of LoadLockedReq hits
318system.cpu0.dcache.StoreCondReq_hits::cpu0.data       363049                       # number of StoreCondReq hits
319system.cpu0.dcache.StoreCondReq_hits::total       363049                       # number of StoreCondReq hits
320system.cpu0.dcache.demand_hits::cpu0.data     34798915                       # number of demand (read+write) hits
321system.cpu0.dcache.demand_hits::total        34798915                       # number of demand (read+write) hits
322system.cpu0.dcache.overall_hits::cpu0.data     35145008                       # number of overall hits
323system.cpu0.dcache.overall_hits::total       35145008                       # number of overall hits
324system.cpu0.dcache.ReadReq_misses::cpu0.data       373099                       # number of ReadReq misses
325system.cpu0.dcache.ReadReq_misses::total       373099                       # number of ReadReq misses
326system.cpu0.dcache.WriteReq_misses::cpu0.data       295764                       # number of WriteReq misses
327system.cpu0.dcache.WriteReq_misses::total       295764                       # number of WriteReq misses
328system.cpu0.dcache.SoftPFReq_misses::cpu0.data       100321                       # number of SoftPFReq misses
329system.cpu0.dcache.SoftPFReq_misses::total       100321                       # number of SoftPFReq misses
330system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6742                       # number of LoadLockedReq misses
331system.cpu0.dcache.LoadLockedReq_misses::total         6742                       # number of LoadLockedReq misses
332system.cpu0.dcache.StoreCondReq_misses::cpu0.data        18436                       # number of StoreCondReq misses
333system.cpu0.dcache.StoreCondReq_misses::total        18436                       # number of StoreCondReq misses
334system.cpu0.dcache.demand_misses::cpu0.data       668863                       # number of demand (read+write) misses
335system.cpu0.dcache.demand_misses::total        668863                       # number of demand (read+write) misses
336system.cpu0.dcache.overall_misses::cpu0.data       769184                       # number of overall misses
337system.cpu0.dcache.overall_misses::total       769184                       # number of overall misses
338system.cpu0.dcache.ReadReq_accesses::cpu0.data     19481638                       # number of ReadReq accesses(hits+misses)
339system.cpu0.dcache.ReadReq_accesses::total     19481638                       # number of ReadReq accesses(hits+misses)
340system.cpu0.dcache.WriteReq_accesses::cpu0.data     15986140                       # number of WriteReq accesses(hits+misses)
341system.cpu0.dcache.WriteReq_accesses::total     15986140                       # number of WriteReq accesses(hits+misses)
342system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446414                       # number of SoftPFReq accesses(hits+misses)
343system.cpu0.dcache.SoftPFReq_accesses::total       446414                       # number of SoftPFReq accesses(hits+misses)
344system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386371                       # number of LoadLockedReq accesses(hits+misses)
345system.cpu0.dcache.LoadLockedReq_accesses::total       386371                       # number of LoadLockedReq accesses(hits+misses)
346system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381485                       # number of StoreCondReq accesses(hits+misses)
347system.cpu0.dcache.StoreCondReq_accesses::total       381485                       # number of StoreCondReq accesses(hits+misses)
348system.cpu0.dcache.demand_accesses::cpu0.data     35467778                       # number of demand (read+write) accesses
349system.cpu0.dcache.demand_accesses::total     35467778                       # number of demand (read+write) accesses
350system.cpu0.dcache.overall_accesses::cpu0.data     35914192                       # number of overall (read+write) accesses
351system.cpu0.dcache.overall_accesses::total     35914192                       # number of overall (read+write) accesses
352system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.019151                       # miss rate for ReadReq accesses
353system.cpu0.dcache.ReadReq_miss_rate::total     0.019151                       # miss rate for ReadReq accesses
354system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018501                       # miss rate for WriteReq accesses
355system.cpu0.dcache.WriteReq_miss_rate::total     0.018501                       # miss rate for WriteReq accesses
356system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.224726                       # miss rate for SoftPFReq accesses
357system.cpu0.dcache.SoftPFReq_miss_rate::total     0.224726                       # miss rate for SoftPFReq accesses
358system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.017450                       # miss rate for LoadLockedReq accesses
359system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.017450                       # miss rate for LoadLockedReq accesses
360system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.048327                       # miss rate for StoreCondReq accesses
361system.cpu0.dcache.StoreCondReq_miss_rate::total     0.048327                       # miss rate for StoreCondReq accesses
362system.cpu0.dcache.demand_miss_rate::cpu0.data     0.018858                       # miss rate for demand accesses
363system.cpu0.dcache.demand_miss_rate::total     0.018858                       # miss rate for demand accesses
364system.cpu0.dcache.overall_miss_rate::cpu0.data     0.021417                       # miss rate for overall accesses
365system.cpu0.dcache.overall_miss_rate::total     0.021417                       # miss rate for overall accesses
366system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
367system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
368system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
369system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
370system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
371system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
372system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
373system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
374system.cpu0.dcache.writebacks::writebacks       511896                       # number of writebacks
375system.cpu0.dcache.writebacks::total           511896                       # number of writebacks
376system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
377system.cpu0.icache.tags.replacements          1109735                       # number of replacements
378system.cpu0.icache.tags.tagsinuse          511.809992                       # Cycle average of tags in use
379system.cpu0.icache.tags.total_refs           96331417                       # Total number of references to valid blocks.
380system.cpu0.icache.tags.sampled_refs          1110247                       # Sample count of references to valid blocks.
381system.cpu0.icache.tags.avg_refs            86.765753                       # Average number of references to valid blocks.
382system.cpu0.icache.tags.warmup_cycle       6345717000                       # Cycle when the warmup percentage was hit.
383system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.809992                       # Average occupied blocks per requestor
384system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999629                       # Average percentage of cache occupancy
385system.cpu0.icache.tags.occ_percent::total     0.999629                       # Average percentage of cache occupancy
386system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
387system.cpu0.icache.tags.age_task_id_blocks_1024::0          212                       # Occupied blocks per task id
388system.cpu0.icache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
389system.cpu0.icache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
390system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
391system.cpu0.icache.tags.tag_accesses        195993602                       # Number of tag accesses
392system.cpu0.icache.tags.data_accesses       195993602                       # Number of data accesses
393system.cpu0.icache.ReadReq_hits::cpu0.inst     96331417                       # number of ReadReq hits
394system.cpu0.icache.ReadReq_hits::total       96331417                       # number of ReadReq hits
395system.cpu0.icache.demand_hits::cpu0.inst     96331417                       # number of demand (read+write) hits
396system.cpu0.icache.demand_hits::total        96331417                       # number of demand (read+write) hits
397system.cpu0.icache.overall_hits::cpu0.inst     96331417                       # number of overall hits
398system.cpu0.icache.overall_hits::total       96331417                       # number of overall hits
399system.cpu0.icache.ReadReq_misses::cpu0.inst      1110256                       # number of ReadReq misses
400system.cpu0.icache.ReadReq_misses::total      1110256                       # number of ReadReq misses
401system.cpu0.icache.demand_misses::cpu0.inst      1110256                       # number of demand (read+write) misses
402system.cpu0.icache.demand_misses::total       1110256                       # number of demand (read+write) misses
403system.cpu0.icache.overall_misses::cpu0.inst      1110256                       # number of overall misses
404system.cpu0.icache.overall_misses::total      1110256                       # number of overall misses
405system.cpu0.icache.ReadReq_accesses::cpu0.inst     97441673                       # number of ReadReq accesses(hits+misses)
406system.cpu0.icache.ReadReq_accesses::total     97441673                       # number of ReadReq accesses(hits+misses)
407system.cpu0.icache.demand_accesses::cpu0.inst     97441673                       # number of demand (read+write) accesses
408system.cpu0.icache.demand_accesses::total     97441673                       # number of demand (read+write) accesses
409system.cpu0.icache.overall_accesses::cpu0.inst     97441673                       # number of overall (read+write) accesses
410system.cpu0.icache.overall_accesses::total     97441673                       # number of overall (read+write) accesses
411system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011394                       # miss rate for ReadReq accesses
412system.cpu0.icache.ReadReq_miss_rate::total     0.011394                       # miss rate for ReadReq accesses
413system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011394                       # miss rate for demand accesses
414system.cpu0.icache.demand_miss_rate::total     0.011394                       # miss rate for demand accesses
415system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011394                       # miss rate for overall accesses
416system.cpu0.icache.overall_miss_rate::total     0.011394                       # miss rate for overall accesses
417system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
418system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
419system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
420system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
421system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
422system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
423system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
424system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
425system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
426system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
427system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
428system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
429system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
430system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
431system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
432system.cpu0.l2cache.tags.replacements          252330                       # number of replacements
433system.cpu0.l2cache.tags.tagsinuse       16129.294754                       # Cycle average of tags in use
434system.cpu0.l2cache.tags.total_refs           1810154                       # Total number of references to valid blocks.
435system.cpu0.l2cache.tags.sampled_refs          268529                       # Sample count of references to valid blocks.
436system.cpu0.l2cache.tags.avg_refs            6.741000                       # Average number of references to valid blocks.
437system.cpu0.l2cache.tags.warmup_cycle      1814550500                       # Cycle when the warmup percentage was hit.
438system.cpu0.l2cache.tags.occ_blocks::writebacks  8067.926153                       # Average occupied blocks per requestor
439system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     3.192846                       # Average occupied blocks per requestor
440system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.094111                       # Average occupied blocks per requestor
441system.cpu0.l2cache.tags.occ_blocks::cpu0.inst  4748.670375                       # Average occupied blocks per requestor
442system.cpu0.l2cache.tags.occ_blocks::cpu0.data  3309.411269                       # Average occupied blocks per requestor
443system.cpu0.l2cache.tags.occ_percent::writebacks     0.492427                       # Average percentage of cache occupancy
444system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000195                       # Average percentage of cache occupancy
445system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000006                       # Average percentage of cache occupancy
446system.cpu0.l2cache.tags.occ_percent::cpu0.inst     0.289836                       # Average percentage of cache occupancy
447system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.201990                       # Average percentage of cache occupancy
448system.cpu0.l2cache.tags.occ_percent::total     0.984454                       # Average percentage of cache occupancy
449system.cpu0.l2cache.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
450system.cpu0.l2cache.tags.occ_task_id_blocks::1024        16192                       # Occupied blocks per task id
451system.cpu0.l2cache.tags.age_task_id_blocks_1023::2            1                       # Occupied blocks per task id
452system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            4                       # Occupied blocks per task id
453system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
454system.cpu0.l2cache.tags.age_task_id_blocks_1024::0           82                       # Occupied blocks per task id
455system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          282                       # Occupied blocks per task id
456system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5555                       # Occupied blocks per task id
457system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7641                       # Occupied blocks per task id
458system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2632                       # Occupied blocks per task id
459system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000427                       # Percentage of cache occupancy per task id
460system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.988281                       # Percentage of cache occupancy per task id
461system.cpu0.l2cache.tags.tag_accesses        39452382                       # Number of tag accesses
462system.cpu0.l2cache.tags.data_accesses       39452382                       # Number of data accesses
463system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker         7540                       # number of ReadReq hits
464system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         3225                       # number of ReadReq hits
465system.cpu0.l2cache.ReadReq_hits::cpu0.inst      1065497                       # number of ReadReq hits
466system.cpu0.l2cache.ReadReq_hits::cpu0.data       351995                       # number of ReadReq hits
467system.cpu0.l2cache.ReadReq_hits::total       1428257                       # number of ReadReq hits
468system.cpu0.l2cache.Writeback_hits::writebacks       511896                       # number of Writeback hits
469system.cpu0.l2cache.Writeback_hits::total       511896                       # number of Writeback hits
470system.cpu0.l2cache.UpgradeReq_hits::cpu0.data           17                       # number of UpgradeReq hits
471system.cpu0.l2cache.UpgradeReq_hits::total           17                       # number of UpgradeReq hits
472system.cpu0.l2cache.ReadExReq_hits::cpu0.data        94089                       # number of ReadExReq hits
473system.cpu0.l2cache.ReadExReq_hits::total        94089                       # number of ReadExReq hits
474system.cpu0.l2cache.demand_hits::cpu0.dtb.walker         7540                       # number of demand (read+write) hits
475system.cpu0.l2cache.demand_hits::cpu0.itb.walker         3225                       # number of demand (read+write) hits
476system.cpu0.l2cache.demand_hits::cpu0.inst      1065497                       # number of demand (read+write) hits
477system.cpu0.l2cache.demand_hits::cpu0.data       446084                       # number of demand (read+write) hits
478system.cpu0.l2cache.demand_hits::total        1522346                       # number of demand (read+write) hits
479system.cpu0.l2cache.overall_hits::cpu0.dtb.walker         7540                       # number of overall hits
480system.cpu0.l2cache.overall_hits::cpu0.itb.walker         3225                       # number of overall hits
481system.cpu0.l2cache.overall_hits::cpu0.inst      1065497                       # number of overall hits
482system.cpu0.l2cache.overall_hits::cpu0.data       446084                       # number of overall hits
483system.cpu0.l2cache.overall_hits::total       1522346                       # number of overall hits
484system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          210                       # number of ReadReq misses
485system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          124                       # number of ReadReq misses
486system.cpu0.l2cache.ReadReq_misses::cpu0.inst        44759                       # number of ReadReq misses
487system.cpu0.l2cache.ReadReq_misses::cpu0.data       128167                       # number of ReadReq misses
488system.cpu0.l2cache.ReadReq_misses::total       173260                       # number of ReadReq misses
489system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26230                       # number of UpgradeReq misses
490system.cpu0.l2cache.UpgradeReq_misses::total        26230                       # number of UpgradeReq misses
491system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18436                       # number of SCUpgradeReq misses
492system.cpu0.l2cache.SCUpgradeReq_misses::total        18436                       # number of SCUpgradeReq misses
493system.cpu0.l2cache.ReadExReq_misses::cpu0.data       175428                       # number of ReadExReq misses
494system.cpu0.l2cache.ReadExReq_misses::total       175428                       # number of ReadExReq misses
495system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          210                       # number of demand (read+write) misses
496system.cpu0.l2cache.demand_misses::cpu0.itb.walker          124                       # number of demand (read+write) misses
497system.cpu0.l2cache.demand_misses::cpu0.inst        44759                       # number of demand (read+write) misses
498system.cpu0.l2cache.demand_misses::cpu0.data       303595                       # number of demand (read+write) misses
499system.cpu0.l2cache.demand_misses::total       348688                       # number of demand (read+write) misses
500system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          210                       # number of overall misses
501system.cpu0.l2cache.overall_misses::cpu0.itb.walker          124                       # number of overall misses
502system.cpu0.l2cache.overall_misses::cpu0.inst        44759                       # number of overall misses
503system.cpu0.l2cache.overall_misses::cpu0.data       303595                       # number of overall misses
504system.cpu0.l2cache.overall_misses::total       348688                       # number of overall misses
505system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker         7750                       # number of ReadReq accesses(hits+misses)
506system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         3349                       # number of ReadReq accesses(hits+misses)
507system.cpu0.l2cache.ReadReq_accesses::cpu0.inst      1110256                       # number of ReadReq accesses(hits+misses)
508system.cpu0.l2cache.ReadReq_accesses::cpu0.data       480162                       # number of ReadReq accesses(hits+misses)
509system.cpu0.l2cache.ReadReq_accesses::total      1601517                       # number of ReadReq accesses(hits+misses)
510system.cpu0.l2cache.Writeback_accesses::writebacks       511896                       # number of Writeback accesses(hits+misses)
511system.cpu0.l2cache.Writeback_accesses::total       511896                       # number of Writeback accesses(hits+misses)
512system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        26247                       # number of UpgradeReq accesses(hits+misses)
513system.cpu0.l2cache.UpgradeReq_accesses::total        26247                       # number of UpgradeReq accesses(hits+misses)
514system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        18436                       # number of SCUpgradeReq accesses(hits+misses)
515system.cpu0.l2cache.SCUpgradeReq_accesses::total        18436                       # number of SCUpgradeReq accesses(hits+misses)
516system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269517                       # number of ReadExReq accesses(hits+misses)
517system.cpu0.l2cache.ReadExReq_accesses::total       269517                       # number of ReadExReq accesses(hits+misses)
518system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker         7750                       # number of demand (read+write) accesses
519system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         3349                       # number of demand (read+write) accesses
520system.cpu0.l2cache.demand_accesses::cpu0.inst      1110256                       # number of demand (read+write) accesses
521system.cpu0.l2cache.demand_accesses::cpu0.data       749679                       # number of demand (read+write) accesses
522system.cpu0.l2cache.demand_accesses::total      1871034                       # number of demand (read+write) accesses
523system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker         7750                       # number of overall (read+write) accesses
524system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         3349                       # number of overall (read+write) accesses
525system.cpu0.l2cache.overall_accesses::cpu0.inst      1110256                       # number of overall (read+write) accesses
526system.cpu0.l2cache.overall_accesses::cpu0.data       749679                       # number of overall (read+write) accesses
527system.cpu0.l2cache.overall_accesses::total      1871034                       # number of overall (read+write) accesses
528system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.027097                       # miss rate for ReadReq accesses
529system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.037026                       # miss rate for ReadReq accesses
530system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst     0.040314                       # miss rate for ReadReq accesses
531system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data     0.266924                       # miss rate for ReadReq accesses
532system.cpu0.l2cache.ReadReq_miss_rate::total     0.108185                       # miss rate for ReadReq accesses
533system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999352                       # miss rate for UpgradeReq accesses
534system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999352                       # miss rate for UpgradeReq accesses
535system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
536system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
537system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.650898                       # miss rate for ReadExReq accesses
538system.cpu0.l2cache.ReadExReq_miss_rate::total     0.650898                       # miss rate for ReadExReq accesses
539system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.027097                       # miss rate for demand accesses
540system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.037026                       # miss rate for demand accesses
541system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.040314                       # miss rate for demand accesses
542system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.404967                       # miss rate for demand accesses
543system.cpu0.l2cache.demand_miss_rate::total     0.186361                       # miss rate for demand accesses
544system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.027097                       # miss rate for overall accesses
545system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.037026                       # miss rate for overall accesses
546system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.040314                       # miss rate for overall accesses
547system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.404967                       # miss rate for overall accesses
548system.cpu0.l2cache.overall_miss_rate::total     0.186361                       # miss rate for overall accesses
549system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
550system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
551system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
552system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
553system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
554system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
555system.cpu0.l2cache.fast_writes                     0                       # number of fast writes performed
556system.cpu0.l2cache.cache_copies                    0                       # number of cache copies performed
557system.cpu0.l2cache.writebacks::writebacks       192974                       # number of writebacks
558system.cpu0.l2cache.writebacks::total          192974                       # number of writebacks
559system.cpu0.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
560system.cpu0.toL2Bus.trans_dist::ReadReq       1651840                       # Transaction distribution
561system.cpu0.toL2Bus.trans_dist::ReadResp      1651840                       # Transaction distribution
562system.cpu0.toL2Bus.trans_dist::WriteReq        28386                       # Transaction distribution
563system.cpu0.toL2Bus.trans_dist::WriteResp        28386                       # Transaction distribution
564system.cpu0.toL2Bus.trans_dist::Writeback       511896                       # Transaction distribution
565system.cpu0.toL2Bus.trans_dist::UpgradeReq        26247                       # Transaction distribution
566system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        18436                       # Transaction distribution
567system.cpu0.toL2Bus.trans_dist::UpgradeResp        44683                       # Transaction distribution
568system.cpu0.toL2Bus.trans_dist::ReadExReq       269517                       # Transaction distribution
569system.cpu0.toL2Bus.trans_dist::ReadExResp       269517                       # Transaction distribution
570system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      2238556                       # Packet count per connected master and slave (bytes)
571system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2220556                       # Packet count per connected master and slave (bytes)
572system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12828                       # Packet count per connected master and slave (bytes)
573system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        28808                       # Packet count per connected master and slave (bytes)
574system.cpu0.toL2Bus.pkt_count::total          4500748                       # Packet count per connected master and slave (bytes)
575system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     71092472                       # Cumulative packet size per connected master and slave (bytes)
576system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     80931536                       # Cumulative packet size per connected master and slave (bytes)
577system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        25656                       # Cumulative packet size per connected master and slave (bytes)
578system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        57616                       # Cumulative packet size per connected master and slave (bytes)
579system.cpu0.toL2Bus.pkt_size::total         152107280                       # Cumulative packet size per connected master and slave (bytes)
580system.cpu0.toL2Bus.snoops                     322019                       # Total snoops (count)
581system.cpu0.toL2Bus.snoop_fanout::samples      2656743                       # Request fanout histogram
582system.cpu0.toL2Bus.snoop_fanout::mean       3.082586                       # Request fanout histogram
583system.cpu0.toL2Bus.snoop_fanout::stdev      0.275256                       # Request fanout histogram
584system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
585system.cpu0.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
586system.cpu0.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
587system.cpu0.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
588system.cpu0.toL2Bus.snoop_fanout::3           2437332     91.74%     91.74% # Request fanout histogram
589system.cpu0.toL2Bus.snoop_fanout::4            219411      8.26%    100.00% # Request fanout histogram
590system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
591system.cpu0.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
592system.cpu0.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
593system.cpu0.toL2Bus.snoop_fanout::total       2656743                       # Request fanout histogram
594system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
595system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
596system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
597system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
598system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
599system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
600system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
601system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
602system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
603system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
604system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
605system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
606system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
607system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
608system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
609system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
610system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
611system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
612system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
613system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
614system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
615system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
616system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
617system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
618system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
619system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
620system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
621system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
622system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
623system.cpu1.dtb.walker.walks                     3358                       # Table walker walks requested
624system.cpu1.dtb.walker.walksShort                3358                       # Table walker walks initiated with short descriptors
625system.cpu1.dtb.walker.walkWaitTime::samples         3358                       # Table walker wait (enqueue to first request) latency
626system.cpu1.dtb.walker.walkWaitTime::0           3358    100.00%    100.00% # Table walker wait (enqueue to first request) latency
627system.cpu1.dtb.walker.walkWaitTime::total         3358                       # Table walker wait (enqueue to first request) latency
628system.cpu1.dtb.walker.walksPending::samples  -1804206736                       # Table walker pending requests distribution
629system.cpu1.dtb.walker.walksPending::0    -1804206736    100.00%    100.00% # Table walker pending requests distribution
630system.cpu1.dtb.walker.walksPending::total  -1804206736                       # Table walker pending requests distribution
631system.cpu1.dtb.walker.walkPageSizes::4K         1919     74.15%     74.15% # Table walker page sizes translated
632system.cpu1.dtb.walker.walkPageSizes::1M          669     25.85%    100.00% # Table walker page sizes translated
633system.cpu1.dtb.walker.walkPageSizes::total         2588                       # Table walker page sizes translated
634system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3358                       # Table walker requests started/completed, data/inst
635system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
636system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3358                       # Table walker requests started/completed, data/inst
637system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2588                       # Table walker requests started/completed, data/inst
638system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
639system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2588                       # Table walker requests started/completed, data/inst
640system.cpu1.dtb.walker.walkRequestOrigin::total         5946                       # Table walker requests started/completed, data/inst
641system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
642system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
643system.cpu1.dtb.read_hits                    12173916                       # DTB read hits
644system.cpu1.dtb.read_misses                      2852                       # DTB read misses
645system.cpu1.dtb.write_hits                    7587209                       # DTB write hits
646system.cpu1.dtb.write_misses                      506                       # DTB write misses
647system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
648system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
649system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
650system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
651system.cpu1.dtb.flush_entries                    2013                       # Number of entries that have been flushed from TLB
652system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
653system.cpu1.dtb.prefetch_faults                   290                       # Number of TLB faults due to prefetch
654system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
655system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
656system.cpu1.dtb.read_accesses                12176768                       # DTB read accesses
657system.cpu1.dtb.write_accesses                7587715                       # DTB write accesses
658system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
659system.cpu1.dtb.hits                         19761125                       # DTB hits
660system.cpu1.dtb.misses                           3358                       # DTB misses
661system.cpu1.dtb.accesses                     19764483                       # DTB accesses
662system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
663system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
664system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
665system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
666system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
667system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
668system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
669system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
670system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
671system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
672system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
673system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
674system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
675system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
676system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
677system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
678system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
679system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
680system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
681system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
682system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
683system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
684system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
685system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
686system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
687system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
688system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
689system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
690system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
691system.cpu1.itb.walker.walks                     1734                       # Table walker walks requested
692system.cpu1.itb.walker.walksShort                1734                       # Table walker walks initiated with short descriptors
693system.cpu1.itb.walker.walkWaitTime::samples         1734                       # Table walker wait (enqueue to first request) latency
694system.cpu1.itb.walker.walkWaitTime::0           1734    100.00%    100.00% # Table walker wait (enqueue to first request) latency
695system.cpu1.itb.walker.walkWaitTime::total         1734                       # Table walker wait (enqueue to first request) latency
696system.cpu1.itb.walker.walksPending::samples  -1804209236                       # Table walker pending requests distribution
697system.cpu1.itb.walker.walksPending::0    -1804209236    100.00%    100.00% # Table walker pending requests distribution
698system.cpu1.itb.walker.walksPending::total  -1804209236                       # Table walker pending requests distribution
699system.cpu1.itb.walker.walkPageSizes::4K          935     85.39%     85.39% # Table walker page sizes translated
700system.cpu1.itb.walker.walkPageSizes::1M          160     14.61%    100.00% # Table walker page sizes translated
701system.cpu1.itb.walker.walkPageSizes::total         1095                       # Table walker page sizes translated
702system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
703system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1734                       # Table walker requests started/completed, data/inst
704system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1734                       # Table walker requests started/completed, data/inst
705system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
706system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1095                       # Table walker requests started/completed, data/inst
707system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1095                       # Table walker requests started/completed, data/inst
708system.cpu1.itb.walker.walkRequestOrigin::total         2829                       # Table walker requests started/completed, data/inst
709system.cpu1.itb.inst_hits                    53671575                       # ITB inst hits
710system.cpu1.itb.inst_misses                      1734                       # ITB inst misses
711system.cpu1.itb.read_hits                           0                       # DTB read hits
712system.cpu1.itb.read_misses                         0                       # DTB read misses
713system.cpu1.itb.write_hits                          0                       # DTB write hits
714system.cpu1.itb.write_misses                        0                       # DTB write misses
715system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
716system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
717system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
718system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
719system.cpu1.itb.flush_entries                    1136                       # Number of entries that have been flushed from TLB
720system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
721system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
722system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
723system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
724system.cpu1.itb.read_accesses                       0                       # DTB read accesses
725system.cpu1.itb.write_accesses                      0                       # DTB write accesses
726system.cpu1.itb.inst_accesses                53673309                       # ITB inst accesses
727system.cpu1.itb.hits                         53671575                       # DTB hits
728system.cpu1.itb.misses                           1734                       # DTB misses
729system.cpu1.itb.accesses                     53673309                       # DTB accesses
730system.cpu1.numCycles                      5605320274                       # number of cpu cycles simulated
731system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
732system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
733system.cpu1.committedInsts                   51401314                       # Number of instructions committed
734system.cpu1.committedOps                     63347612                       # Number of ops (including micro ops) committed
735system.cpu1.num_int_alu_accesses             56984241                       # Number of integer alu accesses
736system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
737system.cpu1.num_func_calls                    9170855                       # number of times a function call or return occured
738system.cpu1.num_conditional_control_insts      5967100                       # number of instructions that are conditional controls
739system.cpu1.num_int_insts                    56984241                       # number of integer instructions
740system.cpu1.num_fp_insts                         1792                       # number of float instructions
741system.cpu1.num_int_register_reads          110674739                       # number of times the integer registers were read
742system.cpu1.num_int_register_writes          41298353                       # number of times the integer registers were written
743system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
744system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
745system.cpu1.num_cc_register_reads           196268655                       # number of times the CC registers were read
746system.cpu1.num_cc_register_writes           18894365                       # number of times the CC registers were written
747system.cpu1.num_mem_refs                     20026381                       # number of memory refs
748system.cpu1.num_load_insts                   12289537                       # Number of load instructions
749system.cpu1.num_store_insts                   7736844                       # Number of store instructions
750system.cpu1.num_idle_cycles              5539706759.565366                       # Number of idle cycles
751system.cpu1.num_busy_cycles              65613514.434634                       # Number of busy cycles
752system.cpu1.not_idle_fraction                0.011706                       # Percentage of non-idle cycles
753system.cpu1.idle_fraction                    0.988294                       # Percentage of idle cycles
754system.cpu1.Branches                         15217493                       # Number of branches fetched
755system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
756system.cpu1.op_class::IntAlu                 45401310     69.36%     69.36% # Class of executed instruction
757system.cpu1.op_class::IntMult                   28388      0.04%     69.40% # Class of executed instruction
758system.cpu1.op_class::IntDiv                        0      0.00%     69.40% # Class of executed instruction
759system.cpu1.op_class::FloatAdd                      0      0.00%     69.40% # Class of executed instruction
760system.cpu1.op_class::FloatCmp                      0      0.00%     69.40% # Class of executed instruction
761system.cpu1.op_class::FloatCvt                      0      0.00%     69.40% # Class of executed instruction
762system.cpu1.op_class::FloatMult                     0      0.00%     69.40% # Class of executed instruction
763system.cpu1.op_class::FloatDiv                      0      0.00%     69.40% # Class of executed instruction
764system.cpu1.op_class::FloatSqrt                     0      0.00%     69.40% # Class of executed instruction
765system.cpu1.op_class::SimdAdd                       0      0.00%     69.40% # Class of executed instruction
766system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.40% # Class of executed instruction
767system.cpu1.op_class::SimdAlu                       0      0.00%     69.40% # Class of executed instruction
768system.cpu1.op_class::SimdCmp                       0      0.00%     69.40% # Class of executed instruction
769system.cpu1.op_class::SimdCvt                       0      0.00%     69.40% # Class of executed instruction
770system.cpu1.op_class::SimdMisc                      0      0.00%     69.40% # Class of executed instruction
771system.cpu1.op_class::SimdMult                      0      0.00%     69.40% # Class of executed instruction
772system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.40% # Class of executed instruction
773system.cpu1.op_class::SimdShift                     0      0.00%     69.40% # Class of executed instruction
774system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.40% # Class of executed instruction
775system.cpu1.op_class::SimdSqrt                      0      0.00%     69.40% # Class of executed instruction
776system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.40% # Class of executed instruction
777system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.40% # Class of executed instruction
778system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.40% # Class of executed instruction
779system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.40% # Class of executed instruction
780system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.40% # Class of executed instruction
781system.cpu1.op_class::SimdFloatMisc              3319      0.01%     69.41% # Class of executed instruction
782system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.41% # Class of executed instruction
783system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.41% # Class of executed instruction
784system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.41% # Class of executed instruction
785system.cpu1.op_class::MemRead                12289537     18.77%     88.18% # Class of executed instruction
786system.cpu1.op_class::MemWrite                7736844     11.82%    100.00% # Class of executed instruction
787system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
788system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
789system.cpu1.op_class::total                  65459464                       # Class of executed instruction
790system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
791system.cpu1.kern.inst.quiesce                    2739                       # number of quiesce instructions executed
792system.cpu1.dcache.tags.replacements           191938                       # number of replacements
793system.cpu1.dcache.tags.tagsinuse          472.735415                       # Cycle average of tags in use
794system.cpu1.dcache.tags.total_refs           19503509                       # Total number of references to valid blocks.
795system.cpu1.dcache.tags.sampled_refs           192292                       # Sample count of references to valid blocks.
796system.cpu1.dcache.tags.avg_refs           101.426523                       # Average number of references to valid blocks.
797system.cpu1.dcache.tags.warmup_cycle     105851601500                       # Cycle when the warmup percentage was hit.
798system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.735415                       # Average occupied blocks per requestor
799system.cpu1.dcache.tags.occ_percent::cpu1.data     0.923311                       # Average percentage of cache occupancy
800system.cpu1.dcache.tags.occ_percent::total     0.923311                       # Average percentage of cache occupancy
801system.cpu1.dcache.tags.occ_task_id_blocks::1024          354                       # Occupied blocks per task id
802system.cpu1.dcache.tags.age_task_id_blocks_1024::2          341                       # Occupied blocks per task id
803system.cpu1.dcache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
804system.cpu1.dcache.tags.occ_task_id_percent::1024     0.691406                       # Percentage of cache occupancy per task id
805system.cpu1.dcache.tags.tag_accesses         39751979                       # Number of tag accesses
806system.cpu1.dcache.tags.data_accesses        39751979                       # Number of data accesses
807system.cpu1.dcache.ReadReq_hits::cpu1.data     11858694                       # number of ReadReq hits
808system.cpu1.dcache.ReadReq_hits::total       11858694                       # number of ReadReq hits
809system.cpu1.dcache.WriteReq_hits::cpu1.data      7397494                       # number of WriteReq hits
810system.cpu1.dcache.WriteReq_hits::total       7397494                       # number of WriteReq hits
811system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50099                       # number of SoftPFReq hits
812system.cpu1.dcache.SoftPFReq_hits::total        50099                       # number of SoftPFReq hits
813system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        91447                       # number of LoadLockedReq hits
814system.cpu1.dcache.LoadLockedReq_hits::total        91447                       # number of LoadLockedReq hits
815system.cpu1.dcache.StoreCondReq_hits::cpu1.data        72460                       # number of StoreCondReq hits
816system.cpu1.dcache.StoreCondReq_hits::total        72460                       # number of StoreCondReq hits
817system.cpu1.dcache.demand_hits::cpu1.data     19256188                       # number of demand (read+write) hits
818system.cpu1.dcache.demand_hits::total        19256188                       # number of demand (read+write) hits
819system.cpu1.dcache.overall_hits::cpu1.data     19306287                       # number of overall hits
820system.cpu1.dcache.overall_hits::total       19306287                       # number of overall hits
821system.cpu1.dcache.ReadReq_misses::cpu1.data       136630                       # number of ReadReq misses
822system.cpu1.dcache.ReadReq_misses::total       136630                       # number of ReadReq misses
823system.cpu1.dcache.WriteReq_misses::cpu1.data        92468                       # number of WriteReq misses
824system.cpu1.dcache.WriteReq_misses::total        92468                       # number of WriteReq misses
825system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30719                       # number of SoftPFReq misses
826system.cpu1.dcache.SoftPFReq_misses::total        30719                       # number of SoftPFReq misses
827system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5318                       # number of LoadLockedReq misses
828system.cpu1.dcache.LoadLockedReq_misses::total         5318                       # number of LoadLockedReq misses
829system.cpu1.dcache.StoreCondReq_misses::cpu1.data        22519                       # number of StoreCondReq misses
830system.cpu1.dcache.StoreCondReq_misses::total        22519                       # number of StoreCondReq misses
831system.cpu1.dcache.demand_misses::cpu1.data       229098                       # number of demand (read+write) misses
832system.cpu1.dcache.demand_misses::total        229098                       # number of demand (read+write) misses
833system.cpu1.dcache.overall_misses::cpu1.data       259817                       # number of overall misses
834system.cpu1.dcache.overall_misses::total       259817                       # number of overall misses
835system.cpu1.dcache.ReadReq_accesses::cpu1.data     11995324                       # number of ReadReq accesses(hits+misses)
836system.cpu1.dcache.ReadReq_accesses::total     11995324                       # number of ReadReq accesses(hits+misses)
837system.cpu1.dcache.WriteReq_accesses::cpu1.data      7489962                       # number of WriteReq accesses(hits+misses)
838system.cpu1.dcache.WriteReq_accesses::total      7489962                       # number of WriteReq accesses(hits+misses)
839system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80818                       # number of SoftPFReq accesses(hits+misses)
840system.cpu1.dcache.SoftPFReq_accesses::total        80818                       # number of SoftPFReq accesses(hits+misses)
841system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96765                       # number of LoadLockedReq accesses(hits+misses)
842system.cpu1.dcache.LoadLockedReq_accesses::total        96765                       # number of LoadLockedReq accesses(hits+misses)
843system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94979                       # number of StoreCondReq accesses(hits+misses)
844system.cpu1.dcache.StoreCondReq_accesses::total        94979                       # number of StoreCondReq accesses(hits+misses)
845system.cpu1.dcache.demand_accesses::cpu1.data     19485286                       # number of demand (read+write) accesses
846system.cpu1.dcache.demand_accesses::total     19485286                       # number of demand (read+write) accesses
847system.cpu1.dcache.overall_accesses::cpu1.data     19566104                       # number of overall (read+write) accesses
848system.cpu1.dcache.overall_accesses::total     19566104                       # number of overall (read+write) accesses
849system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.011390                       # miss rate for ReadReq accesses
850system.cpu1.dcache.ReadReq_miss_rate::total     0.011390                       # miss rate for ReadReq accesses
851system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.012346                       # miss rate for WriteReq accesses
852system.cpu1.dcache.WriteReq_miss_rate::total     0.012346                       # miss rate for WriteReq accesses
853system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.380101                       # miss rate for SoftPFReq accesses
854system.cpu1.dcache.SoftPFReq_miss_rate::total     0.380101                       # miss rate for SoftPFReq accesses
855system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.054958                       # miss rate for LoadLockedReq accesses
856system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.054958                       # miss rate for LoadLockedReq accesses
857system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.237095                       # miss rate for StoreCondReq accesses
858system.cpu1.dcache.StoreCondReq_miss_rate::total     0.237095                       # miss rate for StoreCondReq accesses
859system.cpu1.dcache.demand_miss_rate::cpu1.data     0.011757                       # miss rate for demand accesses
860system.cpu1.dcache.demand_miss_rate::total     0.011757                       # miss rate for demand accesses
861system.cpu1.dcache.overall_miss_rate::cpu1.data     0.013279                       # miss rate for overall accesses
862system.cpu1.dcache.overall_miss_rate::total     0.013279                       # miss rate for overall accesses
863system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
864system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
865system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
866system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
867system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
868system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
869system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
870system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
871system.cpu1.dcache.writebacks::writebacks       120855                       # number of writebacks
872system.cpu1.dcache.writebacks::total           120855                       # number of writebacks
873system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
874system.cpu1.icache.tags.replacements           523373                       # number of replacements
875system.cpu1.icache.tags.tagsinuse          499.711129                       # Cycle average of tags in use
876system.cpu1.icache.tags.total_refs           53148780                       # Total number of references to valid blocks.
877system.cpu1.icache.tags.sampled_refs           523885                       # Sample count of references to valid blocks.
878system.cpu1.icache.tags.avg_refs           101.451235                       # Average number of references to valid blocks.
879system.cpu1.icache.tags.warmup_cycle      76931404500                       # Cycle when the warmup percentage was hit.
880system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.711129                       # Average occupied blocks per requestor
881system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975998                       # Average percentage of cache occupancy
882system.cpu1.icache.tags.occ_percent::total     0.975998                       # Average percentage of cache occupancy
883system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
884system.cpu1.icache.tags.age_task_id_blocks_1024::2          477                       # Occupied blocks per task id
885system.cpu1.icache.tags.age_task_id_blocks_1024::3           35                       # Occupied blocks per task id
886system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
887system.cpu1.icache.tags.tag_accesses        107869215                       # Number of tag accesses
888system.cpu1.icache.tags.data_accesses       107869215                       # Number of data accesses
889system.cpu1.icache.ReadReq_hits::cpu1.inst     53148780                       # number of ReadReq hits
890system.cpu1.icache.ReadReq_hits::total       53148780                       # number of ReadReq hits
891system.cpu1.icache.demand_hits::cpu1.inst     53148780                       # number of demand (read+write) hits
892system.cpu1.icache.demand_hits::total        53148780                       # number of demand (read+write) hits
893system.cpu1.icache.overall_hits::cpu1.inst     53148780                       # number of overall hits
894system.cpu1.icache.overall_hits::total       53148780                       # number of overall hits
895system.cpu1.icache.ReadReq_misses::cpu1.inst       523885                       # number of ReadReq misses
896system.cpu1.icache.ReadReq_misses::total       523885                       # number of ReadReq misses
897system.cpu1.icache.demand_misses::cpu1.inst       523885                       # number of demand (read+write) misses
898system.cpu1.icache.demand_misses::total        523885                       # number of demand (read+write) misses
899system.cpu1.icache.overall_misses::cpu1.inst       523885                       # number of overall misses
900system.cpu1.icache.overall_misses::total       523885                       # number of overall misses
901system.cpu1.icache.ReadReq_accesses::cpu1.inst     53672665                       # number of ReadReq accesses(hits+misses)
902system.cpu1.icache.ReadReq_accesses::total     53672665                       # number of ReadReq accesses(hits+misses)
903system.cpu1.icache.demand_accesses::cpu1.inst     53672665                       # number of demand (read+write) accesses
904system.cpu1.icache.demand_accesses::total     53672665                       # number of demand (read+write) accesses
905system.cpu1.icache.overall_accesses::cpu1.inst     53672665                       # number of overall (read+write) accesses
906system.cpu1.icache.overall_accesses::total     53672665                       # number of overall (read+write) accesses
907system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009761                       # miss rate for ReadReq accesses
908system.cpu1.icache.ReadReq_miss_rate::total     0.009761                       # miss rate for ReadReq accesses
909system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009761                       # miss rate for demand accesses
910system.cpu1.icache.demand_miss_rate::total     0.009761                       # miss rate for demand accesses
911system.cpu1.icache.overall_miss_rate::cpu1.inst     0.009761                       # miss rate for overall accesses
912system.cpu1.icache.overall_miss_rate::total     0.009761                       # miss rate for overall accesses
913system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
914system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
915system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
916system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
917system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
918system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
919system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
920system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
921system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
922system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
923system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
924system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
925system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
926system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
927system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
928system.cpu1.l2cache.tags.replacements           48604                       # number of replacements
929system.cpu1.l2cache.tags.tagsinuse       15305.333897                       # Cycle average of tags in use
930system.cpu1.l2cache.tags.total_refs            716708                       # Total number of references to valid blocks.
931system.cpu1.l2cache.tags.sampled_refs           63433                       # Sample count of references to valid blocks.
932system.cpu1.l2cache.tags.avg_refs           11.298662                       # Average number of references to valid blocks.
933system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
934system.cpu1.l2cache.tags.occ_blocks::writebacks  8327.809694                       # Average occupied blocks per requestor
935system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     4.091002                       # Average occupied blocks per requestor
936system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.023143                       # Average occupied blocks per requestor
937system.cpu1.l2cache.tags.occ_blocks::cpu1.inst  3278.979607                       # Average occupied blocks per requestor
938system.cpu1.l2cache.tags.occ_blocks::cpu1.data  3692.430451                       # Average occupied blocks per requestor
939system.cpu1.l2cache.tags.occ_percent::writebacks     0.508289                       # Average percentage of cache occupancy
940system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000250                       # Average percentage of cache occupancy
941system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000123                       # Average percentage of cache occupancy
942system.cpu1.l2cache.tags.occ_percent::cpu1.inst     0.200133                       # Average percentage of cache occupancy
943system.cpu1.l2cache.tags.occ_percent::cpu1.data     0.225368                       # Average percentage of cache occupancy
944system.cpu1.l2cache.tags.occ_percent::total     0.934163                       # Average percentage of cache occupancy
945system.cpu1.l2cache.tags.occ_task_id_blocks::1023           22                       # Occupied blocks per task id
946system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14807                       # Occupied blocks per task id
947system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
948system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
949system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           15                       # Occupied blocks per task id
950system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          539                       # Occupied blocks per task id
951system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         9357                       # Occupied blocks per task id
952system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         4911                       # Occupied blocks per task id
953system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001343                       # Percentage of cache occupancy per task id
954system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.903748                       # Percentage of cache occupancy per task id
955system.cpu1.l2cache.tags.tag_accesses        15213345                       # Number of tag accesses
956system.cpu1.l2cache.tags.data_accesses       15213345                       # Number of data accesses
957system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3151                       # number of ReadReq hits
958system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1735                       # number of ReadReq hits
959system.cpu1.l2cache.ReadReq_hits::cpu1.inst       510036                       # number of ReadReq hits
960system.cpu1.l2cache.ReadReq_hits::cpu1.data        99375                       # number of ReadReq hits
961system.cpu1.l2cache.ReadReq_hits::total        614297                       # number of ReadReq hits
962system.cpu1.l2cache.Writeback_hits::writebacks       120855                       # number of Writeback hits
963system.cpu1.l2cache.Writeback_hits::total       120855                       # number of Writeback hits
964system.cpu1.l2cache.UpgradeReq_hits::cpu1.data            8                       # number of UpgradeReq hits
965system.cpu1.l2cache.UpgradeReq_hits::total            8                       # number of UpgradeReq hits
966system.cpu1.l2cache.ReadExReq_hits::cpu1.data        19784                       # number of ReadExReq hits
967system.cpu1.l2cache.ReadExReq_hits::total        19784                       # number of ReadExReq hits
968system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3151                       # number of demand (read+write) hits
969system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1735                       # number of demand (read+write) hits
970system.cpu1.l2cache.demand_hits::cpu1.inst       510036                       # number of demand (read+write) hits
971system.cpu1.l2cache.demand_hits::cpu1.data       119159                       # number of demand (read+write) hits
972system.cpu1.l2cache.demand_hits::total         634081                       # number of demand (read+write) hits
973system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3151                       # number of overall hits
974system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1735                       # number of overall hits
975system.cpu1.l2cache.overall_hits::cpu1.inst       510036                       # number of overall hits
976system.cpu1.l2cache.overall_hits::cpu1.data       119159                       # number of overall hits
977system.cpu1.l2cache.overall_hits::total        634081                       # number of overall hits
978system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          338                       # number of ReadReq misses
979system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          261                       # number of ReadReq misses
980system.cpu1.l2cache.ReadReq_misses::cpu1.inst        13849                       # number of ReadReq misses
981system.cpu1.l2cache.ReadReq_misses::cpu1.data        73292                       # number of ReadReq misses
982system.cpu1.l2cache.ReadReq_misses::total        87740                       # number of ReadReq misses
983system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28844                       # number of UpgradeReq misses
984system.cpu1.l2cache.UpgradeReq_misses::total        28844                       # number of UpgradeReq misses
985system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22519                       # number of SCUpgradeReq misses
986system.cpu1.l2cache.SCUpgradeReq_misses::total        22519                       # number of SCUpgradeReq misses
987system.cpu1.l2cache.ReadExReq_misses::cpu1.data        43832                       # number of ReadExReq misses
988system.cpu1.l2cache.ReadExReq_misses::total        43832                       # number of ReadExReq misses
989system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          338                       # number of demand (read+write) misses
990system.cpu1.l2cache.demand_misses::cpu1.itb.walker          261                       # number of demand (read+write) misses
991system.cpu1.l2cache.demand_misses::cpu1.inst        13849                       # number of demand (read+write) misses
992system.cpu1.l2cache.demand_misses::cpu1.data       117124                       # number of demand (read+write) misses
993system.cpu1.l2cache.demand_misses::total       131572                       # number of demand (read+write) misses
994system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          338                       # number of overall misses
995system.cpu1.l2cache.overall_misses::cpu1.itb.walker          261                       # number of overall misses
996system.cpu1.l2cache.overall_misses::cpu1.inst        13849                       # number of overall misses
997system.cpu1.l2cache.overall_misses::cpu1.data       117124                       # number of overall misses
998system.cpu1.l2cache.overall_misses::total       131572                       # number of overall misses
999system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3489                       # number of ReadReq accesses(hits+misses)
1000system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         1996                       # number of ReadReq accesses(hits+misses)
1001system.cpu1.l2cache.ReadReq_accesses::cpu1.inst       523885                       # number of ReadReq accesses(hits+misses)
1002system.cpu1.l2cache.ReadReq_accesses::cpu1.data       172667                       # number of ReadReq accesses(hits+misses)
1003system.cpu1.l2cache.ReadReq_accesses::total       702037                       # number of ReadReq accesses(hits+misses)
1004system.cpu1.l2cache.Writeback_accesses::writebacks       120855                       # number of Writeback accesses(hits+misses)
1005system.cpu1.l2cache.Writeback_accesses::total       120855                       # number of Writeback accesses(hits+misses)
1006system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28852                       # number of UpgradeReq accesses(hits+misses)
1007system.cpu1.l2cache.UpgradeReq_accesses::total        28852                       # number of UpgradeReq accesses(hits+misses)
1008system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        22519                       # number of SCUpgradeReq accesses(hits+misses)
1009system.cpu1.l2cache.SCUpgradeReq_accesses::total        22519                       # number of SCUpgradeReq accesses(hits+misses)
1010system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        63616                       # number of ReadExReq accesses(hits+misses)
1011system.cpu1.l2cache.ReadExReq_accesses::total        63616                       # number of ReadExReq accesses(hits+misses)
1012system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3489                       # number of demand (read+write) accesses
1013system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         1996                       # number of demand (read+write) accesses
1014system.cpu1.l2cache.demand_accesses::cpu1.inst       523885                       # number of demand (read+write) accesses
1015system.cpu1.l2cache.demand_accesses::cpu1.data       236283                       # number of demand (read+write) accesses
1016system.cpu1.l2cache.demand_accesses::total       765653                       # number of demand (read+write) accesses
1017system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3489                       # number of overall (read+write) accesses
1018system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         1996                       # number of overall (read+write) accesses
1019system.cpu1.l2cache.overall_accesses::cpu1.inst       523885                       # number of overall (read+write) accesses
1020system.cpu1.l2cache.overall_accesses::cpu1.data       236283                       # number of overall (read+write) accesses
1021system.cpu1.l2cache.overall_accesses::total       765653                       # number of overall (read+write) accesses
1022system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.096876                       # miss rate for ReadReq accesses
1023system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.130762                       # miss rate for ReadReq accesses
1024system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst     0.026435                       # miss rate for ReadReq accesses
1025system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data     0.424470                       # miss rate for ReadReq accesses
1026system.cpu1.l2cache.ReadReq_miss_rate::total     0.124979                       # miss rate for ReadReq accesses
1027system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999723                       # miss rate for UpgradeReq accesses
1028system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999723                       # miss rate for UpgradeReq accesses
1029system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
1030system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
1031system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.689009                       # miss rate for ReadExReq accesses
1032system.cpu1.l2cache.ReadExReq_miss_rate::total     0.689009                       # miss rate for ReadExReq accesses
1033system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.096876                       # miss rate for demand accesses
1034system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.130762                       # miss rate for demand accesses
1035system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.026435                       # miss rate for demand accesses
1036system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.495694                       # miss rate for demand accesses
1037system.cpu1.l2cache.demand_miss_rate::total     0.171843                       # miss rate for demand accesses
1038system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.096876                       # miss rate for overall accesses
1039system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.130762                       # miss rate for overall accesses
1040system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.026435                       # miss rate for overall accesses
1041system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.495694                       # miss rate for overall accesses
1042system.cpu1.l2cache.overall_miss_rate::total     0.171843                       # miss rate for overall accesses
1043system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
1044system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
1045system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
1046system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
1047system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
1048system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
1049system.cpu1.l2cache.fast_writes                     0                       # number of fast writes performed
1050system.cpu1.l2cache.cache_copies                    0                       # number of cache copies performed
1051system.cpu1.l2cache.writebacks::writebacks        32977                       # number of writebacks
1052system.cpu1.l2cache.writebacks::total           32977                       # number of writebacks
1053system.cpu1.l2cache.no_allocate_misses              0                       # Number of misses that were no-allocate
1054system.cpu1.toL2Bus.trans_dist::ReadReq        709301                       # Transaction distribution
1055system.cpu1.toL2Bus.trans_dist::ReadResp       709301                       # Transaction distribution
1056system.cpu1.toL2Bus.trans_dist::WriteReq         2505                       # Transaction distribution
1057system.cpu1.toL2Bus.trans_dist::WriteResp         2505                       # Transaction distribution
1058system.cpu1.toL2Bus.trans_dist::Writeback       120855                       # Transaction distribution
1059system.cpu1.toL2Bus.trans_dist::UpgradeReq        28852                       # Transaction distribution
1060system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        22519                       # Transaction distribution
1061system.cpu1.toL2Bus.trans_dist::UpgradeResp        51371                       # Transaction distribution
1062system.cpu1.toL2Bus.trans_dist::ReadExReq        63616                       # Transaction distribution
1063system.cpu1.toL2Bus.trans_dist::ReadExResp        63616                       # Transaction distribution
1064system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1048124                       # Packet count per connected master and slave (bytes)
1065system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       707623                       # Packet count per connected master and slave (bytes)
1066system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6616                       # Packet count per connected master and slave (bytes)
1067system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        12078                       # Packet count per connected master and slave (bytes)
1068system.cpu1.toL2Bus.pkt_count::total          1774441                       # Packet count per connected master and slave (bytes)
1069system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     33529348                       # Cumulative packet size per connected master and slave (bytes)
1070system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     22876014                       # Cumulative packet size per connected master and slave (bytes)
1071system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        13232                       # Cumulative packet size per connected master and slave (bytes)
1072system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        24156                       # Cumulative packet size per connected master and slave (bytes)
1073system.cpu1.toL2Bus.pkt_size::total          56442750                       # Cumulative packet size per connected master and slave (bytes)
1074system.cpu1.toL2Bus.snoops                     499492                       # Total snoops (count)
1075system.cpu1.toL2Bus.snoop_fanout::samples      1371571                       # Request fanout histogram
1076system.cpu1.toL2Bus.snoop_fanout::mean       3.313385                       # Request fanout histogram
1077system.cpu1.toL2Bus.snoop_fanout::stdev      0.463870                       # Request fanout histogram
1078system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
1079system.cpu1.toL2Bus.snoop_fanout::0                 0      0.00%      0.00% # Request fanout histogram
1080system.cpu1.toL2Bus.snoop_fanout::1                 0      0.00%      0.00% # Request fanout histogram
1081system.cpu1.toL2Bus.snoop_fanout::2                 0      0.00%      0.00% # Request fanout histogram
1082system.cpu1.toL2Bus.snoop_fanout::3            941741     68.66%     68.66% # Request fanout histogram
1083system.cpu1.toL2Bus.snoop_fanout::4            429830     31.34%    100.00% # Request fanout histogram
1084system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
1085system.cpu1.toL2Bus.snoop_fanout::min_value            3                       # Request fanout histogram
1086system.cpu1.toL2Bus.snoop_fanout::max_value            4                       # Request fanout histogram
1087system.cpu1.toL2Bus.snoop_fanout::total       1371571                       # Request fanout histogram
1088system.iobus.trans_dist::ReadReq                30995                       # Transaction distribution
1089system.iobus.trans_dist::ReadResp               30995                       # Transaction distribution
1090system.iobus.trans_dist::WriteReq               59419                       # Transaction distribution
1091system.iobus.trans_dist::WriteResp              23195                       # Transaction distribution
1092system.iobus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
1093system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56582                       # Packet count per connected master and slave (bytes)
1094system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
1095system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
1096system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
1097system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
1098system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          834                       # Packet count per connected master and slave (bytes)
1099system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
1100system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
1101system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
1102system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
1103system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
1104system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
1105system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
1106system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
1107system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
1108system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
1109system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
1110system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf          210                       # Packet count per connected master and slave (bytes)
1111system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
1112system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf          164                       # Packet count per connected master and slave (bytes)
1113system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio           60                       # Packet count per connected master and slave (bytes)
1114system.iobus.pkt_count_system.bridge.master::total       107876                       # Packet count per connected master and slave (bytes)
1115system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
1116system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
1117system.iobus.pkt_count::total                  180828                       # Packet count per connected master and slave (bytes)
1118system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71526                       # Cumulative packet size per connected master and slave (bytes)
1119system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
1120system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
1121system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
1122system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
1123system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          441                       # Cumulative packet size per connected master and slave (bytes)
1124system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
1125system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
1126system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
1127system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
1128system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
1129system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
1130system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
1131system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
1132system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
1133system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
1134system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
1135system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf          265                       # Cumulative packet size per connected master and slave (bytes)
1136system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
1137system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf          253                       # Cumulative packet size per connected master and slave (bytes)
1138system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio          120                       # Cumulative packet size per connected master and slave (bytes)
1139system.iobus.pkt_size_system.bridge.master::total       162766                       # Cumulative packet size per connected master and slave (bytes)
1140system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
1141system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
1142system.iobus.pkt_size::total                  2484014                       # Cumulative packet size per connected master and slave (bytes)
1143system.iocache.tags.replacements                36442                       # number of replacements
1144system.iocache.tags.tagsinuse               14.586092                       # Cycle average of tags in use
1145system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
1146system.iocache.tags.sampled_refs                36458                       # Sample count of references to valid blocks.
1147system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
1148system.iocache.tags.warmup_cycle         246641286009                       # Cycle when the warmup percentage was hit.
1149system.iocache.tags.occ_blocks::realview.ide    14.586092                       # Average occupied blocks per requestor
1150system.iocache.tags.occ_percent::realview.ide     0.911631                       # Average percentage of cache occupancy
1151system.iocache.tags.occ_percent::total       0.911631                       # Average percentage of cache occupancy
1152system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
1153system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
1154system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
1155system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
1156system.iocache.tags.data_accesses              328284                       # Number of data accesses
1157system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
1158system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
1159system.iocache.WriteInvalidateReq_misses::realview.ide        36224                       # number of WriteInvalidateReq misses
1160system.iocache.WriteInvalidateReq_misses::total        36224                       # number of WriteInvalidateReq misses
1161system.iocache.demand_misses::realview.ide          252                       # number of demand (read+write) misses
1162system.iocache.demand_misses::total               252                       # number of demand (read+write) misses
1163system.iocache.overall_misses::realview.ide          252                       # number of overall misses
1164system.iocache.overall_misses::total              252                       # number of overall misses
1165system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
1166system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
1167system.iocache.WriteInvalidateReq_accesses::realview.ide        36224                       # number of WriteInvalidateReq accesses(hits+misses)
1168system.iocache.WriteInvalidateReq_accesses::total        36224                       # number of WriteInvalidateReq accesses(hits+misses)
1169system.iocache.demand_accesses::realview.ide          252                       # number of demand (read+write) accesses
1170system.iocache.demand_accesses::total             252                       # number of demand (read+write) accesses
1171system.iocache.overall_accesses::realview.ide          252                       # number of overall (read+write) accesses
1172system.iocache.overall_accesses::total            252                       # number of overall (read+write) accesses
1173system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
1174system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
1175system.iocache.WriteInvalidateReq_miss_rate::realview.ide            1                       # miss rate for WriteInvalidateReq accesses
1176system.iocache.WriteInvalidateReq_miss_rate::total            1                       # miss rate for WriteInvalidateReq accesses
1177system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
1178system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
1179system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
1180system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
1181system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
1182system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
1183system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
1184system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
1185system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
1186system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
1187system.iocache.fast_writes                          0                       # number of fast writes performed
1188system.iocache.cache_copies                         0                       # number of cache copies performed
1189system.iocache.writebacks::writebacks           36190                       # number of writebacks
1190system.iocache.writebacks::total                36190                       # number of writebacks
1191system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
1192system.l2c.tags.replacements                   107683                       # number of replacements
1193system.l2c.tags.tagsinuse                62052.473518                       # Cycle average of tags in use
1194system.l2c.tags.total_refs                     207875                       # Total number of references to valid blocks.
1195system.l2c.tags.sampled_refs                   168125                       # Sample count of references to valid blocks.
1196system.l2c.tags.avg_refs                     1.236431                       # Average number of references to valid blocks.
1197system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
1198system.l2c.tags.occ_blocks::writebacks   48595.677496                       # Average occupied blocks per requestor
1199system.l2c.tags.occ_blocks::cpu0.dtb.walker     2.972785                       # Average occupied blocks per requestor
1200system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030393                       # Average occupied blocks per requestor
1201system.l2c.tags.occ_blocks::cpu0.inst     7329.722723                       # Average occupied blocks per requestor
1202system.l2c.tags.occ_blocks::cpu0.data     3756.747244                       # Average occupied blocks per requestor
1203system.l2c.tags.occ_blocks::cpu1.dtb.walker     1.823230                       # Average occupied blocks per requestor
1204system.l2c.tags.occ_blocks::cpu1.inst     1654.505866                       # Average occupied blocks per requestor
1205system.l2c.tags.occ_blocks::cpu1.data      710.993782                       # Average occupied blocks per requestor
1206system.l2c.tags.occ_percent::writebacks      0.741511                       # Average percentage of cache occupancy
1207system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000045                       # Average percentage of cache occupancy
1208system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
1209system.l2c.tags.occ_percent::cpu0.inst       0.111843                       # Average percentage of cache occupancy
1210system.l2c.tags.occ_percent::cpu0.data       0.057323                       # Average percentage of cache occupancy
1211system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000028                       # Average percentage of cache occupancy
1212system.l2c.tags.occ_percent::cpu1.inst       0.025246                       # Average percentage of cache occupancy
1213system.l2c.tags.occ_percent::cpu1.data       0.010849                       # Average percentage of cache occupancy
1214system.l2c.tags.occ_percent::total           0.946846                       # Average percentage of cache occupancy
1215system.l2c.tags.occ_task_id_blocks::1023            7                       # Occupied blocks per task id
1216system.l2c.tags.occ_task_id_blocks::1024        60435                       # Occupied blocks per task id
1217system.l2c.tags.age_task_id_blocks_1023::4            7                       # Occupied blocks per task id
1218system.l2c.tags.age_task_id_blocks_1024::0           40                       # Occupied blocks per task id
1219system.l2c.tags.age_task_id_blocks_1024::1           68                       # Occupied blocks per task id
1220system.l2c.tags.age_task_id_blocks_1024::2         1875                       # Occupied blocks per task id
1221system.l2c.tags.age_task_id_blocks_1024::3        13095                       # Occupied blocks per task id
1222system.l2c.tags.age_task_id_blocks_1024::4        45357                       # Occupied blocks per task id
1223system.l2c.tags.occ_task_id_percent::1023     0.000107                       # Percentage of cache occupancy per task id
1224system.l2c.tags.occ_task_id_percent::1024     0.922165                       # Percentage of cache occupancy per task id
1225system.l2c.tags.tag_accesses                  4904261                       # Number of tag accesses
1226system.l2c.tags.data_accesses                 4904261                       # Number of data accesses
1227system.l2c.ReadReq_hits::cpu0.dtb.walker           71                       # number of ReadReq hits
1228system.l2c.ReadReq_hits::cpu0.itb.walker           63                       # number of ReadReq hits
1229system.l2c.ReadReq_hits::cpu0.inst              27858                       # number of ReadReq hits
1230system.l2c.ReadReq_hits::cpu0.data              76068                       # number of ReadReq hits
1231system.l2c.ReadReq_hits::cpu1.dtb.walker           39                       # number of ReadReq hits
1232system.l2c.ReadReq_hits::cpu1.itb.walker           20                       # number of ReadReq hits
1233system.l2c.ReadReq_hits::cpu1.inst              11484                       # number of ReadReq hits
1234system.l2c.ReadReq_hits::cpu1.data              11410                       # number of ReadReq hits
1235system.l2c.ReadReq_hits::total                 127013                       # number of ReadReq hits
1236system.l2c.Writeback_hits::writebacks          225951                       # number of Writeback hits
1237system.l2c.Writeback_hits::total               225951                       # number of Writeback hits
1238system.l2c.UpgradeReq_hits::cpu0.data             487                       # number of UpgradeReq hits
1239system.l2c.UpgradeReq_hits::cpu1.data              65                       # number of UpgradeReq hits
1240system.l2c.UpgradeReq_hits::total                 552                       # number of UpgradeReq hits
1241system.l2c.SCUpgradeReq_hits::cpu0.data            64                       # number of SCUpgradeReq hits
1242system.l2c.SCUpgradeReq_hits::cpu1.data            10                       # number of SCUpgradeReq hits
1243system.l2c.SCUpgradeReq_hits::total                74                       # number of SCUpgradeReq hits
1244system.l2c.ReadExReq_hits::cpu0.data            13938                       # number of ReadExReq hits
1245system.l2c.ReadExReq_hits::cpu1.data             3112                       # number of ReadExReq hits
1246system.l2c.ReadExReq_hits::total                17050                       # number of ReadExReq hits
1247system.l2c.demand_hits::cpu0.dtb.walker            71                       # number of demand (read+write) hits
1248system.l2c.demand_hits::cpu0.itb.walker            63                       # number of demand (read+write) hits
1249system.l2c.demand_hits::cpu0.inst               27858                       # number of demand (read+write) hits
1250system.l2c.demand_hits::cpu0.data               90006                       # number of demand (read+write) hits
1251system.l2c.demand_hits::cpu1.dtb.walker            39                       # number of demand (read+write) hits
1252system.l2c.demand_hits::cpu1.itb.walker            20                       # number of demand (read+write) hits
1253system.l2c.demand_hits::cpu1.inst               11484                       # number of demand (read+write) hits
1254system.l2c.demand_hits::cpu1.data               14522                       # number of demand (read+write) hits
1255system.l2c.demand_hits::total                  144063                       # number of demand (read+write) hits
1256system.l2c.overall_hits::cpu0.dtb.walker           71                       # number of overall hits
1257system.l2c.overall_hits::cpu0.itb.walker           63                       # number of overall hits
1258system.l2c.overall_hits::cpu0.inst              27858                       # number of overall hits
1259system.l2c.overall_hits::cpu0.data              90006                       # number of overall hits
1260system.l2c.overall_hits::cpu1.dtb.walker           39                       # number of overall hits
1261system.l2c.overall_hits::cpu1.itb.walker           20                       # number of overall hits
1262system.l2c.overall_hits::cpu1.inst              11484                       # number of overall hits
1263system.l2c.overall_hits::cpu1.data              14522                       # number of overall hits
1264system.l2c.overall_hits::total                 144063                       # number of overall hits
1265system.l2c.ReadReq_misses::cpu0.dtb.walker            7                       # number of ReadReq misses
1266system.l2c.ReadReq_misses::cpu0.itb.walker            2                       # number of ReadReq misses
1267system.l2c.ReadReq_misses::cpu0.inst            16901                       # number of ReadReq misses
1268system.l2c.ReadReq_misses::cpu0.data            11313                       # number of ReadReq misses
1269system.l2c.ReadReq_misses::cpu1.dtb.walker            2                       # number of ReadReq misses
1270system.l2c.ReadReq_misses::cpu1.inst             2365                       # number of ReadReq misses
1271system.l2c.ReadReq_misses::cpu1.data             1118                       # number of ReadReq misses
1272system.l2c.ReadReq_misses::total                31708                       # number of ReadReq misses
1273system.l2c.UpgradeReq_misses::cpu0.data         10019                       # number of UpgradeReq misses
1274system.l2c.UpgradeReq_misses::cpu1.data          3288                       # number of UpgradeReq misses
1275system.l2c.UpgradeReq_misses::total             13307                       # number of UpgradeReq misses
1276system.l2c.SCUpgradeReq_misses::cpu0.data          752                       # number of SCUpgradeReq misses
1277system.l2c.SCUpgradeReq_misses::cpu1.data         1179                       # number of SCUpgradeReq misses
1278system.l2c.SCUpgradeReq_misses::total            1931                       # number of SCUpgradeReq misses
1279system.l2c.ReadExReq_misses::cpu0.data         136795                       # number of ReadExReq misses
1280system.l2c.ReadExReq_misses::cpu1.data          15822                       # number of ReadExReq misses
1281system.l2c.ReadExReq_misses::total             152617                       # number of ReadExReq misses
1282system.l2c.demand_misses::cpu0.dtb.walker            7                       # number of demand (read+write) misses
1283system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
1284system.l2c.demand_misses::cpu0.inst             16901                       # number of demand (read+write) misses
1285system.l2c.demand_misses::cpu0.data            148108                       # number of demand (read+write) misses
1286system.l2c.demand_misses::cpu1.dtb.walker            2                       # number of demand (read+write) misses
1287system.l2c.demand_misses::cpu1.inst              2365                       # number of demand (read+write) misses
1288system.l2c.demand_misses::cpu1.data             16940                       # number of demand (read+write) misses
1289system.l2c.demand_misses::total                184325                       # number of demand (read+write) misses
1290system.l2c.overall_misses::cpu0.dtb.walker            7                       # number of overall misses
1291system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
1292system.l2c.overall_misses::cpu0.inst            16901                       # number of overall misses
1293system.l2c.overall_misses::cpu0.data           148108                       # number of overall misses
1294system.l2c.overall_misses::cpu1.dtb.walker            2                       # number of overall misses
1295system.l2c.overall_misses::cpu1.inst             2365                       # number of overall misses
1296system.l2c.overall_misses::cpu1.data            16940                       # number of overall misses
1297system.l2c.overall_misses::total               184325                       # number of overall misses
1298system.l2c.ReadReq_accesses::cpu0.dtb.walker           78                       # number of ReadReq accesses(hits+misses)
1299system.l2c.ReadReq_accesses::cpu0.itb.walker           65                       # number of ReadReq accesses(hits+misses)
1300system.l2c.ReadReq_accesses::cpu0.inst          44759                       # number of ReadReq accesses(hits+misses)
1301system.l2c.ReadReq_accesses::cpu0.data          87381                       # number of ReadReq accesses(hits+misses)
1302system.l2c.ReadReq_accesses::cpu1.dtb.walker           41                       # number of ReadReq accesses(hits+misses)
1303system.l2c.ReadReq_accesses::cpu1.itb.walker           20                       # number of ReadReq accesses(hits+misses)
1304system.l2c.ReadReq_accesses::cpu1.inst          13849                       # number of ReadReq accesses(hits+misses)
1305system.l2c.ReadReq_accesses::cpu1.data          12528                       # number of ReadReq accesses(hits+misses)
1306system.l2c.ReadReq_accesses::total             158721                       # number of ReadReq accesses(hits+misses)
1307system.l2c.Writeback_accesses::writebacks       225951                       # number of Writeback accesses(hits+misses)
1308system.l2c.Writeback_accesses::total           225951                       # number of Writeback accesses(hits+misses)
1309system.l2c.UpgradeReq_accesses::cpu0.data        10506                       # number of UpgradeReq accesses(hits+misses)
1310system.l2c.UpgradeReq_accesses::cpu1.data         3353                       # number of UpgradeReq accesses(hits+misses)
1311system.l2c.UpgradeReq_accesses::total           13859                       # number of UpgradeReq accesses(hits+misses)
1312system.l2c.SCUpgradeReq_accesses::cpu0.data          816                       # number of SCUpgradeReq accesses(hits+misses)
1313system.l2c.SCUpgradeReq_accesses::cpu1.data         1189                       # number of SCUpgradeReq accesses(hits+misses)
1314system.l2c.SCUpgradeReq_accesses::total          2005                       # number of SCUpgradeReq accesses(hits+misses)
1315system.l2c.ReadExReq_accesses::cpu0.data       150733                       # number of ReadExReq accesses(hits+misses)
1316system.l2c.ReadExReq_accesses::cpu1.data        18934                       # number of ReadExReq accesses(hits+misses)
1317system.l2c.ReadExReq_accesses::total           169667                       # number of ReadExReq accesses(hits+misses)
1318system.l2c.demand_accesses::cpu0.dtb.walker           78                       # number of demand (read+write) accesses
1319system.l2c.demand_accesses::cpu0.itb.walker           65                       # number of demand (read+write) accesses
1320system.l2c.demand_accesses::cpu0.inst           44759                       # number of demand (read+write) accesses
1321system.l2c.demand_accesses::cpu0.data          238114                       # number of demand (read+write) accesses
1322system.l2c.demand_accesses::cpu1.dtb.walker           41                       # number of demand (read+write) accesses
1323system.l2c.demand_accesses::cpu1.itb.walker           20                       # number of demand (read+write) accesses
1324system.l2c.demand_accesses::cpu1.inst           13849                       # number of demand (read+write) accesses
1325system.l2c.demand_accesses::cpu1.data           31462                       # number of demand (read+write) accesses
1326system.l2c.demand_accesses::total              328388                       # number of demand (read+write) accesses
1327system.l2c.overall_accesses::cpu0.dtb.walker           78                       # number of overall (read+write) accesses
1328system.l2c.overall_accesses::cpu0.itb.walker           65                       # number of overall (read+write) accesses
1329system.l2c.overall_accesses::cpu0.inst          44759                       # number of overall (read+write) accesses
1330system.l2c.overall_accesses::cpu0.data         238114                       # number of overall (read+write) accesses
1331system.l2c.overall_accesses::cpu1.dtb.walker           41                       # number of overall (read+write) accesses
1332system.l2c.overall_accesses::cpu1.itb.walker           20                       # number of overall (read+write) accesses
1333system.l2c.overall_accesses::cpu1.inst          13849                       # number of overall (read+write) accesses
1334system.l2c.overall_accesses::cpu1.data          31462                       # number of overall (read+write) accesses
1335system.l2c.overall_accesses::total             328388                       # number of overall (read+write) accesses
1336system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.089744                       # miss rate for ReadReq accesses
1337system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.030769                       # miss rate for ReadReq accesses
1338system.l2c.ReadReq_miss_rate::cpu0.inst      0.377600                       # miss rate for ReadReq accesses
1339system.l2c.ReadReq_miss_rate::cpu0.data      0.129468                       # miss rate for ReadReq accesses
1340system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.048780                       # miss rate for ReadReq accesses
1341system.l2c.ReadReq_miss_rate::cpu1.inst      0.170770                       # miss rate for ReadReq accesses
1342system.l2c.ReadReq_miss_rate::cpu1.data      0.089240                       # miss rate for ReadReq accesses
1343system.l2c.ReadReq_miss_rate::total          0.199772                       # miss rate for ReadReq accesses
1344system.l2c.UpgradeReq_miss_rate::cpu0.data     0.953646                       # miss rate for UpgradeReq accesses
1345system.l2c.UpgradeReq_miss_rate::cpu1.data     0.980614                       # miss rate for UpgradeReq accesses
1346system.l2c.UpgradeReq_miss_rate::total       0.960170                       # miss rate for UpgradeReq accesses
1347system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.921569                       # miss rate for SCUpgradeReq accesses
1348system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.991590                       # miss rate for SCUpgradeReq accesses
1349system.l2c.SCUpgradeReq_miss_rate::total     0.963092                       # miss rate for SCUpgradeReq accesses
1350system.l2c.ReadExReq_miss_rate::cpu0.data     0.907532                       # miss rate for ReadExReq accesses
1351system.l2c.ReadExReq_miss_rate::cpu1.data     0.835640                       # miss rate for ReadExReq accesses
1352system.l2c.ReadExReq_miss_rate::total        0.899509                       # miss rate for ReadExReq accesses
1353system.l2c.demand_miss_rate::cpu0.dtb.walker     0.089744                       # miss rate for demand accesses
1354system.l2c.demand_miss_rate::cpu0.itb.walker     0.030769                       # miss rate for demand accesses
1355system.l2c.demand_miss_rate::cpu0.inst       0.377600                       # miss rate for demand accesses
1356system.l2c.demand_miss_rate::cpu0.data       0.622005                       # miss rate for demand accesses
1357system.l2c.demand_miss_rate::cpu1.dtb.walker     0.048780                       # miss rate for demand accesses
1358system.l2c.demand_miss_rate::cpu1.inst       0.170770                       # miss rate for demand accesses
1359system.l2c.demand_miss_rate::cpu1.data       0.538427                       # miss rate for demand accesses
1360system.l2c.demand_miss_rate::total           0.561302                       # miss rate for demand accesses
1361system.l2c.overall_miss_rate::cpu0.dtb.walker     0.089744                       # miss rate for overall accesses
1362system.l2c.overall_miss_rate::cpu0.itb.walker     0.030769                       # miss rate for overall accesses
1363system.l2c.overall_miss_rate::cpu0.inst      0.377600                       # miss rate for overall accesses
1364system.l2c.overall_miss_rate::cpu0.data      0.622005                       # miss rate for overall accesses
1365system.l2c.overall_miss_rate::cpu1.dtb.walker     0.048780                       # miss rate for overall accesses
1366system.l2c.overall_miss_rate::cpu1.inst      0.170770                       # miss rate for overall accesses
1367system.l2c.overall_miss_rate::cpu1.data      0.538427                       # miss rate for overall accesses
1368system.l2c.overall_miss_rate::total          0.561302                       # miss rate for overall accesses
1369system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
1370system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
1371system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
1372system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
1373system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
1374system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
1375system.l2c.fast_writes                              0                       # number of fast writes performed
1376system.l2c.cache_copies                             0                       # number of cache copies performed
1377system.l2c.writebacks::writebacks               94914                       # number of writebacks
1378system.l2c.writebacks::total                    94914                       # number of writebacks
1379system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
1380system.membus.trans_dist::ReadReq               75966                       # Transaction distribution
1381system.membus.trans_dist::ReadResp              75966                       # Transaction distribution
1382system.membus.trans_dist::WriteReq              30891                       # Transaction distribution
1383system.membus.trans_dist::WriteResp             30891                       # Transaction distribution
1384system.membus.trans_dist::Writeback            131104                       # Transaction distribution
1385system.membus.trans_dist::WriteInvalidateReq        36224                       # Transaction distribution
1386system.membus.trans_dist::WriteInvalidateResp        36224                       # Transaction distribution
1387system.membus.trans_dist::UpgradeReq            60393                       # Transaction distribution
1388system.membus.trans_dist::SCUpgradeReq          40881                       # Transaction distribution
1389system.membus.trans_dist::UpgradeResp           15635                       # Transaction distribution
1390system.membus.trans_dist::ReadExReq            196339                       # Transaction distribution
1391system.membus.trans_dist::ReadExResp           152220                       # Transaction distribution
1392system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107876                       # Packet count per connected master and slave (bytes)
1393system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
1394system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13474                       # Packet count per connected master and slave (bytes)
1395system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       652208                       # Packet count per connected master and slave (bytes)
1396system.membus.pkt_count_system.l2c.mem_side::total       773592                       # Packet count per connected master and slave (bytes)
1397system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109142                       # Packet count per connected master and slave (bytes)
1398system.membus.pkt_count_system.iocache.mem_side::total       109142                       # Packet count per connected master and slave (bytes)
1399system.membus.pkt_count::total                 882734                       # Packet count per connected master and slave (bytes)
1400system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162766                       # Cumulative packet size per connected master and slave (bytes)
1401system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
1402system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        26948                       # Cumulative packet size per connected master and slave (bytes)
1403system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17902820                       # Cumulative packet size per connected master and slave (bytes)
1404system.membus.pkt_size_system.l2c.mem_side::total     18092602                       # Cumulative packet size per connected master and slave (bytes)
1405system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      4650624                       # Cumulative packet size per connected master and slave (bytes)
1406system.membus.pkt_size_system.iocache.mem_side::total      4650624                       # Cumulative packet size per connected master and slave (bytes)
1407system.membus.pkt_size::total                22743226                       # Cumulative packet size per connected master and slave (bytes)
1408system.membus.snoops                                0                       # Total snoops (count)
1409system.membus.snoop_fanout::samples            496901                       # Request fanout histogram
1410system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
1411system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
1412system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
1413system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
1414system.membus.snoop_fanout::1                  496901    100.00%    100.00% # Request fanout histogram
1415system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
1416system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
1417system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
1418system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
1419system.membus.snoop_fanout::total              496901                       # Request fanout histogram
1420system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
1421system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
1422system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
1423system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
1424system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
1425system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
1426system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
1427system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
1428system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
1429system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
1430system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
1431system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
1432system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
1433system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
1434system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
1435system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
1436system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
1437system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
1438system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
1439system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
1440system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
1441system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
1442system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
1443system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
1444system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
1445system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
1446system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
1447system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
1448system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
1449system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
1450system.realview.ethernet.droppedPackets             0                       # number of packets dropped
1451system.toL2Bus.trans_dist::ReadReq             305006                       # Transaction distribution
1452system.toL2Bus.trans_dist::ReadResp            305006                       # Transaction distribution
1453system.toL2Bus.trans_dist::WriteReq             30891                       # Transaction distribution
1454system.toL2Bus.trans_dist::WriteResp            30891                       # Transaction distribution
1455system.toL2Bus.trans_dist::Writeback           225951                       # Transaction distribution
1456system.toL2Bus.trans_dist::UpgradeReq           60548                       # Transaction distribution
1457system.toL2Bus.trans_dist::SCUpgradeReq         40955                       # Transaction distribution
1458system.toL2Bus.trans_dist::UpgradeResp         101503                       # Transaction distribution
1459system.toL2Bus.trans_dist::ReadExReq           213786                       # Transaction distribution
1460system.toL2Bus.trans_dist::ReadExResp          213786                       # Transaction distribution
1461system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1117662                       # Packet count per connected master and slave (bytes)
1462system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       410661                       # Packet count per connected master and slave (bytes)
1463system.toL2Bus.pkt_count::total               1528323                       # Packet count per connected master and slave (bytes)
1464system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34664008                       # Cumulative packet size per connected master and slave (bytes)
1465system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10429874                       # Cumulative packet size per connected master and slave (bytes)
1466system.toL2Bus.pkt_size::total               45093882                       # Cumulative packet size per connected master and slave (bytes)
1467system.toL2Bus.snoops                           36713                       # Total snoops (count)
1468system.toL2Bus.snoop_fanout::samples           838716                       # Request fanout histogram
1469system.toL2Bus.snoop_fanout::mean            1.043490                       # Request fanout histogram
1470system.toL2Bus.snoop_fanout::stdev           0.203958                       # Request fanout histogram
1471system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
1472system.toL2Bus.snoop_fanout::0                      0      0.00%      0.00% # Request fanout histogram
1473system.toL2Bus.snoop_fanout::1                 802240     95.65%     95.65% # Request fanout histogram
1474system.toL2Bus.snoop_fanout::2                  36476      4.35%    100.00% # Request fanout histogram
1475system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
1476system.toL2Bus.snoop_fanout::min_value              1                       # Request fanout histogram
1477system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
1478system.toL2Bus.snoop_fanout::total             838716                       # Request fanout histogram
1479
1480---------- End Simulation Statistics   ----------
1481