stats.txt revision 9988
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 39134Ssaidi@eecs.umich.edusim_seconds 0.912097 # Number of seconds simulated 49134Ssaidi@eecs.umich.edusim_ticks 912096763500 # Number of ticks simulated 59134Ssaidi@eecs.umich.edufinal_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 79988Snilay@cs.wisc.eduhost_inst_rate 1031681 # Simulator instruction rate (inst/s) 89988Snilay@cs.wisc.eduhost_op_rate 1328287 # Simulator op (including micro ops) rate (op/s) 99988Snilay@cs.wisc.eduhost_tick_rate 15269405009 # Simulator tick rate (ticks/s) 109988Snilay@cs.wisc.eduhost_mem_usage 443324 # Number of bytes of host memory used 119988Snilay@cs.wisc.eduhost_seconds 59.73 # Real time elapsed on the host 129134Ssaidi@eecs.umich.edusim_insts 61625970 # Number of instructions simulated 139134Ssaidi@eecs.umich.edusim_ops 79343340 # Number of ops (including micro ops) simulated 149134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 159134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 169134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 179134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory 189449SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory 199134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 209134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory 219134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory 229449SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 49638500 # Number of bytes read from this memory 239134Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory 249134Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory 259134Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory 269134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory 279134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 289134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory 299134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::total 7222864 # Number of bytes written to this memory 309134Ssaidi@eecs.umich.edusystem.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 319134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 329134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 339134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory 349449SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory 359134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 369134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory 379134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory 389449SAli.Saidi@ARM.comsystem.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory 399134Ssaidi@eecs.umich.edusystem.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory 409134Ssaidi@eecs.umich.edusystem.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 419134Ssaidi@eecs.umich.edusystem.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory 429134Ssaidi@eecs.umich.edusystem.physmem.num_writes::total 822331 # Number of write requests responded to by this memory 439134Ssaidi@eecs.umich.edusystem.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) 449134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) 459134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) 469134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s) 479449SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s) 489134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) 499134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s) 509134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s) 519449SAli.Saidi@ARM.comsystem.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s) 529134Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s) 539134Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s) 549134Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s) 559134Ssaidi@eecs.umich.edusystem.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s) 569134Ssaidi@eecs.umich.edusystem.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) 579134Ssaidi@eecs.umich.edusystem.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) 589134Ssaidi@eecs.umich.edusystem.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) 599134Ssaidi@eecs.umich.edusystem.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s) 609134Ssaidi@eecs.umich.edusystem.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) 619134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) 629134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) 639134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s) 649449SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s) 659134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) 669134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) 679134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) 689449SAli.Saidi@ARM.comsystem.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s) 699481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 709481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 719481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 729481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 739481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 749481Snilay@cs.wisc.edusystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 759481Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 769481Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 779481Snilay@cs.wisc.edusystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 789481Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 799481Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 809481Snilay@cs.wisc.edusystem.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 819481Snilay@cs.wisc.edusystem.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 829481Snilay@cs.wisc.edusystem.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 839481Snilay@cs.wisc.edusystem.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 849481Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 859481Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 869481Snilay@cs.wisc.edusystem.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 879729Sandreas.hansson@arm.comsystem.membus.throughput 64986577 # Throughput (bytes/s) 889729Sandreas.hansson@arm.comsystem.membus.data_through_bus 59274047 # Total data (bytes) 899729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 909885Sstever@gmail.comsystem.l2c.tags.replacements 70658 # number of replacements 919885Sstever@gmail.comsystem.l2c.tags.tagsinuse 51560.149653 # Cycle average of tags in use 929885Sstever@gmail.comsystem.l2c.tags.total_refs 1623339 # Total number of references to valid blocks. 939885Sstever@gmail.comsystem.l2c.tags.sampled_refs 135810 # Sample count of references to valid blocks. 949885Sstever@gmail.comsystem.l2c.tags.avg_refs 11.953015 # Average number of references to valid blocks. 959885Sstever@gmail.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 969885Sstever@gmail.comsystem.l2c.tags.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor 979885Sstever@gmail.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor 989885Sstever@gmail.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor 999885Sstever@gmail.comsystem.l2c.tags.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor 1009885Sstever@gmail.comsystem.l2c.tags.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor 1019885Sstever@gmail.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor 1029885Sstever@gmail.comsystem.l2c.tags.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor 1039885Sstever@gmail.comsystem.l2c.tags.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor 1049885Sstever@gmail.comsystem.l2c.tags.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy 1059885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 1069885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 1079885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy 1089885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy 1099885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 1109885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy 1119885Sstever@gmail.comsystem.l2c.tags.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy 1129885Sstever@gmail.comsystem.l2c.tags.occ_percent::total 0.786745 # Average percentage of cache occupancy 1139134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits 1149134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits 1159134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits 1169134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits 1179134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits 1189134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits 1199134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits 1209134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.data 169511 # number of ReadReq hits 1219134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::total 1209106 # number of ReadReq hits 1229134Ssaidi@eecs.umich.edusystem.l2c.Writeback_hits::writebacks 567807 # number of Writeback hits 1239134Ssaidi@eecs.umich.edusystem.l2c.Writeback_hits::total 567807 # number of Writeback hits 1249134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits 1259134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits 1269134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits 1279134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits 1289134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits 1299134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits 1309449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits 1319134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits 1329449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits 1339134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits 1349134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits 1359134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits 1369449SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits 1379134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits 1389134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits 1399134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits 1409134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits 1419449SAli.Saidi@ARM.comsystem.l2c.demand_hits::total 1317466 # number of demand (read+write) hits 1429134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits 1439134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits 1449134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.inst 421038 # number of overall hits 1459449SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.data 233336 # number of overall hits 1469134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits 1479134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits 1489134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.inst 430511 # number of overall hits 1499134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.data 219723 # number of overall hits 1509449SAli.Saidi@ARM.comsystem.l2c.overall_hits::total 1317466 # number of overall hits 1519079SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 1529134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 1539134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses 1549134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses 1559079SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 1569134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses 1579134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses 1589134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::total 22454 # number of ReadReq misses 1599134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses 1609134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses 1619134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses 1629134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses 1639134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses 1649134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses 1659449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses 1669134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses 1679449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses 1689079SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 1699134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 1709134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses 1719449SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses 1729079SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 1739134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses 1749134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses 1759449SAli.Saidi@ARM.comsystem.l2c.demand_misses::total 163290 # number of demand (read+write) misses 1769079SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 1779134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 1789134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.inst 7432 # number of overall misses 1799449SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.data 98856 # number of overall misses 1809079SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 1819134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu1.inst 3347 # number of overall misses 1829134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu1.data 53648 # number of overall misses 1839449SAli.Saidi@ARM.comsystem.l2c.overall_misses::total 163290 # number of overall misses 1849134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) 1859134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) 1869134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) 1879134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses) 1889134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses) 1899134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses) 1909134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses) 1919134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses) 1929134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) 1939134Ssaidi@eecs.umich.edusystem.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) 1949134Ssaidi@eecs.umich.edusystem.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) 1959134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses) 1969134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses) 1979134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses) 1989134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) 1999134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) 2009134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) 2019134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses) 2029134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses) 2039134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses) 2049134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses 2059134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses 2069134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses 2079134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses 2089134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses 2099134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses 2109134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses 2119134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses 2129134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses 2139134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses 2149134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses 2159134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses 2169134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses 2179134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses 2189134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses 2199134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses 2209134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses 2219134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses 2229134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses 2239134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses 2249134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses 2259134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses 2269134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses 2279134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses 2289134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses 2299134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses 2309134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses 2319134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses 2329134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses 2339134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses 2349134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses 2359134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses 2369449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses 2379134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses 2389449SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses 2399134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses 2409134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses 2419134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses 2429449SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses 2439134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses 2449134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses 2459134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses 2469449SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses 2479134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses 2489134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses 2499134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses 2509449SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses 2519134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses 2529134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses 2539134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses 2549449SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses 2558844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2568844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2578844SAli.Saidi@ARM.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2588844SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 2598983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2608983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2618844SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 2628844SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 2639134Ssaidi@eecs.umich.edusystem.l2c.writebacks::writebacks 65559 # number of writebacks 2649134Ssaidi@eecs.umich.edusystem.l2c.writebacks::total 65559 # number of writebacks 2658844SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2668844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2678844SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2688844SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2698844SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 2708844SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 2718844SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 0 # Number of DMA write transactions. 2729729Sandreas.hansson@arm.comsystem.toL2Bus.throughput 154009014 # Throughput (bytes/s) 2739729Sandreas.hansson@arm.comsystem.toL2Bus.data_through_bus 140471123 # Total data (bytes) 2749729Sandreas.hansson@arm.comsystem.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 2759729Sandreas.hansson@arm.comsystem.iobus.throughput 45730949 # Throughput (bytes/s) 2769729Sandreas.hansson@arm.comsystem.iobus.data_through_bus 41711051 # Total data (bytes) 2778844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 2788844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 2799134Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_hits 7975768 # DTB read hits 2809134Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_misses 3611 # DTB read misses 2819134Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_hits 5966574 # DTB write hits 2829134Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_misses 672 # DTB write misses 2838844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 2848844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2858844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2868844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 2879134Ssaidi@eecs.umich.edusystem.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB 2888844SAli.Saidi@ARM.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2899134Ssaidi@eecs.umich.edusystem.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch 2908844SAli.Saidi@ARM.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2919134Ssaidi@eecs.umich.edusystem.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 2929134Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_accesses 7979379 # DTB read accesses 2939134Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_accesses 5967246 # DTB write accesses 2948844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 2959134Ssaidi@eecs.umich.edusystem.cpu0.dtb.hits 13942342 # DTB hits 2969134Ssaidi@eecs.umich.edusystem.cpu0.dtb.misses 4283 # DTB misses 2979134Ssaidi@eecs.umich.edusystem.cpu0.dtb.accesses 13946625 # DTB accesses 2989134Ssaidi@eecs.umich.edusystem.cpu0.itb.inst_hits 30238804 # ITB inst hits 2999134Ssaidi@eecs.umich.edusystem.cpu0.itb.inst_misses 2175 # ITB inst misses 3008844SAli.Saidi@ARM.comsystem.cpu0.itb.read_hits 0 # DTB read hits 3018844SAli.Saidi@ARM.comsystem.cpu0.itb.read_misses 0 # DTB read misses 3028844SAli.Saidi@ARM.comsystem.cpu0.itb.write_hits 0 # DTB write hits 3038844SAli.Saidi@ARM.comsystem.cpu0.itb.write_misses 0 # DTB write misses 3048844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 3058844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3068844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 3078844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 3089134Ssaidi@eecs.umich.edusystem.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB 3098844SAli.Saidi@ARM.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3108844SAli.Saidi@ARM.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3118844SAli.Saidi@ARM.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3128844SAli.Saidi@ARM.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3138844SAli.Saidi@ARM.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 3148844SAli.Saidi@ARM.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 3159134Ssaidi@eecs.umich.edusystem.cpu0.itb.inst_accesses 30240979 # ITB inst accesses 3169134Ssaidi@eecs.umich.edusystem.cpu0.itb.hits 30238804 # DTB hits 3179134Ssaidi@eecs.umich.edusystem.cpu0.itb.misses 2175 # DTB misses 3189134Ssaidi@eecs.umich.edusystem.cpu0.itb.accesses 30240979 # DTB accesses 3199988Snilay@cs.wisc.edusystem.cpu0.numCycles 1823671407 # number of cpu cycles simulated 3208844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 3218844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 3229134Ssaidi@eecs.umich.edusystem.cpu0.committedInsts 29750005 # Number of instructions committed 3239134Ssaidi@eecs.umich.edusystem.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed 3249134Ssaidi@eecs.umich.edusystem.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses 3259134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses 3269134Ssaidi@eecs.umich.edusystem.cpu0.num_func_calls 1241903 # number of times a function call or return occured 3279265SAli.Saidi@ARM.comsystem.cpu0.num_conditional_control_insts 4044057 # number of instructions that are conditional controls 3289134Ssaidi@eecs.umich.edusystem.cpu0.num_int_insts 34471201 # number of integer instructions 3299134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_insts 5449 # number of float instructions 3309134Ssaidi@eecs.umich.edusystem.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read 3319134Ssaidi@eecs.umich.edusystem.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written 3329134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read 3339134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_register_writes 916 # number of times the floating registers were written 3349134Ssaidi@eecs.umich.edusystem.cpu0.num_mem_refs 14626951 # number of memory refs 3359134Ssaidi@eecs.umich.edusystem.cpu0.num_load_insts 8357226 # Number of load instructions 3369134Ssaidi@eecs.umich.edusystem.cpu0.num_store_insts 6269725 # Number of store instructions 3379988Snilay@cs.wisc.edusystem.cpu0.num_idle_cycles 1784006336.868180 # Number of idle cycles 3389988Snilay@cs.wisc.edusystem.cpu0.num_busy_cycles 39665070.131821 # Number of busy cycles 3399134Ssaidi@eecs.umich.edusystem.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles 3409134Ssaidi@eecs.umich.edusystem.cpu0.idle_fraction 0.978250 # Percentage of idle cycles 3418844SAli.Saidi@ARM.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 3429134Ssaidi@eecs.umich.edusystem.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed 3439885Sstever@gmail.comsystem.cpu0.icache.tags.replacements 428546 # number of replacements 3449885Sstever@gmail.comsystem.cpu0.icache.tags.tagsinuse 511.015216 # Cycle average of tags in use 3459885Sstever@gmail.comsystem.cpu0.icache.tags.total_refs 29811115 # Total number of references to valid blocks. 3469885Sstever@gmail.comsystem.cpu0.icache.tags.sampled_refs 429058 # Sample count of references to valid blocks. 3479885Sstever@gmail.comsystem.cpu0.icache.tags.avg_refs 69.480385 # Average number of references to valid blocks. 3489885Sstever@gmail.comsystem.cpu0.icache.tags.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. 3499797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor 3509797Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy 3519885Sstever@gmail.comsystem.cpu0.icache.tags.occ_percent::total 0.998077 # Average percentage of cache occupancy 3529134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits 3539134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits 3549134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits 3559134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits 3569134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits 3579134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_hits::total 29811115 # number of overall hits 3589134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses 3599134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses 3609134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses 3619134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses 3629134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses 3639134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_misses::total 429059 # number of overall misses 3649134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses) 3659134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses) 3669134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses 3679134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses 3689134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses 3699134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses 3709134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses 3719134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses 3729134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses 3739134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses 3749134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses 3759134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses 3768844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3778844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3788844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3798844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 3808983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3818983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3828844SAli.Saidi@ARM.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 3838844SAli.Saidi@ARM.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 3848844SAli.Saidi@ARM.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3859885Sstever@gmail.comsystem.cpu0.dcache.tags.replacements 323609 # number of replacements 3869885Sstever@gmail.comsystem.cpu0.dcache.tags.tagsinuse 494.763091 # Cycle average of tags in use 3879885Sstever@gmail.comsystem.cpu0.dcache.tags.total_refs 12467604 # Total number of references to valid blocks. 3889885Sstever@gmail.comsystem.cpu0.dcache.tags.sampled_refs 323981 # Sample count of references to valid blocks. 3899885Sstever@gmail.comsystem.cpu0.dcache.tags.avg_refs 38.482516 # Average number of references to valid blocks. 3909885Sstever@gmail.comsystem.cpu0.dcache.tags.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. 3919797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor 3929797Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy 3939885Sstever@gmail.comsystem.cpu0.dcache.tags.occ_percent::total 0.966334 # Average percentage of cache occupancy 3949134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits 3959134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits 3969134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits 3979134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits 3989134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits 3999134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits 4009134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits 4019134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits 4029134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits 4039134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits 4049134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits 4059134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_hits::total 12143186 # number of overall hits 4069134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses 4079134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses 4089134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses 4099134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses 4109134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses 4119134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses 4129134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 7469 # number of StoreCondReq misses 4139134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_misses::total 7469 # number of StoreCondReq misses 4149134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses 4159134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses 4169134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses 4179134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_misses::total 364509 # number of overall misses 4189134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses) 4199134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses) 4209134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses) 4219134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) 4229134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) 4239134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) 4249134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160649 # number of StoreCondReq accesses(hits+misses) 4259134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_accesses::total 160649 # number of StoreCondReq accesses(hits+misses) 4269134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses 4279134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses 4289134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses 4299134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses 4309134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses 4319134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses 4329134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses 4339134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses 4349134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses 4359134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses 4369134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046493 # miss rate for StoreCondReq accesses 4379134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.046493 # miss rate for StoreCondReq accesses 4389134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses 4399134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses 4409134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses 4419134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses 4428844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4438844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4448844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4458844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 4468983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4478983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4488844SAli.Saidi@ARM.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 4498844SAli.Saidi@ARM.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 4509134Ssaidi@eecs.umich.edusystem.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks 4519134Ssaidi@eecs.umich.edusystem.cpu0.dcache.writebacks::total 300958 # number of writebacks 4528844SAli.Saidi@ARM.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4538844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 4548844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 4559134Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_hits 7364781 # DTB read hits 4569134Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_misses 3705 # DTB read misses 4579134Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_hits 5489656 # DTB write hits 4589134Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_misses 1595 # DTB write misses 4598844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 4608844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4618844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 4628844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 4639134Ssaidi@eecs.umich.edusystem.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB 4648844SAli.Saidi@ARM.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 4659134Ssaidi@eecs.umich.edusystem.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch 4668844SAli.Saidi@ARM.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 4679134Ssaidi@eecs.umich.edusystem.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 4689134Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_accesses 7368486 # DTB read accesses 4699134Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_accesses 5491251 # DTB write accesses 4708844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 4719134Ssaidi@eecs.umich.edusystem.cpu1.dtb.hits 12854437 # DTB hits 4729134Ssaidi@eecs.umich.edusystem.cpu1.dtb.misses 5300 # DTB misses 4739134Ssaidi@eecs.umich.edusystem.cpu1.dtb.accesses 12859737 # DTB accesses 4749134Ssaidi@eecs.umich.edusystem.cpu1.itb.inst_hits 32412306 # ITB inst hits 4759134Ssaidi@eecs.umich.edusystem.cpu1.itb.inst_misses 2200 # ITB inst misses 4768844SAli.Saidi@ARM.comsystem.cpu1.itb.read_hits 0 # DTB read hits 4778844SAli.Saidi@ARM.comsystem.cpu1.itb.read_misses 0 # DTB read misses 4788844SAli.Saidi@ARM.comsystem.cpu1.itb.write_hits 0 # DTB write hits 4798844SAli.Saidi@ARM.comsystem.cpu1.itb.write_misses 0 # DTB write misses 4808844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 4818844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4828844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 4838844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 4849134Ssaidi@eecs.umich.edusystem.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB 4858844SAli.Saidi@ARM.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4868844SAli.Saidi@ARM.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4878844SAli.Saidi@ARM.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4888844SAli.Saidi@ARM.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4898844SAli.Saidi@ARM.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 4908844SAli.Saidi@ARM.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 4919134Ssaidi@eecs.umich.edusystem.cpu1.itb.inst_accesses 32414506 # ITB inst accesses 4929134Ssaidi@eecs.umich.edusystem.cpu1.itb.hits 32412306 # DTB hits 4939134Ssaidi@eecs.umich.edusystem.cpu1.itb.misses 2200 # DTB misses 4949134Ssaidi@eecs.umich.edusystem.cpu1.itb.accesses 32414506 # DTB accesses 4959988Snilay@cs.wisc.edusystem.cpu1.numCycles 1824193528 # number of cpu cycles simulated 4968844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 4978844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 4989134Ssaidi@eecs.umich.edusystem.cpu1.committedInsts 31875965 # Number of instructions committed 4999134Ssaidi@eecs.umich.edusystem.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed 5009134Ssaidi@eecs.umich.edusystem.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses 5019134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses 5029134Ssaidi@eecs.umich.edusystem.cpu1.num_func_calls 955227 # number of times a function call or return occured 5039265SAli.Saidi@ARM.comsystem.cpu1.num_conditional_control_insts 4048022 # number of instructions that are conditional controls 5049134Ssaidi@eecs.umich.edusystem.cpu1.num_int_insts 35797832 # number of integer instructions 5059134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_insts 4436 # number of float instructions 5069134Ssaidi@eecs.umich.edusystem.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read 5079134Ssaidi@eecs.umich.edusystem.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written 5089134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read 5099134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written 5109134Ssaidi@eecs.umich.edusystem.cpu1.num_mem_refs 13370713 # number of memory refs 5119134Ssaidi@eecs.umich.edusystem.cpu1.num_load_insts 7642673 # Number of load instructions 5129134Ssaidi@eecs.umich.edusystem.cpu1.num_store_insts 5728040 # Number of store instructions 5139988Snilay@cs.wisc.edusystem.cpu1.num_idle_cycles 1783401357.733683 # Number of idle cycles 5149988Snilay@cs.wisc.edusystem.cpu1.num_busy_cycles 40792170.266317 # Number of busy cycles 5159134Ssaidi@eecs.umich.edusystem.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles 5169134Ssaidi@eecs.umich.edusystem.cpu1.idle_fraction 0.977638 # Percentage of idle cycles 5178844SAli.Saidi@ARM.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 5189134Ssaidi@eecs.umich.edusystem.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed 5199885Sstever@gmail.comsystem.cpu1.icache.tags.replacements 433942 # number of replacements 5209885Sstever@gmail.comsystem.cpu1.icache.tags.tagsinuse 475.447912 # Cycle average of tags in use 5219885Sstever@gmail.comsystem.cpu1.icache.tags.total_refs 31979125 # Total number of references to valid blocks. 5229885Sstever@gmail.comsystem.cpu1.icache.tags.sampled_refs 434454 # Sample count of references to valid blocks. 5239885Sstever@gmail.comsystem.cpu1.icache.tags.avg_refs 73.607620 # Average number of references to valid blocks. 5249885Sstever@gmail.comsystem.cpu1.icache.tags.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. 5259797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor 5269797Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy 5279885Sstever@gmail.comsystem.cpu1.icache.tags.occ_percent::total 0.928609 # Average percentage of cache occupancy 5289134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits 5299134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits 5309134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits 5319134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits 5329134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits 5339134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_hits::total 31979125 # number of overall hits 5349134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses 5359134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses 5369134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses 5379134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses 5389134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses 5399134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_misses::total 434454 # number of overall misses 5409134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses) 5419134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses) 5429134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses 5439134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses 5449134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses 5459134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses 5469134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses 5479134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses 5489134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses 5499134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses 5509134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses 5519134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses 5528844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5538844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5548844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 5558844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 5568983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5578983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5588844SAli.Saidi@ARM.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 5598844SAli.Saidi@ARM.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 5608844SAli.Saidi@ARM.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5619885Sstever@gmail.comsystem.cpu1.dcache.tags.replacements 294289 # number of replacements 5629885Sstever@gmail.comsystem.cpu1.dcache.tags.tagsinuse 447.573682 # Cycle average of tags in use 5639885Sstever@gmail.comsystem.cpu1.dcache.tags.total_refs 11707745 # Total number of references to valid blocks. 5649885Sstever@gmail.comsystem.cpu1.dcache.tags.sampled_refs 294801 # Sample count of references to valid blocks. 5659885Sstever@gmail.comsystem.cpu1.dcache.tags.avg_refs 39.714061 # Average number of references to valid blocks. 5669885Sstever@gmail.comsystem.cpu1.dcache.tags.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. 5679797Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor 5689797Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy 5699885Sstever@gmail.comsystem.cpu1.dcache.tags.occ_percent::total 0.874167 # Average percentage of cache occupancy 5709134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits 5719134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits 5729134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits 5739134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits 5749134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits 5759134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits 5769134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits 5779134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits 5789134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits 5799134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits 5809134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits 5819134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_hits::total 11522522 # number of overall hits 5829134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses 5839134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses 5849134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses 5859134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses 5869134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses 5879134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses 5889134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 10139 # number of StoreCondReq misses 5899134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_misses::total 10139 # number of StoreCondReq misses 5909134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses 5919134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses 5929134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses 5939134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_misses::total 324195 # number of overall misses 5949134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses) 5959134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses) 5969134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses) 5979134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) 5989134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) 5999134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) 6009134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89169 # number of StoreCondReq accesses(hits+misses) 6019134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_accesses::total 89169 # number of StoreCondReq accesses(hits+misses) 6029134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses 6039134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses 6049134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses 6059134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses 6069134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses 6079134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses 6089134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses 6099134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses 6109134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses 6119134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses 6129134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113705 # miss rate for StoreCondReq accesses 6139134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.113705 # miss rate for StoreCondReq accesses 6149134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses 6159134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses 6169134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses 6179134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses 6188844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6198844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6208844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 6218844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 6228983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6238983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6248844SAli.Saidi@ARM.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 6258844SAli.Saidi@ARM.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 6269134Ssaidi@eecs.umich.edusystem.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks 6279134Ssaidi@eecs.umich.edusystem.cpu1.dcache.writebacks::total 266849 # number of writebacks 6288844SAli.Saidi@ARM.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 6299885Sstever@gmail.comsystem.iocache.tags.replacements 0 # number of replacements 6309885Sstever@gmail.comsystem.iocache.tags.tagsinuse 0 # Cycle average of tags in use 6319885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 6329885Sstever@gmail.comsystem.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. 6339885Sstever@gmail.comsystem.iocache.tags.avg_refs nan # Average number of references to valid blocks. 6349885Sstever@gmail.comsystem.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6358844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6368844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6378844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 6388844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 6398983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6408983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6418844SAli.Saidi@ARM.comsystem.iocache.fast_writes 0 # number of fast writes performed 6428844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 6438844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 6448844SAli.Saidi@ARM.com 6458844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 646