stats.txt revision 9134
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 39134Ssaidi@eecs.umich.edusim_seconds 0.912097 # Number of seconds simulated 49134Ssaidi@eecs.umich.edusim_ticks 912096763500 # Number of ticks simulated 59134Ssaidi@eecs.umich.edufinal_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 79134Ssaidi@eecs.umich.eduhost_inst_rate 1622636 # Simulator instruction rate (inst/s) 89134Ssaidi@eecs.umich.eduhost_op_rate 2089140 # Simulator op (including micro ops) rate (op/s) 99134Ssaidi@eecs.umich.eduhost_tick_rate 24015838223 # Simulator tick rate (ticks/s) 109134Ssaidi@eecs.umich.eduhost_mem_usage 388524 # Number of bytes of host memory used 119134Ssaidi@eecs.umich.eduhost_seconds 37.98 # Real time elapsed on the host 129134Ssaidi@eecs.umich.edusim_insts 61625970 # Number of instructions simulated 139134Ssaidi@eecs.umich.edusim_ops 79343340 # Number of ops (including micro ops) simulated 149134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 159134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory 169134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory 179134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory 189134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.data 6234996 # Number of bytes read from this memory 199134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory 209134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory 219134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory 229134Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 49638308 # Number of bytes read from this memory 239134Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory 249134Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory 259134Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory 269134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory 279134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 289134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory 299134Ssaidi@eecs.umich.edusystem.physmem.bytes_written::total 7222864 # Number of bytes written to this memory 309134Ssaidi@eecs.umich.edusystem.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 319134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory 329134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory 339134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory 349134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.data 97494 # Number of read requests responded to by this memory 359134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory 369134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory 379134Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory 389134Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 5082797 # Number of read requests responded to by this memory 399134Ssaidi@eecs.umich.edusystem.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory 409134Ssaidi@eecs.umich.edusystem.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 419134Ssaidi@eecs.umich.edusystem.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory 429134Ssaidi@eecs.umich.edusystem.physmem.num_writes::total 822331 # Number of write requests responded to by this memory 439134Ssaidi@eecs.umich.edusystem.physmem.bw_read::realview.clcd 43111215 # Total read bandwidth from this memory (bytes/s) 449134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) 459134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) 469134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s) 479134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.data 6835893 # Total read bandwidth from this memory (bytes/s) 489134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) 499134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s) 509134Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s) 519134Ssaidi@eecs.umich.edusystem.physmem.bw_read::total 54422195 # Total read bandwidth from this memory (bytes/s) 529134Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s) 539134Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s) 549134Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s) 559134Ssaidi@eecs.umich.edusystem.physmem.bw_write::writebacks 4600144 # Write bandwidth from this memory (bytes/s) 569134Ssaidi@eecs.umich.edusystem.physmem.bw_write::cpu0.data 18638 # Write bandwidth from this memory (bytes/s) 579134Ssaidi@eecs.umich.edusystem.physmem.bw_write::cpu1.data 3300185 # Write bandwidth from this memory (bytes/s) 589134Ssaidi@eecs.umich.edusystem.physmem.bw_write::total 7918967 # Write bandwidth from this memory (bytes/s) 599134Ssaidi@eecs.umich.edusystem.physmem.bw_total::writebacks 4600144 # Total bandwidth to/from this memory (bytes/s) 609134Ssaidi@eecs.umich.edusystem.physmem.bw_total::realview.clcd 43111215 # Total bandwidth to/from this memory (bytes/s) 619134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) 629134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) 639134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s) 649134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.data 6854532 # Total bandwidth to/from this memory (bytes/s) 659134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) 669134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) 679134Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) 689134Ssaidi@eecs.umich.edusystem.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s) 699055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 709055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 719055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 729055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 739055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 749055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 759055Ssaidi@eecs.umich.edusystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 769055Ssaidi@eecs.umich.edusystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 779055Ssaidi@eecs.umich.edusystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 789055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 799055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 809055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 819055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 829055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 839055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 849055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 859055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 869055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 879134Ssaidi@eecs.umich.edusystem.l2c.replacements 70662 # number of replacements 889134Ssaidi@eecs.umich.edusystem.l2c.tagsinuse 51560.217790 # Cycle average of tags in use 899134Ssaidi@eecs.umich.edusystem.l2c.total_refs 1623342 # Total number of references to valid blocks. 909134Ssaidi@eecs.umich.edusystem.l2c.sampled_refs 135814 # Sample count of references to valid blocks. 919134Ssaidi@eecs.umich.edusystem.l2c.avg_refs 11.952685 # Average number of references to valid blocks. 928844SAli.Saidi@ARM.comsystem.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 939134Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::writebacks 39276.104351 # Average occupied blocks per requestor 949079SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor 959134Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor 969134Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu0.inst 4360.752038 # Average occupied blocks per requestor 979134Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu0.data 2483.307369 # Average occupied blocks per requestor 989134Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor 999134Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor 1009134Ssaidi@eecs.umich.edusystem.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor 1019134Ssaidi@eecs.umich.edusystem.l2c.occ_percent::writebacks 0.599306 # Average percentage of cache occupancy 1029079SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy 1039079SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 1049134Ssaidi@eecs.umich.edusystem.l2c.occ_percent::cpu0.inst 0.066540 # Average percentage of cache occupancy 1059134Ssaidi@eecs.umich.edusystem.l2c.occ_percent::cpu0.data 0.037892 # Average percentage of cache occupancy 1069079SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy 1079134Ssaidi@eecs.umich.edusystem.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy 1089134Ssaidi@eecs.umich.edusystem.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy 1099134Ssaidi@eecs.umich.edusystem.l2c.occ_percent::total 0.786746 # Average percentage of cache occupancy 1109134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits 1119134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits 1129134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits 1139134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu0.data 175188 # number of ReadReq hits 1149134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.dtb.walker 5331 # number of ReadReq hits 1159134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.itb.walker 1734 # number of ReadReq hits 1169134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.inst 430511 # number of ReadReq hits 1179134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::cpu1.data 169511 # number of ReadReq hits 1189134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_hits::total 1209106 # number of ReadReq hits 1199134Ssaidi@eecs.umich.edusystem.l2c.Writeback_hits::writebacks 567807 # number of Writeback hits 1209134Ssaidi@eecs.umich.edusystem.l2c.Writeback_hits::total 567807 # number of Writeback hits 1219134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu0.data 611 # number of UpgradeReq hits 1229134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::cpu1.data 663 # number of UpgradeReq hits 1239134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_hits::total 1274 # number of UpgradeReq hits 1249134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits 1259134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits 1269134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits 1279134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_hits::cpu0.data 58151 # number of ReadExReq hits 1289134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits 1299134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_hits::total 108363 # number of ReadExReq hits 1309134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits 1319134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits 1329134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits 1339134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu0.data 233339 # number of demand (read+write) hits 1349134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits 1359134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits 1369134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits 1379134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits 1389134Ssaidi@eecs.umich.edusystem.l2c.demand_hits::total 1317469 # number of demand (read+write) hits 1399134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits 1409134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits 1419134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.inst 421038 # number of overall hits 1429134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu0.data 233339 # number of overall hits 1439134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits 1449134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits 1459134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.inst 430511 # number of overall hits 1469134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::cpu1.data 219723 # number of overall hits 1479134Ssaidi@eecs.umich.edusystem.l2c.overall_hits::total 1317469 # number of overall hits 1489079SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses 1499134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses 1509134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses 1519134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu0.data 6392 # number of ReadReq misses 1529079SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 3 # number of ReadReq misses 1539134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu1.inst 3347 # number of ReadReq misses 1549134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::cpu1.data 5276 # number of ReadReq misses 1559134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_misses::total 22454 # number of ReadReq misses 1569134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::cpu0.data 4932 # number of UpgradeReq misses 1579134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::cpu1.data 4304 # number of UpgradeReq misses 1589134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_misses::total 9236 # number of UpgradeReq misses 1599134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses 1609134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses 1619134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses 1629134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_misses::cpu0.data 92461 # number of ReadExReq misses 1639134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses 1649134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_misses::total 140833 # number of ReadExReq misses 1659079SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses 1669134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses 1679134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses 1689134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu0.data 98853 # number of demand (read+write) misses 1699079SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses 1709134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses 1719134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses 1729134Ssaidi@eecs.umich.edusystem.l2c.demand_misses::total 163287 # number of demand (read+write) misses 1739079SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses 1749134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses 1759134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.inst 7432 # number of overall misses 1769134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu0.data 98853 # number of overall misses 1779079SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses 1789134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu1.inst 3347 # number of overall misses 1799134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::cpu1.data 53648 # number of overall misses 1809134Ssaidi@eecs.umich.edusystem.l2c.overall_misses::total 163287 # number of overall misses 1819134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) 1829134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) 1839134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) 1849134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses) 1859134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses) 1869134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses) 1879134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses) 1889134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses) 1899134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) 1909134Ssaidi@eecs.umich.edusystem.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) 1919134Ssaidi@eecs.umich.edusystem.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) 1929134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses) 1939134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses) 1949134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses) 1959134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) 1969134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) 1979134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) 1989134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses) 1999134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses) 2009134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses) 2019134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses 2029134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses 2039134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses 2049134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses 2059134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses 2069134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses 2079134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses 2089134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses 2099134Ssaidi@eecs.umich.edusystem.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses 2109134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses 2119134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses 2129134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses 2139134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses 2149134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses 2159134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses 2169134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses 2179134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses 2189134Ssaidi@eecs.umich.edusystem.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses 2199134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses 2209134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses 2219134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses 2229134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses 2239134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses 2249134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses 2259134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses 2269134Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses 2279134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses 2289134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses 2299134Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses 2309134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses 2319134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses 2329134Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses 2339134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_rate::cpu0.data 0.613902 # miss rate for ReadExReq accesses 2349134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses 2359134Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_rate::total 0.565150 # miss rate for ReadExReq accesses 2369134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses 2379134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses 2389134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses 2399134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu0.data 0.297578 # miss rate for demand accesses 2409134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses 2419134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses 2429134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses 2439134Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::total 0.110273 # miss rate for demand accesses 2449134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses 2459134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses 2469134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses 2479134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu0.data 0.297578 # miss rate for overall accesses 2489134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses 2499134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses 2509134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses 2519134Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::total 0.110273 # miss rate for overall accesses 2528844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2538844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2548844SAli.Saidi@ARM.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2558844SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 2568983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2578983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2588844SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 2598844SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 2609134Ssaidi@eecs.umich.edusystem.l2c.writebacks::writebacks 65559 # number of writebacks 2619134Ssaidi@eecs.umich.edusystem.l2c.writebacks::total 65559 # number of writebacks 2628844SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2638844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2648844SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2658844SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2668844SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 2678844SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 2688844SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 0 # Number of DMA write transactions. 2698844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 2708844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 2719134Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_hits 7975768 # DTB read hits 2729134Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_misses 3611 # DTB read misses 2739134Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_hits 5966574 # DTB write hits 2749134Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_misses 672 # DTB write misses 2758844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 2768844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2778844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2788844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 2799134Ssaidi@eecs.umich.edusystem.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB 2808844SAli.Saidi@ARM.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2819134Ssaidi@eecs.umich.edusystem.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch 2828844SAli.Saidi@ARM.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2839134Ssaidi@eecs.umich.edusystem.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions 2849134Ssaidi@eecs.umich.edusystem.cpu0.dtb.read_accesses 7979379 # DTB read accesses 2859134Ssaidi@eecs.umich.edusystem.cpu0.dtb.write_accesses 5967246 # DTB write accesses 2868844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 2879134Ssaidi@eecs.umich.edusystem.cpu0.dtb.hits 13942342 # DTB hits 2889134Ssaidi@eecs.umich.edusystem.cpu0.dtb.misses 4283 # DTB misses 2899134Ssaidi@eecs.umich.edusystem.cpu0.dtb.accesses 13946625 # DTB accesses 2909134Ssaidi@eecs.umich.edusystem.cpu0.itb.inst_hits 30238804 # ITB inst hits 2919134Ssaidi@eecs.umich.edusystem.cpu0.itb.inst_misses 2175 # ITB inst misses 2928844SAli.Saidi@ARM.comsystem.cpu0.itb.read_hits 0 # DTB read hits 2938844SAli.Saidi@ARM.comsystem.cpu0.itb.read_misses 0 # DTB read misses 2948844SAli.Saidi@ARM.comsystem.cpu0.itb.write_hits 0 # DTB write hits 2958844SAli.Saidi@ARM.comsystem.cpu0.itb.write_misses 0 # DTB write misses 2968844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 2978844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2988844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2998844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 3009134Ssaidi@eecs.umich.edusystem.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB 3018844SAli.Saidi@ARM.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3028844SAli.Saidi@ARM.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3038844SAli.Saidi@ARM.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3048844SAli.Saidi@ARM.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3058844SAli.Saidi@ARM.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 3068844SAli.Saidi@ARM.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 3079134Ssaidi@eecs.umich.edusystem.cpu0.itb.inst_accesses 30240979 # ITB inst accesses 3089134Ssaidi@eecs.umich.edusystem.cpu0.itb.hits 30238804 # DTB hits 3099134Ssaidi@eecs.umich.edusystem.cpu0.itb.misses 2175 # DTB misses 3109134Ssaidi@eecs.umich.edusystem.cpu0.itb.accesses 30240979 # DTB accesses 3119134Ssaidi@eecs.umich.edusystem.cpu0.numCycles 1823633059 # number of cpu cycles simulated 3128844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 3138844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 3149134Ssaidi@eecs.umich.edusystem.cpu0.committedInsts 29750005 # Number of instructions committed 3159134Ssaidi@eecs.umich.edusystem.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed 3169134Ssaidi@eecs.umich.edusystem.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses 3179134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses 3189134Ssaidi@eecs.umich.edusystem.cpu0.num_func_calls 1241903 # number of times a function call or return occured 3199134Ssaidi@eecs.umich.edusystem.cpu0.num_conditional_control_insts 4025450 # number of instructions that are conditional controls 3209134Ssaidi@eecs.umich.edusystem.cpu0.num_int_insts 34471201 # number of integer instructions 3219134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_insts 5449 # number of float instructions 3229134Ssaidi@eecs.umich.edusystem.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read 3239134Ssaidi@eecs.umich.edusystem.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written 3249134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read 3259134Ssaidi@eecs.umich.edusystem.cpu0.num_fp_register_writes 916 # number of times the floating registers were written 3269134Ssaidi@eecs.umich.edusystem.cpu0.num_mem_refs 14626951 # number of memory refs 3279134Ssaidi@eecs.umich.edusystem.cpu0.num_load_insts 8357226 # Number of load instructions 3289134Ssaidi@eecs.umich.edusystem.cpu0.num_store_insts 6269725 # Number of store instructions 3299134Ssaidi@eecs.umich.edusystem.cpu0.num_idle_cycles 1783968822.941743 # Number of idle cycles 3309134Ssaidi@eecs.umich.edusystem.cpu0.num_busy_cycles 39664236.058257 # Number of busy cycles 3319134Ssaidi@eecs.umich.edusystem.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles 3329134Ssaidi@eecs.umich.edusystem.cpu0.idle_fraction 0.978250 # Percentage of idle cycles 3338844SAli.Saidi@ARM.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 3349134Ssaidi@eecs.umich.edusystem.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed 3359134Ssaidi@eecs.umich.edusystem.cpu0.icache.replacements 428547 # number of replacements 3369134Ssaidi@eecs.umich.edusystem.cpu0.icache.tagsinuse 511.020000 # Cycle average of tags in use 3379134Ssaidi@eecs.umich.edusystem.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks. 3389134Ssaidi@eecs.umich.edusystem.cpu0.icache.sampled_refs 429059 # Sample count of references to valid blocks. 3399134Ssaidi@eecs.umich.edusystem.cpu0.icache.avg_refs 69.480223 # Average number of references to valid blocks. 3409134Ssaidi@eecs.umich.edusystem.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. 3419134Ssaidi@eecs.umich.edusystem.cpu0.icache.occ_blocks::cpu0.inst 511.020000 # Average occupied blocks per requestor 3429134Ssaidi@eecs.umich.edusystem.cpu0.icache.occ_percent::cpu0.inst 0.998086 # Average percentage of cache occupancy 3439134Ssaidi@eecs.umich.edusystem.cpu0.icache.occ_percent::total 0.998086 # Average percentage of cache occupancy 3449134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits 3459134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits 3469134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits 3479134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits 3489134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits 3499134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_hits::total 29811115 # number of overall hits 3509134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses 3519134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses 3529134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses 3539134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses 3549134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses 3559134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_misses::total 429059 # number of overall misses 3569134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses) 3579134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses) 3589134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses 3599134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses 3609134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses 3619134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses 3629134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses 3639134Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses 3649134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses 3659134Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses 3669134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses 3679134Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses 3688844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3698844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3708844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3718844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 3728983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3738983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3748844SAli.Saidi@ARM.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 3758844SAli.Saidi@ARM.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 3768844SAli.Saidi@ARM.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3779134Ssaidi@eecs.umich.edusystem.cpu0.dcache.replacements 323609 # number of replacements 3789134Ssaidi@eecs.umich.edusystem.cpu0.dcache.tagsinuse 494.763091 # Cycle average of tags in use 3799134Ssaidi@eecs.umich.edusystem.cpu0.dcache.total_refs 12467604 # Total number of references to valid blocks. 3809134Ssaidi@eecs.umich.edusystem.cpu0.dcache.sampled_refs 323981 # Sample count of references to valid blocks. 3819134Ssaidi@eecs.umich.edusystem.cpu0.dcache.avg_refs 38.482516 # Average number of references to valid blocks. 3828844SAli.Saidi@ARM.comsystem.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. 3839134Ssaidi@eecs.umich.edusystem.cpu0.dcache.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor 3849134Ssaidi@eecs.umich.edusystem.cpu0.dcache.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy 3859134Ssaidi@eecs.umich.edusystem.cpu0.dcache.occ_percent::total 0.966334 # Average percentage of cache occupancy 3869134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits 3879134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits 3889134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits 3899134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits 3909134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits 3919134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits 3929134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits 3939134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits 3949134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits 3959134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits 3969134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits 3979134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_hits::total 12143186 # number of overall hits 3989134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses 3999134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses 4009134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses 4019134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses 4029134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses 4039134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses 4049134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 7469 # number of StoreCondReq misses 4059134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_misses::total 7469 # number of StoreCondReq misses 4069134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses 4079134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses 4089134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses 4099134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_misses::total 364509 # number of overall misses 4109134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses) 4119134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses) 4129134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses) 4139134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) 4149134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) 4159134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) 4169134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160649 # number of StoreCondReq accesses(hits+misses) 4179134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_accesses::total 160649 # number of StoreCondReq accesses(hits+misses) 4189134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses 4199134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses 4209134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses 4219134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses 4229134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses 4239134Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses 4249134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses 4259134Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses 4269134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses 4279134Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses 4289134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046493 # miss rate for StoreCondReq accesses 4299134Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.046493 # miss rate for StoreCondReq accesses 4309134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses 4319134Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses 4329134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses 4339134Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses 4348844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4358844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4368844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4378844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 4388983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4398983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4408844SAli.Saidi@ARM.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 4418844SAli.Saidi@ARM.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 4429134Ssaidi@eecs.umich.edusystem.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks 4439134Ssaidi@eecs.umich.edusystem.cpu0.dcache.writebacks::total 300958 # number of writebacks 4448844SAli.Saidi@ARM.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4458844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 4468844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 4479134Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_hits 7364781 # DTB read hits 4489134Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_misses 3705 # DTB read misses 4499134Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_hits 5489656 # DTB write hits 4509134Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_misses 1595 # DTB write misses 4518844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 4528844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4538844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 4548844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 4559134Ssaidi@eecs.umich.edusystem.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB 4568844SAli.Saidi@ARM.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 4579134Ssaidi@eecs.umich.edusystem.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch 4588844SAli.Saidi@ARM.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 4599134Ssaidi@eecs.umich.edusystem.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions 4609134Ssaidi@eecs.umich.edusystem.cpu1.dtb.read_accesses 7368486 # DTB read accesses 4619134Ssaidi@eecs.umich.edusystem.cpu1.dtb.write_accesses 5491251 # DTB write accesses 4628844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 4639134Ssaidi@eecs.umich.edusystem.cpu1.dtb.hits 12854437 # DTB hits 4649134Ssaidi@eecs.umich.edusystem.cpu1.dtb.misses 5300 # DTB misses 4659134Ssaidi@eecs.umich.edusystem.cpu1.dtb.accesses 12859737 # DTB accesses 4669134Ssaidi@eecs.umich.edusystem.cpu1.itb.inst_hits 32412306 # ITB inst hits 4679134Ssaidi@eecs.umich.edusystem.cpu1.itb.inst_misses 2200 # ITB inst misses 4688844SAli.Saidi@ARM.comsystem.cpu1.itb.read_hits 0 # DTB read hits 4698844SAli.Saidi@ARM.comsystem.cpu1.itb.read_misses 0 # DTB read misses 4708844SAli.Saidi@ARM.comsystem.cpu1.itb.write_hits 0 # DTB write hits 4718844SAli.Saidi@ARM.comsystem.cpu1.itb.write_misses 0 # DTB write misses 4728844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 4738844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4748844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 4758844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 4769134Ssaidi@eecs.umich.edusystem.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB 4778844SAli.Saidi@ARM.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4788844SAli.Saidi@ARM.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4798844SAli.Saidi@ARM.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4808844SAli.Saidi@ARM.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4818844SAli.Saidi@ARM.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 4828844SAli.Saidi@ARM.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 4839134Ssaidi@eecs.umich.edusystem.cpu1.itb.inst_accesses 32414506 # ITB inst accesses 4849134Ssaidi@eecs.umich.edusystem.cpu1.itb.hits 32412306 # DTB hits 4859134Ssaidi@eecs.umich.edusystem.cpu1.itb.misses 2200 # DTB misses 4869134Ssaidi@eecs.umich.edusystem.cpu1.itb.accesses 32414506 # DTB accesses 4879134Ssaidi@eecs.umich.edusystem.cpu1.numCycles 1824154149 # number of cpu cycles simulated 4888844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 4898844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 4909134Ssaidi@eecs.umich.edusystem.cpu1.committedInsts 31875965 # Number of instructions committed 4919134Ssaidi@eecs.umich.edusystem.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed 4929134Ssaidi@eecs.umich.edusystem.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses 4939134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses 4949134Ssaidi@eecs.umich.edusystem.cpu1.num_func_calls 955227 # number of times a function call or return occured 4959134Ssaidi@eecs.umich.edusystem.cpu1.num_conditional_control_insts 4028429 # number of instructions that are conditional controls 4969134Ssaidi@eecs.umich.edusystem.cpu1.num_int_insts 35797832 # number of integer instructions 4979134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_insts 4436 # number of float instructions 4989134Ssaidi@eecs.umich.edusystem.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read 4999134Ssaidi@eecs.umich.edusystem.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written 5009134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read 5019134Ssaidi@eecs.umich.edusystem.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written 5029134Ssaidi@eecs.umich.edusystem.cpu1.num_mem_refs 13370713 # number of memory refs 5039134Ssaidi@eecs.umich.edusystem.cpu1.num_load_insts 7642673 # Number of load instructions 5049134Ssaidi@eecs.umich.edusystem.cpu1.num_store_insts 5728040 # Number of store instructions 5059134Ssaidi@eecs.umich.edusystem.cpu1.num_idle_cycles 1783362859.317266 # Number of idle cycles 5069134Ssaidi@eecs.umich.edusystem.cpu1.num_busy_cycles 40791289.682734 # Number of busy cycles 5079134Ssaidi@eecs.umich.edusystem.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles 5089134Ssaidi@eecs.umich.edusystem.cpu1.idle_fraction 0.977638 # Percentage of idle cycles 5098844SAli.Saidi@ARM.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 5109134Ssaidi@eecs.umich.edusystem.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed 5119134Ssaidi@eecs.umich.edusystem.cpu1.icache.replacements 433942 # number of replacements 5129134Ssaidi@eecs.umich.edusystem.cpu1.icache.tagsinuse 475.447912 # Cycle average of tags in use 5139134Ssaidi@eecs.umich.edusystem.cpu1.icache.total_refs 31979125 # Total number of references to valid blocks. 5149134Ssaidi@eecs.umich.edusystem.cpu1.icache.sampled_refs 434454 # Sample count of references to valid blocks. 5159134Ssaidi@eecs.umich.edusystem.cpu1.icache.avg_refs 73.607620 # Average number of references to valid blocks. 5169134Ssaidi@eecs.umich.edusystem.cpu1.icache.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. 5179134Ssaidi@eecs.umich.edusystem.cpu1.icache.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor 5189134Ssaidi@eecs.umich.edusystem.cpu1.icache.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy 5199134Ssaidi@eecs.umich.edusystem.cpu1.icache.occ_percent::total 0.928609 # Average percentage of cache occupancy 5209134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits 5219134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits 5229134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits 5239134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits 5249134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits 5259134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_hits::total 31979125 # number of overall hits 5269134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses 5279134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses 5289134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses 5299134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses 5309134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses 5319134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_misses::total 434454 # number of overall misses 5329134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses) 5339134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses) 5349134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses 5359134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses 5369134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses 5379134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses 5389134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses 5399134Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses 5409134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses 5419134Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses 5429134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses 5439134Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses 5448844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5458844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5468844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 5478844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 5488983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5498983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5508844SAli.Saidi@ARM.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 5518844SAli.Saidi@ARM.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 5528844SAli.Saidi@ARM.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5539134Ssaidi@eecs.umich.edusystem.cpu1.dcache.replacements 294289 # number of replacements 5549134Ssaidi@eecs.umich.edusystem.cpu1.dcache.tagsinuse 447.573682 # Cycle average of tags in use 5559134Ssaidi@eecs.umich.edusystem.cpu1.dcache.total_refs 11707745 # Total number of references to valid blocks. 5569134Ssaidi@eecs.umich.edusystem.cpu1.dcache.sampled_refs 294801 # Sample count of references to valid blocks. 5579134Ssaidi@eecs.umich.edusystem.cpu1.dcache.avg_refs 39.714061 # Average number of references to valid blocks. 5589134Ssaidi@eecs.umich.edusystem.cpu1.dcache.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. 5599134Ssaidi@eecs.umich.edusystem.cpu1.dcache.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor 5609134Ssaidi@eecs.umich.edusystem.cpu1.dcache.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy 5619134Ssaidi@eecs.umich.edusystem.cpu1.dcache.occ_percent::total 0.874167 # Average percentage of cache occupancy 5629134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits 5639134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits 5649134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits 5659134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits 5669134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits 5679134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits 5689134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits 5699134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits 5709134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits 5719134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits 5729134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits 5739134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_hits::total 11522522 # number of overall hits 5749134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses 5759134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses 5769134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses 5779134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses 5789134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses 5799134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses 5809134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 10139 # number of StoreCondReq misses 5819134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_misses::total 10139 # number of StoreCondReq misses 5829134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses 5839134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses 5849134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses 5859134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_misses::total 324195 # number of overall misses 5869134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses) 5879134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses) 5889134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses) 5899134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) 5909134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) 5919134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) 5929134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89169 # number of StoreCondReq accesses(hits+misses) 5939134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_accesses::total 89169 # number of StoreCondReq accesses(hits+misses) 5949134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses 5959134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses 5969134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses 5979134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses 5989134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses 5999134Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses 6009134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses 6019134Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses 6029134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses 6039134Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses 6049134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113705 # miss rate for StoreCondReq accesses 6059134Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.113705 # miss rate for StoreCondReq accesses 6069134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses 6079134Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses 6089134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses 6099134Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses 6108844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6118844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6128844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 6138844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 6148983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6158983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6168844SAli.Saidi@ARM.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 6178844SAli.Saidi@ARM.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 6189134Ssaidi@eecs.umich.edusystem.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks 6199134Ssaidi@eecs.umich.edusystem.cpu1.dcache.writebacks::total 266849 # number of writebacks 6208844SAli.Saidi@ARM.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 6218844SAli.Saidi@ARM.comsystem.iocache.replacements 0 # number of replacements 6228844SAli.Saidi@ARM.comsystem.iocache.tagsinuse 0 # Cycle average of tags in use 6238844SAli.Saidi@ARM.comsystem.iocache.total_refs 0 # Total number of references to valid blocks. 6248844SAli.Saidi@ARM.comsystem.iocache.sampled_refs 0 # Sample count of references to valid blocks. 6258983Snate@binkert.orgsystem.iocache.avg_refs nan # Average number of references to valid blocks. 6268844SAli.Saidi@ARM.comsystem.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6278844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6288844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6298844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 6308844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 6318983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6328983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6338844SAli.Saidi@ARM.comsystem.iocache.fast_writes 0 # number of fast writes performed 6348844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 6358844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 6368844SAli.Saidi@ARM.com 6378844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 638