stats.txt revision 9055
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 39005SAli.Saidi@ARM.comsim_seconds 0.911654 # Number of seconds simulated 49005SAli.Saidi@ARM.comsim_ticks 911653589000 # Number of ticks simulated 59005SAli.Saidi@ARM.comfinal_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 79055Ssaidi@eecs.umich.eduhost_inst_rate 1520101 # Simulator instruction rate (inst/s) 89055Ssaidi@eecs.umich.eduhost_op_rate 1964640 # Simulator op (including micro ops) rate (op/s) 99055Ssaidi@eecs.umich.eduhost_tick_rate 22862175544 # Simulator tick rate (ticks/s) 109055Ssaidi@eecs.umich.eduhost_mem_usage 382804 # Number of bytes of host memory used 119055Ssaidi@eecs.umich.eduhost_seconds 39.88 # Real time elapsed on the host 129005SAli.Saidi@ARM.comsim_insts 60615585 # Number of instructions simulated 139005SAli.Saidi@ARM.comsim_ops 78342060 # Number of ops (including micro ops) simulated 149055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 159055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 169055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 179055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 189055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 199055Ssaidi@eecs.umich.edusystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 209055Ssaidi@eecs.umich.edusystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 219055Ssaidi@eecs.umich.edusystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 229055Ssaidi@eecs.umich.edusystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 239055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) 249055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) 259055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) 269055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) 279055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) 289055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) 299055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) 309055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) 319055Ssaidi@eecs.umich.edusystem.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) 329055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory 339055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory 349055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory 359055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.inst 661924 # Number of bytes read from this memory 369055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu0.data 6760756 # Number of bytes read from this memory 379055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.dtb.walker 1024 # Number of bytes read from this memory 389055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.itb.walker 1152 # Number of bytes read from this memory 399055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.inst 341852 # Number of bytes read from this memory 409055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::cpu1.data 3873968 # Number of bytes read from this memory 419055Ssaidi@eecs.umich.edusystem.physmem.bytes_read::total 50963556 # Number of bytes read from this memory 429055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu0.inst 661924 # Number of instructions bytes read from this memory 439055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::cpu1.inst 341852 # Number of instructions bytes read from this memory 449055Ssaidi@eecs.umich.edusystem.physmem.bytes_inst_read::total 1003776 # Number of instructions bytes read from this memory 459055Ssaidi@eecs.umich.edusystem.physmem.bytes_written::writebacks 7197696 # Number of bytes written to this memory 469055Ssaidi@eecs.umich.edusystem.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory 479055Ssaidi@eecs.umich.edusystem.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory 489055Ssaidi@eecs.umich.edusystem.physmem.bytes_written::total 10224784 # Number of bytes written to this memory 499055Ssaidi@eecs.umich.edusystem.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory 509055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory 519055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory 529055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.inst 16561 # Number of read requests responded to by this memory 539055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu0.data 105709 # Number of read requests responded to by this memory 549055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.dtb.walker 16 # Number of read requests responded to by this memory 559055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.itb.walker 18 # Number of read requests responded to by this memory 569055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.inst 5423 # Number of read requests responded to by this memory 579055Ssaidi@eecs.umich.edusystem.physmem.num_reads::cpu1.data 60557 # Number of read requests responded to by this memory 589055Ssaidi@eecs.umich.edusystem.physmem.num_reads::total 5103504 # Number of read requests responded to by this memory 599055Ssaidi@eecs.umich.edusystem.physmem.num_writes::writebacks 112464 # Number of write requests responded to by this memory 609055Ssaidi@eecs.umich.edusystem.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory 619055Ssaidi@eecs.umich.edusystem.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory 629055Ssaidi@eecs.umich.edusystem.physmem.num_writes::total 869236 # Number of write requests responded to by this memory 639055Ssaidi@eecs.umich.edusystem.physmem.bw_read::realview.clcd 43132173 # Total read bandwidth from this memory (bytes/s) 649055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.dtb.walker 842 # Total read bandwidth from this memory (bytes/s) 659055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.itb.walker 562 # Total read bandwidth from this memory (bytes/s) 669055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.inst 726070 # Total read bandwidth from this memory (bytes/s) 679055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu0.data 7415926 # Total read bandwidth from this memory (bytes/s) 689055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.dtb.walker 1123 # Total read bandwidth from this memory (bytes/s) 699055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) 709055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.inst 374980 # Total read bandwidth from this memory (bytes/s) 719055Ssaidi@eecs.umich.edusystem.physmem.bw_read::cpu1.data 4249386 # Total read bandwidth from this memory (bytes/s) 729055Ssaidi@eecs.umich.edusystem.physmem.bw_read::total 55902326 # Total read bandwidth from this memory (bytes/s) 739055Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu0.inst 726070 # Instruction read bandwidth from this memory (bytes/s) 749055Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::cpu1.inst 374980 # Instruction read bandwidth from this memory (bytes/s) 759055Ssaidi@eecs.umich.edusystem.physmem.bw_inst_read::total 1101050 # Instruction read bandwidth from this memory (bytes/s) 769055Ssaidi@eecs.umich.edusystem.physmem.bw_write::writebacks 7895209 # Write bandwidth from this memory (bytes/s) 779055Ssaidi@eecs.umich.edusystem.physmem.bw_write::cpu0.data 18647 # Write bandwidth from this memory (bytes/s) 789055Ssaidi@eecs.umich.edusystem.physmem.bw_write::cpu1.data 3301789 # Write bandwidth from this memory (bytes/s) 799055Ssaidi@eecs.umich.edusystem.physmem.bw_write::total 11215646 # Write bandwidth from this memory (bytes/s) 809055Ssaidi@eecs.umich.edusystem.physmem.bw_total::writebacks 7895209 # Total bandwidth to/from this memory (bytes/s) 819055Ssaidi@eecs.umich.edusystem.physmem.bw_total::realview.clcd 43132173 # Total bandwidth to/from this memory (bytes/s) 829055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.dtb.walker 842 # Total bandwidth to/from this memory (bytes/s) 839055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.itb.walker 562 # Total bandwidth to/from this memory (bytes/s) 849055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.inst 726070 # Total bandwidth to/from this memory (bytes/s) 859055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu0.data 7434574 # Total bandwidth to/from this memory (bytes/s) 869055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.dtb.walker 1123 # Total bandwidth to/from this memory (bytes/s) 879055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) 889055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.inst 374980 # Total bandwidth to/from this memory (bytes/s) 899055Ssaidi@eecs.umich.edusystem.physmem.bw_total::cpu1.data 7551175 # Total bandwidth to/from this memory (bytes/s) 909055Ssaidi@eecs.umich.edusystem.physmem.bw_total::total 67117972 # Total bandwidth to/from this memory (bytes/s) 919005SAli.Saidi@ARM.comsystem.l2c.replacements 127935 # number of replacements 929005SAli.Saidi@ARM.comsystem.l2c.tagsinuse 26245.835103 # Cycle average of tags in use 939005SAli.Saidi@ARM.comsystem.l2c.total_refs 1477463 # Total number of references to valid blocks. 949005SAli.Saidi@ARM.comsystem.l2c.sampled_refs 156884 # Sample count of references to valid blocks. 959005SAli.Saidi@ARM.comsystem.l2c.avg_refs 9.417551 # Average number of references to valid blocks. 968844SAli.Saidi@ARM.comsystem.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 979005SAli.Saidi@ARM.comsystem.l2c.occ_blocks::writebacks 16687.001530 # Average occupied blocks per requestor 989005SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu0.dtb.walker 1.397314 # Average occupied blocks per requestor 999005SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu0.itb.walker 0.122168 # Average occupied blocks per requestor 1009005SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu0.inst 2780.380300 # Average occupied blocks per requestor 1019005SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu0.data 1123.317941 # Average occupied blocks per requestor 1029005SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu1.dtb.walker 4.426009 # Average occupied blocks per requestor 1039005SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu1.itb.walker 0.092136 # Average occupied blocks per requestor 1049005SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu1.inst 1942.464102 # Average occupied blocks per requestor 1059005SAli.Saidi@ARM.comsystem.l2c.occ_blocks::cpu1.data 3706.633603 # Average occupied blocks per requestor 1069005SAli.Saidi@ARM.comsystem.l2c.occ_percent::writebacks 0.254623 # Average percentage of cache occupancy 1079005SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu0.dtb.walker 0.000021 # Average percentage of cache occupancy 1089005SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy 1099005SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu0.inst 0.042425 # Average percentage of cache occupancy 1109005SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu0.data 0.017140 # Average percentage of cache occupancy 1119005SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu1.dtb.walker 0.000068 # Average percentage of cache occupancy 1129005SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu1.itb.walker 0.000001 # Average percentage of cache occupancy 1139005SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu1.inst 0.029640 # Average percentage of cache occupancy 1149005SAli.Saidi@ARM.comsystem.l2c.occ_percent::cpu1.data 0.056559 # Average percentage of cache occupancy 1159005SAli.Saidi@ARM.comsystem.l2c.occ_percent::total 0.400480 # Average percentage of cache occupancy 1169005SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 5294 # number of ReadReq hits 1179005SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 2199 # number of ReadReq hits 1189005SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.inst 485527 # number of ReadReq hits 1199005SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu0.data 213776 # number of ReadReq hits 1209005SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 4291 # number of ReadReq hits 1219005SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 1552 # number of ReadReq hits 1229005SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.inst 359854 # number of ReadReq hits 1239005SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::cpu1.data 128180 # number of ReadReq hits 1249005SAli.Saidi@ARM.comsystem.l2c.ReadReq_hits::total 1200673 # number of ReadReq hits 1259005SAli.Saidi@ARM.comsystem.l2c.Writeback_hits::writebacks 578200 # number of Writeback hits 1269005SAli.Saidi@ARM.comsystem.l2c.Writeback_hits::total 578200 # number of Writeback hits 1279005SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_hits::cpu0.data 835 # number of UpgradeReq hits 1289005SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_hits::cpu1.data 757 # number of UpgradeReq hits 1299005SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_hits::total 1592 # number of UpgradeReq hits 1309005SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 134 # number of SCUpgradeReq hits 1319005SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 214 # number of SCUpgradeReq hits 1329005SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_hits::total 348 # number of SCUpgradeReq hits 1339005SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::cpu0.data 68011 # number of ReadExReq hits 1349005SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::cpu1.data 33233 # number of ReadExReq hits 1359005SAli.Saidi@ARM.comsystem.l2c.ReadExReq_hits::total 101244 # number of ReadExReq hits 1369005SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.dtb.walker 5294 # number of demand (read+write) hits 1379005SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.itb.walker 2199 # number of demand (read+write) hits 1389005SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.inst 485527 # number of demand (read+write) hits 1399005SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu0.data 281787 # number of demand (read+write) hits 1409005SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.dtb.walker 4291 # number of demand (read+write) hits 1419005SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.itb.walker 1552 # number of demand (read+write) hits 1429005SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.inst 359854 # number of demand (read+write) hits 1439005SAli.Saidi@ARM.comsystem.l2c.demand_hits::cpu1.data 161413 # number of demand (read+write) hits 1449005SAli.Saidi@ARM.comsystem.l2c.demand_hits::total 1301917 # number of demand (read+write) hits 1459005SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.dtb.walker 5294 # number of overall hits 1469005SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.itb.walker 2199 # number of overall hits 1479005SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.inst 485527 # number of overall hits 1489005SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu0.data 281787 # number of overall hits 1499005SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.dtb.walker 4291 # number of overall hits 1509005SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.itb.walker 1552 # number of overall hits 1519005SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.inst 359854 # number of overall hits 1529005SAli.Saidi@ARM.comsystem.l2c.overall_hits::cpu1.data 161413 # number of overall hits 1539005SAli.Saidi@ARM.comsystem.l2c.overall_hits::total 1301917 # number of overall hits 1549005SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses 1559005SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses 1569005SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.inst 9928 # number of ReadReq misses 1579005SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu0.data 9109 # number of ReadReq misses 1589005SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 16 # number of ReadReq misses 1599005SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.itb.walker 18 # number of ReadReq misses 1609005SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.inst 5336 # number of ReadReq misses 1619005SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::cpu1.data 10106 # number of ReadReq misses 1629005SAli.Saidi@ARM.comsystem.l2c.ReadReq_misses::total 34533 # number of ReadReq misses 1639005SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::cpu0.data 6262 # number of UpgradeReq misses 1649005SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::cpu1.data 3142 # number of UpgradeReq misses 1659005SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_misses::total 9404 # number of UpgradeReq misses 1669005SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 731 # number of SCUpgradeReq misses 1679005SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 408 # number of SCUpgradeReq misses 1689005SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_misses::total 1139 # number of SCUpgradeReq misses 1699005SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::cpu0.data 98092 # number of ReadExReq misses 1709005SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::cpu1.data 50861 # number of ReadExReq misses 1719005SAli.Saidi@ARM.comsystem.l2c.ReadExReq_misses::total 148953 # number of ReadExReq misses 1729005SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses 1739005SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses 1749005SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.inst 9928 # number of demand (read+write) misses 1759005SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu0.data 107201 # number of demand (read+write) misses 1769005SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.dtb.walker 16 # number of demand (read+write) misses 1779005SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.itb.walker 18 # number of demand (read+write) misses 1789005SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.inst 5336 # number of demand (read+write) misses 1799005SAli.Saidi@ARM.comsystem.l2c.demand_misses::cpu1.data 60967 # number of demand (read+write) misses 1809005SAli.Saidi@ARM.comsystem.l2c.demand_misses::total 183486 # number of demand (read+write) misses 1819005SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses 1829005SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses 1839005SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.inst 9928 # number of overall misses 1849005SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu0.data 107201 # number of overall misses 1859005SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.dtb.walker 16 # number of overall misses 1869005SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.itb.walker 18 # number of overall misses 1879005SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.inst 5336 # number of overall misses 1889005SAli.Saidi@ARM.comsystem.l2c.overall_misses::cpu1.data 60967 # number of overall misses 1899005SAli.Saidi@ARM.comsystem.l2c.overall_misses::total 183486 # number of overall misses 1909005SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 5306 # number of ReadReq accesses(hits+misses) 1919005SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 2207 # number of ReadReq accesses(hits+misses) 1929005SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.inst 495455 # number of ReadReq accesses(hits+misses) 1939005SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu0.data 222885 # number of ReadReq accesses(hits+misses) 1949005SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 4307 # number of ReadReq accesses(hits+misses) 1959005SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 1570 # number of ReadReq accesses(hits+misses) 1969005SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.inst 365190 # number of ReadReq accesses(hits+misses) 1979005SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::cpu1.data 138286 # number of ReadReq accesses(hits+misses) 1989005SAli.Saidi@ARM.comsystem.l2c.ReadReq_accesses::total 1235206 # number of ReadReq accesses(hits+misses) 1999005SAli.Saidi@ARM.comsystem.l2c.Writeback_accesses::writebacks 578200 # number of Writeback accesses(hits+misses) 2009005SAli.Saidi@ARM.comsystem.l2c.Writeback_accesses::total 578200 # number of Writeback accesses(hits+misses) 2019005SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::cpu0.data 7097 # number of UpgradeReq accesses(hits+misses) 2029005SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3899 # number of UpgradeReq accesses(hits+misses) 2039005SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_accesses::total 10996 # number of UpgradeReq accesses(hits+misses) 2049005SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 865 # number of SCUpgradeReq accesses(hits+misses) 2059005SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 622 # number of SCUpgradeReq accesses(hits+misses) 2069005SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_accesses::total 1487 # number of SCUpgradeReq accesses(hits+misses) 2079005SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses::cpu0.data 166103 # number of ReadExReq accesses(hits+misses) 2089005SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses::cpu1.data 84094 # number of ReadExReq accesses(hits+misses) 2099005SAli.Saidi@ARM.comsystem.l2c.ReadExReq_accesses::total 250197 # number of ReadExReq accesses(hits+misses) 2109005SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.dtb.walker 5306 # number of demand (read+write) accesses 2119005SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.itb.walker 2207 # number of demand (read+write) accesses 2129005SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.inst 495455 # number of demand (read+write) accesses 2139005SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu0.data 388988 # number of demand (read+write) accesses 2149005SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.dtb.walker 4307 # number of demand (read+write) accesses 2159005SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.itb.walker 1570 # number of demand (read+write) accesses 2169005SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.inst 365190 # number of demand (read+write) accesses 2179005SAli.Saidi@ARM.comsystem.l2c.demand_accesses::cpu1.data 222380 # number of demand (read+write) accesses 2189005SAli.Saidi@ARM.comsystem.l2c.demand_accesses::total 1485403 # number of demand (read+write) accesses 2199005SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.dtb.walker 5306 # number of overall (read+write) accesses 2209005SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.itb.walker 2207 # number of overall (read+write) accesses 2219005SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.inst 495455 # number of overall (read+write) accesses 2229005SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.data 388988 # number of overall (read+write) accesses 2239005SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.dtb.walker 4307 # number of overall (read+write) accesses 2249005SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.itb.walker 1570 # number of overall (read+write) accesses 2259005SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.inst 365190 # number of overall (read+write) accesses 2269005SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu1.data 222380 # number of overall (read+write) accesses 2279005SAli.Saidi@ARM.comsystem.l2c.overall_accesses::total 1485403 # number of overall (read+write) accesses 2289005SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for ReadReq accesses 2299005SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.003625 # miss rate for ReadReq accesses 2309005SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.020038 # miss rate for ReadReq accesses 2319005SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.040869 # miss rate for ReadReq accesses 2329005SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for ReadReq accesses 2339005SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011465 # miss rate for ReadReq accesses 2349005SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.014612 # miss rate for ReadReq accesses 2359005SAli.Saidi@ARM.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.073080 # miss rate for ReadReq accesses 2369055Ssaidi@eecs.umich.edusystem.l2c.ReadReq_miss_rate::total 0.027957 # miss rate for ReadReq accesses 2379005SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.882345 # miss rate for UpgradeReq accesses 2389005SAli.Saidi@ARM.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.805848 # miss rate for UpgradeReq accesses 2399055Ssaidi@eecs.umich.edusystem.l2c.UpgradeReq_miss_rate::total 0.855220 # miss rate for UpgradeReq accesses 2409005SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.845087 # miss rate for SCUpgradeReq accesses 2419005SAli.Saidi@ARM.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.655949 # miss rate for SCUpgradeReq accesses 2429055Ssaidi@eecs.umich.edusystem.l2c.SCUpgradeReq_miss_rate::total 0.765972 # miss rate for SCUpgradeReq accesses 2439005SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.590549 # miss rate for ReadExReq accesses 2449005SAli.Saidi@ARM.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.604811 # miss rate for ReadExReq accesses 2459055Ssaidi@eecs.umich.edusystem.l2c.ReadExReq_miss_rate::total 0.595343 # miss rate for ReadExReq accesses 2469005SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for demand accesses 2479005SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.003625 # miss rate for demand accesses 2489005SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.inst 0.020038 # miss rate for demand accesses 2499005SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu0.data 0.275589 # miss rate for demand accesses 2509005SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for demand accesses 2519005SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.011465 # miss rate for demand accesses 2529005SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu1.inst 0.014612 # miss rate for demand accesses 2539005SAli.Saidi@ARM.comsystem.l2c.demand_miss_rate::cpu1.data 0.274157 # miss rate for demand accesses 2549055Ssaidi@eecs.umich.edusystem.l2c.demand_miss_rate::total 0.123526 # miss rate for demand accesses 2559005SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.002262 # miss rate for overall accesses 2569005SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.003625 # miss rate for overall accesses 2579005SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.inst 0.020038 # miss rate for overall accesses 2589005SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu0.data 0.275589 # miss rate for overall accesses 2599005SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.003715 # miss rate for overall accesses 2609005SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.011465 # miss rate for overall accesses 2619005SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu1.inst 0.014612 # miss rate for overall accesses 2629005SAli.Saidi@ARM.comsystem.l2c.overall_miss_rate::cpu1.data 0.274157 # miss rate for overall accesses 2639055Ssaidi@eecs.umich.edusystem.l2c.overall_miss_rate::total 0.123526 # miss rate for overall accesses 2648844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2658844SAli.Saidi@ARM.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2668844SAli.Saidi@ARM.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 2678844SAli.Saidi@ARM.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 2688983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2698983Snate@binkert.orgsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2708844SAli.Saidi@ARM.comsystem.l2c.fast_writes 0 # number of fast writes performed 2718844SAli.Saidi@ARM.comsystem.l2c.cache_copies 0 # number of cache copies performed 2729005SAli.Saidi@ARM.comsystem.l2c.writebacks::writebacks 112464 # number of writebacks 2739005SAli.Saidi@ARM.comsystem.l2c.writebacks::total 112464 # number of writebacks 2748844SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 2758844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 2768844SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 2778844SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). 2788844SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. 2798844SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. 2808844SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 0 # Number of DMA write transactions. 2818844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 2828844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 2839005SAli.Saidi@ARM.comsystem.cpu0.dtb.read_hits 9312139 # DTB read hits 2849005SAli.Saidi@ARM.comsystem.cpu0.dtb.read_misses 5476 # DTB read misses 2859005SAli.Saidi@ARM.comsystem.cpu0.dtb.write_hits 6895585 # DTB write hits 2869005SAli.Saidi@ARM.comsystem.cpu0.dtb.write_misses 1137 # DTB write misses 2878844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed 2888844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 2898844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 2908844SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 2919005SAli.Saidi@ARM.comsystem.cpu0.dtb.flush_entries 2449 # Number of entries that have been flushed from TLB 2928844SAli.Saidi@ARM.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 2939005SAli.Saidi@ARM.comsystem.cpu0.dtb.prefetch_faults 187 # Number of TLB faults due to prefetch 2948844SAli.Saidi@ARM.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 2959005SAli.Saidi@ARM.comsystem.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions 2969005SAli.Saidi@ARM.comsystem.cpu0.dtb.read_accesses 9317615 # DTB read accesses 2979005SAli.Saidi@ARM.comsystem.cpu0.dtb.write_accesses 6896722 # DTB write accesses 2988844SAli.Saidi@ARM.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 2999005SAli.Saidi@ARM.comsystem.cpu0.dtb.hits 16207724 # DTB hits 3009005SAli.Saidi@ARM.comsystem.cpu0.dtb.misses 6613 # DTB misses 3019005SAli.Saidi@ARM.comsystem.cpu0.dtb.accesses 16214337 # DTB accesses 3029005SAli.Saidi@ARM.comsystem.cpu0.itb.inst_hits 34683994 # ITB inst hits 3039005SAli.Saidi@ARM.comsystem.cpu0.itb.inst_misses 3170 # ITB inst misses 3048844SAli.Saidi@ARM.comsystem.cpu0.itb.read_hits 0 # DTB read hits 3058844SAli.Saidi@ARM.comsystem.cpu0.itb.read_misses 0 # DTB read misses 3068844SAli.Saidi@ARM.comsystem.cpu0.itb.write_hits 0 # DTB write hits 3078844SAli.Saidi@ARM.comsystem.cpu0.itb.write_misses 0 # DTB write misses 3088844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed 3098844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 3108844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 3118844SAli.Saidi@ARM.comsystem.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 3129005SAli.Saidi@ARM.comsystem.cpu0.itb.flush_entries 1558 # Number of entries that have been flushed from TLB 3138844SAli.Saidi@ARM.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 3148844SAli.Saidi@ARM.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 3158844SAli.Saidi@ARM.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 3168844SAli.Saidi@ARM.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 3178844SAli.Saidi@ARM.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 3188844SAli.Saidi@ARM.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 3199005SAli.Saidi@ARM.comsystem.cpu0.itb.inst_accesses 34687164 # ITB inst accesses 3209005SAli.Saidi@ARM.comsystem.cpu0.itb.hits 34683994 # DTB hits 3219005SAli.Saidi@ARM.comsystem.cpu0.itb.misses 3170 # DTB misses 3229005SAli.Saidi@ARM.comsystem.cpu0.itb.accesses 34687164 # DTB accesses 3239005SAli.Saidi@ARM.comsystem.cpu0.numCycles 1823259919 # number of cpu cycles simulated 3248844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 3258844SAli.Saidi@ARM.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 3269005SAli.Saidi@ARM.comsystem.cpu0.committedInsts 33900598 # Number of instructions committed 3279005SAli.Saidi@ARM.comsystem.cpu0.committedOps 44786074 # Number of ops (including micro ops) committed 3289005SAli.Saidi@ARM.comsystem.cpu0.num_int_alu_accesses 39685287 # Number of integer alu accesses 3299005SAli.Saidi@ARM.comsystem.cpu0.num_fp_alu_accesses 5074 # Number of float alu accesses 3309005SAli.Saidi@ARM.comsystem.cpu0.num_func_calls 1296918 # number of times a function call or return occured 3319005SAli.Saidi@ARM.comsystem.cpu0.num_conditional_control_insts 4494112 # number of instructions that are conditional controls 3329005SAli.Saidi@ARM.comsystem.cpu0.num_int_insts 39685287 # number of integer instructions 3339005SAli.Saidi@ARM.comsystem.cpu0.num_fp_insts 5074 # number of float instructions 3349005SAli.Saidi@ARM.comsystem.cpu0.num_int_register_reads 201262894 # number of times the integer registers were read 3359005SAli.Saidi@ARM.comsystem.cpu0.num_int_register_writes 42034263 # number of times the integer registers were written 3369005SAli.Saidi@ARM.comsystem.cpu0.num_fp_register_reads 3706 # number of times the floating registers were read 3379005SAli.Saidi@ARM.comsystem.cpu0.num_fp_register_writes 1372 # number of times the floating registers were written 3389005SAli.Saidi@ARM.comsystem.cpu0.num_mem_refs 16978573 # number of memory refs 3399005SAli.Saidi@ARM.comsystem.cpu0.num_load_insts 9760184 # Number of load instructions 3409005SAli.Saidi@ARM.comsystem.cpu0.num_store_insts 7218389 # Number of store instructions 3419005SAli.Saidi@ARM.comsystem.cpu0.num_idle_cycles 1777623684.411826 # Number of idle cycles 3429005SAli.Saidi@ARM.comsystem.cpu0.num_busy_cycles 45636234.588174 # Number of busy cycles 3439005SAli.Saidi@ARM.comsystem.cpu0.not_idle_fraction 0.025030 # Percentage of non-idle cycles 3449005SAli.Saidi@ARM.comsystem.cpu0.idle_fraction 0.974970 # Percentage of idle cycles 3458844SAli.Saidi@ARM.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 3469005SAli.Saidi@ARM.comsystem.cpu0.kern.inst.quiesce 58955 # number of quiesce instructions executed 3479005SAli.Saidi@ARM.comsystem.cpu0.icache.replacements 497177 # number of replacements 3489005SAli.Saidi@ARM.comsystem.cpu0.icache.tagsinuse 511.014795 # Cycle average of tags in use 3499005SAli.Saidi@ARM.comsystem.cpu0.icache.total_refs 34187980 # Total number of references to valid blocks. 3509005SAli.Saidi@ARM.comsystem.cpu0.icache.sampled_refs 497689 # Sample count of references to valid blocks. 3519005SAli.Saidi@ARM.comsystem.cpu0.icache.avg_refs 68.693461 # Average number of references to valid blocks. 3529005SAli.Saidi@ARM.comsystem.cpu0.icache.warmup_cycle 64536851000 # Cycle when the warmup percentage was hit. 3539005SAli.Saidi@ARM.comsystem.cpu0.icache.occ_blocks::cpu0.inst 511.014795 # Average occupied blocks per requestor 3549005SAli.Saidi@ARM.comsystem.cpu0.icache.occ_percent::cpu0.inst 0.998076 # Average percentage of cache occupancy 3559005SAli.Saidi@ARM.comsystem.cpu0.icache.occ_percent::total 0.998076 # Average percentage of cache occupancy 3569005SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 34187980 # number of ReadReq hits 3579005SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_hits::total 34187980 # number of ReadReq hits 3589005SAli.Saidi@ARM.comsystem.cpu0.icache.demand_hits::cpu0.inst 34187980 # number of demand (read+write) hits 3599005SAli.Saidi@ARM.comsystem.cpu0.icache.demand_hits::total 34187980 # number of demand (read+write) hits 3609005SAli.Saidi@ARM.comsystem.cpu0.icache.overall_hits::cpu0.inst 34187980 # number of overall hits 3619005SAli.Saidi@ARM.comsystem.cpu0.icache.overall_hits::total 34187980 # number of overall hits 3629005SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 497690 # number of ReadReq misses 3639005SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_misses::total 497690 # number of ReadReq misses 3649005SAli.Saidi@ARM.comsystem.cpu0.icache.demand_misses::cpu0.inst 497690 # number of demand (read+write) misses 3659005SAli.Saidi@ARM.comsystem.cpu0.icache.demand_misses::total 497690 # number of demand (read+write) misses 3669005SAli.Saidi@ARM.comsystem.cpu0.icache.overall_misses::cpu0.inst 497690 # number of overall misses 3679005SAli.Saidi@ARM.comsystem.cpu0.icache.overall_misses::total 497690 # number of overall misses 3689005SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 34685670 # number of ReadReq accesses(hits+misses) 3699005SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_accesses::total 34685670 # number of ReadReq accesses(hits+misses) 3709005SAli.Saidi@ARM.comsystem.cpu0.icache.demand_accesses::cpu0.inst 34685670 # number of demand (read+write) accesses 3719005SAli.Saidi@ARM.comsystem.cpu0.icache.demand_accesses::total 34685670 # number of demand (read+write) accesses 3729005SAli.Saidi@ARM.comsystem.cpu0.icache.overall_accesses::cpu0.inst 34685670 # number of overall (read+write) accesses 3739005SAli.Saidi@ARM.comsystem.cpu0.icache.overall_accesses::total 34685670 # number of overall (read+write) accesses 3749005SAli.Saidi@ARM.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014349 # miss rate for ReadReq accesses 3759055Ssaidi@eecs.umich.edusystem.cpu0.icache.ReadReq_miss_rate::total 0.014349 # miss rate for ReadReq accesses 3769005SAli.Saidi@ARM.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.014349 # miss rate for demand accesses 3779055Ssaidi@eecs.umich.edusystem.cpu0.icache.demand_miss_rate::total 0.014349 # miss rate for demand accesses 3789005SAli.Saidi@ARM.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.014349 # miss rate for overall accesses 3799055Ssaidi@eecs.umich.edusystem.cpu0.icache.overall_miss_rate::total 0.014349 # miss rate for overall accesses 3808844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3818844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3828844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3838844SAli.Saidi@ARM.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 3848983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3858983Snate@binkert.orgsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3868844SAli.Saidi@ARM.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 3878844SAli.Saidi@ARM.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 3889005SAli.Saidi@ARM.comsystem.cpu0.icache.writebacks::writebacks 26062 # number of writebacks 3899005SAli.Saidi@ARM.comsystem.cpu0.icache.writebacks::total 26062 # number of writebacks 3908844SAli.Saidi@ARM.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 3919005SAli.Saidi@ARM.comsystem.cpu0.dcache.replacements 385595 # number of replacements 3929005SAli.Saidi@ARM.comsystem.cpu0.dcache.tagsinuse 475.569441 # Cycle average of tags in use 3939005SAli.Saidi@ARM.comsystem.cpu0.dcache.total_refs 14667576 # Total number of references to valid blocks. 3949005SAli.Saidi@ARM.comsystem.cpu0.dcache.sampled_refs 386107 # Sample count of references to valid blocks. 3959005SAli.Saidi@ARM.comsystem.cpu0.dcache.avg_refs 37.988371 # Average number of references to valid blocks. 3968844SAli.Saidi@ARM.comsystem.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. 3979005SAli.Saidi@ARM.comsystem.cpu0.dcache.occ_blocks::cpu0.data 475.569441 # Average occupied blocks per requestor 3989005SAli.Saidi@ARM.comsystem.cpu0.dcache.occ_percent::cpu0.data 0.928847 # Average percentage of cache occupancy 3999005SAli.Saidi@ARM.comsystem.cpu0.dcache.occ_percent::total 0.928847 # Average percentage of cache occupancy 4009005SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 7775792 # number of ReadReq hits 4019005SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_hits::total 7775792 # number of ReadReq hits 4029005SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 6519223 # number of WriteReq hits 4039005SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_hits::total 6519223 # number of WriteReq hits 4049005SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 172927 # number of LoadLockedReq hits 4059005SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_hits::total 172927 # number of LoadLockedReq hits 4069005SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 175483 # number of StoreCondReq hits 4079005SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_hits::total 175483 # number of StoreCondReq hits 4089005SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_hits::cpu0.data 14295015 # number of demand (read+write) hits 4099005SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_hits::total 14295015 # number of demand (read+write) hits 4109005SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_hits::cpu0.data 14295015 # number of overall hits 4119005SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_hits::total 14295015 # number of overall hits 4129005SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 240570 # number of ReadReq misses 4139005SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_misses::total 240570 # number of ReadReq misses 4149005SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 186007 # number of WriteReq misses 4159005SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_misses::total 186007 # number of WriteReq misses 4169005SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9987 # number of LoadLockedReq misses 4179005SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_misses::total 9987 # number of LoadLockedReq misses 4189005SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 7377 # number of StoreCondReq misses 4199005SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_misses::total 7377 # number of StoreCondReq misses 4209005SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_misses::cpu0.data 426577 # number of demand (read+write) misses 4219005SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_misses::total 426577 # number of demand (read+write) misses 4229005SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_misses::cpu0.data 426577 # number of overall misses 4239005SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_misses::total 426577 # number of overall misses 4249005SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 8016362 # number of ReadReq accesses(hits+misses) 4259005SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_accesses::total 8016362 # number of ReadReq accesses(hits+misses) 4269005SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 6705230 # number of WriteReq accesses(hits+misses) 4279005SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_accesses::total 6705230 # number of WriteReq accesses(hits+misses) 4289005SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182914 # number of LoadLockedReq accesses(hits+misses) 4299005SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 182914 # number of LoadLockedReq accesses(hits+misses) 4309005SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182860 # number of StoreCondReq accesses(hits+misses) 4319005SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_accesses::total 182860 # number of StoreCondReq accesses(hits+misses) 4329005SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_accesses::cpu0.data 14721592 # number of demand (read+write) accesses 4339005SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_accesses::total 14721592 # number of demand (read+write) accesses 4349005SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses 4359005SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses 4369005SAli.Saidi@ARM.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030010 # miss rate for ReadReq accesses 4379055Ssaidi@eecs.umich.edusystem.cpu0.dcache.ReadReq_miss_rate::total 0.030010 # miss rate for ReadReq accesses 4389005SAli.Saidi@ARM.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027741 # miss rate for WriteReq accesses 4399055Ssaidi@eecs.umich.edusystem.cpu0.dcache.WriteReq_miss_rate::total 0.027741 # miss rate for WriteReq accesses 4409005SAli.Saidi@ARM.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054599 # miss rate for LoadLockedReq accesses 4419055Ssaidi@eecs.umich.edusystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054599 # miss rate for LoadLockedReq accesses 4429005SAli.Saidi@ARM.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040342 # miss rate for StoreCondReq accesses 4439055Ssaidi@eecs.umich.edusystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.040342 # miss rate for StoreCondReq accesses 4449005SAli.Saidi@ARM.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.028976 # miss rate for demand accesses 4459055Ssaidi@eecs.umich.edusystem.cpu0.dcache.demand_miss_rate::total 0.028976 # miss rate for demand accesses 4469005SAli.Saidi@ARM.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.028976 # miss rate for overall accesses 4479055Ssaidi@eecs.umich.edusystem.cpu0.dcache.overall_miss_rate::total 0.028976 # miss rate for overall accesses 4488844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 4498844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4508844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 4518844SAli.Saidi@ARM.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 4528983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 4538983Snate@binkert.orgsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4548844SAli.Saidi@ARM.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 4558844SAli.Saidi@ARM.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 4569005SAli.Saidi@ARM.comsystem.cpu0.dcache.writebacks::writebacks 342703 # number of writebacks 4579005SAli.Saidi@ARM.comsystem.cpu0.dcache.writebacks::total 342703 # number of writebacks 4588844SAli.Saidi@ARM.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 4598844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 4608844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 4619005SAli.Saidi@ARM.comsystem.cpu1.dtb.read_hits 6036043 # DTB read hits 4629005SAli.Saidi@ARM.comsystem.cpu1.dtb.read_misses 1895 # DTB read misses 4639005SAli.Saidi@ARM.comsystem.cpu1.dtb.write_hits 4565126 # DTB write hits 4649005SAli.Saidi@ARM.comsystem.cpu1.dtb.write_misses 1147 # DTB write misses 4658844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed 4668844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4678844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 4688844SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 4699005SAli.Saidi@ARM.comsystem.cpu1.dtb.flush_entries 1364 # Number of entries that have been flushed from TLB 4708844SAli.Saidi@ARM.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 4719005SAli.Saidi@ARM.comsystem.cpu1.dtb.prefetch_faults 95 # Number of TLB faults due to prefetch 4728844SAli.Saidi@ARM.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 4739005SAli.Saidi@ARM.comsystem.cpu1.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions 4749005SAli.Saidi@ARM.comsystem.cpu1.dtb.read_accesses 6037938 # DTB read accesses 4759005SAli.Saidi@ARM.comsystem.cpu1.dtb.write_accesses 4566273 # DTB write accesses 4768844SAli.Saidi@ARM.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 4779005SAli.Saidi@ARM.comsystem.cpu1.dtb.hits 10601169 # DTB hits 4789005SAli.Saidi@ARM.comsystem.cpu1.dtb.misses 3042 # DTB misses 4799005SAli.Saidi@ARM.comsystem.cpu1.dtb.accesses 10604211 # DTB accesses 4809005SAli.Saidi@ARM.comsystem.cpu1.itb.inst_hits 26944447 # ITB inst hits 4819005SAli.Saidi@ARM.comsystem.cpu1.itb.inst_misses 1203 # ITB inst misses 4828844SAli.Saidi@ARM.comsystem.cpu1.itb.read_hits 0 # DTB read hits 4838844SAli.Saidi@ARM.comsystem.cpu1.itb.read_misses 0 # DTB read misses 4848844SAli.Saidi@ARM.comsystem.cpu1.itb.write_hits 0 # DTB write hits 4858844SAli.Saidi@ARM.comsystem.cpu1.itb.write_misses 0 # DTB write misses 4868844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed 4878844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 4888844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID 4898844SAli.Saidi@ARM.comsystem.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID 4909005SAli.Saidi@ARM.comsystem.cpu1.itb.flush_entries 1228 # Number of entries that have been flushed from TLB 4918844SAli.Saidi@ARM.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 4928844SAli.Saidi@ARM.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 4938844SAli.Saidi@ARM.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 4948844SAli.Saidi@ARM.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 4958844SAli.Saidi@ARM.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 4968844SAli.Saidi@ARM.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 4979005SAli.Saidi@ARM.comsystem.cpu1.itb.inst_accesses 26945650 # ITB inst accesses 4989005SAli.Saidi@ARM.comsystem.cpu1.itb.hits 26944447 # DTB hits 4999005SAli.Saidi@ARM.comsystem.cpu1.itb.misses 1203 # DTB misses 5009005SAli.Saidi@ARM.comsystem.cpu1.itb.accesses 26945650 # DTB accesses 5019005SAli.Saidi@ARM.comsystem.cpu1.numCycles 1822760078 # number of cpu cycles simulated 5028844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 5038844SAli.Saidi@ARM.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 5049005SAli.Saidi@ARM.comsystem.cpu1.committedInsts 26714987 # Number of instructions committed 5059005SAli.Saidi@ARM.comsystem.cpu1.committedOps 33555986 # Number of ops (including micro ops) committed 5069005SAli.Saidi@ARM.comsystem.cpu1.num_int_alu_accesses 30087808 # Number of integer alu accesses 5079005SAli.Saidi@ARM.comsystem.cpu1.num_fp_alu_accesses 5643 # Number of float alu accesses 5089005SAli.Saidi@ARM.comsystem.cpu1.num_func_calls 723750 # number of times a function call or return occured 5099005SAli.Saidi@ARM.comsystem.cpu1.num_conditional_control_insts 3301562 # number of instructions that are conditional controls 5109005SAli.Saidi@ARM.comsystem.cpu1.num_int_insts 30087808 # number of integer instructions 5119005SAli.Saidi@ARM.comsystem.cpu1.num_fp_insts 5643 # number of float instructions 5129005SAli.Saidi@ARM.comsystem.cpu1.num_int_register_reads 152234781 # number of times the integer registers were read 5139005SAli.Saidi@ARM.comsystem.cpu1.num_int_register_writes 32495677 # number of times the integer registers were written 5149005SAli.Saidi@ARM.comsystem.cpu1.num_fp_register_reads 3915 # number of times the floating registers were read 5159005SAli.Saidi@ARM.comsystem.cpu1.num_fp_register_writes 1728 # number of times the floating registers were written 5169005SAli.Saidi@ARM.comsystem.cpu1.num_mem_refs 11031013 # number of memory refs 5179005SAli.Saidi@ARM.comsystem.cpu1.num_load_insts 6247466 # Number of load instructions 5189005SAli.Saidi@ARM.comsystem.cpu1.num_store_insts 4783547 # Number of store instructions 5199005SAli.Saidi@ARM.comsystem.cpu1.num_idle_cycles 1788952556.347001 # Number of idle cycles 5209005SAli.Saidi@ARM.comsystem.cpu1.num_busy_cycles 33807521.652999 # Number of busy cycles 5219005SAli.Saidi@ARM.comsystem.cpu1.not_idle_fraction 0.018547 # Percentage of non-idle cycles 5229005SAli.Saidi@ARM.comsystem.cpu1.idle_fraction 0.981453 # Percentage of idle cycles 5238844SAli.Saidi@ARM.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 5249005SAli.Saidi@ARM.comsystem.cpu1.kern.inst.quiesce 31471 # number of quiesce instructions executed 5259005SAli.Saidi@ARM.comsystem.cpu1.icache.replacements 365832 # number of replacements 5269005SAli.Saidi@ARM.comsystem.cpu1.icache.tagsinuse 475.430525 # Cycle average of tags in use 5279005SAli.Saidi@ARM.comsystem.cpu1.icache.total_refs 26579068 # Total number of references to valid blocks. 5289005SAli.Saidi@ARM.comsystem.cpu1.icache.sampled_refs 366344 # Sample count of references to valid blocks. 5299005SAli.Saidi@ARM.comsystem.cpu1.icache.avg_refs 72.552213 # Average number of references to valid blocks. 5309005SAli.Saidi@ARM.comsystem.cpu1.icache.warmup_cycle 69967043000 # Cycle when the warmup percentage was hit. 5319005SAli.Saidi@ARM.comsystem.cpu1.icache.occ_blocks::cpu1.inst 475.430525 # Average occupied blocks per requestor 5329005SAli.Saidi@ARM.comsystem.cpu1.icache.occ_percent::cpu1.inst 0.928575 # Average percentage of cache occupancy 5339005SAli.Saidi@ARM.comsystem.cpu1.icache.occ_percent::total 0.928575 # Average percentage of cache occupancy 5349005SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 26579068 # number of ReadReq hits 5359005SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_hits::total 26579068 # number of ReadReq hits 5369005SAli.Saidi@ARM.comsystem.cpu1.icache.demand_hits::cpu1.inst 26579068 # number of demand (read+write) hits 5379005SAli.Saidi@ARM.comsystem.cpu1.icache.demand_hits::total 26579068 # number of demand (read+write) hits 5389005SAli.Saidi@ARM.comsystem.cpu1.icache.overall_hits::cpu1.inst 26579068 # number of overall hits 5399005SAli.Saidi@ARM.comsystem.cpu1.icache.overall_hits::total 26579068 # number of overall hits 5409005SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 366344 # number of ReadReq misses 5419005SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_misses::total 366344 # number of ReadReq misses 5429005SAli.Saidi@ARM.comsystem.cpu1.icache.demand_misses::cpu1.inst 366344 # number of demand (read+write) misses 5439005SAli.Saidi@ARM.comsystem.cpu1.icache.demand_misses::total 366344 # number of demand (read+write) misses 5449005SAli.Saidi@ARM.comsystem.cpu1.icache.overall_misses::cpu1.inst 366344 # number of overall misses 5459005SAli.Saidi@ARM.comsystem.cpu1.icache.overall_misses::total 366344 # number of overall misses 5469005SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 26945412 # number of ReadReq accesses(hits+misses) 5479005SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_accesses::total 26945412 # number of ReadReq accesses(hits+misses) 5489005SAli.Saidi@ARM.comsystem.cpu1.icache.demand_accesses::cpu1.inst 26945412 # number of demand (read+write) accesses 5499005SAli.Saidi@ARM.comsystem.cpu1.icache.demand_accesses::total 26945412 # number of demand (read+write) accesses 5509005SAli.Saidi@ARM.comsystem.cpu1.icache.overall_accesses::cpu1.inst 26945412 # number of overall (read+write) accesses 5519005SAli.Saidi@ARM.comsystem.cpu1.icache.overall_accesses::total 26945412 # number of overall (read+write) accesses 5529005SAli.Saidi@ARM.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013596 # miss rate for ReadReq accesses 5539055Ssaidi@eecs.umich.edusystem.cpu1.icache.ReadReq_miss_rate::total 0.013596 # miss rate for ReadReq accesses 5549005SAli.Saidi@ARM.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.013596 # miss rate for demand accesses 5559055Ssaidi@eecs.umich.edusystem.cpu1.icache.demand_miss_rate::total 0.013596 # miss rate for demand accesses 5569005SAli.Saidi@ARM.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.013596 # miss rate for overall accesses 5579055Ssaidi@eecs.umich.edusystem.cpu1.icache.overall_miss_rate::total 0.013596 # miss rate for overall accesses 5588844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5598844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5608844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 5618844SAli.Saidi@ARM.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 5628983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5638983Snate@binkert.orgsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5648844SAli.Saidi@ARM.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 5658844SAli.Saidi@ARM.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 5669005SAli.Saidi@ARM.comsystem.cpu1.icache.writebacks::writebacks 12806 # number of writebacks 5679005SAli.Saidi@ARM.comsystem.cpu1.icache.writebacks::total 12806 # number of writebacks 5688844SAli.Saidi@ARM.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 5699005SAli.Saidi@ARM.comsystem.cpu1.dcache.replacements 240038 # number of replacements 5709005SAli.Saidi@ARM.comsystem.cpu1.dcache.tagsinuse 389.638585 # Cycle average of tags in use 5719005SAli.Saidi@ARM.comsystem.cpu1.dcache.total_refs 9512122 # Total number of references to valid blocks. 5729005SAli.Saidi@ARM.comsystem.cpu1.dcache.sampled_refs 240396 # Sample count of references to valid blocks. 5739005SAli.Saidi@ARM.comsystem.cpu1.dcache.avg_refs 39.568554 # Average number of references to valid blocks. 5749005SAli.Saidi@ARM.comsystem.cpu1.dcache.warmup_cycle 69263687500 # Cycle when the warmup percentage was hit. 5759005SAli.Saidi@ARM.comsystem.cpu1.dcache.occ_blocks::cpu1.data 389.638585 # Average occupied blocks per requestor 5769005SAli.Saidi@ARM.comsystem.cpu1.dcache.occ_percent::cpu1.data 0.761013 # Average percentage of cache occupancy 5779005SAli.Saidi@ARM.comsystem.cpu1.dcache.occ_percent::total 0.761013 # Average percentage of cache occupancy 5789005SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 5740038 # number of ReadReq hits 5799005SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_hits::total 5740038 # number of ReadReq hits 5809005SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 3634687 # number of WriteReq hits 5819005SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_hits::total 3634687 # number of WriteReq hits 5829005SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56514 # number of LoadLockedReq hits 5839005SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_hits::total 56514 # number of LoadLockedReq hits 5849005SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 57060 # number of StoreCondReq hits 5859005SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_hits::total 57060 # number of StoreCondReq hits 5869005SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_hits::cpu1.data 9374725 # number of demand (read+write) hits 5879005SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_hits::total 9374725 # number of demand (read+write) hits 5889005SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_hits::cpu1.data 9374725 # number of overall hits 5899005SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_hits::total 9374725 # number of overall hits 5909005SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 161066 # number of ReadReq misses 5919005SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_misses::total 161066 # number of ReadReq misses 5929005SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 108913 # number of WriteReq misses 5939005SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_misses::total 108913 # number of WriteReq misses 5949005SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10616 # number of LoadLockedReq misses 5959005SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_misses::total 10616 # number of LoadLockedReq misses 5969005SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 10014 # number of StoreCondReq misses 5979005SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_misses::total 10014 # number of StoreCondReq misses 5989005SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_misses::cpu1.data 269979 # number of demand (read+write) misses 5999005SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_misses::total 269979 # number of demand (read+write) misses 6009005SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_misses::cpu1.data 269979 # number of overall misses 6019005SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_misses::total 269979 # number of overall misses 6029005SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 5901104 # number of ReadReq accesses(hits+misses) 6039005SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_accesses::total 5901104 # number of ReadReq accesses(hits+misses) 6049005SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 3743600 # number of WriteReq accesses(hits+misses) 6059005SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_accesses::total 3743600 # number of WriteReq accesses(hits+misses) 6069005SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 67130 # number of LoadLockedReq accesses(hits+misses) 6079005SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 67130 # number of LoadLockedReq accesses(hits+misses) 6089005SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 67074 # number of StoreCondReq accesses(hits+misses) 6099005SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_accesses::total 67074 # number of StoreCondReq accesses(hits+misses) 6109005SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_accesses::cpu1.data 9644704 # number of demand (read+write) accesses 6119005SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_accesses::total 9644704 # number of demand (read+write) accesses 6129005SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses 6139005SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses 6149005SAli.Saidi@ARM.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027294 # miss rate for ReadReq accesses 6159055Ssaidi@eecs.umich.edusystem.cpu1.dcache.ReadReq_miss_rate::total 0.027294 # miss rate for ReadReq accesses 6169005SAli.Saidi@ARM.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.029093 # miss rate for WriteReq accesses 6179055Ssaidi@eecs.umich.edusystem.cpu1.dcache.WriteReq_miss_rate::total 0.029093 # miss rate for WriteReq accesses 6189005SAli.Saidi@ARM.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.158141 # miss rate for LoadLockedReq accesses 6199055Ssaidi@eecs.umich.edusystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.158141 # miss rate for LoadLockedReq accesses 6209005SAli.Saidi@ARM.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.149298 # miss rate for StoreCondReq accesses 6219055Ssaidi@eecs.umich.edusystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.149298 # miss rate for StoreCondReq accesses 6229005SAli.Saidi@ARM.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.027992 # miss rate for demand accesses 6239055Ssaidi@eecs.umich.edusystem.cpu1.dcache.demand_miss_rate::total 0.027992 # miss rate for demand accesses 6249005SAli.Saidi@ARM.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.027992 # miss rate for overall accesses 6259055Ssaidi@eecs.umich.edusystem.cpu1.dcache.overall_miss_rate::total 0.027992 # miss rate for overall accesses 6268844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6278844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6288844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 6298844SAli.Saidi@ARM.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 6308983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6318983Snate@binkert.orgsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6328844SAli.Saidi@ARM.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 6338844SAli.Saidi@ARM.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 6349005SAli.Saidi@ARM.comsystem.cpu1.dcache.writebacks::writebacks 196629 # number of writebacks 6359005SAli.Saidi@ARM.comsystem.cpu1.dcache.writebacks::total 196629 # number of writebacks 6368844SAli.Saidi@ARM.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 6378844SAli.Saidi@ARM.comsystem.iocache.replacements 0 # number of replacements 6388844SAli.Saidi@ARM.comsystem.iocache.tagsinuse 0 # Cycle average of tags in use 6398844SAli.Saidi@ARM.comsystem.iocache.total_refs 0 # Total number of references to valid blocks. 6408844SAli.Saidi@ARM.comsystem.iocache.sampled_refs 0 # Sample count of references to valid blocks. 6418983Snate@binkert.orgsystem.iocache.avg_refs nan # Average number of references to valid blocks. 6428844SAli.Saidi@ARM.comsystem.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 6438844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6448844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6458844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 6468844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 6478983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6488983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6498844SAli.Saidi@ARM.comsystem.iocache.fast_writes 0 # number of fast writes performed 6508844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 6518844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 6528844SAli.Saidi@ARM.com 6538844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 654