stats.txt revision 11687
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311336Sandreas.hansson@arm.comsim_seconds 2.802883 # Number of seconds simulated 411570SCurtis.Dunham@arm.comsim_ticks 2802883274000 # Number of ticks simulated 511570SCurtis.Dunham@arm.comfinal_tick 2802883274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711687Sandreas.hansson@arm.comhost_inst_rate 1537557 # Simulator instruction rate (inst/s) 811687Sandreas.hansson@arm.comhost_op_rate 1873488 # Simulator op (including micro ops) rate (op/s) 911687Sandreas.hansson@arm.comhost_tick_rate 29353729253 # Simulator tick rate (ticks/s) 1011687Sandreas.hansson@arm.comhost_mem_usage 598048 # Number of bytes of host memory used 1111687Sandreas.hansson@arm.comhost_seconds 95.49 # Real time elapsed on the host 1211570SCurtis.Dunham@arm.comsim_insts 146815798 # Number of instructions simulated 1311570SCurtis.Dunham@arm.comsim_ops 178892721 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611570SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1711606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 1810409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1911606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.inst 1163300 # Number of bytes read from this memory 2011606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu0.data 9541412 # Number of bytes read from this memory 2111606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.inst 165332 # Number of bytes read from this memory 2211606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu1.data 1112336 # Number of bytes read from this memory 2310535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2411606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 11983980 # Number of bytes read from this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 1163300 # Number of instructions bytes read from this memory 2611606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 165332 # Number of instructions bytes read from this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.bytes_inst_read::total 1328632 # Number of instructions bytes read from this memory 2811606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 8870080 # Number of bytes written to this memory 2910827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 3010409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3111606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 8887644 # Number of bytes written to this memory 3211606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 3310409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 3411606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.inst 26630 # Number of read requests responded to by this memory 3511606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu0.data 149604 # Number of read requests responded to by this memory 3611606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.inst 2738 # Number of read requests responded to by this memory 3711606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu1.data 17400 # Number of read requests responded to by this memory 3810535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 3911606Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 196397 # Number of read requests responded to by this memory 4011606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 138595 # Number of write requests responded to by this memory 4110827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 4210409Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4311606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 142986 # Number of write requests responded to by this memory 4411606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 4510513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4611606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.inst 415037 # Total read bandwidth from this memory (bytes/s) 4711606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu0.data 3404142 # Total read bandwidth from this memory (bytes/s) 4811606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.inst 58986 # Total read bandwidth from this memory (bytes/s) 4911606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu1.data 396854 # Total read bandwidth from this memory (bytes/s) 5010535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 5111606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 4275590 # Total read bandwidth from this memory (bytes/s) 5211606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu0.inst 415037 # Instruction read bandwidth from this memory (bytes/s) 5311606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu1.inst 58986 # Instruction read bandwidth from this memory (bytes/s) 5411606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 474023 # Instruction read bandwidth from this memory (bytes/s) 5511606Sandreas.sandberg@arm.comsystem.physmem.bw_write::writebacks 3164627 # Write bandwidth from this memory (bytes/s) 5610827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 5710513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 5811606Sandreas.sandberg@arm.comsystem.physmem.bw_write::total 3170893 # Write bandwidth from this memory (bytes/s) 5911606Sandreas.sandberg@arm.comsystem.physmem.bw_total::writebacks 3164627 # Total bandwidth to/from this memory (bytes/s) 6011606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 6110513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.inst 415037 # Total bandwidth to/from this memory (bytes/s) 6311606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu0.data 3410394 # Total bandwidth to/from this memory (bytes/s) 6411606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.inst 58986 # Total bandwidth to/from this memory (bytes/s) 6511606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu1.data 396868 # Total bandwidth to/from this memory (bytes/s) 6610585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 6711606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 7446483 # Total bandwidth to/from this memory (bytes/s) 6811570SCurtis.Dunham@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 6910517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 7010517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 7110517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7210517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7310517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7410517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 7510517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 7610517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 7710517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 7810517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 7910517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 8010517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 8110517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 8210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 8310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 8410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 8510517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 8610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 8711570SCurtis.Dunham@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 8811570SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 8911570SCurtis.Dunham@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 908844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 9110513SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 9210513SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 9310513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 9410513SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 9510513SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 9610535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 9711570SCurtis.Dunham@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 9810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 9910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 10010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 10110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 10210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 10310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 10410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 10510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 10610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 10710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 10810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 10910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 11010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 11110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 11210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 11310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 11410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 11510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 11610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 11710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 11810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 11910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 12010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 12110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 12210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 12310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 12410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 12510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 12610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 12711570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 12811336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 7964 # Table walker walks requested 12911336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors 13011336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency 13111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 13211336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency 13310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 13410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 13510628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 13611336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated 13711336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated 13811336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated 13911336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst 14010628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 14111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 14211336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 14310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 14411336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 14511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 14610535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 14710535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 14811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 20338226 # DTB read hits 14911336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 6871 # DTB read misses 15011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 16389726 # DTB write hits 15110535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1093 # DTB write misses 15210535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 15310535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 15410535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 15510535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 15611547Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB 15710535Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 15810535Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 15910535Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 16010535Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 16111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 20345097 # DTB read accesses 16211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 16390819 # DTB write accesses 16310535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 16411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.hits 36727952 # DTB hits 16511336Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 7964 # DTB misses 16611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.accesses 36735916 # DTB accesses 16711570SCurtis.Dunham@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 16810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 16910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 17010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 17110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 17210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 17310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 17410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 17510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 17610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 17710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 17810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 17910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 18010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 18110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 18210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 18310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 18410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 18510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 18610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 18710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 18810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 18910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 19010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 19110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 19210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 19310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 19410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 19510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 19610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 19711570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 19810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 3358 # Table walker walks requested 19910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 20010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 20110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 20210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 20310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 20410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 20510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 20610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 20710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 20810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 20910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 21010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 21110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 21210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 21310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 21410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 21510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 21611570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 97433318 # ITB inst hits 21710535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 3358 # ITB inst misses 21810535Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 21910535Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 22010535Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 22110535Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 22210535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 22310535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 22410535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 22510535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 22611547Sandreas.sandberg@arm.comsystem.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB 22710535Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 22810535Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 22910535Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 23010535Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 23110535Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 23210535Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 23311570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_accesses 97436676 # ITB inst accesses 23411570SCurtis.Dunham@arm.comsystem.cpu0.itb.hits 97433318 # DTB hits 23510535Sandreas.hansson@arm.comsystem.cpu0.itb.misses 3358 # DTB misses 23611570SCurtis.Dunham@arm.comsystem.cpu0.itb.accesses 97436676 # DTB accesses 23711570SCurtis.Dunham@arm.comsystem.cpu0.numPwrStateTransitions 3946 # Number of power state transitions 23811570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::samples 1973 # Distribution of time spent in the clock gated state 23911570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::mean 1390823508.162189 # Distribution of time spent in the clock gated state 24011570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 23082851772.246098 # Distribution of time spent in the clock gated state 24111570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 1157 58.64% 58.64% # Distribution of time spent in the clock gated state 24211570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 810 41.05% 99.70% # Distribution of time spent in the clock gated state 24311530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state 24411530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state 24511530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state 24611570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 24711570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 499983361388 # Distribution of time spent in the clock gated state 24811570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::total 1973 # Distribution of time spent in the clock gated state 24911570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 58788492396 # Cumulative time (in ticks) in various power states 25011570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 2744094781604 # Cumulative time (in ticks) in various power states 25111570SCurtis.Dunham@arm.comsystem.cpu0.numCycles 5605768522 # number of cpu cycles simulated 25210535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 25310535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 25411201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 25511570SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 1973 # number of quiesce instructions executed 25611570SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 95420875 # Number of instructions committed 25711570SCurtis.Dunham@arm.comsystem.cpu0.committedOps 115552929 # Number of ops (including micro ops) committed 25811570SCurtis.Dunham@arm.comsystem.cpu0.num_int_alu_accesses 100755950 # Number of integer alu accesses 25910535Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 26011570SCurtis.Dunham@arm.comsystem.cpu0.num_func_calls 8000037 # number of times a function call or return occured 26111570SCurtis.Dunham@arm.comsystem.cpu0.num_conditional_control_insts 13203579 # number of instructions that are conditional controls 26211570SCurtis.Dunham@arm.comsystem.cpu0.num_int_insts 100755950 # number of integer instructions 26310535Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 9755 # number of float instructions 26411589SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_reads 182434923 # number of times the integer registers were read 26511570SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_writes 69130439 # number of times the integer registers were written 26610535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 26710535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 26811570SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_reads 349948963 # number of times the CC registers were read 26911570SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_writes 44904772 # number of times the CC registers were written 27011570SCurtis.Dunham@arm.comsystem.cpu0.num_mem_refs 37870790 # number of memory refs 27111570SCurtis.Dunham@arm.comsystem.cpu0.num_load_insts 20595754 # Number of load instructions 27211570SCurtis.Dunham@arm.comsystem.cpu0.num_store_insts 17275036 # Number of store instructions 27311570SCurtis.Dunham@arm.comsystem.cpu0.num_idle_cycles 5488191495.802790 # Number of idle cycles 27411570SCurtis.Dunham@arm.comsystem.cpu0.num_busy_cycles 117577026.197211 # Number of busy cycles 27511570SCurtis.Dunham@arm.comsystem.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles 27611570SCurtis.Dunham@arm.comsystem.cpu0.idle_fraction 0.979026 # Percentage of idle cycles 27711570SCurtis.Dunham@arm.comsystem.cpu0.Branches 21940702 # Number of branches fetched 27810535Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 27911570SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntAlu 78882840 67.49% 67.50% # Class of executed instruction 28011570SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction 28110535Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 28210535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 28310535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 28410535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 28510535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 28611687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMultAcc 0 0.00% 67.59% # Class of executed instruction 28710535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 28811687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMisc 0 0.00% 67.59% # Class of executed instruction 28910535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 29010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 29110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 29210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 29310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 29410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 29510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 29610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 29710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 29810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 29910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 30010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 30110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 30210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 30310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 30410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 30510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 30610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 30710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 30810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 30910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 31011687Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 20593498 17.62% 85.22% # Class of executed instruction 31111687Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 17267541 14.77% 99.99% # Class of executed instruction 31211687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemRead 2256 0.00% 99.99% # Class of executed instruction 31311687Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMemWrite 7495 0.01% 100.00% # Class of executed instruction 31410535Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 31510535Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 31611570SCurtis.Dunham@arm.comsystem.cpu0.op_class::total 116874608 # Class of executed instruction 31711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 31811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 693483 # number of replacements 31911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 494.728102 # Cycle average of tags in use 32011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 35929530 # Total number of references to valid blocks. 32111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 693995 # Sample count of references to valid blocks. 32211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 51.772030 # Average number of references to valid blocks. 32310827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 32411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.728102 # Average occupied blocks per requestor 32511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966266 # Average percentage of cache occupancy 32611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.966266 # Average percentage of cache occupancy 32710535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 32810535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 32910535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 33010535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 33110535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 33211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 74108220 # Number of tag accesses 33311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 74108220 # Number of data accesses 33411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 33511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 19107088 # number of ReadReq hits 33611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 19107088 # number of ReadReq hits 33711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 15689072 # number of WriteReq hits 33811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_hits::total 15689072 # number of WriteReq hits 33911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 346042 # number of SoftPFReq hits 34011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 346042 # number of SoftPFReq hits 34111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379604 # number of LoadLockedReq hits 34211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 379604 # number of LoadLockedReq hits 34311606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 363048 # number of StoreCondReq hits 34411606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 363048 # number of StoreCondReq hits 34511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 34796160 # number of demand (read+write) hits 34611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_hits::total 34796160 # number of demand (read+write) hits 34711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 35142202 # number of overall hits 34811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_hits::total 35142202 # number of overall hits 34911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 373135 # number of ReadReq misses 35011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 373135 # number of ReadReq misses 35111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 295787 # number of WriteReq misses 35211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_misses::total 295787 # number of WriteReq misses 35311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses 35411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses 35511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6741 # number of LoadLockedReq misses 35611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 6741 # number of LoadLockedReq misses 35711606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 18411 # number of StoreCondReq misses 35811606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 18411 # number of StoreCondReq misses 35911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 668922 # number of demand (read+write) misses 36011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.demand_misses::total 668922 # number of demand (read+write) misses 36111606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 769244 # number of overall misses 36211606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_misses::total 769244 # number of overall misses 36311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 19480223 # number of ReadReq accesses(hits+misses) 36411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 19480223 # number of ReadReq accesses(hits+misses) 36511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 15984859 # number of WriteReq accesses(hits+misses) 36611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 15984859 # number of WriteReq accesses(hits+misses) 36711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446364 # number of SoftPFReq accesses(hits+misses) 36811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 446364 # number of SoftPFReq accesses(hits+misses) 36911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386345 # number of LoadLockedReq accesses(hits+misses) 37011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 386345 # number of LoadLockedReq accesses(hits+misses) 37111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381459 # number of StoreCondReq accesses(hits+misses) 37211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 381459 # number of StoreCondReq accesses(hits+misses) 37311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 35465082 # number of demand (read+write) accesses 37411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 35465082 # number of demand (read+write) accesses 37511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 35911446 # number of overall (read+write) accesses 37611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 35911446 # number of overall (read+write) accesses 37711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019155 # miss rate for ReadReq accesses 37811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.019155 # miss rate for ReadReq accesses 37911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018504 # miss rate for WriteReq accesses 38011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018504 # miss rate for WriteReq accesses 38111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224754 # miss rate for SoftPFReq accesses 38211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.224754 # miss rate for SoftPFReq accesses 38311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017448 # miss rate for LoadLockedReq accesses 38411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017448 # miss rate for LoadLockedReq accesses 38511606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048265 # miss rate for StoreCondReq accesses 38611606Sandreas.sandberg@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.048265 # miss rate for StoreCondReq accesses 38711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.018861 # miss rate for demand accesses 38811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.018861 # miss rate for demand accesses 38911606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.021421 # miss rate for overall accesses 39011606Sandreas.sandberg@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.021421 # miss rate for overall accesses 39110535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 39210535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 39310535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 39410535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 39510535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39610535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 693483 # number of writebacks 39811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 693483 # number of writebacks 39911570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 40011570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 1109362 # number of replacements 40111336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 40211570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 96325777 # Total number of references to valid blocks. 40311570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 1109874 # Sample count of references to valid blocks. 40411570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 86.789831 # Average number of references to valid blocks. 40511570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 6345718500 # Cycle when the warmup percentage was hit. 40611336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 40710535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 40810535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 40910535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 41010535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 41110535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 41210535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 41310535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 41411570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 195981203 # Number of tag accesses 41511570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 195981203 # Number of data accesses 41611570SCurtis.Dunham@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 41711570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 96325777 # number of ReadReq hits 41811570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 96325777 # number of ReadReq hits 41911570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 96325777 # number of demand (read+write) hits 42011570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 96325777 # number of demand (read+write) hits 42111570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 96325777 # number of overall hits 42211570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 96325777 # number of overall hits 42311570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1109883 # number of ReadReq misses 42411570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 1109883 # number of ReadReq misses 42511570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 1109883 # number of demand (read+write) misses 42611570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 1109883 # number of demand (read+write) misses 42711570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 1109883 # number of overall misses 42811570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 1109883 # number of overall misses 42911570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 97435660 # number of ReadReq accesses(hits+misses) 43011570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 97435660 # number of ReadReq accesses(hits+misses) 43111570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 97435660 # number of demand (read+write) accesses 43211570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 97435660 # number of demand (read+write) accesses 43311570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 97435660 # number of overall (read+write) accesses 43411570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 97435660 # number of overall (read+write) accesses 43511570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011391 # miss rate for ReadReq accesses 43611570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 43711570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011391 # miss rate for demand accesses 43811570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011391 # miss rate for demand accesses 43911570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011391 # miss rate for overall accesses 44011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011391 # miss rate for overall accesses 44110535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 44210535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 44310535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 44410535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 44510535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 44610535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 44711570SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 1109362 # number of writebacks 44811570SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 1109362 # number of writebacks 44911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 45010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 45110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 45210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 45310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 45410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 45510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 45611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 45711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.replacements 244755 # number of replacements 45811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15690.306286 # Cycle average of tags in use 45911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.total_refs 1516961 # Total number of references to valid blocks. 46011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.sampled_refs 260398 # Sample count of references to valid blocks. 46111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.avg_refs 5.825548 # Average number of references to valid blocks. 46211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 46311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 15688.001822 # Average occupied blocks per requestor 46411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.238695 # Average occupied blocks per requestor 46511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065768 # Average occupied blocks per requestor 46611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.957520 # Average percentage of cache occupancy 46711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000137 # Average percentage of cache occupancy 46811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 46911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.957660 # Average percentage of cache occupancy 47011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 47111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 15637 # Occupied blocks per task id 47211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id 47311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 47411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id 47511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 527 # Occupied blocks per task id 47611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 887 # Occupied blocks per task id 47711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7822 # Occupied blocks per task id 47811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5177 # Occupied blocks per task id 47911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1224 # Occupied blocks per task id 48011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id 48111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.954407 # Percentage of cache occupancy per task id 48211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.tag_accesses 60864487 # Number of tag accesses 48311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.tags.data_accesses 60864487 # Number of data accesses 48411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 48511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10088 # number of ReadReq hits 48611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4467 # number of ReadReq hits 48711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 14555 # number of ReadReq hits 48811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 510065 # number of WritebackDirty hits 48911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 510065 # number of WritebackDirty hits 49011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 1264919 # number of WritebackClean hits 49111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 1264919 # number of WritebackClean hits 49211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 94269 # number of ReadExReq hits 49311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 94269 # number of ReadExReq hits 49411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1050188 # number of ReadCleanReq hits 49511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 1050188 # number of ReadCleanReq hits 49611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 344415 # number of ReadSharedReq hits 49711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 344415 # number of ReadSharedReq hits 49811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10088 # number of demand (read+write) hits 49911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 4467 # number of demand (read+write) hits 50011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 1050188 # number of demand (read+write) hits 50111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 438684 # number of demand (read+write) hits 50211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_hits::total 1503427 # number of demand (read+write) hits 50311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10088 # number of overall hits 50411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 4467 # number of overall hits 50511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 1050188 # number of overall hits 50611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 438684 # number of overall hits 50711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_hits::total 1503427 # number of overall hits 50811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 274 # number of ReadReq misses 50911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 140 # number of ReadReq misses 51011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 414 # number of ReadReq misses 51111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26265 # number of UpgradeReq misses 51211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 26265 # number of UpgradeReq misses 51311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18411 # number of SCUpgradeReq misses 51411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 18411 # number of SCUpgradeReq misses 51511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 175253 # number of ReadExReq misses 51611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 175253 # number of ReadExReq misses 51711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 59695 # number of ReadCleanReq misses 51811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 59695 # number of ReadCleanReq misses 51911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 135783 # number of ReadSharedReq misses 52011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 135783 # number of ReadSharedReq misses 52111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 274 # number of demand (read+write) misses 52211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 140 # number of demand (read+write) misses 52311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 59695 # number of demand (read+write) misses 52411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 311036 # number of demand (read+write) misses 52511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_misses::total 371145 # number of demand (read+write) misses 52611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 274 # number of overall misses 52711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 140 # number of overall misses 52811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 59695 # number of overall misses 52911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 311036 # number of overall misses 53011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_misses::total 371145 # number of overall misses 53111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10362 # number of ReadReq accesses(hits+misses) 53211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4607 # number of ReadReq accesses(hits+misses) 53311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 14969 # number of ReadReq accesses(hits+misses) 53411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 510065 # number of WritebackDirty accesses(hits+misses) 53511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 510065 # number of WritebackDirty accesses(hits+misses) 53611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 1264919 # number of WritebackClean accesses(hits+misses) 53711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 1264919 # number of WritebackClean accesses(hits+misses) 53811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26265 # number of UpgradeReq accesses(hits+misses) 53911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 26265 # number of UpgradeReq accesses(hits+misses) 54011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18411 # number of SCUpgradeReq accesses(hits+misses) 54111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 18411 # number of SCUpgradeReq accesses(hits+misses) 54211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269522 # number of ReadExReq accesses(hits+misses) 54311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 269522 # number of ReadExReq accesses(hits+misses) 54411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1109883 # number of ReadCleanReq accesses(hits+misses) 54511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 1109883 # number of ReadCleanReq accesses(hits+misses) 54611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480198 # number of ReadSharedReq accesses(hits+misses) 54711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 480198 # number of ReadSharedReq accesses(hits+misses) 54811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10362 # number of demand (read+write) accesses 54911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4607 # number of demand (read+write) accesses 55011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 1109883 # number of demand (read+write) accesses 55111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 749720 # number of demand (read+write) accesses 55211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_accesses::total 1874572 # number of demand (read+write) accesses 55311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10362 # number of overall (read+write) accesses 55411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4607 # number of overall (read+write) accesses 55511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 1109883 # number of overall (read+write) accesses 55611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 749720 # number of overall (read+write) accesses 55711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_accesses::total 1874572 # number of overall (read+write) accesses 55811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for ReadReq accesses 55911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030389 # miss rate for ReadReq accesses 56011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.027657 # miss rate for ReadReq accesses 56111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 56211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 56310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 56410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 56511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650236 # miss rate for ReadExReq accesses 56611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.650236 # miss rate for ReadExReq accesses 56711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.053785 # miss rate for ReadCleanReq accesses 56811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.053785 # miss rate for ReadCleanReq accesses 56911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.282765 # miss rate for ReadSharedReq accesses 57011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.282765 # miss rate for ReadSharedReq accesses 57111606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for demand accesses 57211606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.030389 # miss rate for demand accesses 57311606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.053785 # miss rate for demand accesses 57411606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.414870 # miss rate for demand accesses 57511606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.197989 # miss rate for demand accesses 57611606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026443 # miss rate for overall accesses 57711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.030389 # miss rate for overall accesses 57811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.053785 # miss rate for overall accesses 57911606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.414870 # miss rate for overall accesses 58011606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.197989 # miss rate for overall accesses 58110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 58410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 58510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 58610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 58711606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.writebacks::writebacks 192868 # number of writebacks 58811606Sandreas.sandberg@arm.comsystem.cpu0.l2cache.writebacks::total 192868 # number of writebacks 58911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 3719490 # Total number of requests made to the snoop filter. 59011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859911 # Number of requests hitting in the snoop filter with a single holder of the requested data. 59111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 59211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 111560 # Total number of snoops made to the snoop filter. 59311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 109856 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 59411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1704 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 59511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 59611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution 59711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 1651491 # Transaction distribution 59811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28340 # Transaction distribution 59911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28340 # Transaction distribution 60011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 510065 # Transaction distribution 60111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 1292780 # Transaction distribution 60211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 26265 # Transaction distribution 60311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18411 # Transaction distribution 60411606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 44676 # Transaction distribution 60511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 269522 # Transaction distribution 60611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 269522 # Transaction distribution 60711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 1109883 # Transaction distribution 60811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 480198 # Transaction distribution 60911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347172 # Packet count per connected master and slave (bytes) 61011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402107 # Packet count per connected master and slave (bytes) 61110535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 61211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 61311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.pkt_count::total 5790903 # Packet count per connected master and slave (bytes) 61411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142067768 # Cumulative packet size per connected master and slave (bytes) 61511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92555520 # Cumulative packet size per connected master and slave (bytes) 61610535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 61711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 61811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size::total 234706536 # Cumulative packet size per connected master and slave (bytes) 61911606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoops 530280 # Total snoops (count) 62011606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoopTraffic 12377344 # Total snoop traffic (bytes) 62111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 4224545 # Request fanout histogram 62211606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.042934 # Request fanout histogram 62311606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.204688 # Request fanout histogram 62410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 62511606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 4044873 95.75% 95.75% # Request fanout histogram 62611606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 177968 4.21% 99.96% # Request fanout histogram 62711606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 1704 0.04% 100.00% # Request fanout histogram 62810535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 62911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 63010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 63111606Sandreas.sandberg@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 4224545 # Request fanout histogram 63211570SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 63310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 63410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 63510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 63610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 63710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 63810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 63910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 64010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 64110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 64210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 64310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 64410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 64510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 64610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 64710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 64810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 65110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 65210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 65310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 65410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 65710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 65910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 66110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 66211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 66311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 3359 # Table walker walks requested 66411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 66511336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 66611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 66711336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 66811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::samples -1804201736 # Table walker pending requests distribution 66911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1804201736 100.00% 100.00% # Table walker pending requests distribution 67011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::total -1804201736 # Table walker pending requests distribution 67111336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated 67211336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated 67311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated 67411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst 67510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 67611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst 67711336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst 67810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 67911336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst 68011336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst 68110535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 68210535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 68311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 12172373 # DTB read hits 68411336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 2853 # DTB read misses 68511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 7586083 # DTB write hits 68610535Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 506 # DTB write misses 68710535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 68810535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 68910535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 69010535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 69111547Sandreas.sandberg@arm.comsystem.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB 69210535Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 69310535Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 69410535Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 69510535Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 69611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 12175226 # DTB read accesses 69711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 7586589 # DTB write accesses 69810535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 69911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 19758456 # DTB hits 70011336Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 3359 # DTB misses 70111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.accesses 19761815 # DTB accesses 70211570SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 70310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 70410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 70610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 70810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 70910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 71010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 71110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 71210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 71310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 71410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 71510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 71610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 71710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 71810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 71910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 72110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 72210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 72310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 72410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 72510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 72610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 72810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 72910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 73010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 73110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 73211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 73310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 1734 # Table walker walks requested 73410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 73510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 73610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 73710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 73811570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::samples -1804204236 # Table walker pending requests distribution 73911570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::0 -1804204236 100.00% 100.00% # Table walker pending requests distribution 74011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::total -1804204236 # Table walker pending requests distribution 74110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 74210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 74310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 74410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 74610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 74710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 74910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 75010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 75111570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_hits 53665127 # ITB inst hits 75210535Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 1734 # ITB inst misses 75310535Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 75410535Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 75510535Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 75610535Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 75710535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 75810535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 75910535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 76010535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 76111547Sandreas.sandberg@arm.comsystem.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB 76210535Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 76310535Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 76410535Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 76510535Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 76610535Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 76710535Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 76811570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_accesses 53666861 # ITB inst accesses 76911570SCurtis.Dunham@arm.comsystem.cpu1.itb.hits 53665127 # DTB hits 77010535Sandreas.hansson@arm.comsystem.cpu1.itb.misses 1734 # DTB misses 77111570SCurtis.Dunham@arm.comsystem.cpu1.itb.accesses 53666861 # DTB accesses 77211570SCurtis.Dunham@arm.comsystem.cpu1.numPwrStateTransitions 5467 # Number of power state transitions 77311570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::samples 2734 # Distribution of time spent in the clock gated state 77411570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::mean 1013195942.406364 # Distribution of time spent in the clock gated state 77511570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 25944771719.895676 # Distribution of time spent in the clock gated state 77611570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 1955 71.51% 71.51% # Distribution of time spent in the clock gated state 77711570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 774 28.31% 99.82% # Distribution of time spent in the clock gated state 77811530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state 77911530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 78011530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 78111530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 78211570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 78311570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 979984970108 # Distribution of time spent in the clock gated state 78411570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::total 2734 # Distribution of time spent in the clock gated state 78511570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 32805567461 # Cumulative time (in ticks) in various power states 78611570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 2770077706539 # Cumulative time (in ticks) in various power states 78711570SCurtis.Dunham@arm.comsystem.cpu1.numCycles 5605297416 # number of cpu cycles simulated 78810535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 78910535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 79011201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 79111570SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed 79211570SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 51394923 # Number of instructions committed 79311570SCurtis.Dunham@arm.comsystem.cpu1.committedOps 63339792 # Number of ops (including micro ops) committed 79411570SCurtis.Dunham@arm.comsystem.cpu1.num_int_alu_accesses 56977163 # Number of integer alu accesses 79510535Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 79611570SCurtis.Dunham@arm.comsystem.cpu1.num_func_calls 9170267 # number of times a function call or return occured 79711570SCurtis.Dunham@arm.comsystem.cpu1.num_conditional_control_insts 5966436 # number of instructions that are conditional controls 79811570SCurtis.Dunham@arm.comsystem.cpu1.num_int_insts 56977163 # number of integer instructions 79910535Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 1792 # number of float instructions 80011589SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_reads 110657326 # number of times the integer registers were read 80111570SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_writes 41293408 # number of times the integer registers were written 80210535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 80310535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 80411570SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_reads 196244999 # number of times the CC registers were read 80511570SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_writes 18891882 # number of times the CC registers were written 80611570SCurtis.Dunham@arm.comsystem.cpu1.num_mem_refs 20023552 # number of memory refs 80711570SCurtis.Dunham@arm.comsystem.cpu1.num_load_insts 12287954 # Number of load instructions 80811570SCurtis.Dunham@arm.comsystem.cpu1.num_store_insts 7735598 # Number of store instructions 80911570SCurtis.Dunham@arm.comsystem.cpu1.num_idle_cycles 5539691771.902995 # Number of idle cycles 81011570SCurtis.Dunham@arm.comsystem.cpu1.num_busy_cycles 65605644.097005 # Number of busy cycles 81111570SCurtis.Dunham@arm.comsystem.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles 81211570SCurtis.Dunham@arm.comsystem.cpu1.idle_fraction 0.988296 # Percentage of idle cycles 81311570SCurtis.Dunham@arm.comsystem.cpu1.Branches 15216243 # Number of branches fetched 81410535Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 81511570SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntAlu 45396317 69.36% 69.36% # Class of executed instruction 81611570SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntMult 28337 0.04% 69.40% # Class of executed instruction 81710535Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 81810535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 81910535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 82010535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 82110535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 82211687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMultAcc 0 0.00% 69.40% # Class of executed instruction 82310535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 82411687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMisc 0 0.00% 69.40% # Class of executed instruction 82510535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 82610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 82710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 82810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 82910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 83010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 83110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 83210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 83310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 83410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 83510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 83610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 83710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 83810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 83910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 84010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 84110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 84211570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction 84310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 84410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 84510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 84611687Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 12287438 18.77% 88.18% # Class of executed instruction 84711687Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 7734322 11.82% 100.00% # Class of executed instruction 84811687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemRead 516 0.00% 100.00% # Class of executed instruction 84911687Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMemWrite 1276 0.00% 100.00% # Class of executed instruction 85010535Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 85110535Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 85211570SCurtis.Dunham@arm.comsystem.cpu1.op_class::total 65451587 # Class of executed instruction 85311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 85411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 191903 # number of replacements 85511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 472.757938 # Cycle average of tags in use 85611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 19500903 # Total number of references to valid blocks. 85711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 192257 # Sample count of references to valid blocks. 85811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 101.431433 # Average number of references to valid blocks. 85911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 105851556000 # Cycle when the warmup percentage was hit. 86011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757938 # Average occupied blocks per requestor 86111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy 86211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy 86310535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 86410535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 86510535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 86610535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 86711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 39746590 # Number of tag accesses 86811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 39746590 # Number of data accesses 86911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 87011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 11857228 # number of ReadReq hits 87111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 11857228 # number of ReadReq hits 87211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 7396381 # number of WriteReq hits 87311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_hits::total 7396381 # number of WriteReq hits 87411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 50103 # number of SoftPFReq hits 87511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 50103 # number of SoftPFReq hits 87611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91426 # number of LoadLockedReq hits 87711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 91426 # number of LoadLockedReq hits 87811606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 72441 # number of StoreCondReq hits 87911606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 72441 # number of StoreCondReq hits 88011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 19253609 # number of demand (read+write) hits 88111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_hits::total 19253609 # number of demand (read+write) hits 88211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 19303712 # number of overall hits 88311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_hits::total 19303712 # number of overall hits 88411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 136574 # number of ReadReq misses 88511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 136574 # number of ReadReq misses 88611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 92475 # number of WriteReq misses 88711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_misses::total 92475 # number of WriteReq misses 88811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 30717 # number of SoftPFReq misses 88911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 30717 # number of SoftPFReq misses 89010535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 89110535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 89211606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 22520 # number of StoreCondReq misses 89311606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 22520 # number of StoreCondReq misses 89411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 229049 # number of demand (read+write) misses 89511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.demand_misses::total 229049 # number of demand (read+write) misses 89611606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 259766 # number of overall misses 89711606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_misses::total 259766 # number of overall misses 89811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 11993802 # number of ReadReq accesses(hits+misses) 89911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 11993802 # number of ReadReq accesses(hits+misses) 90011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 7488856 # number of WriteReq accesses(hits+misses) 90111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 7488856 # number of WriteReq accesses(hits+misses) 90211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80820 # number of SoftPFReq accesses(hits+misses) 90311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 80820 # number of SoftPFReq accesses(hits+misses) 90411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96744 # number of LoadLockedReq accesses(hits+misses) 90511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 96744 # number of LoadLockedReq accesses(hits+misses) 90611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94961 # number of StoreCondReq accesses(hits+misses) 90711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 94961 # number of StoreCondReq accesses(hits+misses) 90811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 19482658 # number of demand (read+write) accesses 90911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 19482658 # number of demand (read+write) accesses 91011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 19563478 # number of overall (read+write) accesses 91111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 19563478 # number of overall (read+write) accesses 91211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011387 # miss rate for ReadReq accesses 91311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.011387 # miss rate for ReadReq accesses 91411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses 91511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses 91611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380067 # miss rate for SoftPFReq accesses 91711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.380067 # miss rate for SoftPFReq accesses 91811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054970 # miss rate for LoadLockedReq accesses 91911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054970 # miss rate for LoadLockedReq accesses 92011606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237150 # miss rate for StoreCondReq accesses 92111606Sandreas.sandberg@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.237150 # miss rate for StoreCondReq accesses 92211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 92311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 92411606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.013278 # miss rate for overall accesses 92511606Sandreas.sandberg@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.013278 # miss rate for overall accesses 92610535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 92710535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92810535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 92910535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 93010535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 93110535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 93211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::writebacks 191903 # number of writebacks 93311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::total 191903 # number of writebacks 93411570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 93511570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 523286 # number of replacements 93611570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 499.709347 # Cycle average of tags in use 93711570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 53142419 # Total number of references to valid blocks. 93811570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 523798 # Sample count of references to valid blocks. 93911570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 101.455941 # Average number of references to valid blocks. 94011570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 76931398500 # Cycle when the warmup percentage was hit. 94111570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 499.709347 # Average occupied blocks per requestor 94211570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.975995 # Average percentage of cache occupancy 94311570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.975995 # Average percentage of cache occupancy 94410535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 94510535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 94610535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 94710535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 94811570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 107856232 # Number of tag accesses 94911570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 107856232 # Number of data accesses 95011570SCurtis.Dunham@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 95111570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 53142419 # number of ReadReq hits 95211570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 53142419 # number of ReadReq hits 95311570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 53142419 # number of demand (read+write) hits 95411570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 53142419 # number of demand (read+write) hits 95511570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 53142419 # number of overall hits 95611570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 53142419 # number of overall hits 95711570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 523798 # number of ReadReq misses 95811570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 523798 # number of ReadReq misses 95911570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 523798 # number of demand (read+write) misses 96011570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 523798 # number of demand (read+write) misses 96111570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 523798 # number of overall misses 96211570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 523798 # number of overall misses 96311570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 53666217 # number of ReadReq accesses(hits+misses) 96411570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 53666217 # number of ReadReq accesses(hits+misses) 96511570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 53666217 # number of demand (read+write) accesses 96611570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 53666217 # number of demand (read+write) accesses 96711570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 53666217 # number of overall (read+write) accesses 96811570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 53666217 # number of overall (read+write) accesses 96911570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009760 # miss rate for ReadReq accesses 97011570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009760 # miss rate for ReadReq accesses 97111570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009760 # miss rate for demand accesses 97211570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009760 # miss rate for demand accesses 97311570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009760 # miss rate for overall accesses 97411570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009760 # miss rate for overall accesses 97510535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 97610535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97710535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 97810535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 97910535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 98010535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 98111570SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 523286 # number of writebacks 98211570SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 523286 # number of writebacks 98311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 98410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 98510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 98610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 98710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 98810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 98910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 99011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 99111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.replacements 45747 # number of replacements 99211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.tagsinuse 14812.613567 # Cycle average of tags in use 99311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.total_refs 613917 # Total number of references to valid blocks. 99411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.sampled_refs 60319 # Sample count of references to valid blocks. 99511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.avg_refs 10.177838 # Average number of references to valid blocks. 99610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 99711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 14808.372104 # Average occupied blocks per requestor 99811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.216207 # Average occupied blocks per requestor 99911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.025256 # Average occupied blocks per requestor 100011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.903831 # Average percentage of cache occupancy 100111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000135 # Average percentage of cache occupancy 100211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy 100311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.904090 # Average percentage of cache occupancy 100411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id 100511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14549 # Occupied blocks per task id 100610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 100711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 100811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id 100911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1590 # Occupied blocks per task id 101011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8844 # Occupied blocks per task id 101111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4115 # Occupied blocks per task id 101211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id 101311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.888000 # Percentage of cache occupancy per task id 101411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.tag_accesses 25046952 # Number of tag accesses 101511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.tags.data_accesses 25046952 # Number of data accesses 101611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 101711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3528 # number of ReadReq hits 101811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1892 # number of ReadReq hits 101911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 5420 # number of ReadReq hits 102011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 120650 # number of WritebackDirty hits 102111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 120650 # number of WritebackDirty hits 102211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 583378 # number of WritebackClean hits 102311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 583378 # number of WritebackClean hits 102411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 19790 # number of ReadExReq hits 102511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 19790 # number of ReadExReq hits 102611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 502408 # number of ReadCleanReq hits 102711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 502408 # number of ReadCleanReq hits 102811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 97451 # number of ReadSharedReq hits 102911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 97451 # number of ReadSharedReq hits 103011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3528 # number of demand (read+write) hits 103111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 1892 # number of demand (read+write) hits 103211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 502408 # number of demand (read+write) hits 103311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 117241 # number of demand (read+write) hits 103411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_hits::total 625069 # number of demand (read+write) hits 103511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3528 # number of overall hits 103611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 1892 # number of overall hits 103711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 502408 # number of overall hits 103811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 117241 # number of overall hits 103911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_hits::total 625069 # number of overall hits 104011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 436 # number of ReadReq misses 104111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 299 # number of ReadReq misses 104211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 735 # number of ReadReq misses 104311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28860 # number of UpgradeReq misses 104411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 28860 # number of UpgradeReq misses 104511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22520 # number of SCUpgradeReq misses 104611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 22520 # number of SCUpgradeReq misses 104711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 43825 # number of ReadExReq misses 104811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 43825 # number of ReadExReq misses 104911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 21390 # number of ReadCleanReq misses 105011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 21390 # number of ReadCleanReq misses 105111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 75158 # number of ReadSharedReq misses 105211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 75158 # number of ReadSharedReq misses 105311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 436 # number of demand (read+write) misses 105411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 299 # number of demand (read+write) misses 105511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 21390 # number of demand (read+write) misses 105611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 118983 # number of demand (read+write) misses 105711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_misses::total 141108 # number of demand (read+write) misses 105811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 436 # number of overall misses 105911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 299 # number of overall misses 106011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 21390 # number of overall misses 106111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 118983 # number of overall misses 106211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_misses::total 141108 # number of overall misses 106311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3964 # number of ReadReq accesses(hits+misses) 106411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) 106511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 6155 # number of ReadReq accesses(hits+misses) 106611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 120650 # number of WritebackDirty accesses(hits+misses) 106711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 120650 # number of WritebackDirty accesses(hits+misses) 106811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 583378 # number of WritebackClean accesses(hits+misses) 106911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 583378 # number of WritebackClean accesses(hits+misses) 107011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28860 # number of UpgradeReq accesses(hits+misses) 107111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 28860 # number of UpgradeReq accesses(hits+misses) 107211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22520 # number of SCUpgradeReq accesses(hits+misses) 107311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 22520 # number of SCUpgradeReq accesses(hits+misses) 107411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 107511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 107611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523798 # number of ReadCleanReq accesses(hits+misses) 107711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 523798 # number of ReadCleanReq accesses(hits+misses) 107811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172609 # number of ReadSharedReq accesses(hits+misses) 107911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 172609 # number of ReadSharedReq accesses(hits+misses) 108011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3964 # number of demand (read+write) accesses 108111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses 108211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 523798 # number of demand (read+write) accesses 108311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 236224 # number of demand (read+write) accesses 108411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_accesses::total 766177 # number of demand (read+write) accesses 108511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3964 # number of overall (read+write) accesses 108611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses 108711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 523798 # number of overall (read+write) accesses 108811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 236224 # number of overall (read+write) accesses 108911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_accesses::total 766177 # number of overall (read+write) accesses 109011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for ReadReq accesses 109111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136467 # miss rate for ReadReq accesses 109211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.119415 # miss rate for ReadReq accesses 109311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 109411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 109510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 109610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 109711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688910 # miss rate for ReadExReq accesses 109811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.688910 # miss rate for ReadExReq accesses 109911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.040836 # miss rate for ReadCleanReq accesses 110011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.040836 # miss rate for ReadCleanReq accesses 110111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.435423 # miss rate for ReadSharedReq accesses 110211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.435423 # miss rate for ReadSharedReq accesses 110311606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for demand accesses 110411606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136467 # miss rate for demand accesses 110511606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.040836 # miss rate for demand accesses 110611606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.503687 # miss rate for demand accesses 110711606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.184172 # miss rate for demand accesses 110811606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.109990 # miss rate for overall accesses 110911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136467 # miss rate for overall accesses 111011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.040836 # miss rate for overall accesses 111111606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.503687 # miss rate for overall accesses 111211606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.184172 # miss rate for overall accesses 111310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 111410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 111510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 111610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 111710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 111810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111911606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.writebacks::writebacks 32289 # number of writebacks 112011606Sandreas.sandberg@arm.comsystem.cpu1.l2cache.writebacks::total 32289 # number of writebacks 112111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 1533143 # Total number of requests made to the snoop filter. 112211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 773124 # Number of requests hitting in the snoop filter with a single holder of the requested data. 112311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11161 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 112411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 97275 # Total number of snoops made to the snoop filter. 112511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 90578 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 112611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 6697 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 112711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 112811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution 112911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 709156 # Transaction distribution 113011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution 113111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution 113211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 120650 # Transaction distribution 113311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 594539 # Transaction distribution 113411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 28860 # Transaction distribution 113511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22520 # Transaction distribution 113611606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 51380 # Transaction distribution 113711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 113811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 113911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 523798 # Transaction distribution 114011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 172609 # Transaction distribution 114111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571236 # Packet count per connected master and slave (bytes) 114211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778567 # Packet count per connected master and slave (bytes) 114310535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 114411336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 114511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.pkt_count::total 2368499 # Packet count per connected master and slave (bytes) 114611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67014084 # Cumulative packet size per connected master and slave (bytes) 114711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27419302 # Cumulative packet size per connected master and slave (bytes) 114810535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 114911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 115011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size::total 94470778 # Cumulative packet size per connected master and slave (bytes) 115111606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoops 295837 # Total snoops (count) 115211606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoopTraffic 2333632 # Total snoop traffic (bytes) 115311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 1767980 # Request fanout histogram 115411606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.075142 # Request fanout histogram 115511606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.277617 # Request fanout histogram 115610535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 115711606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 1641828 92.86% 92.86% # Request fanout histogram 115811606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 119455 6.76% 99.62% # Request fanout histogram 115911606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 6697 0.38% 100.00% # Request fanout histogram 116010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 116111138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 116210827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 116311606Sandreas.sandberg@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 1767980 # Request fanout histogram 116411570SCurtis.Dunham@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 116510726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30995 # Transaction distribution 116610726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30995 # Transaction distribution 116710726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59419 # Transaction distribution 116810892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 59419 # Transaction distribution 116910726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 117010513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 117111245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 117210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 117310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 117410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 117510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 117610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 117710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 117810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 117910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 118010513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 118110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 118210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 118310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 118410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 118510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 118610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 118710513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 118810726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 118910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 119010513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 119110726Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 119210726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 119310513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 119411245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 119510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 119610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 119710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 119810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 119910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 120010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120310513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 120410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 120710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 120810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 121010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 121110726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 121210513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 121310513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 121410726Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 121511570SCurtis.Dunham@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 121610513SAli.Saidi@ARM.comsystem.iocache.tags.replacements 36442 # number of replacements 121711570SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use 12189885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 121910513SAli.Saidi@ARM.comsystem.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 122010513SAli.Saidi@ARM.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 122111570SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 246641129509 # Cycle when the warmup percentage was hit. 122211570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor 122311336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 122411336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 122510513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 122610513SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 122710513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 122810513SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 328284 # Number of tag accesses 122910513SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 328284 # Number of data accesses 123011570SCurtis.Dunham@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 123110513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 123210513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::total 252 # number of ReadReq misses 123310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 123410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 123511456Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 123611456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 36476 # number of demand (read+write) misses 123711456Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 36476 # number of overall misses 123811456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 36476 # number of overall misses 123910513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 124010513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 124110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 124210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 124311456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 124411456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 124511456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 124611456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 124710513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 124810513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 124910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 125010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 125110513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 125210513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 125310513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 125410513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 12558844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 12568844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 12578844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 12588844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 12598983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 12608983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 126110585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 126210585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 126311570SCurtis.Dunham@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 126411606Sandreas.sandberg@arm.comsystem.l2c.tags.replacements 135163 # number of replacements 126511606Sandreas.sandberg@arm.comsystem.l2c.tags.tagsinuse 65177.726515 # Cycle average of tags in use 126611606Sandreas.sandberg@arm.comsystem.l2c.tags.total_refs 431584 # Total number of references to valid blocks. 126711606Sandreas.sandberg@arm.comsystem.l2c.tags.sampled_refs 200605 # Sample count of references to valid blocks. 126811606Sandreas.sandberg@arm.comsystem.l2c.tags.avg_refs 2.151412 # Average number of references to valid blocks. 126911606Sandreas.sandberg@arm.comsystem.l2c.tags.warmup_cycle 86559025000 # Cycle when the warmup percentage was hit. 127011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::writebacks 6643.934415 # Average occupied blocks per requestor 127111606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 3.937413 # Average occupied blocks per requestor 127211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.032741 # Average occupied blocks per requestor 127311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 7087.737158 # Average occupied blocks per requestor 127411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 43017.411906 # Average occupied blocks per requestor 127511606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1645.646531 # Average occupied blocks per requestor 127611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 6779.026349 # Average occupied blocks per requestor 127711606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::writebacks 0.101378 # Average percentage of cache occupancy 127811570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy 127911606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 128011606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.108150 # Average percentage of cache occupancy 128111606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.656394 # Average percentage of cache occupancy 128211606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.025111 # Average percentage of cache occupancy 128311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.103440 # Average percentage of cache occupancy 128411606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_percent::total 0.994533 # Average percentage of cache occupancy 128511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 128611606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 65436 # Occupied blocks per task id 128711201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 128811606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id 128911606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id 129011606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 15758 # Occupied blocks per task id 129111606Sandreas.sandberg@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 49214 # Occupied blocks per task id 129211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 129311606Sandreas.sandberg@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.998474 # Percentage of cache occupancy per task id 129411606Sandreas.sandberg@arm.comsystem.l2c.tags.tag_accesses 5327823 # Number of tag accesses 129511606Sandreas.sandberg@arm.comsystem.l2c.tags.data_accesses 5327823 # Number of data accesses 129611570SCurtis.Dunham@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 129711606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::writebacks 225157 # number of WritebackDirty hits 129811606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_hits::total 225157 # number of WritebackDirty hits 129911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 10195 # number of UpgradeReq hits 130011606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 3254 # number of UpgradeReq hits 130111606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_hits::total 13449 # number of UpgradeReq hits 130211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 779 # number of SCUpgradeReq hits 130311606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 1161 # number of SCUpgradeReq hits 130411606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_hits::total 1940 # number of SCUpgradeReq hits 130511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 13430 # number of ReadExReq hits 130611606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 3004 # number of ReadExReq hits 130711606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_hits::total 16434 # number of ReadExReq hits 130811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 116 # number of ReadSharedReq hits 130911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 70 # number of ReadSharedReq hits 131011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 42080 # number of ReadSharedReq hits 131111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 82797 # number of ReadSharedReq hits 131211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 36 # number of ReadSharedReq hits 131311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 24 # number of ReadSharedReq hits 131411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 18817 # number of ReadSharedReq hits 131511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 12978 # number of ReadSharedReq hits 131611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_hits::total 156918 # number of ReadSharedReq hits 131711606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 116 # number of demand (read+write) hits 131811606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 70 # number of demand (read+write) hits 131911606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.inst 42080 # number of demand (read+write) hits 132011606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu0.data 96227 # number of demand (read+write) hits 132111606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 36 # number of demand (read+write) hits 132211606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 24 # number of demand (read+write) hits 132311606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.inst 18817 # number of demand (read+write) hits 132411606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::cpu1.data 15982 # number of demand (read+write) hits 132511606Sandreas.sandberg@arm.comsystem.l2c.demand_hits::total 173352 # number of demand (read+write) hits 132611606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 116 # number of overall hits 132711606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 70 # number of overall hits 132811606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.inst 42080 # number of overall hits 132911606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu0.data 96227 # number of overall hits 133011606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 36 # number of overall hits 133111606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 24 # number of overall hits 133211606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.inst 18817 # number of overall hits 133311606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::cpu1.data 15982 # number of overall hits 133411606Sandreas.sandberg@arm.comsystem.l2c.overall_hits::total 173352 # number of overall hits 133511606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 275 # number of UpgradeReq misses 133611606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 112 # number of UpgradeReq misses 133711606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_misses::total 387 # number of UpgradeReq misses 133811606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 30 # number of SCUpgradeReq misses 133911606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 26 # number of SCUpgradeReq misses 134011606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_misses::total 56 # number of SCUpgradeReq misses 134111606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 137059 # number of ReadExReq misses 134211606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 15933 # number of ReadExReq misses 134311606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_misses::total 152992 # number of ReadExReq misses 134411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses 134510892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 134611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 17615 # number of ReadSharedReq misses 134711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 12278 # number of ReadSharedReq misses 134811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 2573 # number of ReadSharedReq misses 134911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1450 # number of ReadSharedReq misses 135011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_misses::total 33926 # number of ReadSharedReq misses 135111606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 135210535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 135311606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.inst 17615 # number of demand (read+write) misses 135411606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu0.data 149337 # number of demand (read+write) misses 135511606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.inst 2573 # number of demand (read+write) misses 135611606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::cpu1.data 17383 # number of demand (read+write) misses 135711606Sandreas.sandberg@arm.comsystem.l2c.demand_misses::total 186918 # number of demand (read+write) misses 135811606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 135910535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 136011606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.inst 17615 # number of overall misses 136111606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu0.data 149337 # number of overall misses 136211606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.inst 2573 # number of overall misses 136311606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::cpu1.data 17383 # number of overall misses 136411606Sandreas.sandberg@arm.comsystem.l2c.overall_misses::total 186918 # number of overall misses 136511606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 225157 # number of WritebackDirty accesses(hits+misses) 136611606Sandreas.sandberg@arm.comsystem.l2c.WritebackDirty_accesses::total 225157 # number of WritebackDirty accesses(hits+misses) 136711606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 10470 # number of UpgradeReq accesses(hits+misses) 136811606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3366 # number of UpgradeReq accesses(hits+misses) 136911606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_accesses::total 13836 # number of UpgradeReq accesses(hits+misses) 137011606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 809 # number of SCUpgradeReq accesses(hits+misses) 137111606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1187 # number of SCUpgradeReq accesses(hits+misses) 137211606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_accesses::total 1996 # number of SCUpgradeReq accesses(hits+misses) 137311606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 150489 # number of ReadExReq accesses(hits+misses) 137411606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 18937 # number of ReadExReq accesses(hits+misses) 137511606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_accesses::total 169426 # number of ReadExReq accesses(hits+misses) 137611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 124 # number of ReadSharedReq accesses(hits+misses) 137711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 72 # number of ReadSharedReq accesses(hits+misses) 137811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 59695 # number of ReadSharedReq accesses(hits+misses) 137911606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 95075 # number of ReadSharedReq accesses(hits+misses) 138011606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 36 # number of ReadSharedReq accesses(hits+misses) 138111606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 24 # number of ReadSharedReq accesses(hits+misses) 138211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 21390 # number of ReadSharedReq accesses(hits+misses) 138311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 14428 # number of ReadSharedReq accesses(hits+misses) 138411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_accesses::total 190844 # number of ReadSharedReq accesses(hits+misses) 138511606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 124 # number of demand (read+write) accesses 138611606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 72 # number of demand (read+write) accesses 138711606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.inst 59695 # number of demand (read+write) accesses 138811606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu0.data 245564 # number of demand (read+write) accesses 138911606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 36 # number of demand (read+write) accesses 139011606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 24 # number of demand (read+write) accesses 139111606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.inst 21390 # number of demand (read+write) accesses 139211606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::cpu1.data 33365 # number of demand (read+write) accesses 139311606Sandreas.sandberg@arm.comsystem.l2c.demand_accesses::total 360270 # number of demand (read+write) accesses 139411606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 124 # number of overall (read+write) accesses 139511606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 72 # number of overall (read+write) accesses 139611606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.inst 59695 # number of overall (read+write) accesses 139711606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu0.data 245564 # number of overall (read+write) accesses 139811606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 36 # number of overall (read+write) accesses 139911606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 24 # number of overall (read+write) accesses 140011606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.inst 21390 # number of overall (read+write) accesses 140111606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::cpu1.data 33365 # number of overall (read+write) accesses 140211606Sandreas.sandberg@arm.comsystem.l2c.overall_accesses::total 360270 # number of overall (read+write) accesses 140311606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.026266 # miss rate for UpgradeReq accesses 140411606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.033274 # miss rate for UpgradeReq accesses 140511606Sandreas.sandberg@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.027971 # miss rate for UpgradeReq accesses 140611606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.037083 # miss rate for SCUpgradeReq accesses 140711606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.021904 # miss rate for SCUpgradeReq accesses 140811606Sandreas.sandberg@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.028056 # miss rate for SCUpgradeReq accesses 140911606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.910758 # miss rate for ReadExReq accesses 141011606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.841369 # miss rate for ReadExReq accesses 141111606Sandreas.sandberg@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.903002 # miss rate for ReadExReq accesses 141211606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for ReadSharedReq accesses 141311606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.027778 # miss rate for ReadSharedReq accesses 141411606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.295083 # miss rate for ReadSharedReq accesses 141511606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.129140 # miss rate for ReadSharedReq accesses 141611606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.120290 # miss rate for ReadSharedReq accesses 141711606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.100499 # miss rate for ReadSharedReq accesses 141811606Sandreas.sandberg@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.177768 # miss rate for ReadSharedReq accesses 141911606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for demand accesses 142011606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.027778 # miss rate for demand accesses 142111606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.295083 # miss rate for demand accesses 142211606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.608139 # miss rate for demand accesses 142311606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.120290 # miss rate for demand accesses 142411606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.520995 # miss rate for demand accesses 142511606Sandreas.sandberg@arm.comsystem.l2c.demand_miss_rate::total 0.518828 # miss rate for demand accesses 142611606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.064516 # miss rate for overall accesses 142711606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.027778 # miss rate for overall accesses 142811606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.295083 # miss rate for overall accesses 142911606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.608139 # miss rate for overall accesses 143011606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.120290 # miss rate for overall accesses 143111606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.520995 # miss rate for overall accesses 143211606Sandreas.sandberg@arm.comsystem.l2c.overall_miss_rate::total 0.518828 # miss rate for overall accesses 143310535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 143410535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 143510535Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 143610535Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 143710535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 143810535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 143911606Sandreas.sandberg@arm.comsystem.l2c.writebacks::writebacks 102405 # number of writebacks 144011606Sandreas.sandberg@arm.comsystem.l2c.writebacks::total 102405 # number of writebacks 144111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 459549 # Total number of requests made to the snoop filter. 144211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 242014 # Number of requests hitting in the snoop filter with a single holder of the requested data. 144311502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 144411502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 144511502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 144611502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 144711570SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 144811570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 43995 # Transaction distribution 144911606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 78173 # Transaction distribution 145011570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 30844 # Transaction distribution 145111570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 30844 # Transaction distribution 145211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 138595 # Transaction distribution 145311606Sandreas.sandberg@arm.comsystem.membus.trans_dist::CleanEvict 11037 # Transaction distribution 145411606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq 47132 # Transaction distribution 145511606Sandreas.sandberg@arm.comsystem.membus.trans_dist::SCUpgradeReq 38991 # Transaction distribution 145611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeResp 461 # Transaction distribution 145711606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExReq 153373 # Transaction distribution 145811606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExResp 152974 # Transaction distribution 145911606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadSharedReq 34178 # Transaction distribution 146010892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 146110892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 146210726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 146310535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 146411570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) 146511606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 602273 # Packet count per connected master and slave (bytes) 146611606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 723651 # Packet count per connected master and slave (bytes) 146711336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 146811336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) 146911606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 833045 # Packet count per connected master and slave (bytes) 147010726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 147110535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 147211570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) 147311606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18572232 # Cumulative packet size per connected master and slave (bytes) 147411606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 18762002 # Cumulative packet size per connected master and slave (bytes) 147510892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 147610892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 147711606Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 21094290 # Cumulative packet size per connected master and slave (bytes) 147810535Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 147911570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 148011606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 534369 # Request fanout histogram 148111606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::mean 0.010375 # Request fanout histogram 148211606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::stdev 0.101327 # Request fanout histogram 148310535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 148411606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0 528825 98.96% 98.96% # Request fanout histogram 148511606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::1 5544 1.04% 100.00% # Request fanout histogram 148610535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 148710535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 148811502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 148910535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 149011606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 534369 # Request fanout histogram 149111570SCurtis.Dunham@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 149211570SCurtis.Dunham@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 149311570SCurtis.Dunham@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 149411570SCurtis.Dunham@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 149511570SCurtis.Dunham@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 149611570SCurtis.Dunham@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 149711570SCurtis.Dunham@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 149811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 149911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 150011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 150111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 150211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 150311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 150411570SCurtis.Dunham@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 150511570SCurtis.Dunham@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 150610535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 150710535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 150810535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 150910535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 151010535Sandreas.hansson@arm.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 151110535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 151210535Sandreas.hansson@arm.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 151310535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 151410535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 151510535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 151610535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 151710535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 151810535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 151910535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 152010535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 152110535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 152210535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 152310535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 152410535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 152510535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 152610535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 152710535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 152810535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 152910535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 153010535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 153110535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 153210535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 153310535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 153410535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 153510535Sandreas.hansson@arm.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 153610535Sandreas.hansson@arm.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 153711570SCurtis.Dunham@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 153811570SCurtis.Dunham@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 153911570SCurtis.Dunham@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154011570SCurtis.Dunham@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154111570SCurtis.Dunham@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154211570SCurtis.Dunham@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154311570SCurtis.Dunham@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 154511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 154611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 154711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 154811570SCurtis.Dunham@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154911570SCurtis.Dunham@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155011570SCurtis.Dunham@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155111570SCurtis.Dunham@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155211570SCurtis.Dunham@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155311570SCurtis.Dunham@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155411570SCurtis.Dunham@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155511570SCurtis.Dunham@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155611570SCurtis.Dunham@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155711570SCurtis.Dunham@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155811570SCurtis.Dunham@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155911570SCurtis.Dunham@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 156011606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.tot_requests 898844 # Total number of requests made to the snoop filter. 156111606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 454083 # Number of requests hitting in the snoop filter with a single holder of the requested data. 156211606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 154581 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 156311606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 30372 # Total number of snoops made to the snoop filter. 156411606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 29420 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 156511606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 952 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 156611570SCurtis.Dunham@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 156711570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 43999 # Transaction distribution 156811606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadResp 337174 # Transaction distribution 156911570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 30844 # Transaction distribution 157011570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 30844 # Transaction distribution 157111606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 225157 # Transaction distribution 157211606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::CleanEvict 65355 # Transaction distribution 157311606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 60563 # Transaction distribution 157411606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 40931 # Transaction distribution 157511606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 101494 # Transaction distribution 157611606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadExReq 213640 # Transaction distribution 157711606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadExResp 213640 # Transaction distribution 157811606Sandreas.sandberg@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 293175 # Transaction distribution 157911606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1214281 # Packet count per connected master and slave (bytes) 158011606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 442535 # Packet count per connected master and slave (bytes) 158111606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_count::total 1656816 # Packet count per connected master and slave (bytes) 158211606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36095992 # Cumulative packet size per connected master and slave (bytes) 158311606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10996714 # Cumulative packet size per connected master and slave (bytes) 158411606Sandreas.sandberg@arm.comsystem.toL2Bus.pkt_size::total 47092706 # Cumulative packet size per connected master and slave (bytes) 158511606Sandreas.sandberg@arm.comsystem.toL2Bus.snoops 140680 # Total snoops (count) 158611606Sandreas.sandberg@arm.comsystem.toL2Bus.snoopTraffic 6570496 # Total snoop traffic (bytes) 158711606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::samples 1114107 # Request fanout histogram 158811606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::mean 0.326086 # Request fanout histogram 158911606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.470599 # Request fanout histogram 159010535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 159111606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::0 751764 67.48% 67.48% # Request fanout histogram 159211606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::1 361391 32.44% 99.91% # Request fanout histogram 159311606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::2 952 0.09% 100.00% # Request fanout histogram 159410535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 159511138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 159610535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 159711606Sandreas.sandberg@arm.comsystem.toL2Bus.snoop_fanout::total 1114107 # Request fanout histogram 15988844SAli.Saidi@ARM.com 15998844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1600