stats.txt revision 11589
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311336Sandreas.hansson@arm.comsim_seconds 2.802883 # Number of seconds simulated 411570SCurtis.Dunham@arm.comsim_ticks 2802883274000 # Number of ticks simulated 511570SCurtis.Dunham@arm.comfinal_tick 2802883274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711589SCurtis.Dunham@arm.comhost_inst_rate 992891 # Simulator instruction rate (inst/s) 811589SCurtis.Dunham@arm.comhost_op_rate 1209822 # Simulator op (including micro ops) rate (op/s) 911589SCurtis.Dunham@arm.comhost_tick_rate 18955432442 # Simulator tick rate (ticks/s) 1011589SCurtis.Dunham@arm.comhost_mem_usage 590980 # Number of bytes of host memory used 1111589SCurtis.Dunham@arm.comhost_seconds 147.87 # Real time elapsed on the host 1211570SCurtis.Dunham@arm.comsim_insts 146815798 # Number of instructions simulated 1311570SCurtis.Dunham@arm.comsim_ops 178892721 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611570SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 1711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory 1810409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1911570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 1106276 # Number of bytes read from this memory 2011570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 9415076 # Number of bytes read from this memory 2111570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory 2211570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 154452 # Number of bytes read from this memory 2311570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 1081616 # Number of bytes read from this memory 2410535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2511570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 11759020 # Number of bytes read from this memory 2611570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 1106276 # Number of instructions bytes read from this memory 2711570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 154452 # Number of instructions bytes read from this memory 2811570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 1260728 # Number of instructions bytes read from this memory 2911570SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 8476800 # Number of bytes written to this memory 3010827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 3110409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3211570SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 8494364 # Number of bytes written to this memory 3311570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory 3410409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 3511570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 25739 # Number of read requests responded to by this memory 3611570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 147630 # Number of read requests responded to by this memory 3711570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory 3811570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 2568 # Number of read requests responded to by this memory 3911570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 16920 # Number of read requests responded to by this memory 4010535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 4111570SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 192882 # Number of read requests responded to by this memory 4211570SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 132450 # Number of write requests responded to by this memory 4310827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 4410409Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4511570SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 136841 # Number of write requests responded to by this memory 4611570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) 4710513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4811570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 394692 # Total read bandwidth from this memory (bytes/s) 4911570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 3359068 # Total read bandwidth from this memory (bytes/s) 5011570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) 5111570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 55105 # Total read bandwidth from this memory (bytes/s) 5211570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 385894 # Total read bandwidth from this memory (bytes/s) 5310535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 5411570SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 4195330 # Total read bandwidth from this memory (bytes/s) 5511570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 394692 # Instruction read bandwidth from this memory (bytes/s) 5611570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 55105 # Instruction read bandwidth from this memory (bytes/s) 5711570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 449797 # Instruction read bandwidth from this memory (bytes/s) 5811570SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 3024314 # Write bandwidth from this memory (bytes/s) 5910827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 6010513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 6111570SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 3030581 # Write bandwidth from this memory (bytes/s) 6211570SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 3024314 # Total bandwidth to/from this memory (bytes/s) 6311570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) 6410513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6511570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 394692 # Total bandwidth to/from this memory (bytes/s) 6611570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 3365320 # Total bandwidth to/from this memory (bytes/s) 6711570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) 6811570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 55105 # Total bandwidth to/from this memory (bytes/s) 6911570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 385908 # Total bandwidth to/from this memory (bytes/s) 7010585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 7111570SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 7225911 # Total bandwidth to/from this memory (bytes/s) 7211570SCurtis.Dunham@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 7310517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 7410517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 7510517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7610517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7710517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7810517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 7910517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 8010517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 8110517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 8210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 8310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 8410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 8510517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 8610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 8710517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 8810517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 8910517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 9010517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 9111570SCurtis.Dunham@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 9211570SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 9311570SCurtis.Dunham@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 948844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 9510513SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 9610513SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 9710513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 9810513SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 9910513SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 10010535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 10111570SCurtis.Dunham@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 10210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 10310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 10410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 10510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 10610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 10710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 10810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 10910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 11010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 11110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 11210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 11310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 11410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 11510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 11610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 11710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 11810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 11910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 12010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 12110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 12210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 12310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 12410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 12510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 12610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 12710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 12810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 12910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 13010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 13111570SCurtis.Dunham@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 13211336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 7964 # Table walker walks requested 13311336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors 13411336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency 13511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 13611336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency 13710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 13810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 13910628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 14011336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated 14111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated 14211336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated 14311336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst 14410628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 14511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 14611336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 14710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 14811336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 14911336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 15010535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 15110535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 15211570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 20338226 # DTB read hits 15311336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 6871 # DTB read misses 15411570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 16389726 # DTB write hits 15510535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1093 # DTB write misses 15610535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 15710535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 15810535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 15910535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 16011547Sandreas.sandberg@arm.comsystem.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB 16110535Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 16210535Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 16310535Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 16410535Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 16511570SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 20345097 # DTB read accesses 16611570SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 16390819 # DTB write accesses 16710535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 16811570SCurtis.Dunham@arm.comsystem.cpu0.dtb.hits 36727952 # DTB hits 16911336Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 7964 # DTB misses 17011570SCurtis.Dunham@arm.comsystem.cpu0.dtb.accesses 36735916 # DTB accesses 17111570SCurtis.Dunham@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 17210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 17310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 17410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 17510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 17610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 17710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 17810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 17910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 18010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 18110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 18210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 18310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 18410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 18510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 18610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 18710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 18810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 18910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 19010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 19110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 19210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 19310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 19410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 19510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 19610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 19710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 19810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 19910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 20010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 20111570SCurtis.Dunham@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 20210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 3358 # Table walker walks requested 20310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 20410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 20510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 20610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 20710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 20810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 20910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 21010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 21110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 21210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 21310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 21410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 21510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 21610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 21710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 21810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 21910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 22011570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 97433318 # ITB inst hits 22110535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 3358 # ITB inst misses 22210535Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 22310535Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 22410535Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 22510535Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 22610535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 22710535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 22810535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 22910535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 23011547Sandreas.sandberg@arm.comsystem.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB 23110535Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 23210535Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 23310535Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 23410535Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 23510535Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 23610535Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 23711570SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_accesses 97436676 # ITB inst accesses 23811570SCurtis.Dunham@arm.comsystem.cpu0.itb.hits 97433318 # DTB hits 23910535Sandreas.hansson@arm.comsystem.cpu0.itb.misses 3358 # DTB misses 24011570SCurtis.Dunham@arm.comsystem.cpu0.itb.accesses 97436676 # DTB accesses 24111570SCurtis.Dunham@arm.comsystem.cpu0.numPwrStateTransitions 3946 # Number of power state transitions 24211570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::samples 1973 # Distribution of time spent in the clock gated state 24311570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::mean 1390823508.162189 # Distribution of time spent in the clock gated state 24411570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 23082851772.246098 # Distribution of time spent in the clock gated state 24511570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 1157 58.64% 58.64% # Distribution of time spent in the clock gated state 24611570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 810 41.05% 99.70% # Distribution of time spent in the clock gated state 24711530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state 24811530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state 24911530Sandreas.sandberg@arm.comsystem.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state 25011570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 25111570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 499983361388 # Distribution of time spent in the clock gated state 25211570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateClkGateDist::total 1973 # Distribution of time spent in the clock gated state 25311570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 58788492396 # Cumulative time (in ticks) in various power states 25411570SCurtis.Dunham@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 2744094781604 # Cumulative time (in ticks) in various power states 25511570SCurtis.Dunham@arm.comsystem.cpu0.numCycles 5605768522 # number of cpu cycles simulated 25610535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 25710535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 25811201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 25911570SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 1973 # number of quiesce instructions executed 26011570SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 95420875 # Number of instructions committed 26111570SCurtis.Dunham@arm.comsystem.cpu0.committedOps 115552929 # Number of ops (including micro ops) committed 26211570SCurtis.Dunham@arm.comsystem.cpu0.num_int_alu_accesses 100755950 # Number of integer alu accesses 26310535Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 26411570SCurtis.Dunham@arm.comsystem.cpu0.num_func_calls 8000037 # number of times a function call or return occured 26511570SCurtis.Dunham@arm.comsystem.cpu0.num_conditional_control_insts 13203579 # number of instructions that are conditional controls 26611570SCurtis.Dunham@arm.comsystem.cpu0.num_int_insts 100755950 # number of integer instructions 26710535Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 9755 # number of float instructions 26811589SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_reads 182434923 # number of times the integer registers were read 26911570SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_writes 69130439 # number of times the integer registers were written 27010535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 27110535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 27211570SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_reads 349948963 # number of times the CC registers were read 27311570SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_writes 44904772 # number of times the CC registers were written 27411570SCurtis.Dunham@arm.comsystem.cpu0.num_mem_refs 37870790 # number of memory refs 27511570SCurtis.Dunham@arm.comsystem.cpu0.num_load_insts 20595754 # Number of load instructions 27611570SCurtis.Dunham@arm.comsystem.cpu0.num_store_insts 17275036 # Number of store instructions 27711570SCurtis.Dunham@arm.comsystem.cpu0.num_idle_cycles 5488191495.802790 # Number of idle cycles 27811570SCurtis.Dunham@arm.comsystem.cpu0.num_busy_cycles 117577026.197211 # Number of busy cycles 27911570SCurtis.Dunham@arm.comsystem.cpu0.not_idle_fraction 0.020974 # Percentage of non-idle cycles 28011570SCurtis.Dunham@arm.comsystem.cpu0.idle_fraction 0.979026 # Percentage of idle cycles 28111570SCurtis.Dunham@arm.comsystem.cpu0.Branches 21940702 # Number of branches fetched 28210535Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 28311570SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntAlu 78882840 67.49% 67.50% # Class of executed instruction 28411570SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntMult 110618 0.09% 67.59% # Class of executed instruction 28510535Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 28610535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 28710535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 28810535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 28910535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 29010535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 29110535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 29210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 29310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 29410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 29510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 29610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 29710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 29810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 29910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 30010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 30110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 30210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 30310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 30410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 30510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 30610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 30710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 30810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 30910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 31010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 31110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 31211570SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemRead 20595754 17.62% 85.22% # Class of executed instruction 31311570SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemWrite 17275036 14.78% 100.00% # Class of executed instruction 31410535Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 31510535Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 31611570SCurtis.Dunham@arm.comsystem.cpu0.op_class::total 116874608 # Class of executed instruction 31711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 31811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 693483 # number of replacements 31911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 494.728102 # Cycle average of tags in use 32011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 35929530 # Total number of references to valid blocks. 32111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 693995 # Sample count of references to valid blocks. 32211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 51.772030 # Average number of references to valid blocks. 32310827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 32411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.728102 # Average occupied blocks per requestor 32511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966266 # Average percentage of cache occupancy 32611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.966266 # Average percentage of cache occupancy 32710535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 32810535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 32910535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 33010535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 33110535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 33211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 74108220 # Number of tag accesses 33311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 74108220 # Number of data accesses 33411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 33511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 19107088 # number of ReadReq hits 33611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 19107088 # number of ReadReq hits 33711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 15689092 # number of WriteReq hits 33811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 15689092 # number of WriteReq hits 33911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 346042 # number of SoftPFReq hits 34011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 346042 # number of SoftPFReq hits 34111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379604 # number of LoadLockedReq hits 34211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 379604 # number of LoadLockedReq hits 34311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 363038 # number of StoreCondReq hits 34411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 363038 # number of StoreCondReq hits 34511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 34796180 # number of demand (read+write) hits 34611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 34796180 # number of demand (read+write) hits 34711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 35142222 # number of overall hits 34811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 35142222 # number of overall hits 34911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 373135 # number of ReadReq misses 35011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 373135 # number of ReadReq misses 35111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 295767 # number of WriteReq misses 35211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 295767 # number of WriteReq misses 35311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses 35411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses 35511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6741 # number of LoadLockedReq misses 35611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 6741 # number of LoadLockedReq misses 35711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 18421 # number of StoreCondReq misses 35811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 18421 # number of StoreCondReq misses 35911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 668902 # number of demand (read+write) misses 36011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 668902 # number of demand (read+write) misses 36111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 769224 # number of overall misses 36211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 769224 # number of overall misses 36311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 19480223 # number of ReadReq accesses(hits+misses) 36411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 19480223 # number of ReadReq accesses(hits+misses) 36511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 15984859 # number of WriteReq accesses(hits+misses) 36611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 15984859 # number of WriteReq accesses(hits+misses) 36711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446364 # number of SoftPFReq accesses(hits+misses) 36811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 446364 # number of SoftPFReq accesses(hits+misses) 36911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386345 # number of LoadLockedReq accesses(hits+misses) 37011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 386345 # number of LoadLockedReq accesses(hits+misses) 37111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381459 # number of StoreCondReq accesses(hits+misses) 37211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 381459 # number of StoreCondReq accesses(hits+misses) 37311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 35465082 # number of demand (read+write) accesses 37411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 35465082 # number of demand (read+write) accesses 37511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 35911446 # number of overall (read+write) accesses 37611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 35911446 # number of overall (read+write) accesses 37711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019155 # miss rate for ReadReq accesses 37811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.019155 # miss rate for ReadReq accesses 37911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 38011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 38111570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224754 # miss rate for SoftPFReq accesses 38211570SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.224754 # miss rate for SoftPFReq accesses 38311570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017448 # miss rate for LoadLockedReq accesses 38411570SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017448 # miss rate for LoadLockedReq accesses 38511570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048291 # miss rate for StoreCondReq accesses 38611570SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.048291 # miss rate for StoreCondReq accesses 38711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.018861 # miss rate for demand accesses 38811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.018861 # miss rate for demand accesses 38911570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.021420 # miss rate for overall accesses 39011570SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.021420 # miss rate for overall accesses 39110535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 39210535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 39310535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 39410535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 39510535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39610535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39711570SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 693483 # number of writebacks 39811570SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 693483 # number of writebacks 39911570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 40011570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 1109362 # number of replacements 40111336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 40211570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 96325777 # Total number of references to valid blocks. 40311570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 1109874 # Sample count of references to valid blocks. 40411570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 86.789831 # Average number of references to valid blocks. 40511570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.warmup_cycle 6345718500 # Cycle when the warmup percentage was hit. 40611336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 40710535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 40810535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 40910535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 41010535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 41110535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 41210535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 41310535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 41411570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 195981203 # Number of tag accesses 41511570SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 195981203 # Number of data accesses 41611570SCurtis.Dunham@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 41711570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 96325777 # number of ReadReq hits 41811570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 96325777 # number of ReadReq hits 41911570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 96325777 # number of demand (read+write) hits 42011570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 96325777 # number of demand (read+write) hits 42111570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 96325777 # number of overall hits 42211570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 96325777 # number of overall hits 42311570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1109883 # number of ReadReq misses 42411570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 1109883 # number of ReadReq misses 42511570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 1109883 # number of demand (read+write) misses 42611570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 1109883 # number of demand (read+write) misses 42711570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 1109883 # number of overall misses 42811570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 1109883 # number of overall misses 42911570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 97435660 # number of ReadReq accesses(hits+misses) 43011570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 97435660 # number of ReadReq accesses(hits+misses) 43111570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 97435660 # number of demand (read+write) accesses 43211570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 97435660 # number of demand (read+write) accesses 43311570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 97435660 # number of overall (read+write) accesses 43411570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 97435660 # number of overall (read+write) accesses 43511570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011391 # miss rate for ReadReq accesses 43611570SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 43711570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011391 # miss rate for demand accesses 43811570SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011391 # miss rate for demand accesses 43911570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011391 # miss rate for overall accesses 44011570SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011391 # miss rate for overall accesses 44110535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 44210535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 44310535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 44410535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 44510535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 44610535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 44711570SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 1109362 # number of writebacks 44811570SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 1109362 # number of writebacks 44911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 45010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 45110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 45210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 45310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 45410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 45510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 45611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 45711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.replacements 249561 # number of replacements 45811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16130.656320 # Cycle average of tags in use 45911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.total_refs 2729360 # Total number of references to valid blocks. 46011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.sampled_refs 265678 # Sample count of references to valid blocks. 46111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.avg_refs 10.273188 # Average number of references to valid blocks. 46211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 46311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 16129.249413 # Average occupied blocks per requestor 46411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.326952 # Average occupied blocks per requestor 46511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.079954 # Average occupied blocks per requestor 46611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.984451 # Average percentage of cache occupancy 46711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000081 # Average percentage of cache occupancy 46811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 46911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.984537 # Average percentage of cache occupancy 47011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id 47111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 16104 # Occupied blocks per task id 47211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 47311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 47411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id 47511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id 47611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 349 # Occupied blocks per task id 47711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5522 # Occupied blocks per task id 47811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7440 # Occupied blocks per task id 47911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2639 # Occupied blocks per task id 48011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id 48111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.982910 # Percentage of cache occupancy per task id 48211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tag_accesses 59687833 # Number of tag accesses 48311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.data_accesses 59687833 # Number of data accesses 48411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 48511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10176 # number of ReadReq hits 48611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4489 # number of ReadReq hits 48711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 14665 # number of ReadReq hits 48811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 510613 # number of WritebackDirty hits 48911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 510613 # number of WritebackDirty hits 49011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 1264371 # number of WritebackClean hits 49111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 1264371 # number of WritebackClean hits 49211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 94352 # number of ReadExReq hits 49311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 94352 # number of ReadExReq hits 49411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1067857 # number of ReadCleanReq hits 49511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 1067857 # number of ReadCleanReq hits 49611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352287 # number of ReadSharedReq hits 49711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 352287 # number of ReadSharedReq hits 49811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10176 # number of demand (read+write) hits 49911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 4489 # number of demand (read+write) hits 50011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 1067857 # number of demand (read+write) hits 50111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 446639 # number of demand (read+write) hits 50211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::total 1529161 # number of demand (read+write) hits 50311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10176 # number of overall hits 50411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 4489 # number of overall hits 50511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 1067857 # number of overall hits 50611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 446639 # number of overall hits 50711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::total 1529161 # number of overall hits 50811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 214 # number of ReadReq misses 50911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 138 # number of ReadReq misses 51011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 352 # number of ReadReq misses 51111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26245 # number of UpgradeReq misses 51211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 26245 # number of UpgradeReq misses 51311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18421 # number of SCUpgradeReq misses 51411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 18421 # number of SCUpgradeReq misses 51511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 175170 # number of ReadExReq misses 51611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 175170 # number of ReadExReq misses 51711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 42026 # number of ReadCleanReq misses 51811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 42026 # number of ReadCleanReq misses 51911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127911 # number of ReadSharedReq misses 52011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 127911 # number of ReadSharedReq misses 52111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 214 # number of demand (read+write) misses 52211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 138 # number of demand (read+write) misses 52311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 42026 # number of demand (read+write) misses 52411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 303081 # number of demand (read+write) misses 52511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::total 345459 # number of demand (read+write) misses 52611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 214 # number of overall misses 52711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 138 # number of overall misses 52811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 42026 # number of overall misses 52911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 303081 # number of overall misses 53011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::total 345459 # number of overall misses 53111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10390 # number of ReadReq accesses(hits+misses) 53211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) 53311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 15017 # number of ReadReq accesses(hits+misses) 53411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 510613 # number of WritebackDirty accesses(hits+misses) 53511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 510613 # number of WritebackDirty accesses(hits+misses) 53611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 1264371 # number of WritebackClean accesses(hits+misses) 53711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 1264371 # number of WritebackClean accesses(hits+misses) 53811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26245 # number of UpgradeReq accesses(hits+misses) 53911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 26245 # number of UpgradeReq accesses(hits+misses) 54011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18421 # number of SCUpgradeReq accesses(hits+misses) 54111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 18421 # number of SCUpgradeReq accesses(hits+misses) 54211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269522 # number of ReadExReq accesses(hits+misses) 54311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 269522 # number of ReadExReq accesses(hits+misses) 54411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1109883 # number of ReadCleanReq accesses(hits+misses) 54511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 1109883 # number of ReadCleanReq accesses(hits+misses) 54611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480198 # number of ReadSharedReq accesses(hits+misses) 54711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 480198 # number of ReadSharedReq accesses(hits+misses) 54811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10390 # number of demand (read+write) accesses 54911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses 55011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 1109883 # number of demand (read+write) accesses 55111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 749720 # number of demand (read+write) accesses 55211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::total 1874620 # number of demand (read+write) accesses 55311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10390 # number of overall (read+write) accesses 55411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses 55511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 1109883 # number of overall (read+write) accesses 55611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 749720 # number of overall (read+write) accesses 55711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::total 1874620 # number of overall (read+write) accesses 55811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020597 # miss rate for ReadReq accesses 55911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.029825 # miss rate for ReadReq accesses 56011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.023440 # miss rate for ReadReq accesses 56111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 56211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 56310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 56410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 56511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649928 # miss rate for ReadExReq accesses 56611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.649928 # miss rate for ReadExReq accesses 56711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037865 # miss rate for ReadCleanReq accesses 56811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037865 # miss rate for ReadCleanReq accesses 56911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266371 # miss rate for ReadSharedReq accesses 57011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266371 # miss rate for ReadSharedReq accesses 57111570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020597 # miss rate for demand accesses 57211570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.029825 # miss rate for demand accesses 57311570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037865 # miss rate for demand accesses 57411570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404259 # miss rate for demand accesses 57511570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.184282 # miss rate for demand accesses 57611570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020597 # miss rate for overall accesses 57711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.029825 # miss rate for overall accesses 57811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037865 # miss rate for overall accesses 57911570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404259 # miss rate for overall accesses 58011570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.184282 # miss rate for overall accesses 58110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 58210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 58310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 58410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 58510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 58610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 58711570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::writebacks 192746 # number of writebacks 58811570SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::total 192746 # number of writebacks 58911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 3719480 # Total number of requests made to the snoop filter. 59011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 1859901 # Number of requests hitting in the snoop filter with a single holder of the requested data. 59111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27861 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 59211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 218561 # Total number of snoops made to the snoop filter. 59311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215432 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 59411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3129 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 59511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 59611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution 59711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 1651491 # Transaction distribution 59811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28340 # Transaction distribution 59911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28340 # Transaction distribution 60011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 510613 # Transaction distribution 60111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 1292232 # Transaction distribution 60211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 26245 # Transaction distribution 60311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18421 # Transaction distribution 60411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 44666 # Transaction distribution 60511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 269522 # Transaction distribution 60611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 269522 # Transaction distribution 60711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 1109883 # Transaction distribution 60811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 480198 # Transaction distribution 60911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347172 # Packet count per connected master and slave (bytes) 61011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402087 # Packet count per connected master and slave (bytes) 61110535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 61211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 61311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count::total 5790883 # Packet count per connected master and slave (bytes) 61411570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142067768 # Cumulative packet size per connected master and slave (bytes) 61511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92555520 # Cumulative packet size per connected master and slave (bytes) 61610535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 61711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 61811570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size::total 234706536 # Cumulative packet size per connected master and slave (bytes) 61911570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoops 623474 # Total snoops (count) 62011570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoopTraffic 12368448 # Total snoop traffic (bytes) 62111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 4317750 # Request fanout histogram 62211570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.067119 # Request fanout histogram 62311570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.253107 # Request fanout histogram 62410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 62511570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 4031077 93.36% 93.36% # Request fanout histogram 62611570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 283544 6.57% 99.93% # Request fanout histogram 62711570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 3129 0.07% 100.00% # Request fanout histogram 62810535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 62911138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 63010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 63111570SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 4317750 # Request fanout histogram 63211570SCurtis.Dunham@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 63310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 63410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 63510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 63610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 63710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 63810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 63910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 64010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 64110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 64210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 64310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 64410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 64510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 64610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 64710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 64810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 65110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 65210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 65310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 65410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 65710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 65910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 66110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 66211570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 66311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 3359 # Table walker walks requested 66411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 66511336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 66611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 66711336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 66811570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::samples -1804201736 # Table walker pending requests distribution 66911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1804201736 100.00% 100.00% # Table walker pending requests distribution 67011570SCurtis.Dunham@arm.comsystem.cpu1.dtb.walker.walksPending::total -1804201736 # Table walker pending requests distribution 67111336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated 67211336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated 67311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated 67411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst 67510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 67611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst 67711336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst 67810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 67911336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst 68011336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst 68110535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 68210535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 68311570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 12172373 # DTB read hits 68411336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 2853 # DTB read misses 68511570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 7586083 # DTB write hits 68610535Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 506 # DTB write misses 68710535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 68810535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 68910535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 69010535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 69111547Sandreas.sandberg@arm.comsystem.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB 69210535Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 69310535Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 69410535Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 69510535Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 69611570SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 12175226 # DTB read accesses 69711570SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 7586589 # DTB write accesses 69810535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 69911570SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 19758456 # DTB hits 70011336Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 3359 # DTB misses 70111570SCurtis.Dunham@arm.comsystem.cpu1.dtb.accesses 19761815 # DTB accesses 70211570SCurtis.Dunham@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 70310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 70410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 70610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 70810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 70910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 71010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 71110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 71210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 71310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 71410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 71510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 71610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 71710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 71810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 71910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 72110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 72210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 72310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 72410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 72510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 72610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 72810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 72910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 73010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 73110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 73211570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 73310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 1734 # Table walker walks requested 73410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 73510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 73610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 73710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 73811570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::samples -1804204236 # Table walker pending requests distribution 73911570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::0 -1804204236 100.00% 100.00% # Table walker pending requests distribution 74011570SCurtis.Dunham@arm.comsystem.cpu1.itb.walker.walksPending::total -1804204236 # Table walker pending requests distribution 74110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 74210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 74310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 74410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 74610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 74710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 74910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 75010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 75111570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_hits 53665127 # ITB inst hits 75210535Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 1734 # ITB inst misses 75310535Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 75410535Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 75510535Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 75610535Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 75710535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 75810535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 75910535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 76010535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 76111547Sandreas.sandberg@arm.comsystem.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB 76210535Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 76310535Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 76410535Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 76510535Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 76610535Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 76710535Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 76811570SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_accesses 53666861 # ITB inst accesses 76911570SCurtis.Dunham@arm.comsystem.cpu1.itb.hits 53665127 # DTB hits 77010535Sandreas.hansson@arm.comsystem.cpu1.itb.misses 1734 # DTB misses 77111570SCurtis.Dunham@arm.comsystem.cpu1.itb.accesses 53666861 # DTB accesses 77211570SCurtis.Dunham@arm.comsystem.cpu1.numPwrStateTransitions 5467 # Number of power state transitions 77311570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::samples 2734 # Distribution of time spent in the clock gated state 77411570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::mean 1013195942.406364 # Distribution of time spent in the clock gated state 77511570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 25944771719.895676 # Distribution of time spent in the clock gated state 77611570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 1955 71.51% 71.51% # Distribution of time spent in the clock gated state 77711570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 774 28.31% 99.82% # Distribution of time spent in the clock gated state 77811530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state 77911530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 78011530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 78111530Sandreas.sandberg@arm.comsystem.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 78211570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 78311570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 979984970108 # Distribution of time spent in the clock gated state 78411570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateClkGateDist::total 2734 # Distribution of time spent in the clock gated state 78511570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 32805567461 # Cumulative time (in ticks) in various power states 78611570SCurtis.Dunham@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 2770077706539 # Cumulative time (in ticks) in various power states 78711570SCurtis.Dunham@arm.comsystem.cpu1.numCycles 5605297416 # number of cpu cycles simulated 78810535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 78910535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 79011201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 79111570SCurtis.Dunham@arm.comsystem.cpu1.kern.inst.quiesce 2734 # number of quiesce instructions executed 79211570SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 51394923 # Number of instructions committed 79311570SCurtis.Dunham@arm.comsystem.cpu1.committedOps 63339792 # Number of ops (including micro ops) committed 79411570SCurtis.Dunham@arm.comsystem.cpu1.num_int_alu_accesses 56977163 # Number of integer alu accesses 79510535Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 79611570SCurtis.Dunham@arm.comsystem.cpu1.num_func_calls 9170267 # number of times a function call or return occured 79711570SCurtis.Dunham@arm.comsystem.cpu1.num_conditional_control_insts 5966436 # number of instructions that are conditional controls 79811570SCurtis.Dunham@arm.comsystem.cpu1.num_int_insts 56977163 # number of integer instructions 79910535Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 1792 # number of float instructions 80011589SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_reads 110657326 # number of times the integer registers were read 80111570SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_writes 41293408 # number of times the integer registers were written 80210535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 80310535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 80411570SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_reads 196244999 # number of times the CC registers were read 80511570SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_writes 18891882 # number of times the CC registers were written 80611570SCurtis.Dunham@arm.comsystem.cpu1.num_mem_refs 20023552 # number of memory refs 80711570SCurtis.Dunham@arm.comsystem.cpu1.num_load_insts 12287954 # Number of load instructions 80811570SCurtis.Dunham@arm.comsystem.cpu1.num_store_insts 7735598 # Number of store instructions 80911570SCurtis.Dunham@arm.comsystem.cpu1.num_idle_cycles 5539691771.902995 # Number of idle cycles 81011570SCurtis.Dunham@arm.comsystem.cpu1.num_busy_cycles 65605644.097005 # Number of busy cycles 81111570SCurtis.Dunham@arm.comsystem.cpu1.not_idle_fraction 0.011704 # Percentage of non-idle cycles 81211570SCurtis.Dunham@arm.comsystem.cpu1.idle_fraction 0.988296 # Percentage of idle cycles 81311570SCurtis.Dunham@arm.comsystem.cpu1.Branches 15216243 # Number of branches fetched 81410535Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 81511570SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntAlu 45396317 69.36% 69.36% # Class of executed instruction 81611570SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntMult 28337 0.04% 69.40% # Class of executed instruction 81710535Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 81810535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 81910535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 82010535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 82110535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 82210535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 82310535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 82410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 82510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 82610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 82710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 82810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 82910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 83010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 83110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 83210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 83310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 83410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 83510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 83610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 83710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 83810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 83910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 84011570SCurtis.Dunham@arm.comsystem.cpu1.op_class::SimdFloatMisc 3315 0.01% 69.41% # Class of executed instruction 84110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 84210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 84310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 84411570SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemRead 12287954 18.77% 88.18% # Class of executed instruction 84511570SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemWrite 7735598 11.82% 100.00% # Class of executed instruction 84610535Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 84710535Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 84811570SCurtis.Dunham@arm.comsystem.cpu1.op_class::total 65451587 # Class of executed instruction 84911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 85011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.replacements 191903 # number of replacements 85111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 472.757938 # Cycle average of tags in use 85211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 19500903 # Total number of references to valid blocks. 85311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.sampled_refs 192257 # Sample count of references to valid blocks. 85411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 101.431433 # Average number of references to valid blocks. 85511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.warmup_cycle 105851556000 # Cycle when the warmup percentage was hit. 85611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 472.757938 # Average occupied blocks per requestor 85711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.923355 # Average percentage of cache occupancy 85811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.923355 # Average percentage of cache occupancy 85910535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 86010535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 86110535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 86210535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 86311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 39746590 # Number of tag accesses 86411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 39746590 # Number of data accesses 86511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 86611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 11857228 # number of ReadReq hits 86711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 11857228 # number of ReadReq hits 86811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 7396366 # number of WriteReq hits 86911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 7396366 # number of WriteReq hits 87011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 50103 # number of SoftPFReq hits 87111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 50103 # number of SoftPFReq hits 87211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91426 # number of LoadLockedReq hits 87311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 91426 # number of LoadLockedReq hits 87411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 72412 # number of StoreCondReq hits 87511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 72412 # number of StoreCondReq hits 87611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 19253594 # number of demand (read+write) hits 87711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 19253594 # number of demand (read+write) hits 87811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 19303697 # number of overall hits 87911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 19303697 # number of overall hits 88011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 136574 # number of ReadReq misses 88111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_misses::total 136574 # number of ReadReq misses 88211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 92490 # number of WriteReq misses 88311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 92490 # number of WriteReq misses 88411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 30717 # number of SoftPFReq misses 88511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 30717 # number of SoftPFReq misses 88610535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 88710535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 88811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 22549 # number of StoreCondReq misses 88911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 22549 # number of StoreCondReq misses 89011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 229064 # number of demand (read+write) misses 89111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 229064 # number of demand (read+write) misses 89211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 259781 # number of overall misses 89311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 259781 # number of overall misses 89411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 11993802 # number of ReadReq accesses(hits+misses) 89511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 11993802 # number of ReadReq accesses(hits+misses) 89611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 7488856 # number of WriteReq accesses(hits+misses) 89711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 7488856 # number of WriteReq accesses(hits+misses) 89811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80820 # number of SoftPFReq accesses(hits+misses) 89911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 80820 # number of SoftPFReq accesses(hits+misses) 90011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96744 # number of LoadLockedReq accesses(hits+misses) 90111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 96744 # number of LoadLockedReq accesses(hits+misses) 90211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94961 # number of StoreCondReq accesses(hits+misses) 90311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 94961 # number of StoreCondReq accesses(hits+misses) 90411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 19482658 # number of demand (read+write) accesses 90511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 19482658 # number of demand (read+write) accesses 90611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 19563478 # number of overall (read+write) accesses 90711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 19563478 # number of overall (read+write) accesses 90811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011387 # miss rate for ReadReq accesses 90911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.011387 # miss rate for ReadReq accesses 91011570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012350 # miss rate for WriteReq accesses 91111570SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.012350 # miss rate for WriteReq accesses 91211570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380067 # miss rate for SoftPFReq accesses 91311570SCurtis.Dunham@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.380067 # miss rate for SoftPFReq accesses 91411570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054970 # miss rate for LoadLockedReq accesses 91511570SCurtis.Dunham@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054970 # miss rate for LoadLockedReq accesses 91611570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237455 # miss rate for StoreCondReq accesses 91711570SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.237455 # miss rate for StoreCondReq accesses 91811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 91911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 92010892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 92110892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 92210535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 92310535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92410535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 92510535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 92610535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 92710535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92811570SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::writebacks 191903 # number of writebacks 92911570SCurtis.Dunham@arm.comsystem.cpu1.dcache.writebacks::total 191903 # number of writebacks 93011570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 93111570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.replacements 523286 # number of replacements 93211570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tagsinuse 499.709347 # Cycle average of tags in use 93311570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 53142419 # Total number of references to valid blocks. 93411570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.sampled_refs 523798 # Sample count of references to valid blocks. 93511570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 101.455941 # Average number of references to valid blocks. 93611570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.warmup_cycle 76931398500 # Cycle when the warmup percentage was hit. 93711570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 499.709347 # Average occupied blocks per requestor 93811570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.975995 # Average percentage of cache occupancy 93911570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.975995 # Average percentage of cache occupancy 94010535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 94110535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 94210535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 94310535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 94411570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 107856232 # Number of tag accesses 94511570SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 107856232 # Number of data accesses 94611570SCurtis.Dunham@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 94711570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 53142419 # number of ReadReq hits 94811570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 53142419 # number of ReadReq hits 94911570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 53142419 # number of demand (read+write) hits 95011570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 53142419 # number of demand (read+write) hits 95111570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 53142419 # number of overall hits 95211570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 53142419 # number of overall hits 95311570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 523798 # number of ReadReq misses 95411570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_misses::total 523798 # number of ReadReq misses 95511570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 523798 # number of demand (read+write) misses 95611570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_misses::total 523798 # number of demand (read+write) misses 95711570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 523798 # number of overall misses 95811570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_misses::total 523798 # number of overall misses 95911570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 53666217 # number of ReadReq accesses(hits+misses) 96011570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 53666217 # number of ReadReq accesses(hits+misses) 96111570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 53666217 # number of demand (read+write) accesses 96211570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 53666217 # number of demand (read+write) accesses 96311570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 53666217 # number of overall (read+write) accesses 96411570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 53666217 # number of overall (read+write) accesses 96511570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009760 # miss rate for ReadReq accesses 96611570SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009760 # miss rate for ReadReq accesses 96711570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009760 # miss rate for demand accesses 96811570SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009760 # miss rate for demand accesses 96911570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009760 # miss rate for overall accesses 97011570SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009760 # miss rate for overall accesses 97110535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 97210535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 97310535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 97410535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 97510535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 97610535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 97711570SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::writebacks 523286 # number of writebacks 97811570SCurtis.Dunham@arm.comsystem.cpu1.icache.writebacks::total 523286 # number of writebacks 97911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 98010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 98110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 98210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 98310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 98410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 98510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 98611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 98711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.replacements 47270 # number of replacements 98811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tagsinuse 15227.212087 # Cycle average of tags in use 98911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.total_refs 1184400 # Total number of references to valid blocks. 99011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.sampled_refs 62319 # Sample count of references to valid blocks. 99111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.avg_refs 19.005440 # Average number of references to valid blocks. 99210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 99311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 15223.147061 # Average occupied blocks per requestor 99411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 2.040750 # Average occupied blocks per requestor 99511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.024276 # Average occupied blocks per requestor 99611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.929147 # Average percentage of cache occupancy 99711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000125 # Average percentage of cache occupancy 99811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy 99911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.929395 # Average percentage of cache occupancy 100011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id 100111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15029 # Occupied blocks per task id 100210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 100311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 100411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 100511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 528 # Occupied blocks per task id 100611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9407 # Occupied blocks per task id 100711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5094 # Occupied blocks per task id 100811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id 100911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.917297 # Percentage of cache occupancy per task id 101011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tag_accesses 24496500 # Number of tag accesses 101111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.data_accesses 24496500 # Number of data accesses 101211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 101311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3624 # number of ReadReq hits 101411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1921 # number of ReadReq hits 101511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 5545 # number of ReadReq hits 101611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 120975 # number of WritebackDirty hits 101711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 120975 # number of WritebackDirty hits 101811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 583053 # number of WritebackClean hits 101911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 583053 # number of WritebackClean hits 102011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 19849 # number of ReadExReq hits 102111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 19849 # number of ReadExReq hits 102211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510459 # number of ReadCleanReq hits 102311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 510459 # number of ReadCleanReq hits 102411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99238 # number of ReadSharedReq hits 102511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 99238 # number of ReadSharedReq hits 102611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3624 # number of demand (read+write) hits 102711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 1921 # number of demand (read+write) hits 102811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 510459 # number of demand (read+write) hits 102911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 119087 # number of demand (read+write) hits 103011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::total 635091 # number of demand (read+write) hits 103111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3624 # number of overall hits 103211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 1921 # number of overall hits 103311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 510459 # number of overall hits 103411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 119087 # number of overall hits 103511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::total 635091 # number of overall hits 103611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 336 # number of ReadReq misses 103711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 270 # number of ReadReq misses 103811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 606 # number of ReadReq misses 103911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28875 # number of UpgradeReq misses 104011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 28875 # number of UpgradeReq misses 104111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22549 # number of SCUpgradeReq misses 104211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 22549 # number of SCUpgradeReq misses 104311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 43766 # number of ReadExReq misses 104411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 43766 # number of ReadExReq misses 104511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13339 # number of ReadCleanReq misses 104611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 13339 # number of ReadCleanReq misses 104711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73371 # number of ReadSharedReq misses 104811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 73371 # number of ReadSharedReq misses 104911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 336 # number of demand (read+write) misses 105011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 270 # number of demand (read+write) misses 105111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 13339 # number of demand (read+write) misses 105211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 117137 # number of demand (read+write) misses 105311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::total 131082 # number of demand (read+write) misses 105411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 336 # number of overall misses 105511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 270 # number of overall misses 105611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 13339 # number of overall misses 105711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 117137 # number of overall misses 105811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::total 131082 # number of overall misses 105911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3960 # number of ReadReq accesses(hits+misses) 106011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) 106111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 6151 # number of ReadReq accesses(hits+misses) 106211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 120975 # number of WritebackDirty accesses(hits+misses) 106311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 120975 # number of WritebackDirty accesses(hits+misses) 106411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 583053 # number of WritebackClean accesses(hits+misses) 106511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 583053 # number of WritebackClean accesses(hits+misses) 106611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28875 # number of UpgradeReq accesses(hits+misses) 106711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 28875 # number of UpgradeReq accesses(hits+misses) 106811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22549 # number of SCUpgradeReq accesses(hits+misses) 106911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 22549 # number of SCUpgradeReq accesses(hits+misses) 107011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 107111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 107211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523798 # number of ReadCleanReq accesses(hits+misses) 107311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 523798 # number of ReadCleanReq accesses(hits+misses) 107411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172609 # number of ReadSharedReq accesses(hits+misses) 107511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 172609 # number of ReadSharedReq accesses(hits+misses) 107611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3960 # number of demand (read+write) accesses 107711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses 107811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 523798 # number of demand (read+write) accesses 107911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 236224 # number of demand (read+write) accesses 108011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_accesses::total 766173 # number of demand (read+write) accesses 108111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3960 # number of overall (read+write) accesses 108211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses 108311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 523798 # number of overall (read+write) accesses 108411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 236224 # number of overall (read+write) accesses 108511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_accesses::total 766173 # number of overall (read+write) accesses 108611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for ReadReq accesses 108711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.123231 # miss rate for ReadReq accesses 108811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.098521 # miss rate for ReadReq accesses 108911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 109011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 109110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 109210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 109311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.687982 # miss rate for ReadExReq accesses 109411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.687982 # miss rate for ReadExReq accesses 109511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025466 # miss rate for ReadCleanReq accesses 109611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025466 # miss rate for ReadCleanReq accesses 109711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425071 # miss rate for ReadSharedReq accesses 109811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425071 # miss rate for ReadSharedReq accesses 109911570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for demand accesses 110011570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.123231 # miss rate for demand accesses 110111570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025466 # miss rate for demand accesses 110211570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495873 # miss rate for demand accesses 110311570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.171087 # miss rate for demand accesses 110411570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.084848 # miss rate for overall accesses 110511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.123231 # miss rate for overall accesses 110611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025466 # miss rate for overall accesses 110711570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495873 # miss rate for overall accesses 110811570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.171087 # miss rate for overall accesses 110910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 111010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 111110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 111210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 111310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 111410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111511570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::writebacks 32649 # number of writebacks 111611570SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::total 32649 # number of writebacks 111711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 1533187 # Total number of requests made to the snoop filter. 111811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 773168 # Number of requests hitting in the snoop filter with a single holder of the requested data. 111911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11161 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 112011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 166233 # Total number of snoops made to the snoop filter. 112111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164289 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 112211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1944 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 112311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 112411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 12749 # Transaction distribution 112511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 709156 # Transaction distribution 112611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 2504 # Transaction distribution 112711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 2504 # Transaction distribution 112811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 120975 # Transaction distribution 112911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 594214 # Transaction distribution 113011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 28875 # Transaction distribution 113111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22549 # Transaction distribution 113211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 51424 # Transaction distribution 113311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 113411336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 113511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 523798 # Transaction distribution 113611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 172609 # Transaction distribution 113711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571236 # Packet count per connected master and slave (bytes) 113811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778655 # Packet count per connected master and slave (bytes) 113910535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 114011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 114111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count::total 2368587 # Packet count per connected master and slave (bytes) 114211570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67014084 # Cumulative packet size per connected master and slave (bytes) 114311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27419302 # Cumulative packet size per connected master and slave (bytes) 114410535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 114511336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 114611570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_size::total 94470778 # Cumulative packet size per connected master and slave (bytes) 114711570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoops 347619 # Total snoops (count) 114811570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoopTraffic 2342400 # Total snoop traffic (bytes) 114911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 1819791 # Request fanout histogram 115011570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.108284 # Request fanout histogram 115111570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.314158 # Request fanout histogram 115210535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 115311570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 1624681 89.28% 89.28% # Request fanout histogram 115411570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 193166 10.61% 99.89% # Request fanout histogram 115511570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 1944 0.11% 100.00% # Request fanout histogram 115610535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 115711138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 115810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 115911570SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 1819791 # Request fanout histogram 116011570SCurtis.Dunham@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 116110726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30995 # Transaction distribution 116210726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30995 # Transaction distribution 116310726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59419 # Transaction distribution 116410892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 59419 # Transaction distribution 116510726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 116610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 116711245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 116810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 116910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 117010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 117110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 117210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 117310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 117410409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 117510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 117610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 117710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 117810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 117910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 118010513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 118110409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 118210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 118310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 118410726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 118510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 118610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 118710726Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 118810726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 118910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 119011245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 119110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 119210513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 119310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 119410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 119510513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 119610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 120010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120210513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 120310513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 120410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 120510513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 120610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 120710726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 120810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 120910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 121010726Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 121111570SCurtis.Dunham@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 121210513SAli.Saidi@ARM.comsystem.iocache.tags.replacements 36442 # number of replacements 121311570SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use 12149885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 121510513SAli.Saidi@ARM.comsystem.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 121610513SAli.Saidi@ARM.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 121711570SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 246641129509 # Cycle when the warmup percentage was hit. 121811570SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor 121911336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 122011336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 122110513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 122210513SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 122310513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 122410513SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 328284 # Number of tag accesses 122510513SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 328284 # Number of data accesses 122611570SCurtis.Dunham@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 122710513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 122810513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::total 252 # number of ReadReq misses 122910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 123010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 123111456Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 123211456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 36476 # number of demand (read+write) misses 123311456Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 36476 # number of overall misses 123411456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 36476 # number of overall misses 123510513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 123610513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 123710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 123810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 123911456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 124011456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 124111456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 124211456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 124310513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 124410513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 124510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 124610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 124710513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 124810513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 124910513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 125010513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 12518844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 12528844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 12538844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 12548844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 12558983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 12568983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 125710585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 125810585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 125911570SCurtis.Dunham@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 126011570SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 107708 # number of replacements 126111570SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 62491.556145 # Cycle average of tags in use 126211570SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 243932 # Total number of references to valid blocks. 126311570SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 168376 # Sample count of references to valid blocks. 126411570SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 1.448734 # Average number of references to valid blocks. 126510535Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 126611570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 48154.057665 # Average occupied blocks per requestor 126711570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 3.929229 # Average occupied blocks per requestor 126811570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.998273 # Average occupied blocks per requestor 126911570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 7781.790625 # Average occupied blocks per requestor 127011570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4106.660422 # Average occupied blocks per requestor 127111570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 0.967503 # Average occupied blocks per requestor 127211570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1678.829831 # Average occupied blocks per requestor 127311570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 764.322598 # Average occupied blocks per requestor 127411570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.734773 # Average percentage of cache occupancy 127511570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy 127611570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy 127711570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.118741 # Average percentage of cache occupancy 127811570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.062663 # Average percentage of cache occupancy 127911570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy 128011570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.025617 # Average percentage of cache occupancy 128111570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.011663 # Average percentage of cache occupancy 128211570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.953545 # Average percentage of cache occupancy 128311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 128411570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 60662 # Occupied blocks per task id 128511201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 128611570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id 128711570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id 128811570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1796 # Occupied blocks per task id 128911570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 13211 # Occupied blocks per task id 129011570SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 45580 # Occupied blocks per task id 129111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 129211570SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.925629 # Percentage of cache occupancy per task id 129311570SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 5178046 # Number of tag accesses 129411570SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 5178046 # Number of data accesses 129511570SCurtis.Dunham@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 129611570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 225395 # number of WritebackDirty hits 129711570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 225395 # number of WritebackDirty hits 129811570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 578 # number of UpgradeReq hits 129911570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 107 # number of UpgradeReq hits 130011570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 685 # number of UpgradeReq hits 130111570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 78 # number of SCUpgradeReq hits 130211570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 52 # number of SCUpgradeReq hits 130311570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::total 130 # number of SCUpgradeReq hits 130411570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 13904 # number of ReadExReq hits 130511570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 3026 # number of ReadExReq hits 130611570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::total 16930 # number of ReadExReq hits 130711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 73 # number of ReadSharedReq hits 130811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 78 # number of ReadSharedReq hits 130911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 25302 # number of ReadSharedReq hits 131011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 75954 # number of ReadSharedReq hits 131111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 40 # number of ReadSharedReq hits 131211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 44 # number of ReadSharedReq hits 131311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 10936 # number of ReadSharedReq hits 131411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 11571 # number of ReadSharedReq hits 131511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 123998 # number of ReadSharedReq hits 131611570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 73 # number of demand (read+write) hits 131711570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 78 # number of demand (read+write) hits 131811570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 25302 # number of demand (read+write) hits 131911570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 89858 # number of demand (read+write) hits 132011570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 40 # number of demand (read+write) hits 132111570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 44 # number of demand (read+write) hits 132211570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 10936 # number of demand (read+write) hits 132311570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 14597 # number of demand (read+write) hits 132411570SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 140928 # number of demand (read+write) hits 132511570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 73 # number of overall hits 132611570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 78 # number of overall hits 132711570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 25302 # number of overall hits 132811570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 89858 # number of overall hits 132911570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 40 # number of overall hits 133011570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 44 # number of overall hits 133111570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 10936 # number of overall hits 133211570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 14597 # number of overall hits 133311570SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 140928 # number of overall hits 133411570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 9941 # number of UpgradeReq misses 133511570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 3286 # number of UpgradeReq misses 133611570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 13227 # number of UpgradeReq misses 133711570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 736 # number of SCUpgradeReq misses 133811570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1140 # number of SCUpgradeReq misses 133911502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::total 1876 # number of SCUpgradeReq misses 134011570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 136523 # number of ReadExReq misses 134111570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 15823 # number of ReadExReq misses 134211502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 152346 # number of ReadExReq misses 134311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 7 # number of ReadSharedReq misses 134410892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 134511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 16724 # number of ReadSharedReq misses 134611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 11220 # number of ReadSharedReq misses 134711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1 # number of ReadSharedReq misses 134811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 2403 # number of ReadSharedReq misses 134911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1107 # number of ReadSharedReq misses 135011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 31464 # number of ReadSharedReq misses 135111570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses 135210535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 135311570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 16724 # number of demand (read+write) misses 135411570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 147743 # number of demand (read+write) misses 135511570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses 135611570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 2403 # number of demand (read+write) misses 135711570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 16930 # number of demand (read+write) misses 135811570SCurtis.Dunham@arm.comsystem.l2c.demand_misses::total 183810 # number of demand (read+write) misses 135911570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses 136010535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 136111570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 16724 # number of overall misses 136211570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 147743 # number of overall misses 136311570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses 136411570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 2403 # number of overall misses 136511570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 16930 # number of overall misses 136611570SCurtis.Dunham@arm.comsystem.l2c.overall_misses::total 183810 # number of overall misses 136711570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 225395 # number of WritebackDirty accesses(hits+misses) 136811570SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 225395 # number of WritebackDirty accesses(hits+misses) 136911570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 10519 # number of UpgradeReq accesses(hits+misses) 137011570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3393 # number of UpgradeReq accesses(hits+misses) 137111570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 13912 # number of UpgradeReq accesses(hits+misses) 137211570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 814 # number of SCUpgradeReq accesses(hits+misses) 137311570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1192 # number of SCUpgradeReq accesses(hits+misses) 137411570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2006 # number of SCUpgradeReq accesses(hits+misses) 137511570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 150427 # number of ReadExReq accesses(hits+misses) 137611570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 18849 # number of ReadExReq accesses(hits+misses) 137711570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 169276 # number of ReadExReq accesses(hits+misses) 137811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 80 # number of ReadSharedReq accesses(hits+misses) 137911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 80 # number of ReadSharedReq accesses(hits+misses) 138011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 42026 # number of ReadSharedReq accesses(hits+misses) 138111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 87174 # number of ReadSharedReq accesses(hits+misses) 138211570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 41 # number of ReadSharedReq accesses(hits+misses) 138311570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 44 # number of ReadSharedReq accesses(hits+misses) 138411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 13339 # number of ReadSharedReq accesses(hits+misses) 138511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 12678 # number of ReadSharedReq accesses(hits+misses) 138611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 155462 # number of ReadSharedReq accesses(hits+misses) 138711570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 80 # number of demand (read+write) accesses 138811570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 80 # number of demand (read+write) accesses 138911570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 42026 # number of demand (read+write) accesses 139011570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 237601 # number of demand (read+write) accesses 139111570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 41 # number of demand (read+write) accesses 139211570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 44 # number of demand (read+write) accesses 139311570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 13339 # number of demand (read+write) accesses 139411570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 31527 # number of demand (read+write) accesses 139511570SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 324738 # number of demand (read+write) accesses 139611570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 80 # number of overall (read+write) accesses 139711570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 80 # number of overall (read+write) accesses 139811570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 42026 # number of overall (read+write) accesses 139911570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 237601 # number of overall (read+write) accesses 140011570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 41 # number of overall (read+write) accesses 140111570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 44 # number of overall (read+write) accesses 140211570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 13339 # number of overall (read+write) accesses 140311570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 31527 # number of overall (read+write) accesses 140411570SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 324738 # number of overall (read+write) accesses 140511570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.945052 # miss rate for UpgradeReq accesses 140611570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.968464 # miss rate for UpgradeReq accesses 140711570SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.950762 # miss rate for UpgradeReq accesses 140811570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.904177 # miss rate for SCUpgradeReq accesses 140911570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.956376 # miss rate for SCUpgradeReq accesses 141011570SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.935194 # miss rate for SCUpgradeReq accesses 141111570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.907570 # miss rate for ReadExReq accesses 141211570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.839461 # miss rate for ReadExReq accesses 141311570SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.899986 # miss rate for ReadExReq accesses 141411570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.087500 # miss rate for ReadSharedReq accesses 141511570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.025000 # miss rate for ReadSharedReq accesses 141611570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.397944 # miss rate for ReadSharedReq accesses 141711570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128708 # miss rate for ReadSharedReq accesses 141811570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for ReadSharedReq accesses 141911570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.180148 # miss rate for ReadSharedReq accesses 142011570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087317 # miss rate for ReadSharedReq accesses 142111570SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.202390 # miss rate for ReadSharedReq accesses 142211570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.087500 # miss rate for demand accesses 142311570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.025000 # miss rate for demand accesses 142411570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.397944 # miss rate for demand accesses 142511570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.621811 # miss rate for demand accesses 142611570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for demand accesses 142711570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.180148 # miss rate for demand accesses 142811570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.537000 # miss rate for demand accesses 142911570SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.566026 # miss rate for demand accesses 143011570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.087500 # miss rate for overall accesses 143111570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.025000 # miss rate for overall accesses 143211570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.397944 # miss rate for overall accesses 143311570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.621811 # miss rate for overall accesses 143411570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.024390 # miss rate for overall accesses 143511570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.180148 # miss rate for overall accesses 143611570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.537000 # miss rate for overall accesses 143711570SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.566026 # miss rate for overall accesses 143810535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 143910535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 144010535Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 144110535Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 144210535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 144310535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 144411570SCurtis.Dunham@arm.comsystem.l2c.writebacks::writebacks 96260 # number of writebacks 144511570SCurtis.Dunham@arm.comsystem.l2c.writebacks::total 96260 # number of writebacks 144611570SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 462665 # Total number of requests made to the snoop filter. 144711570SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 248104 # Number of requests hitting in the snoop filter with a single holder of the requested data. 144811502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 144911502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 145011502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 145111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 145211570SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 145311570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadReq 43995 # Transaction distribution 145411570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 75711 # Transaction distribution 145511570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteReq 30844 # Transaction distribution 145611570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WriteResp 30844 # Transaction distribution 145711570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 132450 # Transaction distribution 145811570SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 8737 # Transaction distribution 145911570SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 60370 # Transaction distribution 146011570SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 40840 # Transaction distribution 146111570SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 15528 # Transaction distribution 146211570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 152316 # Transaction distribution 146311570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 151921 # Transaction distribution 146411570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 31716 # Transaction distribution 146510892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 146610892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 146710726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 146810535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 146911570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13468 # Packet count per connected master and slave (bytes) 147011570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 616948 # Packet count per connected master and slave (bytes) 147111570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 738326 # Packet count per connected master and slave (bytes) 147211336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 147311336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) 147411570SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 847720 # Packet count per connected master and slave (bytes) 147510726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 147610535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 147711570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26936 # Cumulative packet size per connected master and slave (bytes) 147811570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17953992 # Cumulative packet size per connected master and slave (bytes) 147911570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 18143762 # Cumulative packet size per connected master and slave (bytes) 148010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 148110892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 148211570SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 20476050 # Cumulative packet size per connected master and slave (bytes) 148310535Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 148411570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 148511570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 537492 # Request fanout histogram 148611570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0.010359 # Request fanout histogram 148711570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0.101252 # Request fanout histogram 148810535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 148911570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 531924 98.96% 98.96% # Request fanout histogram 149011570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 5568 1.04% 100.00% # Request fanout histogram 149110535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 149210535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 149311502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 149410535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 149511570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 537492 # Request fanout histogram 149611570SCurtis.Dunham@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 149711570SCurtis.Dunham@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 149811570SCurtis.Dunham@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 149911570SCurtis.Dunham@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 150011570SCurtis.Dunham@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 150111570SCurtis.Dunham@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 150211570SCurtis.Dunham@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 150311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 150411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 150511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 150611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 150711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 150811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 150911570SCurtis.Dunham@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 151011570SCurtis.Dunham@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 151110535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 151210535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 151310535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 151410535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 151510535Sandreas.hansson@arm.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 151610535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 151710535Sandreas.hansson@arm.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 151810535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 151910535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 152010535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 152110535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 152210535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 152310535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 152410535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 152510535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 152610535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 152710535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 152810535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 152910535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 153010535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 153110535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 153210535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 153310535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 153410535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 153510535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 153610535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 153710535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 153810535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 153910535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 154010535Sandreas.hansson@arm.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 154110535Sandreas.hansson@arm.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 154211570SCurtis.Dunham@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154311570SCurtis.Dunham@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154411570SCurtis.Dunham@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154511570SCurtis.Dunham@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154611570SCurtis.Dunham@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154711570SCurtis.Dunham@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154811570SCurtis.Dunham@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 154911239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 155011239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 155111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 155211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 155311570SCurtis.Dunham@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155411570SCurtis.Dunham@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155511570SCurtis.Dunham@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155611570SCurtis.Dunham@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155711570SCurtis.Dunham@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155811570SCurtis.Dunham@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 155911570SCurtis.Dunham@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 156011570SCurtis.Dunham@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 156111570SCurtis.Dunham@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 156211570SCurtis.Dunham@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 156311570SCurtis.Dunham@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 156411570SCurtis.Dunham@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 156511570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 862712 # Total number of requests made to the snoop filter. 156611570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 444233 # Number of requests hitting in the snoop filter with a single holder of the requested data. 156711570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 128693 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 156811570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 9862 # Total number of snoops made to the snoop filter. 156911570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 9359 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 157011570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 503 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 157111570SCurtis.Dunham@arm.comsystem.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802883274000 # Cumulative time (in ticks) in various power states 157211570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadReq 43999 # Transaction distribution 157311570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 301604 # Transaction distribution 157411570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteReq 30844 # Transaction distribution 157511570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WriteResp 30844 # Transaction distribution 157611570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 225395 # Transaction distribution 157711570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 64670 # Transaction distribution 157811570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 60630 # Transaction distribution 157911570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 40970 # Transaction distribution 158011570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 101600 # Transaction distribution 158111570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 213426 # Transaction distribution 158211570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 213426 # Transaction distribution 158311570SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 257605 # Transaction distribution 158411570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1162374 # Packet count per connected master and slave (bytes) 158511570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 422639 # Packet count per connected master and slave (bytes) 158611570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 1585013 # Packet count per connected master and slave (bytes) 158711570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34441336 # Cumulative packet size per connected master and slave (bytes) 158811570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10376426 # Cumulative packet size per connected master and slave (bytes) 158911570SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 44817762 # Cumulative packet size per connected master and slave (bytes) 159011570SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 113249 # Total snoops (count) 159111570SCurtis.Dunham@arm.comsystem.toL2Bus.snoopTraffic 6177216 # Total snoop traffic (bytes) 159211570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 1050551 # Request fanout histogram 159311570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 0.300796 # Request fanout histogram 159411570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.459647 # Request fanout histogram 159510535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 159611570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 735052 69.97% 69.97% # Request fanout histogram 159711570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 314996 29.98% 99.95% # Request fanout histogram 159811570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 503 0.05% 100.00% # Request fanout histogram 159910535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 160011138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 160110535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 160211570SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 1050551 # Request fanout histogram 16038844SAli.Saidi@ARM.com 16048844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1605