stats.txt revision 11547
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 310517SAli.Saidi@ARM.comsim_seconds 2.802883 # Number of seconds simulated 410535Sandreas.hansson@arm.comsim_ticks 2802882797500 # Number of ticks simulated 510535Sandreas.hansson@arm.comfinal_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 710535Sandreas.hansson@arm.comhost_inst_rate 808897 # Simulator instruction rate (inst/s) 810535Sandreas.hansson@arm.comhost_op_rate 985629 # Simulator op (including micro ops) rate (op/s) 910535Sandreas.hansson@arm.comhost_tick_rate 15441476365 # Simulator tick rate (ticks/s) 1010535Sandreas.hansson@arm.comhost_mem_usage 596572 # Number of bytes of host memory used 1110535Sandreas.hansson@arm.comhost_seconds 181.52 # Real time elapsed on the host 1210535Sandreas.hansson@arm.comsim_insts 146828219 # Number of instructions simulated 1310535Sandreas.hansson@arm.comsim_ops 178907974 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610517SAli.Saidi@ARM.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 1810535Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1910535Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory 2010513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory 2110535Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory 2210535Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 1081872 # Number of bytes read from this memory 2310535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2410535Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11758444 # Number of bytes read from this memory 2510535Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 1109284 # Number of instructions bytes read from this memory 2610535Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory 2710535Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 1263160 # Number of instructions bytes read from this memory 2810535Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 8475520 # Number of bytes written to this memory 2910513SAli.Saidi@ARM.comsystem.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 3010409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3110535Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 8493084 # Number of bytes written to this memory 3210535Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 3310517SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 3410409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 25786 # Number of read requests responded to by this memory 3510535Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 147579 # Number of read requests responded to by this memory 3610535Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory 3710513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu1.data 16924 # Number of read requests responded to by this memory 3810535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 3910535Sandreas.hansson@arm.comsystem.physmem.num_reads::total 192873 # Number of read requests responded to by this memory 4010535Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 132430 # Number of write requests responded to by this memory 4110535Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 4210535Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4310513SAli.Saidi@ARM.comsystem.physmem.num_writes::total 136821 # Number of write requests responded to by this memory 4410409Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 4510535Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4610535Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 395765 # Total read bandwidth from this memory (bytes/s) 4710517SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.data 3357904 # Total read bandwidth from this memory (bytes/s) 4810513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) 4910535Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 385985 # Total read bandwidth from this memory (bytes/s) 5010535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 5110513SAli.Saidi@ARM.comsystem.physmem.bw_read::total 4195125 # Total read bandwidth from this memory (bytes/s) 5210535Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 395765 # Instruction read bandwidth from this memory (bytes/s) 5310535Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) 5410535Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 450665 # Instruction read bandwidth from this memory (bytes/s) 5510535Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 3023858 # Write bandwidth from this memory (bytes/s) 5610535Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 5710535Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 5810535Sandreas.hansson@arm.comsystem.physmem.bw_write::total 3030125 # Write bandwidth from this memory (bytes/s) 5910535Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 3023858 # Total bandwidth to/from this memory (bytes/s) 6010513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 6110513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6210535Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 395765 # Total bandwidth to/from this memory (bytes/s) 6310535Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 3364156 # Total bandwidth to/from this memory (bytes/s) 6410535Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) 6510517SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu1.data 386000 # Total bandwidth to/from this memory (bytes/s) 6610513SAli.Saidi@ARM.comsystem.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 6710535Sandreas.hansson@arm.comsystem.physmem.bw_total::total 7225250 # Total bandwidth to/from this memory (bytes/s) 6810535Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 6910513SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 7010535Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 7110535Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7210535Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7310535Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7410517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 7510517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 7610517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 7710517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 7810517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 7910517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 8010517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 8110517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 8210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 8310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 8410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 8510517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 8610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 8710517SAli.Saidi@ARM.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 8810517SAli.Saidi@ARM.comsystem.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 8910517SAli.Saidi@ARM.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 9010517SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 9110517SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 928844SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 9310513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 9410513SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 9510513SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 9610513SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 9710513SAli.Saidi@ARM.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 9810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 9910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 10010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 10110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 10210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 10310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 10410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 10510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 10610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 10710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 10810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 10910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 11010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 11110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 11210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 11310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 11410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 11510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 11610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 11710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 11810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 11910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 12010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 12110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 12210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 12310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 12410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 12510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 12610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 12710535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 12810535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 7964 # Table walker walks requested 12910535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors 13010535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency 13110535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 13210535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency 13310535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 13410535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 13510535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 13610535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated 13710535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated 13810535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated 13910535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst 14010535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 14110535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 14210535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 14310535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 14410535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 14510535Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 14610535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 14710535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 14810535Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 20339694 # DTB read hits 14910535Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 6871 # DTB read misses 15010535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 16391004 # DTB write hits 15110535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1093 # DTB write misses 15210535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 15310535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 15410535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 15510535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 15610535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 3435 # Number of entries that have been flushed from TLB 15710535Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 15810535Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 15910535Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 16010535Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 16110535Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 20346565 # DTB read accesses 16210535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 16392097 # DTB write accesses 16310535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 16410535Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 36730698 # DTB hits 16510535Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 7964 # DTB misses 16610535Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 36738662 # DTB accesses 16710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 16810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 16910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 17010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 17110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 17210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 17310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 17410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 17510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 17610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 17710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 17810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 17910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 18010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 18110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 18210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 18310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 18410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 18510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 18610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 18710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 18810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 18910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 19010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 19110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 19210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 19310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 19410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 19510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 19610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 19710535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 19810535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 3358 # Table walker walks requested 19910535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 20010535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 20110535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 20210535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 20310535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 20410535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 20510535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 20610535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 20710535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 20810535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 20910535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 21010535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 21110535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 21210535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 21310535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 21410535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 21510535Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 21610535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 97439155 # ITB inst hits 21710535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 3358 # ITB inst misses 21810535Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 21910535Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 22010535Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 22110535Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 22210535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 22310535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 22410535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 22510535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 22610535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 2096 # Number of entries that have been flushed from TLB 22710535Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 22810535Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 22910535Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 23010535Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 23110535Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 23210535Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 23310535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 97442513 # ITB inst accesses 23410535Sandreas.hansson@arm.comsystem.cpu0.itb.hits 97439155 # DTB hits 23510535Sandreas.hansson@arm.comsystem.cpu0.itb.misses 3358 # DTB misses 23610535Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 97442513 # DTB accesses 23710535Sandreas.hansson@arm.comsystem.cpu0.numPwrStateTransitions 3932 # Number of power state transitions 23810535Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::samples 1966 # Distribution of time spent in the clock gated state 23910535Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::mean 1395773493.506104 # Distribution of time spent in the clock gated state 24010535Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::stdev 23114974453.612934 # Distribution of time spent in the clock gated state 24110535Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::underflows 1154 58.70% 58.70% # Distribution of time spent in the clock gated state 24210535Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1000-5e+10 806 41.00% 99.69% # Distribution of time spent in the clock gated state 24310535Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.75% # Distribution of time spent in the clock gated state 24410535Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.80% # Distribution of time spent in the clock gated state 24510535Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.20% 100.00% # Distribution of time spent in the clock gated state 24610535Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 24710535Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::max_value 499983242180 # Distribution of time spent in the clock gated state 24810535Sandreas.hansson@arm.comsystem.cpu0.pwrStateClkGateDist::total 1966 # Distribution of time spent in the clock gated state 24910535Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::ON 58792109267 # Cumulative time (in ticks) in various power states 25010535Sandreas.hansson@arm.comsystem.cpu0.pwrStateResidencyTicks::CLK_GATED 2744090688233 # Cumulative time (in ticks) in various power states 25110535Sandreas.hansson@arm.comsystem.cpu0.numCycles 5605767562 # number of cpu cycles simulated 25210535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 25310535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 25410535Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 25510535Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 1966 # number of quiesce instructions executed 25610535Sandreas.hansson@arm.comsystem.cpu0.committedInsts 95426725 # Number of instructions committed 25710535Sandreas.hansson@arm.comsystem.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed 25810535Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses 25910535Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 26010535Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 8000241 # number of times a function call or return occured 26110535Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 13204192 # number of instructions that are conditional controls 26210535Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 100762477 # number of integer instructions 26310535Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 9755 # number of float instructions 26410535Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 182433257 # number of times the integer registers were read 26510535Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 69135397 # number of times the integer registers were written 26610535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 26710535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 26810535Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read 26910535Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 44907357 # number of times the CC registers were written 27010535Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 37873679 # number of memory refs 27110535Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 20597264 # Number of load instructions 27210535Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 17276415 # Number of store instructions 27310535Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 5488183302.205065 # Number of idle cycles 27410535Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 117584259.794936 # Number of busy cycles 27510535Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 27610535Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 27710535Sandreas.hansson@arm.comsystem.cpu0.Branches 21941548 # Number of branches fetched 27810535Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 27910535Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 78887162 67.49% 67.50% # Class of executed instruction 28010535Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction 28110535Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 28210535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 28310535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 28410535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 28510535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 28610535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 28710535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 28810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 28910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 29010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 29110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 29210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 29310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 29410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 29510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 29610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 29710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 29810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 29910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 30010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 30110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 30210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 30310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 30410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 30510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 30610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 30710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 30810535Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction 30910535Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction 31010535Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 31110535Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 31210535Sandreas.hansson@arm.comsystem.cpu0.op_class::total 116881836 # Class of executed instruction 31310535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 31410535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 693478 # number of replacements 31510535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use 31610535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 35932315 # Total number of references to valid blocks. 31710535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. 31810535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 51.776416 # Average number of references to valid blocks. 31910535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 32010535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor 32110535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 32210535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 32310535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 32410535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 32510535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 32610535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 32710535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 32810535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 74113673 # Number of tag accesses 32910535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 74113673 # Number of data accesses 33010535Sandreas.hansson@arm.comsystem.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 33110535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 19108531 # number of ReadReq hits 33210535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 19108531 # number of ReadReq hits 33310535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 15690320 # number of WriteReq hits 33410535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 15690320 # number of WriteReq hits 33510535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits 33610535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits 33710535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits 33810535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits 33910535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits 34010535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits 34110535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 34798851 # number of demand (read+write) hits 34210535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 34798851 # number of demand (read+write) hits 34310535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 35144936 # number of overall hits 34410535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 35144936 # number of overall hits 34510535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses 34610535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses 34710535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses 34810535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 295799 # number of WriteReq misses 34910535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 35010535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 35110535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses 35210535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses 35310535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 18431 # number of StoreCondReq misses 35410535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 18431 # number of StoreCondReq misses 35510535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses 35610535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses 35710535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses 35810535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 769220 # number of overall misses 35910535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 19481631 # number of ReadReq accesses(hits+misses) 36010535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 19481631 # number of ReadReq accesses(hits+misses) 36110535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 15986119 # number of WriteReq accesses(hits+misses) 36210535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 15986119 # number of WriteReq accesses(hits+misses) 36310535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses) 36410535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses) 36510535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses) 36610535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses) 36710535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses) 36810535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses) 36910535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 35467750 # number of demand (read+write) accesses 37010535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 35467750 # number of demand (read+write) accesses 37110535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 35914156 # number of overall (read+write) accesses 37210535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 35914156 # number of overall (read+write) accesses 37310535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 37410535Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 37510535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 37610535Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 37710535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224730 # miss rate for SoftPFReq accesses 37810535Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.224730 # miss rate for SoftPFReq accesses 37910535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses 38010535Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses 38110535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048315 # miss rate for StoreCondReq accesses 38210535Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.048315 # miss rate for StoreCondReq accesses 38310535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses 38410535Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses 38510535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses 38610535Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses 38710535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 38810535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 38910535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 39010535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 39110535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 39210535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 39310535Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 693478 # number of writebacks 39410535Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 693478 # number of writebacks 39510535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 39610535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 1109639 # number of replacements 39710535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 39810535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 96331337 # Total number of references to valid blocks. 39910535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 1110151 # Sample count of references to valid blocks. 40010535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 86.773184 # Average number of references to valid blocks. 40110535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 40210535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 40310535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 40410535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 40510535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 40610535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 40710535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 40810535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 40910535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 41010535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 195993154 # Number of tag accesses 41110535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 195993154 # Number of data accesses 41210535Sandreas.hansson@arm.comsystem.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 41310535Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 96331337 # number of ReadReq hits 41410535Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 96331337 # number of ReadReq hits 41510535Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 96331337 # number of demand (read+write) hits 41610535Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 96331337 # number of demand (read+write) hits 41710535Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 96331337 # number of overall hits 41810535Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 96331337 # number of overall hits 41910535Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1110160 # number of ReadReq misses 42010535Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 1110160 # number of ReadReq misses 42110535Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 1110160 # number of demand (read+write) misses 42210535Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 1110160 # number of demand (read+write) misses 42310535Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 1110160 # number of overall misses 42410535Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 1110160 # number of overall misses 42510535Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 97441497 # number of ReadReq accesses(hits+misses) 42610535Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 97441497 # number of ReadReq accesses(hits+misses) 42710535Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 97441497 # number of demand (read+write) accesses 42810535Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 97441497 # number of demand (read+write) accesses 42910535Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 97441497 # number of overall (read+write) accesses 43010535Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 97441497 # number of overall (read+write) accesses 43110535Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses 43210535Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses 43310535Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses 43410535Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses 43510535Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses 43610535Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses 43710535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 43810535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 43910535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 44010535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 44110535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 44210535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 44310535Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 1109639 # number of writebacks 44410535Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 1109639 # number of writebacks 44510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 44610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 44710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 44810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 44910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 45010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 45110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 45210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 45310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 249747 # number of replacements 45410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16131.550435 # Cycle average of tags in use 45510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 2729892 # Total number of references to valid blocks. 45610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 265865 # Sample count of references to valid blocks. 45710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 10.267963 # Average number of references to valid blocks. 45810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 45910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 16129.097151 # Average occupied blocks per requestor 46010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.376905 # Average occupied blocks per requestor 46110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076379 # Average occupied blocks per requestor 46210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.984442 # Average percentage of cache occupancy 46310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy 46410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 46510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.984592 # Average percentage of cache occupancy 46610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 46710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 16110 # Occupied blocks per task id 46810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 46910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 47010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 47110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id 47210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id 47310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5562 # Occupied blocks per task id 47410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7431 # Occupied blocks per task id 47510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2624 # Occupied blocks per task id 47610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 47710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983276 # Percentage of cache occupancy per task id 47810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 59696130 # Number of tag accesses 47910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 59696130 # Number of data accesses 48010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 48110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10179 # number of ReadReq hits 48210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4500 # number of ReadReq hits 48310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 14679 # number of ReadReq hits 48410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 510228 # number of WritebackDirty hits 48510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 510228 # number of WritebackDirty hits 48610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 1265023 # number of WritebackClean hits 48710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 1265023 # number of WritebackClean hits 48810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 94248 # number of ReadExReq hits 48910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 94248 # number of ReadExReq hits 49010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068491 # number of ReadCleanReq hits 49110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 1068491 # number of ReadCleanReq hits 49210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352197 # number of ReadSharedReq hits 49310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 352197 # number of ReadSharedReq hits 49410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10179 # number of demand (read+write) hits 49510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 4500 # number of demand (read+write) hits 49610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 1068491 # number of demand (read+write) hits 49710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 446445 # number of demand (read+write) hits 49810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 1529615 # number of demand (read+write) hits 49910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10179 # number of overall hits 50010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 4500 # number of overall hits 50110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 1068491 # number of overall hits 50210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 446445 # number of overall hits 50310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 1529615 # number of overall hits 50410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 212 # number of ReadReq misses 50510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 127 # number of ReadReq misses 50610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 339 # number of ReadReq misses 50710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26279 # number of UpgradeReq misses 50810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 26279 # number of UpgradeReq misses 50910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18431 # number of SCUpgradeReq misses 51010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 18431 # number of SCUpgradeReq misses 51110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 175272 # number of ReadExReq misses 51210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 175272 # number of ReadExReq misses 51310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41669 # number of ReadCleanReq misses 51410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 41669 # number of ReadCleanReq misses 51510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127964 # number of ReadSharedReq misses 51610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 127964 # number of ReadSharedReq misses 51710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 212 # number of demand (read+write) misses 51810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 127 # number of demand (read+write) misses 51910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 41669 # number of demand (read+write) misses 52010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 303236 # number of demand (read+write) misses 52110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 345244 # number of demand (read+write) misses 52210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 212 # number of overall misses 52310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 127 # number of overall misses 52410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 41669 # number of overall misses 52510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 303236 # number of overall misses 52610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 345244 # number of overall misses 52710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10391 # number of ReadReq accesses(hits+misses) 52810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) 52910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 15018 # number of ReadReq accesses(hits+misses) 53010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 510228 # number of WritebackDirty accesses(hits+misses) 53110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 510228 # number of WritebackDirty accesses(hits+misses) 53210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 1265023 # number of WritebackClean accesses(hits+misses) 53310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 1265023 # number of WritebackClean accesses(hits+misses) 53410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26279 # number of UpgradeReq accesses(hits+misses) 53510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 26279 # number of UpgradeReq accesses(hits+misses) 53610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18431 # number of SCUpgradeReq accesses(hits+misses) 53710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 18431 # number of SCUpgradeReq accesses(hits+misses) 53810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269520 # number of ReadExReq accesses(hits+misses) 53910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 269520 # number of ReadExReq accesses(hits+misses) 54010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110160 # number of ReadCleanReq accesses(hits+misses) 54110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 1110160 # number of ReadCleanReq accesses(hits+misses) 54210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480161 # number of ReadSharedReq accesses(hits+misses) 54310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 480161 # number of ReadSharedReq accesses(hits+misses) 54410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10391 # number of demand (read+write) accesses 54510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses 54610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 1110160 # number of demand (read+write) accesses 54710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 749681 # number of demand (read+write) accesses 54810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 1874859 # number of demand (read+write) accesses 54910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10391 # number of overall (read+write) accesses 55010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses 55110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 1110160 # number of overall (read+write) accesses 55210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 749681 # number of overall (read+write) accesses 55310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 1874859 # number of overall (read+write) accesses 55410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for ReadReq accesses 55510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027448 # miss rate for ReadReq accesses 55610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.022573 # miss rate for ReadReq accesses 55710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 55810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 55910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 56010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 56110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650312 # miss rate for ReadExReq accesses 56210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.650312 # miss rate for ReadExReq accesses 56310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037534 # miss rate for ReadCleanReq accesses 56410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037534 # miss rate for ReadCleanReq accesses 56510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266502 # miss rate for ReadSharedReq accesses 56610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266502 # miss rate for ReadSharedReq accesses 56710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for demand accesses 56810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027448 # miss rate for demand accesses 56910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037534 # miss rate for demand accesses 57010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404487 # miss rate for demand accesses 57110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.184144 # miss rate for demand accesses 57210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for overall accesses 57310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027448 # miss rate for overall accesses 57410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037534 # miss rate for overall accesses 57510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404487 # miss rate for overall accesses 57610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.184144 # miss rate for overall accesses 57710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 57810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 57910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 58010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 58110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 58210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 58310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 193031 # number of writebacks 58410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 193031 # number of writebacks 58510535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 3720034 # Total number of requests made to the snoop filter. 58610535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860217 # Number of requests hitting in the snoop filter with a single holder of the requested data. 58710535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 58810535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 218415 # Total number of snoops made to the snoop filter. 58910535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215401 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 59010535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3014 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 59110535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 59210535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution 59310535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution 59410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 59510535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 59610535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 510228 # Transaction distribution 59710535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 1292889 # Transaction distribution 59810535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 26279 # Transaction distribution 59910535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18431 # Transaction distribution 60010535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 44710 # Transaction distribution 60110535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 269520 # Transaction distribution 60210535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 269520 # Transaction distribution 60310535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110160 # Transaction distribution 60410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 480161 # Transaction distribution 60510535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348003 # Packet count per connected master and slave (bytes) 60610535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402094 # Packet count per connected master and slave (bytes) 60710535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 60810535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 60910535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 5791721 # Packet count per connected master and slave (bytes) 61010535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142103224 # Cumulative packet size per connected master and slave (bytes) 61110535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552708 # Cumulative packet size per connected master and slave (bytes) 61210535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 61310535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 61410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 234739180 # Cumulative packet size per connected master and slave (bytes) 61510535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 623521 # Total snoops (count) 61610535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 4318336 # Request fanout histogram 61710535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.067052 # Request fanout histogram 61810535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.252886 # Request fanout histogram 61910535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 62010535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 4031799 93.36% 93.36% # Request fanout histogram 62110535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 283523 6.57% 99.93% # Request fanout histogram 62210535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 3014 0.07% 100.00% # Request fanout histogram 62310535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 62410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 62510535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 62610535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 4318336 # Request fanout histogram 62710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 62810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 62910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 63010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 63110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 63210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 63310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 63410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 63510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 63610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 63710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 63810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 63910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 64010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 64110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 64210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 64310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 64510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 64610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 64710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 64810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 64910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 65010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 65210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 65410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 65510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 65610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 65710535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 65810535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 3359 # Table walker walks requested 65910535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 66010535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 66110535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 66210535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 66310535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 66410535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 66510535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 66610535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated 66710535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated 66810535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated 66910535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst 67010535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 67110535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst 67210535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst 67310535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 67410535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst 67510535Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst 67610535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 67710535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 67810535Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 12173945 # DTB read hits 67910535Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 2853 # DTB read misses 68010535Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 7587221 # DTB write hits 68110535Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 506 # DTB write misses 68210535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 68310535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 68410535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 68510535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68610535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 1949 # Number of entries that have been flushed from TLB 68710535Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 68810535Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 68910535Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 69010535Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 69110535Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 12176798 # DTB read accesses 69210535Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 7587727 # DTB write accesses 69310535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 69410535Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 19761166 # DTB hits 69510535Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 3359 # DTB misses 69610535Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 19764525 # DTB accesses 69710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 69810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 69910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 70110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 70310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 70410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 70510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 70610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 70710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 70810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 70910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 71010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 71110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 71210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 71310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 71410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 71510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 71610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 71710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 71810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 71910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 72010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 72110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 72310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 72410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 72510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 72610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 72710535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 72810535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 1734 # Table walker walks requested 72910535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 73010535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 73110535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 73210535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 73310535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 73410535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 73510535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 73610535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 73710535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 73810535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 73910535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74010535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 74110535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 74210535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74310535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 74410535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 74510535Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 74610535Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 53671758 # ITB inst hits 74710535Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 1734 # ITB inst misses 74810535Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 74910535Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 75010535Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 75110535Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 75210535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 75310535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 75410535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 75510535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 75610535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 1072 # Number of entries that have been flushed from TLB 75710535Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 75810535Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 75910535Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 76010535Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 76110535Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 76210535Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 76310535Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 53673492 # ITB inst accesses 76410535Sandreas.hansson@arm.comsystem.cpu1.itb.hits 53671758 # DTB hits 76510535Sandreas.hansson@arm.comsystem.cpu1.itb.misses 1734 # DTB misses 76610535Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 53673492 # DTB accesses 76710535Sandreas.hansson@arm.comsystem.cpu1.numPwrStateTransitions 5477 # Number of power state transitions 76810535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::samples 2739 # Distribution of time spent in the clock gated state 76910535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::mean 1011344723.290617 # Distribution of time spent in the clock gated state 77010535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::stdev 25846310002.973743 # Distribution of time spent in the clock gated state 77110535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::underflows 1957 71.45% 71.45% # Distribution of time spent in the clock gated state 77210535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::1000-5e+10 777 28.37% 99.82% # Distribution of time spent in the clock gated state 77310535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.89% # Distribution of time spent in the clock gated state 77410535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state 77510535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state 77610535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state 77710535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state 77810535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::max_value 979984930372 # Distribution of time spent in the clock gated state 77910535Sandreas.hansson@arm.comsystem.cpu1.pwrStateClkGateDist::total 2739 # Distribution of time spent in the clock gated state 78010535Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::ON 32809600407 # Cumulative time (in ticks) in various power states 78110535Sandreas.hansson@arm.comsystem.cpu1.pwrStateResidencyTicks::CLK_GATED 2770073197093 # Cumulative time (in ticks) in various power states 78210535Sandreas.hansson@arm.comsystem.cpu1.numCycles 5605296470 # number of cpu cycles simulated 78310535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 78410535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 78510535Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 78610535Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 78710535Sandreas.hansson@arm.comsystem.cpu1.committedInsts 51401494 # Number of instructions committed 78810535Sandreas.hansson@arm.comsystem.cpu1.committedOps 63347804 # Number of ops (including micro ops) committed 78910535Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 56984416 # Number of integer alu accesses 79010535Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 79110535Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 9170873 # number of times a function call or return occured 79210535Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 5967115 # number of instructions that are conditional controls 79310535Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 56984416 # number of integer instructions 79410535Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 1792 # number of float instructions 79510535Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 110669758 # number of times the integer registers were read 79610535Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 41298494 # number of times the integer registers were written 79710535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 79810535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 79910535Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 196269240 # number of times the CC registers were read 80010535Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 18894452 # number of times the CC registers were written 80110535Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 20026424 # number of memory refs 80210535Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 12289568 # Number of load instructions 80310535Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 7736856 # Number of store instructions 80410535Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 5539682760.605002 # Number of idle cycles 80510535Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 65613709.394997 # Number of busy cycles 80610535Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 80710535Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 80810535Sandreas.hansson@arm.comsystem.cpu1.Branches 15217528 # Number of branches fetched 80910535Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 81010535Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 45401456 69.36% 69.36% # Class of executed instruction 81110535Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction 81210535Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 81310535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 81410535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 81510535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 81610535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 81710535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 81810535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 81910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 82010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 82110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 82210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 82310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 82410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 82510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 82610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 82710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 82810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 82910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 83010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 83110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 83210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 83310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 83410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 83510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 83610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 83710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 83810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 83910535Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 12289568 18.77% 88.18% # Class of executed instruction 84010535Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 7736856 11.82% 100.00% # Class of executed instruction 84110535Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 84210535Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 84310535Sandreas.hansson@arm.comsystem.cpu1.op_class::total 65459659 # Class of executed instruction 84410535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 84510535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 191946 # number of replacements 84610535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 472.736015 # Cycle average of tags in use 84710535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 19503545 # Total number of references to valid blocks. 84810535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks. 84910535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 101.422491 # Average number of references to valid blocks. 85010535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 85110535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736015 # Average occupied blocks per requestor 85210535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy 85310535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy 85410535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 85510535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 85610535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 85710535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 85810535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 39752069 # Number of tag accesses 85910535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 39752069 # Number of data accesses 86010535Sandreas.hansson@arm.comsystem.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 86110535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 11858716 # number of ReadReq hits 86210535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 11858716 # number of ReadReq hits 86310535Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 7397520 # number of WriteReq hits 86410535Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 7397520 # number of WriteReq hits 86510535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits 86610535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits 86710535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 86810535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 86910535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 72399 # number of StoreCondReq hits 87010535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 72399 # number of StoreCondReq hits 87110535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 19256236 # number of demand (read+write) hits 87210535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 19256236 # number of demand (read+write) hits 87310535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 19306336 # number of overall hits 87410535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 19306336 # number of overall hits 87510535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 136638 # number of ReadReq misses 87610535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 136638 # number of ReadReq misses 87710535Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 92454 # number of WriteReq misses 87810535Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 92454 # number of WriteReq misses 87910535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses 88010535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses 88110535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 88210535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 88310535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 22580 # number of StoreCondReq misses 88410535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 22580 # number of StoreCondReq misses 88510535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses 88610535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses 88710535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 259810 # number of overall misses 88810535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 259810 # number of overall misses 88910535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 11995354 # number of ReadReq accesses(hits+misses) 89010535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 11995354 # number of ReadReq accesses(hits+misses) 89110535Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 7489974 # number of WriteReq accesses(hits+misses) 89210535Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 7489974 # number of WriteReq accesses(hits+misses) 89310535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 89410535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 89510535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 89610535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 89710535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 89810535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 89910535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 19485328 # number of demand (read+write) accesses 90010535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 19485328 # number of demand (read+write) accesses 90110535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 19566146 # number of overall (read+write) accesses 90210535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 19566146 # number of overall (read+write) accesses 90310535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses 90410535Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 90510535Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012344 # miss rate for WriteReq accesses 90610535Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.012344 # miss rate for WriteReq accesses 90710535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses 90810535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses 90910535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 91010535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 91110535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237737 # miss rate for StoreCondReq accesses 91210535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.237737 # miss rate for StoreCondReq accesses 91310535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 91410535Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 91510535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 91610535Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 91710535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 91810535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 91910535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 92010535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 92110535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 92210535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92310535Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks 92410535Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 191946 # number of writebacks 92510535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 92610535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 523401 # number of replacements 92710535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use 92810535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 53148935 # Total number of references to valid blocks. 92910535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. 93010535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 101.446108 # Average number of references to valid blocks. 93110535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 93210535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor 93310535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 93410535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 93510535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 93610535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 93710535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 93810535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 93910535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 107869609 # Number of tag accesses 94010535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 107869609 # Number of data accesses 94110535Sandreas.hansson@arm.comsystem.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 94210535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 53148935 # number of ReadReq hits 94310535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 53148935 # number of ReadReq hits 94410535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 53148935 # number of demand (read+write) hits 94510535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 53148935 # number of demand (read+write) hits 94610535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 53148935 # number of overall hits 94710535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 53148935 # number of overall hits 94810535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses 94910535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses 95010535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 523913 # number of demand (read+write) misses 95110535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 523913 # number of demand (read+write) misses 95210535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 523913 # number of overall misses 95310535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 523913 # number of overall misses 95410535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 53672848 # number of ReadReq accesses(hits+misses) 95510535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 53672848 # number of ReadReq accesses(hits+misses) 95610535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 53672848 # number of demand (read+write) accesses 95710535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 53672848 # number of demand (read+write) accesses 95810535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 53672848 # number of overall (read+write) accesses 95910535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 53672848 # number of overall (read+write) accesses 96010535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 96110535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 96210535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 96310535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 96410535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 96510535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 96610535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 96710535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 96810535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 96910535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 97010535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 97110535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 97210535Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 523401 # number of writebacks 97310535Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 523401 # number of writebacks 97410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 97510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 97610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 97710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 97810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 97910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 98010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 98110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 98210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 47503 # number of replacements 98310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 15229.973296 # Cycle average of tags in use 98410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 1184897 # Total number of references to valid blocks. 98510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 62526 # Sample count of references to valid blocks. 98610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 18.950469 # Average number of references to valid blocks. 98710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 98810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 15227.338556 # Average occupied blocks per requestor 98910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 0.619660 # Average occupied blocks per requestor 99010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015081 # Average occupied blocks per requestor 99110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.929403 # Average percentage of cache occupancy 99210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000038 # Average percentage of cache occupancy 99310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 99410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.929564 # Average percentage of cache occupancy 99510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id 99610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15005 # Occupied blocks per task id 99710513SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 99810513SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 99910513SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 100010513SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id 100110513SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9469 # Occupied blocks per task id 100210513SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5007 # Occupied blocks per task id 100310513SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id 100410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.915833 # Percentage of cache occupancy per task id 100510513SAli.Saidi@ARM.comsystem.cpu1.l2cache.tags.tag_accesses 24502168 # Number of tag accesses 100610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 24502168 # Number of data accesses 100710513SAli.Saidi@ARM.comsystem.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 100810513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits 100910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1918 # number of ReadReq hits 101010409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 5539 # number of ReadReq hits 101110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 121092 # number of WritebackDirty hits 101210513SAli.Saidi@ARM.comsystem.cpu1.l2cache.WritebackDirty_hits::total 121092 # number of WritebackDirty hits 101310409Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 583097 # number of WritebackClean hits 101410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 583097 # number of WritebackClean hits 101510513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 19779 # number of ReadExReq hits 101610513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_hits::total 19779 # number of ReadExReq hits 101710409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510372 # number of ReadCleanReq hits 101810513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 510372 # number of ReadCleanReq hits 101910513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99144 # number of ReadSharedReq hits 102010513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 99144 # number of ReadSharedReq hits 102110513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits 102210513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 1918 # number of demand (read+write) hits 102310513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 510372 # number of demand (read+write) hits 102410513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::cpu1.data 118923 # number of demand (read+write) hits 102510513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_hits::total 634834 # number of demand (read+write) hits 102610513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits 102710513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 1918 # number of overall hits 102810513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 510372 # number of overall hits 102910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 118923 # number of overall hits 103010513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_hits::total 634834 # number of overall hits 103110409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses 103210513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 273 # number of ReadReq misses 103310513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_misses::total 617 # number of ReadReq misses 103410409Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28839 # number of UpgradeReq misses 103510409Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 28839 # number of UpgradeReq misses 103610409Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22580 # number of SCUpgradeReq misses 103710513SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 22580 # number of SCUpgradeReq misses 103810409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 43836 # number of ReadExReq misses 103910409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 43836 # number of ReadExReq misses 104010513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13541 # number of ReadCleanReq misses 104110513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 13541 # number of ReadCleanReq misses 104210409Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73530 # number of ReadSharedReq misses 104310513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 73530 # number of ReadSharedReq misses 104410513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses 104510513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 273 # number of demand (read+write) misses 104610513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 13541 # number of demand (read+write) misses 104710513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::cpu1.data 117366 # number of demand (read+write) misses 104810513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_misses::total 131524 # number of demand (read+write) misses 104910513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses 105010513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 273 # number of overall misses 105110513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 13541 # number of overall misses 105210513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_misses::cpu1.data 117366 # number of overall misses 105310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 131524 # number of overall misses 10549885Sstever@gmail.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses) 105510513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) 105610513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses) 105710517SAli.Saidi@ARM.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 121092 # number of WritebackDirty accesses(hits+misses) 105810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 121092 # number of WritebackDirty accesses(hits+misses) 105910513SAli.Saidi@ARM.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 583097 # number of WritebackClean accesses(hits+misses) 106010513SAli.Saidi@ARM.comsystem.cpu1.l2cache.WritebackClean_accesses::total 583097 # number of WritebackClean accesses(hits+misses) 106110513SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28839 # number of UpgradeReq accesses(hits+misses) 106210513SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 28839 # number of UpgradeReq accesses(hits+misses) 106310513SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22580 # number of SCUpgradeReq accesses(hits+misses) 106410513SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 22580 # number of SCUpgradeReq accesses(hits+misses) 106510513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 106610513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 106710513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523913 # number of ReadCleanReq accesses(hits+misses) 106810513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 523913 # number of ReadCleanReq accesses(hits+misses) 106910513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172674 # number of ReadSharedReq accesses(hits+misses) 107010513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 172674 # number of ReadSharedReq accesses(hits+misses) 107110513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3965 # number of demand (read+write) accesses 107210513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses 107310513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 523913 # number of demand (read+write) accesses 107410513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 236289 # number of demand (read+write) accesses 107510513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_accesses::total 766358 # number of demand (read+write) accesses 107610513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3965 # number of overall (read+write) accesses 107710513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses 107810513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 523913 # number of overall (read+write) accesses 107910513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 236289 # number of overall (read+write) accesses 108010513SAli.Saidi@ARM.comsystem.cpu1.l2cache.overall_accesses::total 766358 # number of overall (read+write) accesses 108110513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for ReadReq accesses 108210513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124601 # miss rate for ReadReq accesses 108310513SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.100227 # miss rate for ReadReq accesses 108410513SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 108510513SAli.Saidi@ARM.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 108610513SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 108710513SAli.Saidi@ARM.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 10888844SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689083 # miss rate for ReadExReq accesses 10898844SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.689083 # miss rate for ReadExReq accesses 10908844SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025846 # miss rate for ReadCleanReq accesses 10918844SAli.Saidi@ARM.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025846 # miss rate for ReadCleanReq accesses 10928983Snate@binkert.orgsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425831 # miss rate for ReadSharedReq accesses 10938983Snate@binkert.orgsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425831 # miss rate for ReadSharedReq accesses 109410513SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for demand accesses 10958844SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124601 # miss rate for demand accesses 10968844SAli.Saidi@ARM.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025846 # miss rate for demand accesses 109710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496705 # miss rate for demand accesses 109810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.171622 # miss rate for demand accesses 109910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for overall accesses 110010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124601 # miss rate for overall accesses 110110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025846 # miss rate for overall accesses 110210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496705 # miss rate for overall accesses 110310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.171622 # miss rate for overall accesses 110410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 110510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 110610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 110710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 110810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 110910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 111010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 32790 # number of writebacks 111110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 32790 # number of writebacks 111210535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 1533520 # Total number of requests made to the snoop filter. 111310535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 773321 # Number of requests hitting in the snoop filter with a single holder of the requested data. 111410535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 111510535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 166202 # Total number of snoops made to the snoop filter. 111610535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 111710535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1963 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 111810535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 111910535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution 112010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution 112110535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 112210535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 112310535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 121092 # Transaction distribution 112410535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 594255 # Transaction distribution 112510535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 28839 # Transaction distribution 112610535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22580 # Transaction distribution 112710535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution 112810535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 112910535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 113010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 523913 # Transaction distribution 113110535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 172674 # Transaction distribution 113210535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571581 # Packet count per connected master and slave (bytes) 113310535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778822 # Packet count per connected master and slave (bytes) 113410535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 113510535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 113610535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 2369099 # Packet count per connected master and slave (bytes) 113710535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67028804 # Cumulative packet size per connected master and slave (bytes) 113810535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27426222 # Cumulative packet size per connected master and slave (bytes) 113910535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 114010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 114110535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 94492418 # Cumulative packet size per connected master and slave (bytes) 114210535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 347973 # Total snoops (count) 114310535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 1820541 # Request fanout histogram 114410535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.108229 # Request fanout histogram 114510535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.314122 # Request fanout histogram 114610535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 114710535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 1625468 89.28% 89.28% # Request fanout histogram 114810535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 193110 10.61% 99.89% # Request fanout histogram 114910535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 1963 0.11% 100.00% # Request fanout histogram 115010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 115110535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 115210535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 115310535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 1820541 # Request fanout histogram 115410535Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 115510535Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30995 # Transaction distribution 115610535Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30995 # Transaction distribution 115710535Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59419 # Transaction distribution 115810535Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 59419 # Transaction distribution 115910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 116010535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 116110535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 116210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 116310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 116410535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 116510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 116610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 116710535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 116810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 116910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 117010535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 117110535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 117210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 117310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 117410535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 117510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 117610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 117710535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 117810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 117910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 118010535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 118110535Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 118210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 118310535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 118410535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 118510535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 118610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 118710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 118810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 118910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 119010535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119310535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 119410535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119510535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 119710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 119810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 119910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 120010535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 120110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 120210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 120310535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 120410535Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 120510535Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 120610535Sandreas.hansson@arm.comsystem.iocache.tags.replacements 36442 # number of replacements 120710535Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use 120810535Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 120910535Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 121010535Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 121110535Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 246641287009 # Cycle when the warmup percentage was hit. 121210535Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor 121310535Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 121410535Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 121510535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 121610535Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 121710535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 121810535Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 328284 # Number of tag accesses 121910535Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 328284 # Number of data accesses 122010535Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 122110535Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 122210535Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 252 # number of ReadReq misses 122310535Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 122410535Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 122510535Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 122610535Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 36476 # number of demand (read+write) misses 122710535Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 36476 # number of overall misses 122810535Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 36476 # number of overall misses 122910535Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 123010535Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 123110535Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 123210535Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 123310535Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 123410535Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 123510535Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 123610535Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 123710535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 123810535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 123910535Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 124010535Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 124110535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 124210535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 124310535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 124410535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 124510535Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 124610535Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 124710535Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 124810535Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 124910535Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 125010535Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 125110535Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 125210535Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 125310535Sandreas.hansson@arm.comsystem.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 125410535Sandreas.hansson@arm.comsystem.l2c.tags.replacements 107745 # number of replacements 125510535Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62386.756535 # Cycle average of tags in use 125610535Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 243993 # Total number of references to valid blocks. 125710535Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 168404 # Sample count of references to valid blocks. 125810535Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 1.448855 # Average number of references to valid blocks. 125910535Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 126010535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 48109.911781 # Average occupied blocks per requestor 126110535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010811 # Average occupied blocks per requestor 126210535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.030814 # Average occupied blocks per requestor 126310535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 7778.233869 # Average occupied blocks per requestor 126410535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4058.534945 # Average occupied blocks per requestor 126510535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1666.123091 # Average occupied blocks per requestor 126610535Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 768.911224 # Average occupied blocks per requestor 126710535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.734099 # Average percentage of cache occupancy 126810535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy 126910535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 127010535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.118686 # Average percentage of cache occupancy 127110535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.061928 # Average percentage of cache occupancy 127210535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.025423 # Average percentage of cache occupancy 127310535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.011733 # Average percentage of cache occupancy 127410535Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.951946 # Average percentage of cache occupancy 127510535Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 127610535Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 60653 # Occupied blocks per task id 127710535Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 127810535Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 127910535Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id 128010535Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id 128110535Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id 128210535Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 45523 # Occupied blocks per task id 128310535Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 128410535Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.925491 # Percentage of cache occupancy per task id 128510535Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 5181909 # Number of tag accesses 128610535Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 5181909 # Number of data accesses 128710535Sandreas.hansson@arm.comsystem.l2c.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 128810535Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 225821 # number of WritebackDirty hits 128910535Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 225821 # number of WritebackDirty hits 129010535Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 557 # number of UpgradeReq hits 129110535Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 103 # number of UpgradeReq hits 129210535Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 660 # number of UpgradeReq hits 129310535Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 84 # number of SCUpgradeReq hits 129410535Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 42 # number of SCUpgradeReq hits 129510535Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 126 # number of SCUpgradeReq hits 129610535Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 14022 # number of ReadExReq hits 129710535Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 3121 # number of ReadExReq hits 129810535Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 17143 # number of ReadExReq hits 129910535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 71 # number of ReadSharedReq hits 130010535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 67 # number of ReadSharedReq hits 130110535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 24898 # number of ReadSharedReq hits 130210535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 76097 # number of ReadSharedReq hits 130310535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits 130410535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 38 # number of ReadSharedReq hits 130510535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 11147 # number of ReadSharedReq hits 130610535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 11696 # number of ReadSharedReq hits 130710535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 124060 # number of ReadSharedReq hits 130810535Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits 130910535Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 67 # number of demand (read+write) hits 131010535Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 24898 # number of demand (read+write) hits 131110535Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 90119 # number of demand (read+write) hits 131210535Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 46 # number of demand (read+write) hits 131310535Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 38 # number of demand (read+write) hits 131410535Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 11147 # number of demand (read+write) hits 131510535Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 14817 # number of demand (read+write) hits 131610535Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 141203 # number of demand (read+write) hits 131710535Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 71 # number of overall hits 131810535Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 67 # number of overall hits 131910535Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 24898 # number of overall hits 132010535Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 90119 # number of overall hits 132110535Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 46 # number of overall hits 132210535Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 38 # number of overall hits 132310535Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 11147 # number of overall hits 132410535Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 14817 # number of overall hits 132510535Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 141203 # number of overall hits 132610535Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 9957 # number of UpgradeReq misses 132710535Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 3262 # number of UpgradeReq misses 132810535Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 13219 # number of UpgradeReq misses 132910535Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 737 # number of SCUpgradeReq misses 133010535Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1139 # number of SCUpgradeReq misses 133110535Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1876 # number of SCUpgradeReq misses 133210535Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 136539 # number of ReadExReq misses 133310535Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 15807 # number of ReadExReq misses 133410535Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 152346 # number of ReadExReq misses 133510535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses 133610535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 133710535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 16771 # number of ReadSharedReq misses 133810535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 11196 # number of ReadSharedReq misses 133910535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses 134010535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1129 # number of ReadSharedReq misses 134110535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 31500 # number of ReadSharedReq misses 134210535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 134310535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 134410535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 16771 # number of demand (read+write) misses 134510535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 147735 # number of demand (read+write) misses 134610535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses 134710535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 16936 # number of demand (read+write) misses 134810535Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 183846 # number of demand (read+write) misses 134910535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 135010535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 135110535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 16771 # number of overall misses 135210535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 147735 # number of overall misses 135310535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 2394 # number of overall misses 135410535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 16936 # number of overall misses 135510535Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 183846 # number of overall misses 135610535Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 225821 # number of WritebackDirty accesses(hits+misses) 135710535Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 225821 # number of WritebackDirty accesses(hits+misses) 135810535Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 10514 # number of UpgradeReq accesses(hits+misses) 135910535Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3365 # number of UpgradeReq accesses(hits+misses) 136010535Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 13879 # number of UpgradeReq accesses(hits+misses) 136110535Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) 136210535Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1181 # number of SCUpgradeReq accesses(hits+misses) 136310535Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2002 # number of SCUpgradeReq accesses(hits+misses) 136410535Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 150561 # number of ReadExReq accesses(hits+misses) 136510535Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 18928 # number of ReadExReq accesses(hits+misses) 136610535Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 169489 # number of ReadExReq accesses(hits+misses) 136710535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 79 # number of ReadSharedReq accesses(hits+misses) 136810535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 69 # number of ReadSharedReq accesses(hits+misses) 136910535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 41669 # number of ReadSharedReq accesses(hits+misses) 137010535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 87293 # number of ReadSharedReq accesses(hits+misses) 137110535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 46 # number of ReadSharedReq accesses(hits+misses) 137210535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 38 # number of ReadSharedReq accesses(hits+misses) 137310535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 13541 # number of ReadSharedReq accesses(hits+misses) 137410535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 12825 # number of ReadSharedReq accesses(hits+misses) 137510535Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 155560 # number of ReadSharedReq accesses(hits+misses) 137610535Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 79 # number of demand (read+write) accesses 137710535Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 69 # number of demand (read+write) accesses 137810535Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 41669 # number of demand (read+write) accesses 137910535Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 237854 # number of demand (read+write) accesses 138010535Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 46 # number of demand (read+write) accesses 138110535Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 38 # number of demand (read+write) accesses 138210535Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 13541 # number of demand (read+write) accesses 138310535Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 31753 # number of demand (read+write) accesses 138410535Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 325049 # number of demand (read+write) accesses 13858844SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.dtb.walker 79 # number of overall (read+write) accesses 13868844SAli.Saidi@ARM.comsystem.l2c.overall_accesses::cpu0.itb.walker 69 # number of overall (read+write) accesses 1387system.l2c.overall_accesses::cpu0.inst 41669 # number of overall (read+write) accesses 1388system.l2c.overall_accesses::cpu0.data 237854 # number of overall (read+write) accesses 1389system.l2c.overall_accesses::cpu1.dtb.walker 46 # number of overall (read+write) accesses 1390system.l2c.overall_accesses::cpu1.itb.walker 38 # number of overall (read+write) accesses 1391system.l2c.overall_accesses::cpu1.inst 13541 # number of overall (read+write) accesses 1392system.l2c.overall_accesses::cpu1.data 31753 # number of overall (read+write) accesses 1393system.l2c.overall_accesses::total 325049 # number of overall (read+write) accesses 1394system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947023 # miss rate for UpgradeReq accesses 1395system.l2c.UpgradeReq_miss_rate::cpu1.data 0.969391 # miss rate for UpgradeReq accesses 1396system.l2c.UpgradeReq_miss_rate::total 0.952446 # miss rate for UpgradeReq accesses 1397system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.897686 # miss rate for SCUpgradeReq accesses 1398system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.964437 # miss rate for SCUpgradeReq accesses 1399system.l2c.SCUpgradeReq_miss_rate::total 0.937063 # miss rate for SCUpgradeReq accesses 1400system.l2c.ReadExReq_miss_rate::cpu0.data 0.906868 # miss rate for ReadExReq accesses 1401system.l2c.ReadExReq_miss_rate::cpu1.data 0.835112 # miss rate for ReadExReq accesses 1402system.l2c.ReadExReq_miss_rate::total 0.898855 # miss rate for ReadExReq accesses 1403system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for ReadSharedReq accesses 1404system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028986 # miss rate for ReadSharedReq accesses 1405system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402481 # miss rate for ReadSharedReq accesses 1406system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128258 # miss rate for ReadSharedReq accesses 1407system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176796 # miss rate for ReadSharedReq accesses 1408system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.088031 # miss rate for ReadSharedReq accesses 1409system.l2c.ReadSharedReq_miss_rate::total 0.202494 # miss rate for ReadSharedReq accesses 1410system.l2c.demand_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for demand accesses 1411system.l2c.demand_miss_rate::cpu0.itb.walker 0.028986 # miss rate for demand accesses 1412system.l2c.demand_miss_rate::cpu0.inst 0.402481 # miss rate for demand accesses 1413system.l2c.demand_miss_rate::cpu0.data 0.621116 # miss rate for demand accesses 1414system.l2c.demand_miss_rate::cpu1.inst 0.176796 # miss rate for demand accesses 1415system.l2c.demand_miss_rate::cpu1.data 0.533367 # miss rate for demand accesses 1416system.l2c.demand_miss_rate::total 0.565595 # miss rate for demand accesses 1417system.l2c.overall_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for overall accesses 1418system.l2c.overall_miss_rate::cpu0.itb.walker 0.028986 # miss rate for overall accesses 1419system.l2c.overall_miss_rate::cpu0.inst 0.402481 # miss rate for overall accesses 1420system.l2c.overall_miss_rate::cpu0.data 0.621116 # miss rate for overall accesses 1421system.l2c.overall_miss_rate::cpu1.inst 0.176796 # miss rate for overall accesses 1422system.l2c.overall_miss_rate::cpu1.data 0.533367 # miss rate for overall accesses 1423system.l2c.overall_miss_rate::total 0.565595 # miss rate for overall accesses 1424system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1425system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 1426system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 1427system.l2c.blocked::no_targets 0 # number of cycles access was blocked 1428system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1429system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1430system.l2c.writebacks::writebacks 96240 # number of writebacks 1431system.l2c.writebacks::total 96240 # number of writebacks 1432system.membus.snoop_filter.tot_requests 462691 # Total number of requests made to the snoop filter. 1433system.membus.snoop_filter.hit_single_requests 248163 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1434system.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1435system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1436system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1437system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1438system.membus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1439system.membus.trans_dist::ReadReq 43996 # Transaction distribution 1440system.membus.trans_dist::ReadResp 75748 # Transaction distribution 1441system.membus.trans_dist::WriteReq 30846 # Transaction distribution 1442system.membus.trans_dist::WriteResp 30846 # Transaction distribution 1443system.membus.trans_dist::WritebackDirty 132430 # Transaction distribution 1444system.membus.trans_dist::CleanEvict 8725 # Transaction distribution 1445system.membus.trans_dist::UpgradeReq 60386 # Transaction distribution 1446system.membus.trans_dist::SCUpgradeReq 40885 # Transaction distribution 1447system.membus.trans_dist::UpgradeResp 15565 # Transaction distribution 1448system.membus.trans_dist::ReadExReq 152277 # Transaction distribution 1449system.membus.trans_dist::ReadExResp 151876 # Transaction distribution 1450system.membus.trans_dist::ReadSharedReq 31752 # Transaction distribution 1451system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 1452system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 1453system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 1454system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 1455system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 1456system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617002 # Packet count per connected master and slave (bytes) 1457system.membus.pkt_count_system.l2c.mem_side::total 738386 # Packet count per connected master and slave (bytes) 1458system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 1459system.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) 1460system.membus.pkt_count::total 847780 # Packet count per connected master and slave (bytes) 1461system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 1462system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 1463system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 1464system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17952136 # Cumulative packet size per connected master and slave (bytes) 1465system.membus.pkt_size_system.l2c.mem_side::total 18141918 # Cumulative packet size per connected master and slave (bytes) 1466system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 1467system.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 1468system.membus.pkt_size::total 20474206 # Cumulative packet size per connected master and slave (bytes) 1469system.membus.snoops 0 # Total snoops (count) 1470system.membus.snoop_fanout::samples 537521 # Request fanout histogram 1471system.membus.snoop_fanout::mean 0.010364 # Request fanout histogram 1472system.membus.snoop_fanout::stdev 0.101276 # Request fanout histogram 1473system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1474system.membus.snoop_fanout::0 531950 98.96% 98.96% # Request fanout histogram 1475system.membus.snoop_fanout::1 5571 1.04% 100.00% # Request fanout histogram 1476system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1477system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1478system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1479system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1480system.membus.snoop_fanout::total 537521 # Request fanout histogram 1481system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1482system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1483system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1484system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1485system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1486system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1487system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1488system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1489system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1490system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1491system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1492system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1493system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1494system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1495system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1496system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1497system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1498system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1499system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1500system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1501system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 1502system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1503system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1504system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 1505system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1506system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1507system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 1508system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1509system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1510system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 1511system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1512system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1513system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 1514system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1515system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1516system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 1517system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1518system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1519system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 1520system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1521system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1522system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 1523system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1524system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 1525system.realview.ethernet.postedInterrupts 0 # number of posts to CPU 1526system.realview.ethernet.droppedPackets 0 # number of packets dropped 1527system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1528system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1529system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1530system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1531system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1532system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1533system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1534system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1535system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1536system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1537system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1538system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1539system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1540system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1541system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1542system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1543system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1544system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1545system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1546system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1547system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1548system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1549system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1550system.toL2Bus.snoop_filter.tot_requests 863181 # Total number of requests made to the snoop filter. 1551system.toL2Bus.snoop_filter.hit_single_requests 444499 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1552system.toL2Bus.snoop_filter.hit_multi_requests 128781 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1553system.toL2Bus.snoop_filter.tot_snoops 9832 # Total number of snoops made to the snoop filter. 1554system.toL2Bus.snoop_filter.hit_single_snoops 9332 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1555system.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1556system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2802882797500 # Cumulative time (in ticks) in various power states 1557system.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution 1558system.toL2Bus.trans_dist::ReadResp 301660 # Transaction distribution 1559system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 1560system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 1561system.toL2Bus.trans_dist::WritebackDirty 225821 # Transaction distribution 1562system.toL2Bus.trans_dist::CleanEvict 64447 # Transaction distribution 1563system.toL2Bus.trans_dist::UpgradeReq 60576 # Transaction distribution 1564system.toL2Bus.trans_dist::SCUpgradeReq 41011 # Transaction distribution 1565system.toL2Bus.trans_dist::UpgradeResp 101587 # Transaction distribution 1566system.toL2Bus.trans_dist::ReadExReq 213650 # Transaction distribution 1567system.toL2Bus.trans_dist::ReadExResp 213650 # Transaction distribution 1568system.toL2Bus.trans_dist::ReadSharedReq 257660 # Transaction distribution 1569system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1162060 # Packet count per connected master and slave (bytes) 1570system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423694 # Packet count per connected master and slave (bytes) 1571system.toL2Bus.pkt_count::total 1585754 # Packet count per connected master and slave (bytes) 1572system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34449020 # Cumulative packet size per connected master and slave (bytes) 1573system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10413874 # Cumulative packet size per connected master and slave (bytes) 1574system.toL2Bus.pkt_size::total 44862894 # Cumulative packet size per connected master and slave (bytes) 1575system.toL2Bus.snoops 113289 # Total snoops (count) 1576system.toL2Bus.snoop_fanout::samples 1051063 # Request fanout histogram 1577system.toL2Bus.snoop_fanout::mean 0.300803 # Request fanout histogram 1578system.toL2Bus.snoop_fanout::stdev 0.459644 # Request fanout histogram 1579system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1580system.toL2Bus.snoop_fanout::0 735400 69.97% 69.97% # Request fanout histogram 1581system.toL2Bus.snoop_fanout::1 315163 29.99% 99.95% # Request fanout histogram 1582system.toL2Bus.snoop_fanout::2 500 0.05% 100.00% # Request fanout histogram 1583system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1584system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1585system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1586system.toL2Bus.snoop_fanout::total 1051063 # Request fanout histogram 1587 1588---------- End Simulation Statistics ---------- 1589