stats.txt revision 11502
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311336Sandreas.hansson@arm.comsim_seconds 2.802883 # Number of seconds simulated 411502SCurtis.Dunham@arm.comsim_ticks 2802882797500 # Number of ticks simulated 511502SCurtis.Dunham@arm.comfinal_tick 2802882797500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711502SCurtis.Dunham@arm.comhost_inst_rate 797664 # Simulator instruction rate (inst/s) 811502SCurtis.Dunham@arm.comhost_op_rate 971941 # Simulator op (including micro ops) rate (op/s) 911502SCurtis.Dunham@arm.comhost_tick_rate 15227033289 # Simulator tick rate (ticks/s) 1011502SCurtis.Dunham@arm.comhost_mem_usage 590380 # Number of bytes of host memory used 1111502SCurtis.Dunham@arm.comhost_seconds 184.07 # Real time elapsed on the host 1211502SCurtis.Dunham@arm.comsim_insts 146828219 # Number of instructions simulated 1311502SCurtis.Dunham@arm.comsim_ops 178907974 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1811502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.inst 1109284 # Number of bytes read from this memory 1911502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu0.data 9411812 # Number of bytes read from this memory 2011502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.inst 153876 # Number of bytes read from this memory 2111502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu1.data 1081872 # Number of bytes read from this memory 2210535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2311502SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 11758444 # Number of bytes read from this memory 2411502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 1109284 # Number of instructions bytes read from this memory 2511502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 153876 # Number of instructions bytes read from this memory 2611502SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 1263160 # Number of instructions bytes read from this memory 2711502SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 8475520 # Number of bytes written to this memory 2810827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 2910409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3011502SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 8493084 # Number of bytes written to this memory 3111201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 3210409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 3311502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.inst 25786 # Number of read requests responded to by this memory 3411502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu0.data 147579 # Number of read requests responded to by this memory 3511502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.inst 2559 # Number of read requests responded to by this memory 3611502SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu1.data 16924 # Number of read requests responded to by this memory 3710535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 3811502SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 192873 # Number of read requests responded to by this memory 3911502SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 132430 # Number of write requests responded to by this memory 4010827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 4110409Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4211502SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 136821 # Number of write requests responded to by this memory 4311201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 4410513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4511502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.inst 395765 # Total read bandwidth from this memory (bytes/s) 4611502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu0.data 3357904 # Total read bandwidth from this memory (bytes/s) 4711502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.inst 54899 # Total read bandwidth from this memory (bytes/s) 4811502SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu1.data 385985 # Total read bandwidth from this memory (bytes/s) 4910535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 5011502SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 4195125 # Total read bandwidth from this memory (bytes/s) 5111502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu0.inst 395765 # Instruction read bandwidth from this memory (bytes/s) 5211502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu1.inst 54899 # Instruction read bandwidth from this memory (bytes/s) 5311502SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 450665 # Instruction read bandwidth from this memory (bytes/s) 5411502SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 3023858 # Write bandwidth from this memory (bytes/s) 5510827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 5610513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 5711502SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 3030125 # Write bandwidth from this memory (bytes/s) 5811502SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 3023858 # Total bandwidth to/from this memory (bytes/s) 5911201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 6010513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6111502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.inst 395765 # Total bandwidth to/from this memory (bytes/s) 6211502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu0.data 3364156 # Total bandwidth to/from this memory (bytes/s) 6311502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.inst 54899 # Total bandwidth to/from this memory (bytes/s) 6411502SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu1.data 386000 # Total bandwidth to/from this memory (bytes/s) 6510585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 6611502SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 7225250 # Total bandwidth to/from this memory (bytes/s) 6710517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 6810517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 6910517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7010517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7110517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7210517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 7310517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 7410517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 7510517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 7610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 7710517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 7810517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 7910517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 8010517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 8110517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 8210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 8310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 8410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 858844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 8610513SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 8710513SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 8810513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 8910513SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 9010513SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 9110535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 9210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 9310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 9410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 9510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 9610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 9710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 9810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 9910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 10010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 10110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 10210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 10310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 10410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 10510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 10610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 10710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 10810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 10910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 11010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 11110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 11210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 11310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 11410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 11510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 11610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 11710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 11810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 11910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 12010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 12111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 7964 # Table walker walks requested 12211336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors 12311336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency 12411336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 12511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency 12610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 12710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 12810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 12911336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated 13011336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated 13111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated 13211336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst 13310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 13411336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 13511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 13610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 13711336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 13811336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 13910535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 14010535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 14111502SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_hits 20339693 # DTB read hits 14211336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 6871 # DTB read misses 14311502SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_hits 16391003 # DTB write hits 14410535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1093 # DTB write misses 14510535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 14610535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 14710535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 14810535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 14910535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 15010535Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 15110535Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 15210535Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 15310535Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 15411502SCurtis.Dunham@arm.comsystem.cpu0.dtb.read_accesses 20346564 # DTB read accesses 15511502SCurtis.Dunham@arm.comsystem.cpu0.dtb.write_accesses 16392096 # DTB write accesses 15610535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 15711502SCurtis.Dunham@arm.comsystem.cpu0.dtb.hits 36730696 # DTB hits 15811336Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 7964 # DTB misses 15911502SCurtis.Dunham@arm.comsystem.cpu0.dtb.accesses 36738660 # DTB accesses 16010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 16110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 16210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 16310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 16410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 16510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 16610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 16710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 16810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 16910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 17010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 17110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 17210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 17310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 17410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 17510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 17610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 17710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 17810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 17910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 18010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 18110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 18210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 18310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 18410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 18510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 18610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 18710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 18810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 18910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 3358 # Table walker walks requested 19010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 19110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 19210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 19310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 19410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 19510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 19610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 19710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 19810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 19910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 20010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 20110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 20210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 20310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 20410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 20510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 20610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 20711502SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_hits 97439155 # ITB inst hits 20810535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 3358 # ITB inst misses 20910535Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 21010535Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 21110535Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 21210535Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 21310535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 21410535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 21510535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 21610535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 21710535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 21810535Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 21910535Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 22010535Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 22110535Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 22210535Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 22310535Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 22411502SCurtis.Dunham@arm.comsystem.cpu0.itb.inst_accesses 97442513 # ITB inst accesses 22511502SCurtis.Dunham@arm.comsystem.cpu0.itb.hits 97439155 # DTB hits 22610535Sandreas.hansson@arm.comsystem.cpu0.itb.misses 3358 # DTB misses 22711502SCurtis.Dunham@arm.comsystem.cpu0.itb.accesses 97442513 # DTB accesses 22811502SCurtis.Dunham@arm.comsystem.cpu0.numCycles 5605767562 # number of cpu cycles simulated 22910535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 23010535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 23111201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 23211502SCurtis.Dunham@arm.comsystem.cpu0.kern.inst.quiesce 1966 # number of quiesce instructions executed 23311502SCurtis.Dunham@arm.comsystem.cpu0.committedInsts 95426725 # Number of instructions committed 23411502SCurtis.Dunham@arm.comsystem.cpu0.committedOps 115560170 # Number of ops (including micro ops) committed 23511502SCurtis.Dunham@arm.comsystem.cpu0.num_int_alu_accesses 100762477 # Number of integer alu accesses 23610535Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 23711502SCurtis.Dunham@arm.comsystem.cpu0.num_func_calls 8000241 # number of times a function call or return occured 23811502SCurtis.Dunham@arm.comsystem.cpu0.num_conditional_control_insts 13204192 # number of instructions that are conditional controls 23911502SCurtis.Dunham@arm.comsystem.cpu0.num_int_insts 100762477 # number of integer instructions 24010535Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 9755 # number of float instructions 24111502SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_reads 182456959 # number of times the integer registers were read 24211502SCurtis.Dunham@arm.comsystem.cpu0.num_int_register_writes 69135393 # number of times the integer registers were written 24310535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 24410535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 24511502SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_reads 349970686 # number of times the CC registers were read 24611502SCurtis.Dunham@arm.comsystem.cpu0.num_cc_register_writes 44907357 # number of times the CC registers were written 24711502SCurtis.Dunham@arm.comsystem.cpu0.num_mem_refs 37873679 # number of memory refs 24811502SCurtis.Dunham@arm.comsystem.cpu0.num_load_insts 20597264 # Number of load instructions 24911502SCurtis.Dunham@arm.comsystem.cpu0.num_store_insts 17276415 # Number of store instructions 25011502SCurtis.Dunham@arm.comsystem.cpu0.num_idle_cycles 5488183302.205065 # Number of idle cycles 25111502SCurtis.Dunham@arm.comsystem.cpu0.num_busy_cycles 117584259.794936 # Number of busy cycles 25210535Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 25310535Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 25411502SCurtis.Dunham@arm.comsystem.cpu0.Branches 21941548 # Number of branches fetched 25510535Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 25611502SCurtis.Dunham@arm.comsystem.cpu0.op_class::IntAlu 78887162 67.49% 67.50% # Class of executed instruction 25711336Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction 25810535Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 25910535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 26010535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 26110535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 26210535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 26310535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 26410535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 26510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 26610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 26710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 26810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 26910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 27010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 27110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 27210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 27310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 27410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 27510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 27610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 27710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 27810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 27910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 28010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 28110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 28210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 28310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 28410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 28511502SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemRead 20597264 17.62% 85.22% # Class of executed instruction 28611502SCurtis.Dunham@arm.comsystem.cpu0.op_class::MemWrite 17276415 14.78% 100.00% # Class of executed instruction 28710535Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 28810535Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 28911502SCurtis.Dunham@arm.comsystem.cpu0.op_class::total 116881836 # Class of executed instruction 29011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.replacements 693478 # number of replacements 29111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tagsinuse 494.853458 # Cycle average of tags in use 29211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.total_refs 35932313 # Total number of references to valid blocks. 29311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.sampled_refs 693990 # Sample count of references to valid blocks. 29411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.avg_refs 51.776413 # Average number of references to valid blocks. 29510827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 29611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853458 # Average occupied blocks per requestor 29710535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 29810535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 29910535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 30010535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 30110535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 30210535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 30310535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 30411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.tag_accesses 74113669 # Number of tag accesses 30511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.tags.data_accesses 74113669 # Number of data accesses 30611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 19108530 # number of ReadReq hits 30711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_hits::total 19108530 # number of ReadReq hits 30811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 15690319 # number of WriteReq hits 30911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_hits::total 15690319 # number of WriteReq hits 31011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 346085 # number of SoftPFReq hits 31111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 346085 # number of SoftPFReq hits 31211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379623 # number of LoadLockedReq hits 31311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 379623 # number of LoadLockedReq hits 31411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 363046 # number of StoreCondReq hits 31511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 363046 # number of StoreCondReq hits 31611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 34798849 # number of demand (read+write) hits 31711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_hits::total 34798849 # number of demand (read+write) hits 31811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 35144934 # number of overall hits 31911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_hits::total 35144934 # number of overall hits 32011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 373100 # number of ReadReq misses 32111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_misses::total 373100 # number of ReadReq misses 32211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 295799 # number of WriteReq misses 32311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_misses::total 295799 # number of WriteReq misses 32411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses 32511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses 32611336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses 32711336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses 32811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 18431 # number of StoreCondReq misses 32911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 18431 # number of StoreCondReq misses 33011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 668899 # number of demand (read+write) misses 33111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_misses::total 668899 # number of demand (read+write) misses 33211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 769220 # number of overall misses 33311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_misses::total 769220 # number of overall misses 33411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 19481630 # number of ReadReq accesses(hits+misses) 33511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 19481630 # number of ReadReq accesses(hits+misses) 33611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 15986118 # number of WriteReq accesses(hits+misses) 33711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 15986118 # number of WriteReq accesses(hits+misses) 33811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446406 # number of SoftPFReq accesses(hits+misses) 33911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 446406 # number of SoftPFReq accesses(hits+misses) 34011502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386363 # number of LoadLockedReq accesses(hits+misses) 34111502SCurtis.Dunham@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 386363 # number of LoadLockedReq accesses(hits+misses) 34211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381477 # number of StoreCondReq accesses(hits+misses) 34311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 381477 # number of StoreCondReq accesses(hits+misses) 34411502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 35467748 # number of demand (read+write) accesses 34511502SCurtis.Dunham@arm.comsystem.cpu0.dcache.demand_accesses::total 35467748 # number of demand (read+write) accesses 34611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 35914154 # number of overall (read+write) accesses 34711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.overall_accesses::total 35914154 # number of overall (read+write) accesses 34811336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 34911336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 35011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 35111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 35211502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224730 # miss rate for SoftPFReq accesses 35311502SCurtis.Dunham@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.224730 # miss rate for SoftPFReq accesses 35411336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses 35511336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses 35611502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048315 # miss rate for StoreCondReq accesses 35711502SCurtis.Dunham@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.048315 # miss rate for StoreCondReq accesses 35811201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses 35911201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses 36011201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses 36111201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses 36210535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 36310535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 36410535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 36510535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 36610535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 36710535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 36811502SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::writebacks 693478 # number of writebacks 36911502SCurtis.Dunham@arm.comsystem.cpu0.dcache.writebacks::total 693478 # number of writebacks 37011502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.replacements 1109639 # number of replacements 37111336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 37211502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.total_refs 96331337 # Total number of references to valid blocks. 37311502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.sampled_refs 1110151 # Sample count of references to valid blocks. 37411502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.avg_refs 86.773184 # Average number of references to valid blocks. 37510535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 37611336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 37710535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 37810535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 37910535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 38010535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 38110535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 38210535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 38310535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 38411502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.tag_accesses 195993154 # Number of tag accesses 38511502SCurtis.Dunham@arm.comsystem.cpu0.icache.tags.data_accesses 195993154 # Number of data accesses 38611502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 96331337 # number of ReadReq hits 38711502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_hits::total 96331337 # number of ReadReq hits 38811502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 96331337 # number of demand (read+write) hits 38911502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_hits::total 96331337 # number of demand (read+write) hits 39011502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 96331337 # number of overall hits 39111502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_hits::total 96331337 # number of overall hits 39211502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1110160 # number of ReadReq misses 39311502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_misses::total 1110160 # number of ReadReq misses 39411502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 1110160 # number of demand (read+write) misses 39511502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_misses::total 1110160 # number of demand (read+write) misses 39611502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 1110160 # number of overall misses 39711502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_misses::total 1110160 # number of overall misses 39811502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 97441497 # number of ReadReq accesses(hits+misses) 39911502SCurtis.Dunham@arm.comsystem.cpu0.icache.ReadReq_accesses::total 97441497 # number of ReadReq accesses(hits+misses) 40011502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 97441497 # number of demand (read+write) accesses 40111502SCurtis.Dunham@arm.comsystem.cpu0.icache.demand_accesses::total 97441497 # number of demand (read+write) accesses 40211502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 97441497 # number of overall (read+write) accesses 40311502SCurtis.Dunham@arm.comsystem.cpu0.icache.overall_accesses::total 97441497 # number of overall (read+write) accesses 40411336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses 40511336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses 40611336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses 40711336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses 40811336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses 40911336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses 41010535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41110535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41210535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 41310535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 41410535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 41510535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 41611502SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::writebacks 1109639 # number of writebacks 41711502SCurtis.Dunham@arm.comsystem.cpu0.icache.writebacks::total 1109639 # number of writebacks 41810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 41910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 42010628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 42110628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 42210628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 42310628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 42411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.replacements 249747 # number of replacements 42511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16131.550435 # Cycle average of tags in use 42611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.total_refs 2729892 # Total number of references to valid blocks. 42711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.sampled_refs 265865 # Sample count of references to valid blocks. 42811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.avg_refs 10.267963 # Average number of references to valid blocks. 42911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 43011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 16129.097151 # Average occupied blocks per requestor 43111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.376905 # Average occupied blocks per requestor 43211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.076379 # Average occupied blocks per requestor 43311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.984442 # Average percentage of cache occupancy 43411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy 43511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy 43611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.984592 # Average percentage of cache occupancy 43711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id 43811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 16110 # Occupied blocks per task id 43911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id 44011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id 44111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 44211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id 44311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id 44411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5562 # Occupied blocks per task id 44511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7431 # Occupied blocks per task id 44611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2624 # Occupied blocks per task id 44711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id 44811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983276 # Percentage of cache occupancy per task id 44911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.tag_accesses 59696130 # Number of tag accesses 45011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.tags.data_accesses 59696130 # Number of data accesses 45111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10179 # number of ReadReq hits 45211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4500 # number of ReadReq hits 45311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 14679 # number of ReadReq hits 45411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 510228 # number of WritebackDirty hits 45511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 510228 # number of WritebackDirty hits 45611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 1265023 # number of WritebackClean hits 45711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 1265023 # number of WritebackClean hits 45811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 94248 # number of ReadExReq hits 45911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 94248 # number of ReadExReq hits 46011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068491 # number of ReadCleanReq hits 46111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 1068491 # number of ReadCleanReq hits 46211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352197 # number of ReadSharedReq hits 46311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 352197 # number of ReadSharedReq hits 46411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10179 # number of demand (read+write) hits 46511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 4500 # number of demand (read+write) hits 46611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 1068491 # number of demand (read+write) hits 46711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 446445 # number of demand (read+write) hits 46811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_hits::total 1529615 # number of demand (read+write) hits 46911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10179 # number of overall hits 47011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 4500 # number of overall hits 47111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 1068491 # number of overall hits 47211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 446445 # number of overall hits 47311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_hits::total 1529615 # number of overall hits 47411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 212 # number of ReadReq misses 47511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 127 # number of ReadReq misses 47611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 339 # number of ReadReq misses 47711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26279 # number of UpgradeReq misses 47811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 26279 # number of UpgradeReq misses 47911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18431 # number of SCUpgradeReq misses 48011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 18431 # number of SCUpgradeReq misses 48111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 175272 # number of ReadExReq misses 48211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 175272 # number of ReadExReq misses 48311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41669 # number of ReadCleanReq misses 48411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 41669 # number of ReadCleanReq misses 48511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127964 # number of ReadSharedReq misses 48611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 127964 # number of ReadSharedReq misses 48711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 212 # number of demand (read+write) misses 48811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 127 # number of demand (read+write) misses 48911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 41669 # number of demand (read+write) misses 49011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 303236 # number of demand (read+write) misses 49111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_misses::total 345244 # number of demand (read+write) misses 49211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 212 # number of overall misses 49311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 127 # number of overall misses 49411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 41669 # number of overall misses 49511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 303236 # number of overall misses 49611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_misses::total 345244 # number of overall misses 49711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10391 # number of ReadReq accesses(hits+misses) 49811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) 49911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 15018 # number of ReadReq accesses(hits+misses) 50011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 510228 # number of WritebackDirty accesses(hits+misses) 50111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 510228 # number of WritebackDirty accesses(hits+misses) 50211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 1265023 # number of WritebackClean accesses(hits+misses) 50311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 1265023 # number of WritebackClean accesses(hits+misses) 50411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26279 # number of UpgradeReq accesses(hits+misses) 50511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 26279 # number of UpgradeReq accesses(hits+misses) 50611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18431 # number of SCUpgradeReq accesses(hits+misses) 50711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 18431 # number of SCUpgradeReq accesses(hits+misses) 50811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269520 # number of ReadExReq accesses(hits+misses) 50911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 269520 # number of ReadExReq accesses(hits+misses) 51011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110160 # number of ReadCleanReq accesses(hits+misses) 51111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 1110160 # number of ReadCleanReq accesses(hits+misses) 51211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480161 # number of ReadSharedReq accesses(hits+misses) 51311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 480161 # number of ReadSharedReq accesses(hits+misses) 51411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10391 # number of demand (read+write) accesses 51511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses 51611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 1110160 # number of demand (read+write) accesses 51711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 749681 # number of demand (read+write) accesses 51811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_accesses::total 1874859 # number of demand (read+write) accesses 51911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10391 # number of overall (read+write) accesses 52011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses 52111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 1110160 # number of overall (read+write) accesses 52211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 749681 # number of overall (read+write) accesses 52311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_accesses::total 1874859 # number of overall (read+write) accesses 52411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for ReadReq accesses 52511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027448 # miss rate for ReadReq accesses 52611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.022573 # miss rate for ReadReq accesses 52711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 52811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 52910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 53010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 53111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650312 # miss rate for ReadExReq accesses 53211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.650312 # miss rate for ReadExReq accesses 53311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037534 # miss rate for ReadCleanReq accesses 53411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037534 # miss rate for ReadCleanReq accesses 53511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266502 # miss rate for ReadSharedReq accesses 53611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266502 # miss rate for ReadSharedReq accesses 53711502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for demand accesses 53811502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027448 # miss rate for demand accesses 53911502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037534 # miss rate for demand accesses 54011502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404487 # miss rate for demand accesses 54111502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.184144 # miss rate for demand accesses 54211502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020402 # miss rate for overall accesses 54311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027448 # miss rate for overall accesses 54411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037534 # miss rate for overall accesses 54511502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404487 # miss rate for overall accesses 54611502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.184144 # miss rate for overall accesses 54710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 54810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 54910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 55010535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 55110535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 55210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 55311502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::writebacks 193031 # number of writebacks 55411502SCurtis.Dunham@arm.comsystem.cpu0.l2cache.writebacks::total 193031 # number of writebacks 55511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 3720034 # Total number of requests made to the snoop filter. 55611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860217 # Number of requests hitting in the snoop filter with a single holder of the requested data. 55711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 55811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 218415 # Total number of snoops made to the snoop filter. 55911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215401 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 56011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3014 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 56111336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution 56211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution 56310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 56410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 56511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 510228 # Transaction distribution 56611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 1292889 # Transaction distribution 56711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 26279 # Transaction distribution 56811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18431 # Transaction distribution 56911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 44710 # Transaction distribution 57011336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 269520 # Transaction distribution 57111336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 269520 # Transaction distribution 57211502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110160 # Transaction distribution 57311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 480161 # Transaction distribution 57411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3348003 # Packet count per connected master and slave (bytes) 57511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402094 # Packet count per connected master and slave (bytes) 57610535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 57711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 57811502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_count::total 5791721 # Packet count per connected master and slave (bytes) 57911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142103224 # Cumulative packet size per connected master and slave (bytes) 58011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552708 # Cumulative packet size per connected master and slave (bytes) 58110535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 58211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 58311502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.pkt_size::total 234739180 # Cumulative packet size per connected master and slave (bytes) 58411502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoops 623521 # Total snoops (count) 58511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 4318336 # Request fanout histogram 58611502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.067052 # Request fanout histogram 58711502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.252886 # Request fanout histogram 58810535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 58911502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 4031799 93.36% 93.36% # Request fanout histogram 59011502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 283523 6.57% 99.93% # Request fanout histogram 59111502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 3014 0.07% 100.00% # Request fanout histogram 59210535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 59311138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 59410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 59511502SCurtis.Dunham@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 4318336 # Request fanout histogram 59610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 59710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 59810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 59910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 60010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 60110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 60210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 60310628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 60410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 60510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 60610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 60710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 60810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 60910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 61010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 61110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 61210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 61310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 61510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 61610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 61810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 61910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 62010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 62110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 62210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 62310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 62410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 62511336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 3359 # Table walker walks requested 62611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 62711336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 62811336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 62911336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 63010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 63110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 63210628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 63311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated 63411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated 63511336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated 63611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst 63710628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 63811336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst 63911336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst 64010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 64111336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst 64211336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst 64310535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 64410535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 64511502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_hits 12173945 # DTB read hits 64611336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 2853 # DTB read misses 64711502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_hits 7587221 # DTB write hits 64810535Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 506 # DTB write misses 64910535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 65010535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 65110535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65210535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 65310535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 65410535Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 65510535Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 65610535Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 65710535Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 65811502SCurtis.Dunham@arm.comsystem.cpu1.dtb.read_accesses 12176798 # DTB read accesses 65911502SCurtis.Dunham@arm.comsystem.cpu1.dtb.write_accesses 7587727 # DTB write accesses 66010535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 66111502SCurtis.Dunham@arm.comsystem.cpu1.dtb.hits 19761166 # DTB hits 66211336Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 3359 # DTB misses 66311502SCurtis.Dunham@arm.comsystem.cpu1.dtb.accesses 19764525 # DTB accesses 66410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 66510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 66610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 66710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 66910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 67010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 67110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 67210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 67310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 67410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 67510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 67610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 67710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 67810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 67910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 68010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 68110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 68210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 68310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 68410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 68510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 68610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 68710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 68810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 68910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 69110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 69210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 1734 # Table walker walks requested 69410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 69510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 69610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 69710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 69810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 69910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 70010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 70110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 70210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 70310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 70410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 70610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 70710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 70810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 70910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 71010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 71111502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_hits 53671758 # ITB inst hits 71210535Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 1734 # ITB inst misses 71310535Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 71410535Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 71510535Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 71610535Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 71710535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 71810535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 71910535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72010535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 72110535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 72210535Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 72310535Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 72410535Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 72510535Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 72610535Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 72710535Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 72811502SCurtis.Dunham@arm.comsystem.cpu1.itb.inst_accesses 53673492 # ITB inst accesses 72911502SCurtis.Dunham@arm.comsystem.cpu1.itb.hits 53671758 # DTB hits 73010535Sandreas.hansson@arm.comsystem.cpu1.itb.misses 1734 # DTB misses 73111502SCurtis.Dunham@arm.comsystem.cpu1.itb.accesses 53673492 # DTB accesses 73211502SCurtis.Dunham@arm.comsystem.cpu1.numCycles 5605296470 # number of cpu cycles simulated 73310535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 73410535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 73511201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 73611201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 73711502SCurtis.Dunham@arm.comsystem.cpu1.committedInsts 51401494 # Number of instructions committed 73811502SCurtis.Dunham@arm.comsystem.cpu1.committedOps 63347804 # Number of ops (including micro ops) committed 73911502SCurtis.Dunham@arm.comsystem.cpu1.num_int_alu_accesses 56984416 # Number of integer alu accesses 74010535Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 74111502SCurtis.Dunham@arm.comsystem.cpu1.num_func_calls 9170873 # number of times a function call or return occured 74211502SCurtis.Dunham@arm.comsystem.cpu1.num_conditional_control_insts 5967115 # number of instructions that are conditional controls 74311502SCurtis.Dunham@arm.comsystem.cpu1.num_int_insts 56984416 # number of integer instructions 74410535Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 1792 # number of float instructions 74511502SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_reads 110675031 # number of times the integer registers were read 74611502SCurtis.Dunham@arm.comsystem.cpu1.num_int_register_writes 41298494 # number of times the integer registers were written 74710535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 74810535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 74911502SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_reads 196269240 # number of times the CC registers were read 75011502SCurtis.Dunham@arm.comsystem.cpu1.num_cc_register_writes 18894452 # number of times the CC registers were written 75111502SCurtis.Dunham@arm.comsystem.cpu1.num_mem_refs 20026424 # number of memory refs 75211502SCurtis.Dunham@arm.comsystem.cpu1.num_load_insts 12289568 # Number of load instructions 75311502SCurtis.Dunham@arm.comsystem.cpu1.num_store_insts 7736856 # Number of store instructions 75411502SCurtis.Dunham@arm.comsystem.cpu1.num_idle_cycles 5539682760.605002 # Number of idle cycles 75511502SCurtis.Dunham@arm.comsystem.cpu1.num_busy_cycles 65613709.394997 # Number of busy cycles 75610535Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 75710535Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 75811502SCurtis.Dunham@arm.comsystem.cpu1.Branches 15217528 # Number of branches fetched 75910535Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 76011502SCurtis.Dunham@arm.comsystem.cpu1.op_class::IntAlu 45401456 69.36% 69.36% # Class of executed instruction 76111336Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction 76210535Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 76310535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 76410535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 76510535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 76610535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 76710535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 76810535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 76910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 77010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 77110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 77210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 77310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 77410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 77510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 77610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 77710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 77810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 77910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 78010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 78110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 78210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 78310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 78410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 78510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 78610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 78710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 78810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 78911502SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemRead 12289568 18.77% 88.18% # Class of executed instruction 79011502SCurtis.Dunham@arm.comsystem.cpu1.op_class::MemWrite 7736856 11.82% 100.00% # Class of executed instruction 79110535Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 79210535Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 79311502SCurtis.Dunham@arm.comsystem.cpu1.op_class::total 65459659 # Class of executed instruction 79411336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 191946 # number of replacements 79511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tagsinuse 472.736015 # Cycle average of tags in use 79611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.total_refs 19503545 # Total number of references to valid blocks. 79711336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks. 79811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.avg_refs 101.422491 # Average number of references to valid blocks. 79910535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 80011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736015 # Average occupied blocks per requestor 80111336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy 80211336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy 80310535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 80410535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 80510535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 80610535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 80711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.tag_accesses 39752069 # Number of tag accesses 80811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.tags.data_accesses 39752069 # Number of data accesses 80911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 11858716 # number of ReadReq hits 81011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_hits::total 11858716 # number of ReadReq hits 81111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 7397520 # number of WriteReq hits 81211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_hits::total 7397520 # number of WriteReq hits 81311336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits 81411336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits 81510535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 81610535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 81711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 72399 # number of StoreCondReq hits 81811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 72399 # number of StoreCondReq hits 81911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 19256236 # number of demand (read+write) hits 82011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_hits::total 19256236 # number of demand (read+write) hits 82111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 19306336 # number of overall hits 82211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_hits::total 19306336 # number of overall hits 82311336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 136638 # number of ReadReq misses 82411336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 136638 # number of ReadReq misses 82511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 92454 # number of WriteReq misses 82611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_misses::total 92454 # number of WriteReq misses 82711336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses 82811336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses 82910535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 83010535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 83111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 22580 # number of StoreCondReq misses 83211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 22580 # number of StoreCondReq misses 83311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 229092 # number of demand (read+write) misses 83411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_misses::total 229092 # number of demand (read+write) misses 83511502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 259810 # number of overall misses 83611502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_misses::total 259810 # number of overall misses 83711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 11995354 # number of ReadReq accesses(hits+misses) 83811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 11995354 # number of ReadReq accesses(hits+misses) 83911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 7489974 # number of WriteReq accesses(hits+misses) 84011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 7489974 # number of WriteReq accesses(hits+misses) 84110535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 84210535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 84310535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 84410535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 84510535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 84610535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 84711502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 19485328 # number of demand (read+write) accesses 84811502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_accesses::total 19485328 # number of demand (read+write) accesses 84911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 19566146 # number of overall (read+write) accesses 85011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.overall_accesses::total 19566146 # number of overall (read+write) accesses 85111336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses 85211336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 85311502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012344 # miss rate for WriteReq accesses 85411502SCurtis.Dunham@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.012344 # miss rate for WriteReq accesses 85511336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses 85611336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses 85710535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 85810535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 85911502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237737 # miss rate for StoreCondReq accesses 86011502SCurtis.Dunham@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.237737 # miss rate for StoreCondReq accesses 86111502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses 86211502SCurtis.Dunham@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses 86310892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 86410892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 86510535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 86610535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 86710535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 86810535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 86910535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 87010535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 87111336Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks 87211336Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 191946 # number of writebacks 87311336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 523401 # number of replacements 87411336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use 87511502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.total_refs 53148935 # Total number of references to valid blocks. 87611336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. 87711502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.avg_refs 101.446108 # Average number of references to valid blocks. 87810535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 87911336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor 88010535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 88110535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 88210535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 88310535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 88410535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 88510535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 88611502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.tag_accesses 107869609 # Number of tag accesses 88711502SCurtis.Dunham@arm.comsystem.cpu1.icache.tags.data_accesses 107869609 # Number of data accesses 88811502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 53148935 # number of ReadReq hits 88911502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_hits::total 53148935 # number of ReadReq hits 89011502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 53148935 # number of demand (read+write) hits 89111502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_hits::total 53148935 # number of demand (read+write) hits 89211502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 53148935 # number of overall hits 89311502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_hits::total 53148935 # number of overall hits 89411336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses 89511336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses 89611336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 523913 # number of demand (read+write) misses 89711336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 523913 # number of demand (read+write) misses 89811336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 523913 # number of overall misses 89911336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 523913 # number of overall misses 90011502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 53672848 # number of ReadReq accesses(hits+misses) 90111502SCurtis.Dunham@arm.comsystem.cpu1.icache.ReadReq_accesses::total 53672848 # number of ReadReq accesses(hits+misses) 90211502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 53672848 # number of demand (read+write) accesses 90311502SCurtis.Dunham@arm.comsystem.cpu1.icache.demand_accesses::total 53672848 # number of demand (read+write) accesses 90411502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 53672848 # number of overall (read+write) accesses 90511502SCurtis.Dunham@arm.comsystem.cpu1.icache.overall_accesses::total 53672848 # number of overall (read+write) accesses 90610535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 90710535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 90810535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 90910535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 91010535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 91110535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 91210535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 91310535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 91410535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 91510535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 91610535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 91710535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 91811336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 523401 # number of writebacks 91911336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 523401 # number of writebacks 92010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 92110628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 92210628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 92310628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 92410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 92510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 92611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.replacements 47503 # number of replacements 92711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tagsinuse 15229.973296 # Cycle average of tags in use 92811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.total_refs 1184897 # Total number of references to valid blocks. 92911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.sampled_refs 62526 # Sample count of references to valid blocks. 93011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.avg_refs 18.950469 # Average number of references to valid blocks. 93110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 93211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 15227.338556 # Average occupied blocks per requestor 93311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 0.619660 # Average occupied blocks per requestor 93411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.015081 # Average occupied blocks per requestor 93511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.929403 # Average percentage of cache occupancy 93611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000038 # Average percentage of cache occupancy 93710892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 93811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.929564 # Average percentage of cache occupancy 93911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id 94011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15005 # Occupied blocks per task id 94110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 94210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 94311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 94411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id 94511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9469 # Occupied blocks per task id 94611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5007 # Occupied blocks per task id 94711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id 94811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.915833 # Percentage of cache occupancy per task id 94911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.tag_accesses 24502168 # Number of tag accesses 95011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.tags.data_accesses 24502168 # Number of data accesses 95111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3621 # number of ReadReq hits 95211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1918 # number of ReadReq hits 95311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 5539 # number of ReadReq hits 95411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 121092 # number of WritebackDirty hits 95511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 121092 # number of WritebackDirty hits 95611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 583097 # number of WritebackClean hits 95711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 583097 # number of WritebackClean hits 95811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 19779 # number of ReadExReq hits 95911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 19779 # number of ReadExReq hits 96011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510372 # number of ReadCleanReq hits 96111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 510372 # number of ReadCleanReq hits 96211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99144 # number of ReadSharedReq hits 96311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 99144 # number of ReadSharedReq hits 96411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3621 # number of demand (read+write) hits 96511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 1918 # number of demand (read+write) hits 96611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 510372 # number of demand (read+write) hits 96711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 118923 # number of demand (read+write) hits 96811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_hits::total 634834 # number of demand (read+write) hits 96911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3621 # number of overall hits 97011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 1918 # number of overall hits 97111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 510372 # number of overall hits 97211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 118923 # number of overall hits 97311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_hits::total 634834 # number of overall hits 97411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses 97511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 273 # number of ReadReq misses 97611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 617 # number of ReadReq misses 97711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28839 # number of UpgradeReq misses 97811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 28839 # number of UpgradeReq misses 97911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22580 # number of SCUpgradeReq misses 98011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 22580 # number of SCUpgradeReq misses 98111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 43836 # number of ReadExReq misses 98211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 43836 # number of ReadExReq misses 98311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13541 # number of ReadCleanReq misses 98411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 13541 # number of ReadCleanReq misses 98511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73530 # number of ReadSharedReq misses 98611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 73530 # number of ReadSharedReq misses 98711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses 98811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 273 # number of demand (read+write) misses 98911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 13541 # number of demand (read+write) misses 99011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 117366 # number of demand (read+write) misses 99111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_misses::total 131524 # number of demand (read+write) misses 99211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses 99311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 273 # number of overall misses 99411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 13541 # number of overall misses 99511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 117366 # number of overall misses 99611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_misses::total 131524 # number of overall misses 99711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses) 99811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) 99911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses) 100011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 121092 # number of WritebackDirty accesses(hits+misses) 100111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 121092 # number of WritebackDirty accesses(hits+misses) 100211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 583097 # number of WritebackClean accesses(hits+misses) 100311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 583097 # number of WritebackClean accesses(hits+misses) 100411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28839 # number of UpgradeReq accesses(hits+misses) 100511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 28839 # number of UpgradeReq accesses(hits+misses) 100611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22580 # number of SCUpgradeReq accesses(hits+misses) 100711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 22580 # number of SCUpgradeReq accesses(hits+misses) 100811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 100911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 101011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523913 # number of ReadCleanReq accesses(hits+misses) 101111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 523913 # number of ReadCleanReq accesses(hits+misses) 101211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172674 # number of ReadSharedReq accesses(hits+misses) 101311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 172674 # number of ReadSharedReq accesses(hits+misses) 101411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3965 # number of demand (read+write) accesses 101511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses 101611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 523913 # number of demand (read+write) accesses 101711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 236289 # number of demand (read+write) accesses 101811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 766358 # number of demand (read+write) accesses 101911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3965 # number of overall (read+write) accesses 102011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses 102111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 523913 # number of overall (read+write) accesses 102211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 236289 # number of overall (read+write) accesses 102311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 766358 # number of overall (read+write) accesses 102411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for ReadReq accesses 102511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.124601 # miss rate for ReadReq accesses 102611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.100227 # miss rate for ReadReq accesses 102711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 102811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 102910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 103010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 103111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689083 # miss rate for ReadExReq accesses 103211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.689083 # miss rate for ReadExReq accesses 103311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025846 # miss rate for ReadCleanReq accesses 103411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025846 # miss rate for ReadCleanReq accesses 103511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425831 # miss rate for ReadSharedReq accesses 103611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425831 # miss rate for ReadSharedReq accesses 103711502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for demand accesses 103811502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.124601 # miss rate for demand accesses 103911502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025846 # miss rate for demand accesses 104011502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496705 # miss rate for demand accesses 104111502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.171622 # miss rate for demand accesses 104211502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.086759 # miss rate for overall accesses 104311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.124601 # miss rate for overall accesses 104411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025846 # miss rate for overall accesses 104511502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496705 # miss rate for overall accesses 104611502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.171622 # miss rate for overall accesses 104710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 104810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 104910535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 105010535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 105110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 105210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 105311502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::writebacks 32790 # number of writebacks 105411502SCurtis.Dunham@arm.comsystem.cpu1.l2cache.writebacks::total 32790 # number of writebacks 105511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 1533520 # Total number of requests made to the snoop filter. 105611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 773321 # Number of requests hitting in the snoop filter with a single holder of the requested data. 105711138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 105811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 166202 # Total number of snoops made to the snoop filter. 105911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164239 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 106011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1963 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 106111336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution 106211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution 106310535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 106410535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 106511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 121092 # Transaction distribution 106611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 594255 # Transaction distribution 106711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 28839 # Transaction distribution 106811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22580 # Transaction distribution 106911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution 107011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 107111336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 107211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 523913 # Transaction distribution 107311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 172674 # Transaction distribution 107411336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571581 # Packet count per connected master and slave (bytes) 107511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778822 # Packet count per connected master and slave (bytes) 107610535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 107711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 107811502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.pkt_count::total 2369099 # Packet count per connected master and slave (bytes) 107911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67028804 # Cumulative packet size per connected master and slave (bytes) 108011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27426222 # Cumulative packet size per connected master and slave (bytes) 108110535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 108211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 108311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 94492418 # Cumulative packet size per connected master and slave (bytes) 108411502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoops 347973 # Total snoops (count) 108511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 1820541 # Request fanout histogram 108611502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.108229 # Request fanout histogram 108711502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.314122 # Request fanout histogram 108810535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 108911502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 1625468 89.28% 89.28% # Request fanout histogram 109011502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 193110 10.61% 99.89% # Request fanout histogram 109111502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 1963 0.11% 100.00% # Request fanout histogram 109210535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 109311138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 109410827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 109511502SCurtis.Dunham@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 1820541 # Request fanout histogram 109610726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30995 # Transaction distribution 109710726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30995 # Transaction distribution 109810726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59419 # Transaction distribution 109910892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 59419 # Transaction distribution 110010726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 110110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 110211245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 110310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 110410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 110510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 110610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 110710513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 110810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 110910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 111010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 111110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 111210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 111310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 111410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 111510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 111610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 111710513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 111810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 111910726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 112010513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 112110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 112210726Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 112310726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 112410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 112511245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 112610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 112710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 112810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 112910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 113010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 113110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 113210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 113310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 113410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 113510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 113610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 113710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 113810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 113910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 114010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 114110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 114210726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 114310513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 114410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 114510726Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 114610513SAli.Saidi@ARM.comsystem.iocache.tags.replacements 36442 # number of replacements 114711502SCurtis.Dunham@arm.comsystem.iocache.tags.tagsinuse 14.586085 # Cycle average of tags in use 11489885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 114910513SAli.Saidi@ARM.comsystem.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 115010513SAli.Saidi@ARM.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 115111502SCurtis.Dunham@arm.comsystem.iocache.tags.warmup_cycle 246641287009 # Cycle when the warmup percentage was hit. 115211502SCurtis.Dunham@arm.comsystem.iocache.tags.occ_blocks::realview.ide 14.586085 # Average occupied blocks per requestor 115311336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 115411336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 115510513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 115610513SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 115710513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 115810513SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 328284 # Number of tag accesses 115910513SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 328284 # Number of data accesses 116010513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 116110513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::total 252 # number of ReadReq misses 116210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 116310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 116411456Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 36476 # number of demand (read+write) misses 116511456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 36476 # number of demand (read+write) misses 116611456Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 36476 # number of overall misses 116711456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 36476 # number of overall misses 116810513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 116910513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 117010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 117110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 117211456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 36476 # number of demand (read+write) accesses 117311456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 36476 # number of demand (read+write) accesses 117411456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 36476 # number of overall (read+write) accesses 117511456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 36476 # number of overall (read+write) accesses 117610513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 117710513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 117810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 117910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 118010513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 118110513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 118210513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 118310513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 11848844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 11858844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 11868844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 11878844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 11888983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 11898983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 119010585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 119110585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 119211502SCurtis.Dunham@arm.comsystem.l2c.tags.replacements 107745 # number of replacements 119311502SCurtis.Dunham@arm.comsystem.l2c.tags.tagsinuse 62386.756535 # Cycle average of tags in use 119411502SCurtis.Dunham@arm.comsystem.l2c.tags.total_refs 243993 # Total number of references to valid blocks. 119511502SCurtis.Dunham@arm.comsystem.l2c.tags.sampled_refs 168404 # Sample count of references to valid blocks. 119611502SCurtis.Dunham@arm.comsystem.l2c.tags.avg_refs 1.448855 # Average number of references to valid blocks. 119710535Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 119811502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::writebacks 48109.911781 # Average occupied blocks per requestor 119911502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010811 # Average occupied blocks per requestor 120011336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.030814 # Average occupied blocks per requestor 120111502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 7778.233869 # Average occupied blocks per requestor 120211502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4058.534945 # Average occupied blocks per requestor 120311502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1666.123091 # Average occupied blocks per requestor 120411502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 768.911224 # Average occupied blocks per requestor 120511502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::writebacks 0.734099 # Average percentage of cache occupancy 120611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy 120711138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 120811502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.118686 # Average percentage of cache occupancy 120911502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.061928 # Average percentage of cache occupancy 121011502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.025423 # Average percentage of cache occupancy 121111502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.011733 # Average percentage of cache occupancy 121211502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_percent::total 0.951946 # Average percentage of cache occupancy 121311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 121411502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 60653 # Occupied blocks per task id 121511201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 121611201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 121711502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id 121811502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1824 # Occupied blocks per task id 121911502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 13234 # Occupied blocks per task id 122011502SCurtis.Dunham@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 45523 # Occupied blocks per task id 122111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 122211502SCurtis.Dunham@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.925491 # Percentage of cache occupancy per task id 122311502SCurtis.Dunham@arm.comsystem.l2c.tags.tag_accesses 5181909 # Number of tag accesses 122411502SCurtis.Dunham@arm.comsystem.l2c.tags.data_accesses 5181909 # Number of data accesses 122511502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::writebacks 225821 # number of WritebackDirty hits 122611502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_hits::total 225821 # number of WritebackDirty hits 122711502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 557 # number of UpgradeReq hits 122811502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 103 # number of UpgradeReq hits 122911502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_hits::total 660 # number of UpgradeReq hits 123011502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 84 # number of SCUpgradeReq hits 123111502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 42 # number of SCUpgradeReq hits 123211502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_hits::total 126 # number of SCUpgradeReq hits 123311502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 14022 # number of ReadExReq hits 123411502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 3121 # number of ReadExReq hits 123511502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_hits::total 17143 # number of ReadExReq hits 123611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 71 # number of ReadSharedReq hits 123711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 67 # number of ReadSharedReq hits 123811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 24898 # number of ReadSharedReq hits 123911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 76097 # number of ReadSharedReq hits 124011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 46 # number of ReadSharedReq hits 124111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 38 # number of ReadSharedReq hits 124211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 11147 # number of ReadSharedReq hits 124311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 11696 # number of ReadSharedReq hits 124411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_hits::total 124060 # number of ReadSharedReq hits 124511502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits 124611502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 67 # number of demand (read+write) hits 124711502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.inst 24898 # number of demand (read+write) hits 124811502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu0.data 90119 # number of demand (read+write) hits 124911502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 46 # number of demand (read+write) hits 125011502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 38 # number of demand (read+write) hits 125111502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.inst 11147 # number of demand (read+write) hits 125211502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::cpu1.data 14817 # number of demand (read+write) hits 125311502SCurtis.Dunham@arm.comsystem.l2c.demand_hits::total 141203 # number of demand (read+write) hits 125411502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 71 # number of overall hits 125511502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 67 # number of overall hits 125611502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.inst 24898 # number of overall hits 125711502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu0.data 90119 # number of overall hits 125811502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 46 # number of overall hits 125911502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 38 # number of overall hits 126011502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.inst 11147 # number of overall hits 126111502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::cpu1.data 14817 # number of overall hits 126211502SCurtis.Dunham@arm.comsystem.l2c.overall_hits::total 141203 # number of overall hits 126311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 9957 # number of UpgradeReq misses 126411502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 3262 # number of UpgradeReq misses 126511502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_misses::total 13219 # number of UpgradeReq misses 126611336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 737 # number of SCUpgradeReq misses 126711502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1139 # number of SCUpgradeReq misses 126811502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_misses::total 1876 # number of SCUpgradeReq misses 126911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 136539 # number of ReadExReq misses 127011502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 15807 # number of ReadExReq misses 127111502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_misses::total 152346 # number of ReadExReq misses 127211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses 127310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 127411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 16771 # number of ReadSharedReq misses 127511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 11196 # number of ReadSharedReq misses 127611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 2394 # number of ReadSharedReq misses 127711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1129 # number of ReadSharedReq misses 127811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_misses::total 31500 # number of ReadSharedReq misses 127911201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 128010535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 128111502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.inst 16771 # number of demand (read+write) misses 128211502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu0.data 147735 # number of demand (read+write) misses 128311502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.inst 2394 # number of demand (read+write) misses 128411502SCurtis.Dunham@arm.comsystem.l2c.demand_misses::cpu1.data 16936 # number of demand (read+write) misses 128511336Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 183846 # number of demand (read+write) misses 128611201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 128710535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 128811502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.inst 16771 # number of overall misses 128911502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu0.data 147735 # number of overall misses 129011502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.inst 2394 # number of overall misses 129111502SCurtis.Dunham@arm.comsystem.l2c.overall_misses::cpu1.data 16936 # number of overall misses 129211336Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 183846 # number of overall misses 129311502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 225821 # number of WritebackDirty accesses(hits+misses) 129411502SCurtis.Dunham@arm.comsystem.l2c.WritebackDirty_accesses::total 225821 # number of WritebackDirty accesses(hits+misses) 129511502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 10514 # number of UpgradeReq accesses(hits+misses) 129611502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3365 # number of UpgradeReq accesses(hits+misses) 129711502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_accesses::total 13879 # number of UpgradeReq accesses(hits+misses) 129811502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses) 129911502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1181 # number of SCUpgradeReq accesses(hits+misses) 130011502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2002 # number of SCUpgradeReq accesses(hits+misses) 130111502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 150561 # number of ReadExReq accesses(hits+misses) 130211502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 18928 # number of ReadExReq accesses(hits+misses) 130311502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_accesses::total 169489 # number of ReadExReq accesses(hits+misses) 130411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 79 # number of ReadSharedReq accesses(hits+misses) 130511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 69 # number of ReadSharedReq accesses(hits+misses) 130611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 41669 # number of ReadSharedReq accesses(hits+misses) 130711502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 87293 # number of ReadSharedReq accesses(hits+misses) 130811502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 46 # number of ReadSharedReq accesses(hits+misses) 130911502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 38 # number of ReadSharedReq accesses(hits+misses) 131011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 13541 # number of ReadSharedReq accesses(hits+misses) 131111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 12825 # number of ReadSharedReq accesses(hits+misses) 131211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_accesses::total 155560 # number of ReadSharedReq accesses(hits+misses) 131311502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 79 # number of demand (read+write) accesses 131411502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 69 # number of demand (read+write) accesses 131511502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.inst 41669 # number of demand (read+write) accesses 131611502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu0.data 237854 # number of demand (read+write) accesses 131711502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 46 # number of demand (read+write) accesses 131811502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 38 # number of demand (read+write) accesses 131911502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.inst 13541 # number of demand (read+write) accesses 132011502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::cpu1.data 31753 # number of demand (read+write) accesses 132111502SCurtis.Dunham@arm.comsystem.l2c.demand_accesses::total 325049 # number of demand (read+write) accesses 132211502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 79 # number of overall (read+write) accesses 132311502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 69 # number of overall (read+write) accesses 132411502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.inst 41669 # number of overall (read+write) accesses 132511502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu0.data 237854 # number of overall (read+write) accesses 132611502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 46 # number of overall (read+write) accesses 132711502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 38 # number of overall (read+write) accesses 132811502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.inst 13541 # number of overall (read+write) accesses 132911502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::cpu1.data 31753 # number of overall (read+write) accesses 133011502SCurtis.Dunham@arm.comsystem.l2c.overall_accesses::total 325049 # number of overall (read+write) accesses 133111502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.947023 # miss rate for UpgradeReq accesses 133211502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.969391 # miss rate for UpgradeReq accesses 133311502SCurtis.Dunham@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.952446 # miss rate for UpgradeReq accesses 133411502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.897686 # miss rate for SCUpgradeReq accesses 133511502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.964437 # miss rate for SCUpgradeReq accesses 133611502SCurtis.Dunham@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.937063 # miss rate for SCUpgradeReq accesses 133711502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.906868 # miss rate for ReadExReq accesses 133811502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.835112 # miss rate for ReadExReq accesses 133911502SCurtis.Dunham@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.898855 # miss rate for ReadExReq accesses 134011502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for ReadSharedReq accesses 134111502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.028986 # miss rate for ReadSharedReq accesses 134211502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.402481 # miss rate for ReadSharedReq accesses 134311502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128258 # miss rate for ReadSharedReq accesses 134411502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176796 # miss rate for ReadSharedReq accesses 134511502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.088031 # miss rate for ReadSharedReq accesses 134611502SCurtis.Dunham@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.202494 # miss rate for ReadSharedReq accesses 134711502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for demand accesses 134811502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.028986 # miss rate for demand accesses 134911502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.402481 # miss rate for demand accesses 135011502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.621116 # miss rate for demand accesses 135111502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.176796 # miss rate for demand accesses 135211502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.533367 # miss rate for demand accesses 135311502SCurtis.Dunham@arm.comsystem.l2c.demand_miss_rate::total 0.565595 # miss rate for demand accesses 135411502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.101266 # miss rate for overall accesses 135511502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.028986 # miss rate for overall accesses 135611502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.402481 # miss rate for overall accesses 135711502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.621116 # miss rate for overall accesses 135811502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.176796 # miss rate for overall accesses 135911502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.533367 # miss rate for overall accesses 136011502SCurtis.Dunham@arm.comsystem.l2c.overall_miss_rate::total 0.565595 # miss rate for overall accesses 136110535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 136210535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 136310535Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 136410535Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 136510535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 136610535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 136711502SCurtis.Dunham@arm.comsystem.l2c.writebacks::writebacks 96240 # number of writebacks 136811502SCurtis.Dunham@arm.comsystem.l2c.writebacks::total 96240 # number of writebacks 136911502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_requests 462691 # Total number of requests made to the snoop filter. 137011502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_requests 248163 # Number of requests hitting in the snoop filter with a single holder of the requested data. 137111502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_requests 501 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 137211502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 137311502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 137411502SCurtis.Dunham@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 137511201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 43996 # Transaction distribution 137611502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 75748 # Transaction distribution 137710827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 30846 # Transaction distribution 137810827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 30846 # Transaction distribution 137911502SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 132430 # Transaction distribution 138011502SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 8725 # Transaction distribution 138111502SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeReq 60386 # Transaction distribution 138211502SCurtis.Dunham@arm.comsystem.membus.trans_dist::SCUpgradeReq 40885 # Transaction distribution 138311502SCurtis.Dunham@arm.comsystem.membus.trans_dist::UpgradeResp 15565 # Transaction distribution 138411502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 152277 # Transaction distribution 138511502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 151876 # Transaction distribution 138611502SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 31752 # Transaction distribution 138710892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 138810892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 138910726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 139010535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 139110535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 139211502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617002 # Packet count per connected master and slave (bytes) 139311502SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 738386 # Packet count per connected master and slave (bytes) 139411336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 139511336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) 139611502SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 847780 # Packet count per connected master and slave (bytes) 139710726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 139810535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 139910535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 140011502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17952136 # Cumulative packet size per connected master and slave (bytes) 140111502SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 18141918 # Cumulative packet size per connected master and slave (bytes) 140210892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 140310892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 140411502SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 20474206 # Cumulative packet size per connected master and slave (bytes) 140510535Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 140611502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 537521 # Request fanout histogram 140711502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0.010364 # Request fanout histogram 140811502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0.101276 # Request fanout histogram 140910535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 141011502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 531950 98.96% 98.96% # Request fanout histogram 141111502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 5571 1.04% 100.00% # Request fanout histogram 141210535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 141310535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 141411502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 141510535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 141611502SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 537521 # Request fanout histogram 141711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 141811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 141911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 142011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 142111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 142211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 142310535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 142410535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 142510535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 142610535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 142710535Sandreas.hansson@arm.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 142810535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 142910535Sandreas.hansson@arm.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 143010535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 143110535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 143210535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 143310535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 143410535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 143510535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 143610535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 143710535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 143810535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 143910535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 144010535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 144110535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 144210535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 144310535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 144410535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 144510535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 144610535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 144710535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 144810535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 144910535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 145010535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 145110535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 145210535Sandreas.hansson@arm.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 145310535Sandreas.hansson@arm.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 145411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 145511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 145611239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 145711239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 145811502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_requests 863181 # Total number of requests made to the snoop filter. 145911502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 444499 # Number of requests hitting in the snoop filter with a single holder of the requested data. 146011502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 128781 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 146111502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 9832 # Total number of snoops made to the snoop filter. 146211502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 9332 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 146311502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 146410892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution 146511502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadResp 301660 # Transaction distribution 146610827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 146710827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 146811502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 225821 # Transaction distribution 146911502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::CleanEvict 64447 # Transaction distribution 147011502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 60576 # Transaction distribution 147111502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 41011 # Transaction distribution 147211502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 101587 # Transaction distribution 147311502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExReq 213650 # Transaction distribution 147411502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadExResp 213650 # Transaction distribution 147511502SCurtis.Dunham@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 257660 # Transaction distribution 147611502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1162060 # Packet count per connected master and slave (bytes) 147711502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423694 # Packet count per connected master and slave (bytes) 147811502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_count::total 1585754 # Packet count per connected master and slave (bytes) 147911502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34449020 # Cumulative packet size per connected master and slave (bytes) 148011502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10413874 # Cumulative packet size per connected master and slave (bytes) 148111502SCurtis.Dunham@arm.comsystem.toL2Bus.pkt_size::total 44862894 # Cumulative packet size per connected master and slave (bytes) 148211502SCurtis.Dunham@arm.comsystem.toL2Bus.snoops 113289 # Total snoops (count) 148311502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::samples 1051063 # Request fanout histogram 148411502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::mean 0.300803 # Request fanout histogram 148511502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.459644 # Request fanout histogram 148610535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 148711502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::0 735400 69.97% 69.97% # Request fanout histogram 148811502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::1 315163 29.99% 99.95% # Request fanout histogram 148911502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::2 500 0.05% 100.00% # Request fanout histogram 149010535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 149111138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 149210535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 149311502SCurtis.Dunham@arm.comsystem.toL2Bus.snoop_fanout::total 1051063 # Request fanout histogram 14948844SAli.Saidi@ARM.com 14958844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1496