xref: /gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  2.802883                       # Number of seconds simulated
sim_ticks                                2802882879000                       # Number of ticks simulated
final_tick                               2802882879000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1338296                       # Simulator instruction rate (inst/s)
host_op_rate                                  1630694                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            25547394462                       # Simulator tick rate (ticks/s)
host_mem_usage                                 592020                       # Number of bytes of host memory used
host_seconds                                   109.71                       # Real time elapsed on the host
sim_insts                                   146828562                       # Number of instructions simulated
sim_ops                                     178908371                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu0.dtb.walker          512                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker          128                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          1109732                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data          9413156                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst           152660                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data          1082192                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
system.physmem.bytes_read::total             11759340                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      1109732                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst       152660                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         1262392                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      8477312                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         17524                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data            40                       # Number of bytes written to this memory
system.physmem.bytes_written::total           8494876                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker            8                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker            2                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             25793                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            147600                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst              2540                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data             16929                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                192887                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks          132458                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             4381                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data               10                       # Number of write requests responded to by this memory
system.physmem.num_writes::total               136849                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker           183                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker            46                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst              395925                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data             3358384                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               54465                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              386100                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide              343                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 4195445                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst         395925                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          54465                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             450391                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           3024497                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data               6252                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                 14                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                3030764                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           3024497                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker          183                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker           46                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst             395925                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data            3364636                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              54465                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             386114                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide             343                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                7226208                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst           20                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst           48                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total            68                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst           20                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst           48                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           68                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst           12                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             17                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst           17                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               24                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst           17                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           24                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst           17                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              24                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                        1024                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                             1                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                   540                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    2318336                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                          631                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.walks                     7964                       # Table walker walks requested
system.cpu0.dtb.walker.walksShort                7964                       # Table walker walks initiated with short descriptors
system.cpu0.dtb.walker.walkWaitTime::samples         7964                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0           7964    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total         7964                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walksPending::samples      6705500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0        6705500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total      6705500                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K         5079     77.31%     77.31% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::1M         1491     22.69%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total         6570                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data         7964                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total         7964                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data         6570                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total         6570                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total        14534                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                    20339777                       # DTB read hits
system.cpu0.dtb.read_misses                      6871                       # DTB read misses
system.cpu0.dtb.write_hits                   16391027                       # DTB write hits
system.cpu0.dtb.write_misses                     1093                       # DTB write misses
system.cpu0.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                    3499                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  1788                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                      282                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses                20346648                       # DTB read accesses
system.cpu0.dtb.write_accesses               16392120                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                         36730804                       # DTB hits
system.cpu0.dtb.misses                           7964                       # DTB misses
system.cpu0.dtb.accesses                     36738768                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.walks                     3358                       # Table walker walks requested
system.cpu0.itb.walker.walksShort                3358                       # Table walker walks initiated with short descriptors
system.cpu0.itb.walker.walkWaitTime::samples         3358                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0           3358    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total         3358                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walksPending::samples      6702500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0        6702500    100.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total      6702500                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K         2040     87.11%     87.11% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::1M          302     12.89%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total         2342                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst         3358                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total         3358                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst         2342                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total         2342                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total         5700                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                    97439598                       # ITB inst hits
system.cpu0.itb.inst_misses                      3358                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                    2160                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses                97442956                       # ITB inst accesses
system.cpu0.itb.hits                         97439598                       # DTB hits
system.cpu0.itb.misses                           3358                       # DTB misses
system.cpu0.itb.accesses                     97442956                       # DTB accesses
system.cpu0.numCycles                      5605767724                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    1965                       # number of quiesce instructions executed
system.cpu0.committedInsts                   95427136                       # Number of instructions committed
system.cpu0.committedOps                    115560651                       # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses            100762921                       # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses                  9755                       # Number of float alu accesses
system.cpu0.num_func_calls                    8000357                       # number of times a function call or return occured
system.cpu0.num_conditional_control_insts     13204240                       # number of instructions that are conditional controls
system.cpu0.num_int_insts                   100762921                       # number of integer instructions
system.cpu0.num_fp_insts                         9755                       # number of float instructions
system.cpu0.num_int_register_reads          182457857                       # number of times the integer registers were read
system.cpu0.num_int_register_writes          69135716                       # number of times the integer registers were written
system.cpu0.num_fp_register_reads                7495                       # number of times the floating registers were read
system.cpu0.num_fp_register_writes               2264                       # number of times the floating registers were written
system.cpu0.num_cc_register_reads           349972220                       # number of times the CC registers were read
system.cpu0.num_cc_register_writes           44907498                       # number of times the CC registers were written
system.cpu0.num_mem_refs                     37873797                       # number of memory refs
system.cpu0.num_load_insts                   20597358                       # Number of load instructions
system.cpu0.num_store_insts                  17276439                       # Number of store instructions
system.cpu0.num_idle_cycles              5488182951.223861                       # Number of idle cycles
system.cpu0.num_busy_cycles              117584772.776139                       # Number of busy cycles
system.cpu0.not_idle_fraction                0.020976                       # Percentage of non-idle cycles
system.cpu0.idle_fraction                    0.979024                       # Percentage of idle cycles
system.cpu0.Branches                         21941714                       # Number of branches fetched
system.cpu0.op_class::No_OpClass                 2273      0.00%      0.00% # Class of executed instruction
system.cpu0.op_class::IntAlu                 78887557     67.49%     67.50% # Class of executed instruction
system.cpu0.op_class::IntMult                  110635      0.09%     67.59% # Class of executed instruction
system.cpu0.op_class::IntDiv                        0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::FloatAdd                      0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::FloatCmp                      0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::FloatCvt                      0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::FloatMult                     0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::FloatDiv                      0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::FloatSqrt                     0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdAdd                       0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdAddAcc                    0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdAlu                       0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdCmp                       0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdCvt                       0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdMisc                      0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdMult                      0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdMultAcc                   0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdShift                     0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdShiftAcc                  0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdSqrt                      0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatAdd                  0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatAlu                  0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp                  0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt                  0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv                  0      0.00%     67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatMisc              8087      0.01%     67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult                 0      0.00%     67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc              0      0.00%     67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt                 0      0.00%     67.60% # Class of executed instruction
system.cpu0.op_class::MemRead                20597358     17.62%     85.22% # Class of executed instruction
system.cpu0.op_class::MemWrite               17276439     14.78%    100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu0.op_class::total                 116882349                       # Class of executed instruction
system.cpu0.dcache.tags.replacements           693475                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          494.853481                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs           35932424                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs           693987                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            51.776797                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle         23053500                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.853481                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.966511                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.966511                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0          277                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          205                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           30                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses         74113882                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses        74113882                       # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data     19108626                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       19108626                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     15690357                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      15690357                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       346080                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       346080                       # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       379619                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total       379619                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data       363029                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total       363029                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data     34798983                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total        34798983                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data     35145063                       # number of overall hits
system.cpu0.dcache.overall_hits::total       35145063                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data       373096                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total       373096                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data       295789                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total       295789                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       100322                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       100322                       # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         6740                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total         6740                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data        18444                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total        18444                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data       668885                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total        668885                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data       769207                       # number of overall misses
system.cpu0.dcache.overall_misses::total       769207                       # number of overall misses
system.cpu0.dcache.ReadReq_accesses::cpu0.data     19481722                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     19481722                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     15986146                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     15986146                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       446402                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       446402                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       386359                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total       386359                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       381473                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total       381473                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data     35467868                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total     35467868                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data     35914270                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total     35914270                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.019151                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.019151                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.018503                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.018503                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.224735                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.224735                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.017445                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.017445                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.048349                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.048349                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.018859                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.018859                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.021418                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.021418                       # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks       693475                       # number of writebacks
system.cpu0.dcache.writebacks::total           693475                       # number of writebacks
system.cpu0.icache.tags.replacements          1109624                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.809991                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs           96331795                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          1110136                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            86.774769                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle       6345717000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.809991                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999629                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999629                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          212                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1           90                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2          210                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        195994025                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       195994025                       # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst     96331795                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total       96331795                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst     96331795                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total        96331795                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst     96331795                       # number of overall hits
system.cpu0.icache.overall_hits::total       96331795                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      1110145                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      1110145                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      1110145                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       1110145                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      1110145                       # number of overall misses
system.cpu0.icache.overall_misses::total      1110145                       # number of overall misses
system.cpu0.icache.ReadReq_accesses::cpu0.inst     97441940                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total     97441940                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst     97441940                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total     97441940                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst     97441940                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total     97441940                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.011393                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.011393                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.011393                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.011393                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.011393                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.011393                       # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      1109624                       # number of writebacks
system.cpu0.icache.writebacks::total          1109624                       # number of writebacks
system.cpu0.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.replacements          249486                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       16123.886747                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs           2730668                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs          265599                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs           10.281168                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      1471234000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 16122.057477                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker     1.758477                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker     0.070793                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.984012                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.000107                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.000004                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.984124                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1023            5                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        16108                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          153                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1          353                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         5529                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         7406                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         2667                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.000305                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.983154                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses        59695806                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses       59695806                       # Number of data accesses
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker        10175                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker         4509                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total         14684                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks       510631                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total       510631                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      1264603                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      1264603                       # number of WritebackClean hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data        94360                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total        94360                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      1068362                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      1068362                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data       352230                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total       352230                       # number of ReadSharedReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker        10175                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker         4509                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      1068362                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data       446590                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total        1529636                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker        10175                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker         4509                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      1068362                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data       446590                       # number of overall hits
system.cpu0.l2cache.overall_hits::total       1529636                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker          216                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker          118                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total          334                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data        26269                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total        26269                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data        18444                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total        18444                       # number of SCUpgradeReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       175160                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       175160                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst        41783                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total        41783                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data       127928                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total       127928                       # number of ReadSharedReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker          216                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker          118                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst        41783                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data       303088                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total       345205                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker          216                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker          118                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst        41783                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data       303088                       # number of overall misses
system.cpu0.l2cache.overall_misses::total       345205                       # number of overall misses
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker        10391                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker         4627                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total        15018                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks       510631                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total       510631                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      1264603                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      1264603                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data        26269                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total        26269                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data        18444                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total        18444                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data       269520                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total       269520                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      1110145                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      1110145                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data       480158                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total       480158                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker        10391                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker         4627                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      1110145                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data       749678                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total      1874841                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker        10391                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker         4627                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      1110145                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data       749678                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total      1874841                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.020787                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.025502                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.022240                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.649896                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.649896                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.037637                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.037637                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.266429                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.266429                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.020787                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.025502                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.037637                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.404291                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.184125                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.020787                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.025502                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.037637                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.404291                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.184125                       # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.writebacks::writebacks       193020                       # number of writebacks
system.cpu0.l2cache.writebacks::total          193020                       # number of writebacks
system.cpu0.toL2Bus.snoop_filter.tot_requests      3720001                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests      1860202                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests        27865                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       218277                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       215192                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops         3085                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.trans_dist::ReadReq         61410                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp      1651713                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        28341                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        28341                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty       510631                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      1292468                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq        26269                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq        18444                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp        44713                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq       269520                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp       269520                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      1110145                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq       480158                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side      3347958                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side      2402091                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        12828                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        28796                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total          5791673                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    142101304                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     92552324                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side        25656                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side        57592                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total         234736876                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                     623160                       # Total snoops (count)
system.cpu0.toL2Bus.snoop_fanout::samples      4317939                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.067042                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.252935                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0           4031542     93.37%     93.37% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1            283312      6.56%     99.93% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2              3085      0.07%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total       4317939                       # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.walks                     3359                       # Table walker walks requested
system.cpu1.dtb.walker.walksShort                3359                       # Table walker walks initiated with short descriptors
system.cpu1.dtb.walker.walkWaitTime::samples         3359                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0           3359    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total         3359                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walksPending::samples  -1804206736                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0    -1804206736    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total  -1804206736                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K         1919     74.12%     74.12% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::1M          670     25.88%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total         2589                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data         3359                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total         3359                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data         2589                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total         2589                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total         5948                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    12173929                       # DTB read hits
system.cpu1.dtb.read_misses                      2853                       # DTB read misses
system.cpu1.dtb.write_hits                    7587213                       # DTB write hits
system.cpu1.dtb.write_misses                      506                       # DTB write misses
system.cpu1.dtb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                    2013                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                   290                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                      163                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                12176782                       # DTB read accesses
system.cpu1.dtb.write_accesses                7587719                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                         19761142                       # DTB hits
system.cpu1.dtb.misses                           3359                       # DTB misses
system.cpu1.dtb.accesses                     19764501                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.walks                     1734                       # Table walker walks requested
system.cpu1.itb.walker.walksShort                1734                       # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walkWaitTime::samples         1734                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0           1734    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total         1734                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walksPending::samples  -1804209236                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    -1804209236    100.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total  -1804209236                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K          935     85.39%     85.39% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M          160     14.61%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total         1095                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst         1734                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total         1734                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst         1095                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total         1095                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total         2829                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                    53671686                       # ITB inst hits
system.cpu1.itb.inst_misses                      1734                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          66                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                     917                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid                  0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                      0                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                    1136                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses                53673420                       # ITB inst accesses
system.cpu1.itb.hits                         53671686                       # DTB hits
system.cpu1.itb.misses                           1734                       # DTB misses
system.cpu1.itb.accesses                     53673420                       # DTB accesses
system.cpu1.numCycles                      5605296633                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                    2739                       # number of quiesce instructions executed
system.cpu1.committedInsts                   51401426                       # Number of instructions committed
system.cpu1.committedOps                     63347720                       # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses             56984340                       # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses                  1792                       # Number of float alu accesses
system.cpu1.num_func_calls                    9170857                       # number of times a function call or return occured
system.cpu1.num_conditional_control_insts      5967107                       # number of instructions that are conditional controls
system.cpu1.num_int_insts                    56984340                       # number of integer instructions
system.cpu1.num_fp_insts                         1792                       # number of float instructions
system.cpu1.num_int_register_reads          110674879                       # number of times the integer registers were read
system.cpu1.num_int_register_writes          41298438                       # number of times the integer registers were written
system.cpu1.num_fp_register_reads                1276                       # number of times the floating registers were read
system.cpu1.num_fp_register_writes                516                       # number of times the floating registers were written
system.cpu1.num_cc_register_reads           196268976                       # number of times the CC registers were read
system.cpu1.num_cc_register_writes           18894428                       # number of times the CC registers were written
system.cpu1.num_mem_refs                     20026400                       # number of memory refs
system.cpu1.num_load_insts                   12289552                       # Number of load instructions
system.cpu1.num_store_insts                   7736848                       # Number of store instructions
system.cpu1.num_idle_cycles              5539683011.597479                       # Number of idle cycles
system.cpu1.num_busy_cycles              65613621.402521                       # Number of busy cycles
system.cpu1.not_idle_fraction                0.011706                       # Percentage of non-idle cycles
system.cpu1.idle_fraction                    0.988294                       # Percentage of idle cycles
system.cpu1.Branches                         15217504                       # Number of branches fetched
system.cpu1.op_class::No_OpClass                   66      0.00%      0.00% # Class of executed instruction
system.cpu1.op_class::IntAlu                 45401392     69.36%     69.36% # Class of executed instruction
system.cpu1.op_class::IntMult                   28394      0.04%     69.40% # Class of executed instruction
system.cpu1.op_class::IntDiv                        0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::FloatAdd                      0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::FloatCmp                      0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::FloatCvt                      0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::FloatMult                     0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::FloatDiv                      0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::FloatSqrt                     0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdAdd                       0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdAddAcc                    0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdAlu                       0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdCmp                       0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdCvt                       0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdMisc                      0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdMult                      0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdMultAcc                   0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdShift                     0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdShiftAcc                  0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdSqrt                      0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatAdd                  0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatAlu                  0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp                  0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt                  0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv                  0      0.00%     69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatMisc              3319      0.01%     69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult                 0      0.00%     69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc              0      0.00%     69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt                 0      0.00%     69.41% # Class of executed instruction
system.cpu1.op_class::MemRead                12289552     18.77%     88.18% # Class of executed instruction
system.cpu1.op_class::MemWrite                7736848     11.82%    100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess                     0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch                  0      0.00%    100.00% # Class of executed instruction
system.cpu1.op_class::total                  65459571                       # Class of executed instruction
system.cpu1.dcache.tags.replacements           191946                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          472.736016                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs           19503521                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs           192300                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs           101.422366                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     105851601500                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   472.736016                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.923313                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.923313                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          354                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2          341                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::3           13                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.691406                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses         39752021                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses        39752021                       # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data     11858700                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       11858700                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data      7397505                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total       7397505                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data        50100                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total        50100                       # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        91447                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total        91447                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data        72417                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total        72417                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data     19256205                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total        19256205                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data     19306305                       # number of overall hits
system.cpu1.dcache.overall_hits::total       19306305                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data       136638                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total       136638                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data        92461                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total        92461                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data        30718                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total        30718                       # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         5318                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total         5318                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data        22562                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total        22562                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data       229099                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total        229099                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data       259817                       # number of overall misses
system.cpu1.dcache.overall_misses::total       259817                       # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data     11995338                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     11995338                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data      7489966                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total      7489966                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data        80818                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total        80818                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        96765                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total        96765                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        94979                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total        94979                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data     19485304                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total     19485304                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data     19566122                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total     19566122                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.011391                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.011391                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.012345                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.012345                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.380089                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.380089                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.054958                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.054958                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.237547                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.237547                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.011758                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.011758                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.013279                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.013279                       # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks       191946                       # number of writebacks
system.cpu1.dcache.writebacks::total           191946                       # number of writebacks
system.cpu1.icache.tags.replacements           523401                       # number of replacements
system.cpu1.icache.tags.tagsinuse          499.711077                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs           53148863                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs           523913                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs           101.445971                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle      76931404500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   499.711077                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.975998                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.975998                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2          477                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3           35                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        107869465                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       107869465                       # Number of data accesses
system.cpu1.icache.ReadReq_hits::cpu1.inst     53148863                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total       53148863                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst     53148863                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total        53148863                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst     53148863                       # number of overall hits
system.cpu1.icache.overall_hits::total       53148863                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst       523913                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total       523913                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst       523913                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total        523913                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst       523913                       # number of overall misses
system.cpu1.icache.overall_misses::total       523913                       # number of overall misses
system.cpu1.icache.ReadReq_accesses::cpu1.inst     53672776                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total     53672776                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst     53672776                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total     53672776                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst     53672776                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total     53672776                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.009761                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.009761                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.009761                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.009761                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.009761                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.009761                       # miss rate for overall accesses
system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks       523401                       # number of writebacks
system.cpu1.icache.writebacks::total           523401                       # number of writebacks
system.cpu1.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified            0                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage            0                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.replacements           47378                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       15226.816500                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs           1184475                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs           62425                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs           18.974369                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 15223.544149                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker     1.255151                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker     2.017200                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.929171                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.000077                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.000123                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.929371                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1023           20                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        15027                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2            6                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            3                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4           11                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2          526                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         9441                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         5060                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.001221                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.917175                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses        24501973                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses       24501973                       # Number of data accesses
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker         3627                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker         1923                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total          5550                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks       121108                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total       121108                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks       583081                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total       583081                       # number of WritebackClean hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data        19862                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total        19862                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst       510444                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total       510444                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data        99124                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total        99124                       # number of ReadSharedReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker         3627                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker         1923                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst       510444                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data       118986                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total         634980                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker         3627                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker         1923                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst       510444                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data       118986                       # number of overall hits
system.cpu1.l2cache.overall_hits::total        634980                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker          338                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker          268                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total          606                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data        28846                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total        28846                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data        22562                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total        22562                       # number of SCUpgradeReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data        43753                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total        43753                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst        13469                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total        13469                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data        73550                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total        73550                       # number of ReadSharedReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker          338                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker          268                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst        13469                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data       117303                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total       131378                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker          338                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker          268                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst        13469                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data       117303                       # number of overall misses
system.cpu1.l2cache.overall_misses::total       131378                       # number of overall misses
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker         3965                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker         2191                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total         6156                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks       121108                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total       121108                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks       583081                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total       583081                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data        28846                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total        28846                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data        22562                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total        22562                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data        63615                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total        63615                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst       523913                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total       523913                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data       172674                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total       172674                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker         3965                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker         2191                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst       523913                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data       236289                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total       766358                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker         3965                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker         2191                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst       523913                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data       236289                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total       766358                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.085246                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.122319                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.098441                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total            1                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.687778                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.687778                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.025708                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.025708                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.425947                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.425947                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.085246                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.122319                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.025708                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.496439                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.171432                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.085246                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.122319                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.025708                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.496439                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.171432                       # miss rate for overall accesses
system.cpu1.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs               0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.writebacks::writebacks        32706                       # number of writebacks
system.cpu1.l2cache.writebacks::total           32706                       # number of writebacks
system.cpu1.toL2Bus.snoop_filter.tot_requests      1533509                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests       773310                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests        11158                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       166217                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       164146                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops         2071                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.trans_dist::ReadReq         12750                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp       709337                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq         2505                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp         2505                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty       121108                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean       594239                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq        28846                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq        22562                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp        51408                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq        63615                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp        63615                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq       523913                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq       172674                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side      1571581                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side       778800                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side         6616                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        12080                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total          2369077                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     67028804                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     27426222                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side        13232                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side        24160                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total          94492418                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                     347790                       # Total snoops (count)
system.cpu1.toL2Bus.snoop_fanout::samples      1820349                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.108308                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.314409                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0           1625261     89.28%     89.28% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            193017     10.60%     99.89% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2              2071      0.11%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total       1820349                       # Request fanout histogram
system.iobus.trans_dist::ReadReq                30995                       # Transaction distribution
system.iobus.trans_dist::ReadResp               30995                       # Transaction distribution
system.iobus.trans_dist::WriteReq               59419                       # Transaction distribution
system.iobus.trans_dist::WriteResp              59419                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        56582                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio          122                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           34                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           20                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio          120                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio          834                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           32                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           76                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio            4                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio           10                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio         7244                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        42268                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       107876                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total        72952                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  180828                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        71526                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio          244                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          638                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           68                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           40                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio           84                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio          441                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           64                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio          152                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio            8                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio           20                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio         4753                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        84536                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       162766                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      2321248                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  2484014                       # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements                36442                       # number of replacements
system.iocache.tags.tagsinuse               14.586086                       # Cycle average of tags in use
system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs                36458                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         246641286009                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ide    14.586086                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide     0.911630                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.911630                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses               328284                       # Number of tag accesses
system.iocache.tags.data_accesses              328284                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ide          252                       # number of ReadReq misses
system.iocache.ReadReq_misses::total              252                       # number of ReadReq misses
system.iocache.WriteLineReq_misses::realview.ide        36224                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total        36224                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ide        36476                       # number of demand (read+write) misses
system.iocache.demand_misses::total             36476                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide        36476                       # number of overall misses
system.iocache.overall_misses::total            36476                       # number of overall misses
system.iocache.ReadReq_accesses::realview.ide          252                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total            252                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total        36224                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide        36476                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total           36476                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide        36476                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total          36476                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks           36190                       # number of writebacks
system.iocache.writebacks::total                36190                       # number of writebacks
system.l2c.tags.replacements                   107729                       # number of replacements
system.l2c.tags.tagsinuse                62410.633039                       # Cycle average of tags in use
system.l2c.tags.total_refs                     243914                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                   168410                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     1.448334                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   48132.772899                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker     5.010469                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker     0.030814                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     7764.318269                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data     4071.663088                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     1666.007629                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data      770.829870                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.734448                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000076                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.118474                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.062129                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.025421                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.011762                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.952311                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023            6                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        60675                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4            6                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           20                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1           64                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         1869                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3        13225                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        45497                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023     0.000092                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.925827                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                  5179303                       # Number of tag accesses
system.l2c.tags.data_accesses                 5179303                       # Number of data accesses
system.l2c.WritebackDirty_hits::writebacks       225726                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total          225726                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data             564                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data             115                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total                 679                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data            81                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data            38                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total               119                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            13900                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data             3040                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total                16940                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker           77                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker           58                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst        25005                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data        76077                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker           34                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker           35                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst        11094                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data        11733                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total           124113                       # number of ReadSharedReq hits
system.l2c.demand_hits::cpu0.dtb.walker            77                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker            58                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst               25005                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data               89977                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker            34                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker            35                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst               11094                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data               14773                       # number of demand (read+write) hits
system.l2c.demand_hits::total                  141053                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker           77                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker           58                       # number of overall hits
system.l2c.overall_hits::cpu0.inst              25005                       # number of overall hits
system.l2c.overall_hits::cpu0.data              89977                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker           34                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker           35                       # number of overall hits
system.l2c.overall_hits::cpu1.inst              11094                       # number of overall hits
system.l2c.overall_hits::cpu1.data              14773                       # number of overall hits
system.l2c.overall_hits::total                 141053                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data          9970                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data          3255                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             13225                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          737                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data         1148                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1885                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data         136548                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          15822                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             152370                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker            8                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker            2                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        16778                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data        11188                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst         2375                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data         1125                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total          31476                       # number of ReadSharedReq misses
system.l2c.demand_misses::cpu0.dtb.walker            8                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker            2                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             16778                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            147736                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst              2375                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data             16947                       # number of demand (read+write) misses
system.l2c.demand_misses::total                183846                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker            8                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker            2                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            16778                       # number of overall misses
system.l2c.overall_misses::cpu0.data           147736                       # number of overall misses
system.l2c.overall_misses::cpu1.inst             2375                       # number of overall misses
system.l2c.overall_misses::cpu1.data            16947                       # number of overall misses
system.l2c.overall_misses::total               183846                       # number of overall misses
system.l2c.WritebackDirty_accesses::writebacks       225726                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total       225726                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data        10534                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data         3370                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total           13904                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data          818                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data         1186                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total          2004                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       150448                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data        18862                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           169310                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker           85                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker           60                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst        41783                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data        87265                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker           34                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker           35                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst        13469                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data        12858                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total       155589                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker           85                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker           60                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst           41783                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          237713                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker           34                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker           35                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst           13469                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data           31720                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total              324899                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker           85                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker           60                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst          41783                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         237713                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker           34                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker           35                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst          13469                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data          31720                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total             324899                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.946459                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.965875                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.951165                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.900978                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.967960                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.940619                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.907609                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.838829                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.899947                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.094118                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.033333                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.401551                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.128207                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.176331                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.087494                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.202302                       # miss rate for ReadSharedReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.094118                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.033333                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.401551                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.621489                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.176331                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.534269                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.565856                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.094118                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.033333                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.401551                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.621489                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.176331                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.534269                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.565856                       # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks               96268                       # number of writebacks
system.l2c.writebacks::total                    96268                       # number of writebacks
system.membus.trans_dist::ReadReq               43996                       # Transaction distribution
system.membus.trans_dist::ReadResp              75724                       # Transaction distribution
system.membus.trans_dist::WriteReq              30846                       # Transaction distribution
system.membus.trans_dist::WriteResp             30846                       # Transaction distribution
system.membus.trans_dist::WritebackDirty       132458                       # Transaction distribution
system.membus.trans_dist::CleanEvict             8718                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            60357                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq          40887                       # Transaction distribution
system.membus.trans_dist::UpgradeResp           15566                       # Transaction distribution
system.membus.trans_dist::ReadExReq            152312                       # Transaction distribution
system.membus.trans_dist::ReadExResp           151914                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         31728                       # Transaction distribution
system.membus.trans_dist::InvalidateReq         36224                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        36224                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       107876                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           34                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        13474                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port       617022                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total       738406                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       109394                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       109394                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 847800                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       162766                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port           68                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        26948                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port     17954824                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total     18144606                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      2332288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      2332288                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                20476894                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            537526                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                  537526    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total              537526                       # Request fanout histogram
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi             nan                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle          nan                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk            nan                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc          nan                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk            nan                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle          nan                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc          nan                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn           nan                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal           nan                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts            0                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.toL2Bus.snoop_filter.tot_requests       862694                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests       444199                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests       128774                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops           9862                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops         9376                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops          486                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadReq              44000                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp            301670                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             30846                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            30846                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty       225726                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict           64248                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq           60580                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq         41006                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp         101586                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           213448                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          213448                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq       257670                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side      1161849                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side       423225                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total               1585074                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     34444668                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side     10399858                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total               44844526                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                          180900                       # Total snoops (count)
system.toL2Bus.snoop_fanout::samples          1118187                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.282688                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.451270                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                 802575     71.77%     71.77% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                 315126     28.18%     99.96% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                    486      0.04%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            1118187                       # Request fanout histogram

---------- End Simulation Statistics   ----------