stats.txt revision 11336
18844SAli.Saidi@ARM.com 28844SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311336Sandreas.hansson@arm.comsim_seconds 2.802883 # Number of seconds simulated 411336Sandreas.hansson@arm.comsim_ticks 2802882879000 # Number of ticks simulated 511336Sandreas.hansson@arm.comfinal_tick 2802882879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68844SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711336Sandreas.hansson@arm.comhost_inst_rate 1272297 # Simulator instruction rate (inst/s) 811336Sandreas.hansson@arm.comhost_op_rate 1550275 # Simulator op (including micro ops) rate (op/s) 911336Sandreas.hansson@arm.comhost_tick_rate 24287502010 # Simulator tick rate (ticks/s) 1011336Sandreas.hansson@arm.comhost_mem_usage 596572 # Number of bytes of host memory used 1111336Sandreas.hansson@arm.comhost_seconds 115.40 # Real time elapsed on the host 1211336Sandreas.hansson@arm.comsim_insts 146828562 # Number of instructions simulated 1311336Sandreas.hansson@arm.comsim_ops 178908371 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory 1710409Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory 1811336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 1109732 # Number of bytes read from this memory 1911336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 9413156 # Number of bytes read from this memory 2011336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 152660 # Number of bytes read from this memory 2111336Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 1082192 # Number of bytes read from this memory 2210535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2311336Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11759340 # Number of bytes read from this memory 2411336Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 1109732 # Number of instructions bytes read from this memory 2511336Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 152660 # Number of instructions bytes read from this memory 2611336Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 1262392 # Number of instructions bytes read from this memory 2711336Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 8477312 # Number of bytes written to this memory 2810827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory 2910409Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory 3011336Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 8494876 # Number of bytes written to this memory 3111201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory 3210409Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory 3311336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 25793 # Number of read requests responded to by this memory 3411336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 147600 # Number of read requests responded to by this memory 3511336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 2540 # Number of read requests responded to by this memory 3611336Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 16929 # Number of read requests responded to by this memory 3710535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 3811336Sandreas.hansson@arm.comsystem.physmem.num_reads::total 192887 # Number of read requests responded to by this memory 3911336Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 132458 # Number of write requests responded to by this memory 4010827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory 4110409Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory 4211336Sandreas.hansson@arm.comsystem.physmem.num_writes::total 136849 # Number of write requests responded to by this memory 4311201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s) 4410513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4511336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 395925 # Total read bandwidth from this memory (bytes/s) 4611336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 3358384 # Total read bandwidth from this memory (bytes/s) 4711336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 54465 # Total read bandwidth from this memory (bytes/s) 4811336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 386100 # Total read bandwidth from this memory (bytes/s) 4910535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) 5011336Sandreas.hansson@arm.comsystem.physmem.bw_read::total 4195445 # Total read bandwidth from this memory (bytes/s) 5111336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 395925 # Instruction read bandwidth from this memory (bytes/s) 5211336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 54465 # Instruction read bandwidth from this memory (bytes/s) 5311336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 450391 # Instruction read bandwidth from this memory (bytes/s) 5411336Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 3024497 # Write bandwidth from this memory (bytes/s) 5510827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s) 5610513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) 5711336Sandreas.hansson@arm.comsystem.physmem.bw_write::total 3030764 # Write bandwidth from this memory (bytes/s) 5811336Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 3024497 # Total bandwidth to/from this memory (bytes/s) 5911201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s) 6010513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 6111336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 395925 # Total bandwidth to/from this memory (bytes/s) 6211336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 3364636 # Total bandwidth to/from this memory (bytes/s) 6311336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 54465 # Total bandwidth to/from this memory (bytes/s) 6411336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 386114 # Total bandwidth to/from this memory (bytes/s) 6510585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) 6611336Sandreas.hansson@arm.comsystem.physmem.bw_total::total 7226208 # Total bandwidth to/from this memory (bytes/s) 6710517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory 6810517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory 6910517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory 7010517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory 7110517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory 7210517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory 7310517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory 7410517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory 7510517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory 7610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) 7710517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu1.inst 17 # Total read bandwidth from this memory (bytes/s) 7810517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 24 # Total read bandwidth from this memory (bytes/s) 7910517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) 8010517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 17 # Instruction read bandwidth from this memory (bytes/s) 8110517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 24 # Instruction read bandwidth from this memory (bytes/s) 8210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) 8310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s) 8410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s) 858844SAli.Saidi@ARM.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 8610513SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 8710513SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 8810513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 8910513SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 9010513SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 9110535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 9210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 9310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 9410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 9510628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 9610628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 9710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 9810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 9910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 10010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 10110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 10210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 10310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 10410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 10510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 10610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 10710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 10810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 10910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 11010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 11110535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 11210535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 11310535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 11410535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 11510535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 11610535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 11710535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 11810535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 11910535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 12010535Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 12111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 7964 # Table walker walks requested 12211336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksShort 7964 # Table walker walks initiated with short descriptors 12311336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 7964 # Table walker wait (enqueue to first request) latency 12411336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0 7964 100.00% 100.00% # Table walker wait (enqueue to first request) latency 12511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 7964 # Table walker wait (enqueue to first request) latency 12610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 12710628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 12810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 12911336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 5079 77.31% 77.31% # Table walker page sizes translated 13011336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::1M 1491 22.69% 100.00% # Table walker page sizes translated 13111336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 6570 # Table walker page sizes translated 13211336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7964 # Table walker requests started/completed, data/inst 13310628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 13411336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7964 # Table walker requests started/completed, data/inst 13511336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6570 # Table walker requests started/completed, data/inst 13610628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 13711336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6570 # Table walker requests started/completed, data/inst 13811336Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 14534 # Table walker requests started/completed, data/inst 13910535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 14010535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 14111336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 20339777 # DTB read hits 14211336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 6871 # DTB read misses 14311336Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 16391027 # DTB write hits 14410535Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 1093 # DTB write misses 14510535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed 14610535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 14710535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 14810535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 14910535Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB 15010535Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 15110535Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch 15210535Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 15310535Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions 15411336Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 20346648 # DTB read accesses 15511336Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 16392120 # DTB write accesses 15610535Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 15711336Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 36730804 # DTB hits 15811336Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 7964 # DTB misses 15911336Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 36738768 # DTB accesses 16010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 16110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 16210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 16310628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 16410628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 16510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 16610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 16710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 16810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 16910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 17010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 17110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 17210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 17310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 17410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 17510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 17610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 17710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 17810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 17910535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 18010535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 18110535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 18210535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 18310535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 18410535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 18510535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 18610535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 18710535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 18810535Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 18910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 3358 # Table walker walks requested 19010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksShort 3358 # Table walker walks initiated with short descriptors 19110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 3358 # Table walker wait (enqueue to first request) latency 19210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 3358 100.00% 100.00% # Table walker wait (enqueue to first request) latency 19310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 3358 # Table walker wait (enqueue to first request) latency 19410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 19510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 19610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 19710628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 2040 87.11% 87.11% # Table walker page sizes translated 19810628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::1M 302 12.89% 100.00% # Table walker page sizes translated 19910628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 2342 # Table walker page sizes translated 20010628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 20110628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3358 # Table walker requests started/completed, data/inst 20210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 3358 # Table walker requests started/completed, data/inst 20310628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 20410628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst 20510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst 20610628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst 20711336Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 97439598 # ITB inst hits 20810535Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 3358 # ITB inst misses 20910535Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 21010535Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 21110535Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 21210535Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 21310535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed 21410535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 21510535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 21610535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 21710535Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 2160 # Number of entries that have been flushed from TLB 21810535Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 21910535Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 22010535Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 22110535Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 22210535Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 22310535Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 22411336Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 97442956 # ITB inst accesses 22511336Sandreas.hansson@arm.comsystem.cpu0.itb.hits 97439598 # DTB hits 22610535Sandreas.hansson@arm.comsystem.cpu0.itb.misses 3358 # DTB misses 22711336Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 97442956 # DTB accesses 22811336Sandreas.hansson@arm.comsystem.cpu0.numCycles 5605767724 # number of cpu cycles simulated 22910535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 23010535Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 23111201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 23211336Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed 23311336Sandreas.hansson@arm.comsystem.cpu0.committedInsts 95427136 # Number of instructions committed 23411336Sandreas.hansson@arm.comsystem.cpu0.committedOps 115560651 # Number of ops (including micro ops) committed 23511336Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 100762921 # Number of integer alu accesses 23610535Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses 23711336Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 8000357 # number of times a function call or return occured 23811336Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 13204240 # number of instructions that are conditional controls 23911336Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 100762921 # number of integer instructions 24010535Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 9755 # number of float instructions 24111336Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 182457857 # number of times the integer registers were read 24211336Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 69135716 # number of times the integer registers were written 24310535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read 24410535Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written 24511336Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 349972220 # number of times the CC registers were read 24611336Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 44907498 # number of times the CC registers were written 24711336Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 37873797 # number of memory refs 24811336Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 20597358 # Number of load instructions 24911336Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 17276439 # Number of store instructions 25011336Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 5488182951.223861 # Number of idle cycles 25111336Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 117584772.776139 # Number of busy cycles 25210535Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles 25310535Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.979024 # Percentage of idle cycles 25411336Sandreas.hansson@arm.comsystem.cpu0.Branches 21941714 # Number of branches fetched 25510535Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction 25611336Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 78887557 67.49% 67.50% # Class of executed instruction 25711336Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction 25810535Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction 25910535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction 26010535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction 26110535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 67.59% # Class of executed instruction 26210535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 67.59% # Class of executed instruction 26310535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 67.59% # Class of executed instruction 26410535Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 67.59% # Class of executed instruction 26510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 67.59% # Class of executed instruction 26610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 67.59% # Class of executed instruction 26710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 67.59% # Class of executed instruction 26810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 67.59% # Class of executed instruction 26910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 67.59% # Class of executed instruction 27010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 67.59% # Class of executed instruction 27110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 67.59% # Class of executed instruction 27210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 67.59% # Class of executed instruction 27310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 67.59% # Class of executed instruction 27410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 67.59% # Class of executed instruction 27510535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 67.59% # Class of executed instruction 27610535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 67.59% # Class of executed instruction 27710535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 67.59% # Class of executed instruction 27810535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 67.59% # Class of executed instruction 27910535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 67.59% # Class of executed instruction 28010535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 67.59% # Class of executed instruction 28110535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Class of executed instruction 28210535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction 28310535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction 28410535Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction 28511336Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 20597358 17.62% 85.22% # Class of executed instruction 28611336Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 17276439 14.78% 100.00% # Class of executed instruction 28710535Sandreas.hansson@arm.comsystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 28810535Sandreas.hansson@arm.comsystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 28911336Sandreas.hansson@arm.comsystem.cpu0.op_class::total 116882349 # Class of executed instruction 29011336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 693475 # number of replacements 29111336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 494.853481 # Cycle average of tags in use 29211336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 35932424 # Total number of references to valid blocks. 29311336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 693987 # Sample count of references to valid blocks. 29411336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 51.776797 # Average number of references to valid blocks. 29510827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 29611336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853481 # Average occupied blocks per requestor 29710535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy 29810535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy 29910535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 30010535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id 30110535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id 30210535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 30310535Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 30411336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 74113882 # Number of tag accesses 30511336Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 74113882 # Number of data accesses 30611336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 19108626 # number of ReadReq hits 30711336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 19108626 # number of ReadReq hits 30811336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 15690357 # number of WriteReq hits 30911336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 15690357 # number of WriteReq hits 31011336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits 31111336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits 31211336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits 31311336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits 31411336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits 31511336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits 31611336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 34798983 # number of demand (read+write) hits 31711336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 34798983 # number of demand (read+write) hits 31811336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 35145063 # number of overall hits 31911336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 35145063 # number of overall hits 32011336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 373096 # number of ReadReq misses 32111336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 373096 # number of ReadReq misses 32211336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 295789 # number of WriteReq misses 32311336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 295789 # number of WriteReq misses 32411336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses 32511336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses 32611336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses 32711336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses 32811336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses 32911336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses 33011336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 668885 # number of demand (read+write) misses 33111336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 668885 # number of demand (read+write) misses 33211336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 769207 # number of overall misses 33311336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 769207 # number of overall misses 33411336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 19481722 # number of ReadReq accesses(hits+misses) 33511336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 19481722 # number of ReadReq accesses(hits+misses) 33611336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 15986146 # number of WriteReq accesses(hits+misses) 33711336Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 15986146 # number of WriteReq accesses(hits+misses) 33811336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses) 33911336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses) 34011336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses) 34111336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses) 34211336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses) 34311336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses) 34411336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 35467868 # number of demand (read+write) accesses 34511336Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 35467868 # number of demand (read+write) accesses 34611336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 35914270 # number of overall (read+write) accesses 34711336Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 35914270 # number of overall (read+write) accesses 34811336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses 34911336Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses 35011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018503 # miss rate for WriteReq accesses 35111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018503 # miss rate for WriteReq accesses 35211336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses 35311336Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses 35411336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses 35511336Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses 35611336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses 35711336Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses 35811201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.018859 # miss rate for demand accesses 35911201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.018859 # miss rate for demand accesses 36011201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.021418 # miss rate for overall accesses 36111201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.021418 # miss rate for overall accesses 36210535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 36310535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 36410535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 36510535Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 36610535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 36710535Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 36810535Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 36910535Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 37011336Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 693475 # number of writebacks 37111336Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 693475 # number of writebacks 37210535Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 37311336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 1109624 # number of replacements 37411336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.809991 # Cycle average of tags in use 37511336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 96331795 # Total number of references to valid blocks. 37611336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 1110136 # Sample count of references to valid blocks. 37711336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 86.774769 # Average number of references to valid blocks. 37810535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. 37911336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809991 # Average occupied blocks per requestor 38010535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy 38110535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999629 # Average percentage of cache occupancy 38210535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 38310535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 212 # Occupied blocks per task id 38410535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 38510535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id 38610535Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 38711336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 195994025 # Number of tag accesses 38811336Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 195994025 # Number of data accesses 38911336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 96331795 # number of ReadReq hits 39011336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 96331795 # number of ReadReq hits 39111336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 96331795 # number of demand (read+write) hits 39211336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 96331795 # number of demand (read+write) hits 39311336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 96331795 # number of overall hits 39411336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 96331795 # number of overall hits 39511336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 1110145 # number of ReadReq misses 39611336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 1110145 # number of ReadReq misses 39711336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 1110145 # number of demand (read+write) misses 39811336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 1110145 # number of demand (read+write) misses 39911336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 1110145 # number of overall misses 40011336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 1110145 # number of overall misses 40111336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 97441940 # number of ReadReq accesses(hits+misses) 40211336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 97441940 # number of ReadReq accesses(hits+misses) 40311336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 97441940 # number of demand (read+write) accesses 40411336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 97441940 # number of demand (read+write) accesses 40511336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 97441940 # number of overall (read+write) accesses 40611336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 97441940 # number of overall (read+write) accesses 40711336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011393 # miss rate for ReadReq accesses 40811336Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011393 # miss rate for ReadReq accesses 40911336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011393 # miss rate for demand accesses 41011336Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011393 # miss rate for demand accesses 41111336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011393 # miss rate for overall accesses 41211336Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011393 # miss rate for overall accesses 41310535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 41410535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 41510535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 41610535Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 41710535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 41810535Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 41910535Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 42010535Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 42111336Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 1109624 # number of writebacks 42211336Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 1109624 # number of writebacks 42310535Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 42410628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 42510628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 42610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 42710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 42810628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 42910628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 43011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 249486 # number of replacements 43111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16123.886747 # Cycle average of tags in use 43211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 2730668 # Total number of references to valid blocks. 43311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 265599 # Sample count of references to valid blocks. 43411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 10.281168 # Average number of references to valid blocks. 43511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 1471234000 # Cycle when the warmup percentage was hit. 43611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 16122.057477 # Average occupied blocks per requestor 43711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 1.758477 # Average occupied blocks per requestor 43811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070793 # Average occupied blocks per requestor 43911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.984012 # Average percentage of cache occupancy 44011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000107 # Average percentage of cache occupancy 44111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy 44211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.984124 # Average percentage of cache occupancy 44311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 44411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 16108 # Occupied blocks per task id 44511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 44611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id 44711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id 44811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id 44911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5529 # Occupied blocks per task id 45011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7406 # Occupied blocks per task id 45111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2667 # Occupied blocks per task id 45211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id 45311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.983154 # Percentage of cache occupancy per task id 45411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 59695806 # Number of tag accesses 45511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 59695806 # Number of data accesses 45611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 10175 # number of ReadReq hits 45711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4509 # number of ReadReq hits 45811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 14684 # number of ReadReq hits 45911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 510631 # number of WritebackDirty hits 46011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 510631 # number of WritebackDirty hits 46111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 1264603 # number of WritebackClean hits 46211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 1264603 # number of WritebackClean hits 46311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 94360 # number of ReadExReq hits 46411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 94360 # number of ReadExReq hits 46511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1068362 # number of ReadCleanReq hits 46611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 1068362 # number of ReadCleanReq hits 46711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 352230 # number of ReadSharedReq hits 46811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 352230 # number of ReadSharedReq hits 46911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 10175 # number of demand (read+write) hits 47011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 4509 # number of demand (read+write) hits 47111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 1068362 # number of demand (read+write) hits 47211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 446590 # number of demand (read+write) hits 47311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 1529636 # number of demand (read+write) hits 47411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 10175 # number of overall hits 47511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 4509 # number of overall hits 47611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 1068362 # number of overall hits 47711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 446590 # number of overall hits 47811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 1529636 # number of overall hits 47911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 216 # number of ReadReq misses 48011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 118 # number of ReadReq misses 48111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 334 # number of ReadReq misses 48211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26269 # number of UpgradeReq misses 48311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 26269 # number of UpgradeReq misses 48411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18444 # number of SCUpgradeReq misses 48511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 18444 # number of SCUpgradeReq misses 48611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 175160 # number of ReadExReq misses 48711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 175160 # number of ReadExReq misses 48811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 41783 # number of ReadCleanReq misses 48911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 41783 # number of ReadCleanReq misses 49011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 127928 # number of ReadSharedReq misses 49111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 127928 # number of ReadSharedReq misses 49211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 216 # number of demand (read+write) misses 49311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 118 # number of demand (read+write) misses 49411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 41783 # number of demand (read+write) misses 49511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 303088 # number of demand (read+write) misses 49611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 345205 # number of demand (read+write) misses 49711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 216 # number of overall misses 49811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 118 # number of overall misses 49911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 41783 # number of overall misses 50011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 303088 # number of overall misses 50111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 345205 # number of overall misses 50211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 10391 # number of ReadReq accesses(hits+misses) 50311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4627 # number of ReadReq accesses(hits+misses) 50411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 15018 # number of ReadReq accesses(hits+misses) 50511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 510631 # number of WritebackDirty accesses(hits+misses) 50611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 510631 # number of WritebackDirty accesses(hits+misses) 50711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 1264603 # number of WritebackClean accesses(hits+misses) 50811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 1264603 # number of WritebackClean accesses(hits+misses) 50911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26269 # number of UpgradeReq accesses(hits+misses) 51011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 26269 # number of UpgradeReq accesses(hits+misses) 51111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18444 # number of SCUpgradeReq accesses(hits+misses) 51211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 18444 # number of SCUpgradeReq accesses(hits+misses) 51311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269520 # number of ReadExReq accesses(hits+misses) 51411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 269520 # number of ReadExReq accesses(hits+misses) 51511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1110145 # number of ReadCleanReq accesses(hits+misses) 51611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 1110145 # number of ReadCleanReq accesses(hits+misses) 51711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 480158 # number of ReadSharedReq accesses(hits+misses) 51811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 480158 # number of ReadSharedReq accesses(hits+misses) 51911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 10391 # number of demand (read+write) accesses 52011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4627 # number of demand (read+write) accesses 52111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 1110145 # number of demand (read+write) accesses 52211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses 52311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 1874841 # number of demand (read+write) accesses 52411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 10391 # number of overall (read+write) accesses 52511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4627 # number of overall (read+write) accesses 52611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 1110145 # number of overall (read+write) accesses 52711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses 52811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 1874841 # number of overall (read+write) accesses 52911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for ReadReq accesses 53011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025502 # miss rate for ReadReq accesses 53111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.022240 # miss rate for ReadReq accesses 53211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 53311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 53410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 53510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 53611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.649896 # miss rate for ReadExReq accesses 53711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.649896 # miss rate for ReadExReq accesses 53811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.037637 # miss rate for ReadCleanReq accesses 53911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.037637 # miss rate for ReadCleanReq accesses 54011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.266429 # miss rate for ReadSharedReq accesses 54111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.266429 # miss rate for ReadSharedReq accesses 54211336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for demand accesses 54311336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025502 # miss rate for demand accesses 54411336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.037637 # miss rate for demand accesses 54511336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404291 # miss rate for demand accesses 54611336Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.184125 # miss rate for demand accesses 54711336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020787 # miss rate for overall accesses 54811336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025502 # miss rate for overall accesses 54911336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.037637 # miss rate for overall accesses 55011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404291 # miss rate for overall accesses 55111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.184125 # miss rate for overall accesses 55210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 55310535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 55410535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 55510535Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 55610535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 55710535Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 55810535Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 55910535Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 56011336Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 193020 # number of writebacks 56111336Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 193020 # number of writebacks 56210535Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 56311336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 3720001 # Total number of requests made to the snoop filter. 56411336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 1860202 # Number of requests hitting in the snoop filter with a single holder of the requested data. 56511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 27865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 56611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 218277 # Total number of snoops made to the snoop filter. 56711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 215192 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 56811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3085 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 56911336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 61410 # Transaction distribution 57011336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 1651713 # Transaction distribution 57110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution 57210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution 57311336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 510631 # Transaction distribution 57411336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 1292468 # Transaction distribution 57511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 26269 # Transaction distribution 57611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution 57711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 44713 # Transaction distribution 57811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 269520 # Transaction distribution 57911336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 269520 # Transaction distribution 58011336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 1110145 # Transaction distribution 58111336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 480158 # Transaction distribution 58211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3347958 # Packet count per connected master and slave (bytes) 58311336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2402091 # Packet count per connected master and slave (bytes) 58410535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) 58511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes) 58611336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 5791673 # Packet count per connected master and slave (bytes) 58711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 142101304 # Cumulative packet size per connected master and slave (bytes) 58811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 92552324 # Cumulative packet size per connected master and slave (bytes) 58910535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) 59011336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes) 59111336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 234736876 # Cumulative packet size per connected master and slave (bytes) 59211336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 623160 # Total snoops (count) 59311336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 4317939 # Request fanout histogram 59411336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.067042 # Request fanout histogram 59511336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.252935 # Request fanout histogram 59610535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 59711336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 4031542 93.37% 93.37% # Request fanout histogram 59811336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 283312 6.56% 99.93% # Request fanout histogram 59911336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 3085 0.07% 100.00% # Request fanout histogram 60010535Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 60111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 60210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 60311336Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 4317939 # Request fanout histogram 60410628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 60510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 60610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 60710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 60810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 60910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 61010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 61110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 61210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 61310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 61410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 61510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 61610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 61710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 61810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 61910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 62010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 62110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 62210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 62310535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 62410535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 62510535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62610535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62710535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 62810535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 62910535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 63010535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 63110535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 63210535Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 63311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 3359 # Table walker walks requested 63411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksShort 3359 # Table walker walks initiated with short descriptors 63511336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 3359 # Table walker wait (enqueue to first request) latency 63611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0 3359 100.00% 100.00% # Table walker wait (enqueue to first request) latency 63711336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 3359 # Table walker wait (enqueue to first request) latency 63810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples -1804206736 # Table walker pending requests distribution 63910628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 -1804206736 100.00% 100.00% # Table walker pending requests distribution 64010628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total -1804206736 # Table walker pending requests distribution 64111336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 1919 74.12% 74.12% # Table walker page sizes translated 64211336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::1M 670 25.88% 100.00% # Table walker page sizes translated 64311336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 2589 # Table walker page sizes translated 64411336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3359 # Table walker requests started/completed, data/inst 64510628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 64611336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3359 # Table walker requests started/completed, data/inst 64711336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2589 # Table walker requests started/completed, data/inst 64810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 64911336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2589 # Table walker requests started/completed, data/inst 65011336Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 5948 # Table walker requests started/completed, data/inst 65110535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 65210535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 65311336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 12173929 # DTB read hits 65411336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 2853 # DTB read misses 65511336Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 7587213 # DTB write hits 65610535Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 506 # DTB write misses 65710535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed 65810535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 65910535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 66010535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 66110535Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 2013 # Number of entries that have been flushed from TLB 66210535Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 66310535Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch 66410535Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 66510535Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions 66611336Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 12176782 # DTB read accesses 66711336Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 7587719 # DTB write accesses 66810535Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 66911336Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 19761142 # DTB hits 67011336Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 3359 # DTB misses 67111336Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 19764501 # DTB accesses 67210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 67310628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 67410628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 67510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 67610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 67810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 67910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 68010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 68110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 68210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 68310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 68410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 68510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 68610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 68710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 68810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 68910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 69010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 69110535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 69210535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69310535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 69410535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 69510535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 69610535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 69710535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 69810535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 69910535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 70010535Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 70110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 1734 # Table walker walks requested 70210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksShort 1734 # Table walker walks initiated with short descriptors 70310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 1734 # Table walker wait (enqueue to first request) latency 70410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 1734 100.00% 100.00% # Table walker wait (enqueue to first request) latency 70510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 1734 # Table walker wait (enqueue to first request) latency 70610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples -1804209236 # Table walker pending requests distribution 70710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 -1804209236 100.00% 100.00% # Table walker pending requests distribution 70810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total -1804209236 # Table walker pending requests distribution 70910628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 935 85.39% 85.39% # Table walker page sizes translated 71010628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::1M 160 14.61% 100.00% # Table walker page sizes translated 71110628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 1095 # Table walker page sizes translated 71210628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71310628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1734 # Table walker requests started/completed, data/inst 71410628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 1734 # Table walker requests started/completed, data/inst 71510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71610628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst 71710628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst 71810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst 71911336Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 53671686 # ITB inst hits 72010535Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 1734 # ITB inst misses 72110535Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 72210535Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 72310535Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 72410535Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 72510535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed 72610535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 72710535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72810535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 72910535Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 1136 # Number of entries that have been flushed from TLB 73010535Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 73110535Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 73210535Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 73310535Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73410535Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 73510535Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 73611336Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 53673420 # ITB inst accesses 73711336Sandreas.hansson@arm.comsystem.cpu1.itb.hits 53671686 # DTB hits 73810535Sandreas.hansson@arm.comsystem.cpu1.itb.misses 1734 # DTB misses 73911336Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 53673420 # DTB accesses 74011336Sandreas.hansson@arm.comsystem.cpu1.numCycles 5605296633 # number of cpu cycles simulated 74110535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 74210535Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 74311201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 74411201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed 74511336Sandreas.hansson@arm.comsystem.cpu1.committedInsts 51401426 # Number of instructions committed 74611336Sandreas.hansson@arm.comsystem.cpu1.committedOps 63347720 # Number of ops (including micro ops) committed 74711336Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 56984340 # Number of integer alu accesses 74810535Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses 74911336Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 9170857 # number of times a function call or return occured 75011336Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 5967107 # number of instructions that are conditional controls 75111336Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 56984340 # number of integer instructions 75210535Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 1792 # number of float instructions 75311336Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 110674879 # number of times the integer registers were read 75411336Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 41298438 # number of times the integer registers were written 75510535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read 75610535Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 516 # number of times the floating registers were written 75711336Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 196268976 # number of times the CC registers were read 75811336Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 18894428 # number of times the CC registers were written 75911336Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 20026400 # number of memory refs 76011336Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 12289552 # Number of load instructions 76111336Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 7736848 # Number of store instructions 76211336Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 5539683011.597479 # Number of idle cycles 76311336Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 65613621.402521 # Number of busy cycles 76410535Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles 76510535Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.988294 # Percentage of idle cycles 76611336Sandreas.hansson@arm.comsystem.cpu1.Branches 15217504 # Number of branches fetched 76710535Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction 76811336Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 45401392 69.36% 69.36% # Class of executed instruction 76911336Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 28394 0.04% 69.40% # Class of executed instruction 77010535Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction 77110535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 77210535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 77310535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 77410535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 77510535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 77610535Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 77710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 77810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 77910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 78010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 78110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 78210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 78310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 78410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 78510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 78610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 78710535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 78810535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 78910535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 79010535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 79110535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 79210535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 79310535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Class of executed instruction 79410535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 79510535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 79610535Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 79711336Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 12289552 18.77% 88.18% # Class of executed instruction 79811336Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 7736848 11.82% 100.00% # Class of executed instruction 79910535Sandreas.hansson@arm.comsystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 80010535Sandreas.hansson@arm.comsystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 80111336Sandreas.hansson@arm.comsystem.cpu1.op_class::total 65459571 # Class of executed instruction 80211336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 191946 # number of replacements 80311336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 472.736016 # Cycle average of tags in use 80411336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 19503521 # Total number of references to valid blocks. 80511336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 192300 # Sample count of references to valid blocks. 80611336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 101.422366 # Average number of references to valid blocks. 80710535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. 80811336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor 80911336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.923313 # Average percentage of cache occupancy 81011336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.923313 # Average percentage of cache occupancy 81110535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id 81210535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id 81310535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id 81410535Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id 81511336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 39752021 # Number of tag accesses 81611336Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 39752021 # Number of data accesses 81711336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 11858700 # number of ReadReq hits 81811336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 11858700 # number of ReadReq hits 81911336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 7397505 # number of WriteReq hits 82011336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 7397505 # number of WriteReq hits 82111336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 50100 # number of SoftPFReq hits 82211336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 50100 # number of SoftPFReq hits 82310535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits 82410535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits 82511336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 72417 # number of StoreCondReq hits 82611336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 72417 # number of StoreCondReq hits 82711336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 19256205 # number of demand (read+write) hits 82811336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 19256205 # number of demand (read+write) hits 82911336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 19306305 # number of overall hits 83011336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 19306305 # number of overall hits 83111336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 136638 # number of ReadReq misses 83211336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 136638 # number of ReadReq misses 83311336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 92461 # number of WriteReq misses 83411336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 92461 # number of WriteReq misses 83511336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 30718 # number of SoftPFReq misses 83611336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 30718 # number of SoftPFReq misses 83710535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses 83810535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses 83911336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 22562 # number of StoreCondReq misses 84011336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 22562 # number of StoreCondReq misses 84111336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 229099 # number of demand (read+write) misses 84211336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 229099 # number of demand (read+write) misses 84311336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses 84411336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 259817 # number of overall misses 84511336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 11995338 # number of ReadReq accesses(hits+misses) 84611336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 11995338 # number of ReadReq accesses(hits+misses) 84711336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 7489966 # number of WriteReq accesses(hits+misses) 84811336Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 7489966 # number of WriteReq accesses(hits+misses) 84910535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) 85010535Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) 85110535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) 85210535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) 85310535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) 85410535Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) 85511336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 19485304 # number of demand (read+write) accesses 85611336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 19485304 # number of demand (read+write) accesses 85711336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 19566122 # number of overall (read+write) accesses 85811336Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 19566122 # number of overall (read+write) accesses 85911336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011391 # miss rate for ReadReq accesses 86011336Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.011391 # miss rate for ReadReq accesses 86110892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012345 # miss rate for WriteReq accesses 86210892Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.012345 # miss rate for WriteReq accesses 86311336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380089 # miss rate for SoftPFReq accesses 86411336Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses 86510535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses 86610535Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses 86711336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237547 # miss rate for StoreCondReq accesses 86811336Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.237547 # miss rate for StoreCondReq accesses 86911336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses 87011336Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses 87110892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses 87210892Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses 87310535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 87410535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 87510535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 87610535Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 87710535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 87810535Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 87910535Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 88010535Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 88111336Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 191946 # number of writebacks 88211336Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 191946 # number of writebacks 88310535Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 88411336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 523401 # number of replacements 88511336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 499.711077 # Cycle average of tags in use 88611336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 53148863 # Total number of references to valid blocks. 88711336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 523913 # Sample count of references to valid blocks. 88811336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 101.445971 # Average number of references to valid blocks. 88910535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. 89011336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711077 # Average occupied blocks per requestor 89110535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy 89210535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy 89310535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 89410535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id 89510535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id 89610535Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 89711336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 107869465 # Number of tag accesses 89811336Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 107869465 # Number of data accesses 89911336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 53148863 # number of ReadReq hits 90011336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 53148863 # number of ReadReq hits 90111336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 53148863 # number of demand (read+write) hits 90211336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 53148863 # number of demand (read+write) hits 90311336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 53148863 # number of overall hits 90411336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 53148863 # number of overall hits 90511336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 523913 # number of ReadReq misses 90611336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 523913 # number of ReadReq misses 90711336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 523913 # number of demand (read+write) misses 90811336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 523913 # number of demand (read+write) misses 90911336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 523913 # number of overall misses 91011336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 523913 # number of overall misses 91111336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 53672776 # number of ReadReq accesses(hits+misses) 91211336Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 53672776 # number of ReadReq accesses(hits+misses) 91311336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 53672776 # number of demand (read+write) accesses 91411336Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 53672776 # number of demand (read+write) accesses 91511336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 53672776 # number of overall (read+write) accesses 91611336Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 53672776 # number of overall (read+write) accesses 91710535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses 91810535Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses 91910535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses 92010535Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.009761 # miss rate for demand accesses 92110535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.009761 # miss rate for overall accesses 92210535Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.009761 # miss rate for overall accesses 92310535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 92410535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 92510535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 92610535Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 92710535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 92810535Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 92910535Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 93010535Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 93111336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 523401 # number of writebacks 93211336Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 523401 # number of writebacks 93310535Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 93410628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued 93510628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 0 # number of prefetch candidates identified 93610628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 93710628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 93810628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 93910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 94011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 47378 # number of replacements 94111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 15226.816500 # Cycle average of tags in use 94211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 1184475 # Total number of references to valid blocks. 94311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 62425 # Sample count of references to valid blocks. 94411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 18.974369 # Average number of references to valid blocks. 94510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 94611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 15223.544149 # Average occupied blocks per requestor 94711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 1.255151 # Average occupied blocks per requestor 94811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.017200 # Average occupied blocks per requestor 94911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.929171 # Average percentage of cache occupancy 95011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000077 # Average percentage of cache occupancy 95110892Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy 95211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.929371 # Average percentage of cache occupancy 95311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 20 # Occupied blocks per task id 95411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 15027 # Occupied blocks per task id 95510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 95610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 95711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id 95811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 526 # Occupied blocks per task id 95911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9441 # Occupied blocks per task id 96011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5060 # Occupied blocks per task id 96111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001221 # Percentage of cache occupancy per task id 96211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.917175 # Percentage of cache occupancy per task id 96311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 24501973 # Number of tag accesses 96411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 24501973 # Number of data accesses 96511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3627 # number of ReadReq hits 96611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1923 # number of ReadReq hits 96711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 5550 # number of ReadReq hits 96811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 121108 # number of WritebackDirty hits 96911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 121108 # number of WritebackDirty hits 97011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 583081 # number of WritebackClean hits 97111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 583081 # number of WritebackClean hits 97211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 19862 # number of ReadExReq hits 97311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 19862 # number of ReadExReq hits 97411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 510444 # number of ReadCleanReq hits 97511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 510444 # number of ReadCleanReq hits 97611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 99124 # number of ReadSharedReq hits 97711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 99124 # number of ReadSharedReq hits 97811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3627 # number of demand (read+write) hits 97911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 1923 # number of demand (read+write) hits 98011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 510444 # number of demand (read+write) hits 98111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 118986 # number of demand (read+write) hits 98211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 634980 # number of demand (read+write) hits 98311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3627 # number of overall hits 98411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 1923 # number of overall hits 98511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 510444 # number of overall hits 98611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 118986 # number of overall hits 98711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 634980 # number of overall hits 98811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses 98911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 268 # number of ReadReq misses 99011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 606 # number of ReadReq misses 99111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28846 # number of UpgradeReq misses 99211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 28846 # number of UpgradeReq misses 99311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22562 # number of SCUpgradeReq misses 99411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 22562 # number of SCUpgradeReq misses 99511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 43753 # number of ReadExReq misses 99611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 43753 # number of ReadExReq misses 99711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13469 # number of ReadCleanReq misses 99811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 13469 # number of ReadCleanReq misses 99911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73550 # number of ReadSharedReq misses 100011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 73550 # number of ReadSharedReq misses 100111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses 100211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 268 # number of demand (read+write) misses 100311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 13469 # number of demand (read+write) misses 100411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 117303 # number of demand (read+write) misses 100511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 131378 # number of demand (read+write) misses 100611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses 100711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 268 # number of overall misses 100811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 13469 # number of overall misses 100911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 117303 # number of overall misses 101011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 131378 # number of overall misses 101111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3965 # number of ReadReq accesses(hits+misses) 101211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2191 # number of ReadReq accesses(hits+misses) 101311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 6156 # number of ReadReq accesses(hits+misses) 101411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 121108 # number of WritebackDirty accesses(hits+misses) 101511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 121108 # number of WritebackDirty accesses(hits+misses) 101611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 583081 # number of WritebackClean accesses(hits+misses) 101711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 583081 # number of WritebackClean accesses(hits+misses) 101811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28846 # number of UpgradeReq accesses(hits+misses) 101911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 28846 # number of UpgradeReq accesses(hits+misses) 102011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22562 # number of SCUpgradeReq accesses(hits+misses) 102111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 22562 # number of SCUpgradeReq accesses(hits+misses) 102211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63615 # number of ReadExReq accesses(hits+misses) 102311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 63615 # number of ReadExReq accesses(hits+misses) 102411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 523913 # number of ReadCleanReq accesses(hits+misses) 102511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 523913 # number of ReadCleanReq accesses(hits+misses) 102611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 172674 # number of ReadSharedReq accesses(hits+misses) 102711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 172674 # number of ReadSharedReq accesses(hits+misses) 102811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3965 # number of demand (read+write) accesses 102911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2191 # number of demand (read+write) accesses 103011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 523913 # number of demand (read+write) accesses 103111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 236289 # number of demand (read+write) accesses 103211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 766358 # number of demand (read+write) accesses 103311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3965 # number of overall (read+write) accesses 103411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2191 # number of overall (read+write) accesses 103511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 523913 # number of overall (read+write) accesses 103611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 236289 # number of overall (read+write) accesses 103711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 766358 # number of overall (read+write) accesses 103811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for ReadReq accesses 103911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.122319 # miss rate for ReadReq accesses 104011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.098441 # miss rate for ReadReq accesses 104111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 104211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 104310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 104410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 104511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.687778 # miss rate for ReadExReq accesses 104611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.687778 # miss rate for ReadExReq accesses 104711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.025708 # miss rate for ReadCleanReq accesses 104811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.025708 # miss rate for ReadCleanReq accesses 104911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.425947 # miss rate for ReadSharedReq accesses 105011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.425947 # miss rate for ReadSharedReq accesses 105111336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for demand accesses 105211336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.122319 # miss rate for demand accesses 105311336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.025708 # miss rate for demand accesses 105411336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.496439 # miss rate for demand accesses 105511336Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.171432 # miss rate for demand accesses 105611336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.085246 # miss rate for overall accesses 105711336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.122319 # miss rate for overall accesses 105811336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.025708 # miss rate for overall accesses 105911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.496439 # miss rate for overall accesses 106011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.171432 # miss rate for overall accesses 106110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 106210535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 106310535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 106410535Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 106510535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 106610535Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 106710535Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 106810535Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 106911336Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 32706 # number of writebacks 107011336Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 32706 # number of writebacks 107110535Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 107211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 1533509 # Total number of requests made to the snoop filter. 107311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 773310 # Number of requests hitting in the snoop filter with a single holder of the requested data. 107411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 11158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 107511336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 166217 # Total number of snoops made to the snoop filter. 107611336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 164146 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 107711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2071 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 107811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 12750 # Transaction distribution 107911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 709337 # Transaction distribution 108010535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution 108110535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution 108211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 121108 # Transaction distribution 108311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 594239 # Transaction distribution 108411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 28846 # Transaction distribution 108511336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22562 # Transaction distribution 108611336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 51408 # Transaction distribution 108711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution 108811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution 108911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 523913 # Transaction distribution 109011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 172674 # Transaction distribution 109111336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1571581 # Packet count per connected master and slave (bytes) 109211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 778800 # Packet count per connected master and slave (bytes) 109310535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) 109411336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes) 109511336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 2369077 # Packet count per connected master and slave (bytes) 109611336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 67028804 # Cumulative packet size per connected master and slave (bytes) 109711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 27426222 # Cumulative packet size per connected master and slave (bytes) 109810535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) 109911336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes) 110011336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 94492418 # Cumulative packet size per connected master and slave (bytes) 110111336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 347790 # Total snoops (count) 110211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 1820349 # Request fanout histogram 110311336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.108308 # Request fanout histogram 110411336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.314409 # Request fanout histogram 110510535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 110611336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 1625261 89.28% 89.28% # Request fanout histogram 110711336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 193017 10.60% 99.89% # Request fanout histogram 110811336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 2071 0.11% 100.00% # Request fanout histogram 110910535Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 111011138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 111110827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 111211336Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 1820349 # Request fanout histogram 111310726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30995 # Transaction distribution 111410726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30995 # Transaction distribution 111510726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59419 # Transaction distribution 111610892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 59419 # Transaction distribution 111710726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) 111810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) 111911245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 112010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 112110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 112210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 112310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 112410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 112510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 112610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 112710409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 112810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 112910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 113010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 113110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 113210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 113310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 113410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 113510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 113610726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) 113710513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) 113810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) 113910726Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) 114010726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) 114110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) 114211245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 114310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 114410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 114510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 114610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 114710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 114810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 114910409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 115210409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 115510513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 115610409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 115710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 115810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 115910726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) 116010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) 116110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) 116210726Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) 116310513SAli.Saidi@ARM.comsystem.iocache.tags.replacements 36442 # number of replacements 116411336Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 14.586086 # Cycle average of tags in use 11659885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 116610513SAli.Saidi@ARM.comsystem.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. 116710513SAli.Saidi@ARM.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 116810517SAli.Saidi@ARM.comsystem.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit. 116911336Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 14.586086 # Average occupied blocks per requestor 117011336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.911630 # Average percentage of cache occupancy 117111336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.911630 # Average percentage of cache occupancy 117210513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 117310513SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 117410513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 117510513SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 328284 # Number of tag accesses 117610513SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 328284 # Number of data accesses 117710513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses 117810513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::total 252 # number of ReadReq misses 117910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 118010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 118110513SAli.Saidi@ARM.comsystem.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses 118210513SAli.Saidi@ARM.comsystem.iocache.demand_misses::total 252 # number of demand (read+write) misses 118310513SAli.Saidi@ARM.comsystem.iocache.overall_misses::realview.ide 252 # number of overall misses 118410513SAli.Saidi@ARM.comsystem.iocache.overall_misses::total 252 # number of overall misses 118510513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) 118610513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) 118710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 118810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 118910513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses 119010513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::total 252 # number of demand (read+write) accesses 119110513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses 119210513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::total 252 # number of overall (read+write) accesses 119310513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 119410513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 119510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 119610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 119710513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 119810513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 119910513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 120010513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 12018844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 12028844SAli.Saidi@ARM.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 12038844SAli.Saidi@ARM.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 12048844SAli.Saidi@ARM.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 12058983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 12068983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 120710585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 12088844SAli.Saidi@ARM.comsystem.iocache.cache_copies 0 # number of cache copies performed 120910585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 121010585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 12118844SAli.Saidi@ARM.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 121211336Sandreas.hansson@arm.comsystem.l2c.tags.replacements 107729 # number of replacements 121311336Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 62410.633039 # Cycle average of tags in use 121411336Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 243914 # Total number of references to valid blocks. 121511336Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 168410 # Sample count of references to valid blocks. 121611336Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 1.448334 # Average number of references to valid blocks. 121710535Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 121811336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 48132.772899 # Average occupied blocks per requestor 121911336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 5.010469 # Average occupied blocks per requestor 122011336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 0.030814 # Average occupied blocks per requestor 122111336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 7764.318269 # Average occupied blocks per requestor 122211336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4071.663088 # Average occupied blocks per requestor 122311336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 1666.007629 # Average occupied blocks per requestor 122411336Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 770.829870 # Average occupied blocks per requestor 122511336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.734448 # Average percentage of cache occupancy 122611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000076 # Average percentage of cache occupancy 122711138Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy 122811336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.118474 # Average percentage of cache occupancy 122911336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.062129 # Average percentage of cache occupancy 123011336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.025421 # Average percentage of cache occupancy 123111336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.011762 # Average percentage of cache occupancy 123211336Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.952311 # Average percentage of cache occupancy 123311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id 123411336Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 60675 # Occupied blocks per task id 123511201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id 123611201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id 123711336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id 123811336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1869 # Occupied blocks per task id 123911336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 13225 # Occupied blocks per task id 124011336Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 45497 # Occupied blocks per task id 124111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id 124211336Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.925827 # Percentage of cache occupancy per task id 124311336Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 5179303 # Number of tag accesses 124411336Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 5179303 # Number of data accesses 124511336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 225726 # number of WritebackDirty hits 124611336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 225726 # number of WritebackDirty hits 124711336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 564 # number of UpgradeReq hits 124811336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 115 # number of UpgradeReq hits 124911336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 679 # number of UpgradeReq hits 125011336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 81 # number of SCUpgradeReq hits 125111336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 38 # number of SCUpgradeReq hits 125211336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 119 # number of SCUpgradeReq hits 125311336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 13900 # number of ReadExReq hits 125411336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 3040 # number of ReadExReq hits 125511336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 16940 # number of ReadExReq hits 125611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 77 # number of ReadSharedReq hits 125711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 58 # number of ReadSharedReq hits 125811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 25005 # number of ReadSharedReq hits 125911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 76077 # number of ReadSharedReq hits 126011336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 34 # number of ReadSharedReq hits 126111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 35 # number of ReadSharedReq hits 126211336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 11094 # number of ReadSharedReq hits 126311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 11733 # number of ReadSharedReq hits 126411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 124113 # number of ReadSharedReq hits 126511336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 77 # number of demand (read+write) hits 126611336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 58 # number of demand (read+write) hits 126711336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 25005 # number of demand (read+write) hits 126811336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 89977 # number of demand (read+write) hits 126911336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits 127011336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 35 # number of demand (read+write) hits 127111336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 11094 # number of demand (read+write) hits 127211336Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 14773 # number of demand (read+write) hits 127311336Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 141053 # number of demand (read+write) hits 127411336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 77 # number of overall hits 127511336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 58 # number of overall hits 127611336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 25005 # number of overall hits 127711336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 89977 # number of overall hits 127811336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits 127911336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits 128011336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 11094 # number of overall hits 128111336Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 14773 # number of overall hits 128211336Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 141053 # number of overall hits 128311336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 9970 # number of UpgradeReq misses 128411336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 3255 # number of UpgradeReq misses 128511336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 13225 # number of UpgradeReq misses 128611336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 737 # number of SCUpgradeReq misses 128711336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 1148 # number of SCUpgradeReq misses 128811336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 1885 # number of SCUpgradeReq misses 128911336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 136548 # number of ReadExReq misses 129011336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 15822 # number of ReadExReq misses 129111336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 152370 # number of ReadExReq misses 129211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 8 # number of ReadSharedReq misses 129310892Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2 # number of ReadSharedReq misses 129411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 16778 # number of ReadSharedReq misses 129511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 11188 # number of ReadSharedReq misses 129611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 2375 # number of ReadSharedReq misses 129711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 1125 # number of ReadSharedReq misses 129811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 31476 # number of ReadSharedReq misses 129911201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses 130010535Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses 130111336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 16778 # number of demand (read+write) misses 130211336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 147736 # number of demand (read+write) misses 130311336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 2375 # number of demand (read+write) misses 130411336Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 16947 # number of demand (read+write) misses 130511336Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 183846 # number of demand (read+write) misses 130611201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 8 # number of overall misses 130710535Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 130811336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 16778 # number of overall misses 130911336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 147736 # number of overall misses 131011336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 2375 # number of overall misses 131111336Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 16947 # number of overall misses 131211336Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 183846 # number of overall misses 131311336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 225726 # number of WritebackDirty accesses(hits+misses) 131411336Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 225726 # number of WritebackDirty accesses(hits+misses) 131511336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 10534 # number of UpgradeReq accesses(hits+misses) 131611336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 3370 # number of UpgradeReq accesses(hits+misses) 131711336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 13904 # number of UpgradeReq accesses(hits+misses) 131811336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 818 # number of SCUpgradeReq accesses(hits+misses) 131911336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) 132010892Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 2004 # number of SCUpgradeReq accesses(hits+misses) 132111336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 150448 # number of ReadExReq accesses(hits+misses) 132211336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 18862 # number of ReadExReq accesses(hits+misses) 132311336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 169310 # number of ReadExReq accesses(hits+misses) 132411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 85 # number of ReadSharedReq accesses(hits+misses) 132511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 60 # number of ReadSharedReq accesses(hits+misses) 132611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 41783 # number of ReadSharedReq accesses(hits+misses) 132711336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 87265 # number of ReadSharedReq accesses(hits+misses) 132811336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 34 # number of ReadSharedReq accesses(hits+misses) 132911336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 35 # number of ReadSharedReq accesses(hits+misses) 133011336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 13469 # number of ReadSharedReq accesses(hits+misses) 133111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 12858 # number of ReadSharedReq accesses(hits+misses) 133211336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 155589 # number of ReadSharedReq accesses(hits+misses) 133311336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 85 # number of demand (read+write) accesses 133411336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 60 # number of demand (read+write) accesses 133511336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 41783 # number of demand (read+write) accesses 133611336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 237713 # number of demand (read+write) accesses 133711336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 34 # number of demand (read+write) accesses 133811336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses 133911336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 13469 # number of demand (read+write) accesses 134011336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 31720 # number of demand (read+write) accesses 134111336Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 324899 # number of demand (read+write) accesses 134211336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 85 # number of overall (read+write) accesses 134311336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 60 # number of overall (read+write) accesses 134411336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 41783 # number of overall (read+write) accesses 134511336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 237713 # number of overall (read+write) accesses 134611336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 34 # number of overall (read+write) accesses 134711336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses 134811336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 13469 # number of overall (read+write) accesses 134911336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 31720 # number of overall (read+write) accesses 135011336Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 324899 # number of overall (read+write) accesses 135111336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.946459 # miss rate for UpgradeReq accesses 135211336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.965875 # miss rate for UpgradeReq accesses 135311336Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.951165 # miss rate for UpgradeReq accesses 135411336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.900978 # miss rate for SCUpgradeReq accesses 135511336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.967960 # miss rate for SCUpgradeReq accesses 135611336Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.940619 # miss rate for SCUpgradeReq accesses 135711336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.907609 # miss rate for ReadExReq accesses 135811336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.838829 # miss rate for ReadExReq accesses 135911336Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.899947 # miss rate for ReadExReq accesses 136011336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for ReadSharedReq accesses 136111336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.033333 # miss rate for ReadSharedReq accesses 136211336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.401551 # miss rate for ReadSharedReq accesses 136311336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.128207 # miss rate for ReadSharedReq accesses 136411336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.176331 # miss rate for ReadSharedReq accesses 136511336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.087494 # miss rate for ReadSharedReq accesses 136611336Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.202302 # miss rate for ReadSharedReq accesses 136711336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for demand accesses 136811336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.033333 # miss rate for demand accesses 136911336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.401551 # miss rate for demand accesses 137011336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.621489 # miss rate for demand accesses 137111336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.176331 # miss rate for demand accesses 137211336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.534269 # miss rate for demand accesses 137311336Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.565856 # miss rate for demand accesses 137411336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.094118 # miss rate for overall accesses 137511336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.033333 # miss rate for overall accesses 137611336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.401551 # miss rate for overall accesses 137711336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.621489 # miss rate for overall accesses 137811336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.176331 # miss rate for overall accesses 137911336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.534269 # miss rate for overall accesses 138011336Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.565856 # miss rate for overall accesses 138110535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 138210535Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 138310535Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 138410535Sandreas.hansson@arm.comsystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 138510535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 138610535Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 138710535Sandreas.hansson@arm.comsystem.l2c.fast_writes 0 # number of fast writes performed 138810535Sandreas.hansson@arm.comsystem.l2c.cache_copies 0 # number of cache copies performed 138911336Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 96268 # number of writebacks 139011336Sandreas.hansson@arm.comsystem.l2c.writebacks::total 96268 # number of writebacks 139110535Sandreas.hansson@arm.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 139211201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 43996 # Transaction distribution 139311336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 75724 # Transaction distribution 139410827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 30846 # Transaction distribution 139510827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 30846 # Transaction distribution 139611336Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 132458 # Transaction distribution 139711336Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 8718 # Transaction distribution 139811336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 60357 # Transaction distribution 139911336Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 40887 # Transaction distribution 140011336Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 15566 # Transaction distribution 140111336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 152312 # Transaction distribution 140211336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 151914 # Transaction distribution 140311336Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 31728 # Transaction distribution 140410892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 140510892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 140610726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) 140710535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) 140810535Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) 140911336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 617022 # Packet count per connected master and slave (bytes) 141011336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 738406 # Packet count per connected master and slave (bytes) 141111336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109394 # Packet count per connected master and slave (bytes) 141211336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 109394 # Packet count per connected master and slave (bytes) 141311336Sandreas.hansson@arm.comsystem.membus.pkt_count::total 847800 # Packet count per connected master and slave (bytes) 141410726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) 141510535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) 141610535Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) 141711336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17954824 # Cumulative packet size per connected master and slave (bytes) 141811336Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 18144606 # Cumulative packet size per connected master and slave (bytes) 141910892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2332288 # Cumulative packet size per connected master and slave (bytes) 142010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2332288 # Cumulative packet size per connected master and slave (bytes) 142111336Sandreas.hansson@arm.comsystem.membus.pkt_size::total 20476894 # Cumulative packet size per connected master and slave (bytes) 142210535Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 142311336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 537526 # Request fanout histogram 142410535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 142510535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 142610535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 142710535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 142811336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 537526 100.00% 100.00% # Request fanout histogram 142910535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 143010535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 143110535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 143210535Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 143311336Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 537526 # Request fanout histogram 143411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 143511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 143611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 143711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 143811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 143911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 144010535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 144110535Sandreas.hansson@arm.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 144210535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 144310535Sandreas.hansson@arm.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 144410535Sandreas.hansson@arm.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 144510535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 144610535Sandreas.hansson@arm.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 144710535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 144810535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 144910535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 145010535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 145110535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 145210535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 145310535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 145410535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 145510535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 145610535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 145710535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 145810535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 145910535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 146010535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 146110535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 146210535Sandreas.hansson@arm.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 146310535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 146410535Sandreas.hansson@arm.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 146510535Sandreas.hansson@arm.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 146610535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 146710535Sandreas.hansson@arm.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 146810535Sandreas.hansson@arm.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 146910535Sandreas.hansson@arm.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 147010535Sandreas.hansson@arm.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 147111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 147211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 147311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 147411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 147511336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 862694 # Total number of requests made to the snoop filter. 147611336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 444199 # Number of requests hitting in the snoop filter with a single holder of the requested data. 147711336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 128774 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 147811336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 9862 # Total number of snoops made to the snoop filter. 147911336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 9376 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 148011336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 486 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 148110892Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 44000 # Transaction distribution 148211336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 301670 # Transaction distribution 148310827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution 148410827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution 148511336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 225726 # Transaction distribution 148611336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 64248 # Transaction distribution 148711336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 60580 # Transaction distribution 148811336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 41006 # Transaction distribution 148911336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution 149011336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 213448 # Transaction distribution 149111336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 213448 # Transaction distribution 149211336Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 257670 # Transaction distribution 149311336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1161849 # Packet count per connected master and slave (bytes) 149411336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 423225 # Packet count per connected master and slave (bytes) 149511336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 1585074 # Packet count per connected master and slave (bytes) 149611336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34444668 # Cumulative packet size per connected master and slave (bytes) 149711336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10399858 # Cumulative packet size per connected master and slave (bytes) 149811336Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 44844526 # Cumulative packet size per connected master and slave (bytes) 149911336Sandreas.hansson@arm.comsystem.toL2Bus.snoops 180900 # Total snoops (count) 150011336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 1118187 # Request fanout histogram 150111336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.282688 # Request fanout histogram 150211336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.451270 # Request fanout histogram 150310535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 150411336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 802575 71.77% 71.77% # Request fanout histogram 150511336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 315126 28.18% 99.96% # Request fanout histogram 150611336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 486 0.04% 100.00% # Request fanout histogram 150710535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 150811138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 150910535Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 151011336Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 1118187 # Request fanout histogram 15118844SAli.Saidi@ARM.com 15128844SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 1513